[mirror_ubuntu-bionic-kernel.git] / drivers / cpufreq / sparc-us2e-cpufreq.c

/* us2e_cpufreq.c: UltraSPARC-IIe cpu frequency support
 *
 * Copyright (C) 2003 David S. Miller (davem@redhat.com)
 *
 * Many thanks to Dominik Brodowski for fixing up the cpufreq
 * infrastructure in order to make this driver easier to implement.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/cpufreq.h>
#include <linux/threads.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <asm/asi.h>
#include <asm/timer.h>

static struct cpufreq_driver *cpufreq_us2e_driver;

struct us2e_freq_percpu_info {
	struct cpufreq_frequency_table table[6];
};

/* Indexed by cpu number. */
static struct us2e_freq_percpu_info *us2e_freq_table;

#define HBIRD_MEM_CNTL0_ADDR	0x1fe0000f010UL
#define HBIRD_ESTAR_MODE_ADDR	0x1fe0000f080UL

/* UltraSPARC-IIe has five dividers: 1, 2, 4, 6, and 8.  These are controlled
 * in the ESTAR mode control register.
 */
#define ESTAR_MODE_DIV_1	0x0000000000000000UL
#define ESTAR_MODE_DIV_2	0x0000000000000001UL
#define ESTAR_MODE_DIV_4	0x0000000000000003UL
#define ESTAR_MODE_DIV_6	0x0000000000000002UL
#define ESTAR_MODE_DIV_8	0x0000000000000004UL
#define ESTAR_MODE_DIV_MASK	0x0000000000000007UL

#define MCTRL0_SREFRESH_ENAB	0x0000000000010000UL
#define MCTRL0_REFR_COUNT_MASK	0x0000000000007f00UL
#define MCTRL0_REFR_COUNT_SHIFT	8
#define MCTRL0_REFR_INTERVAL	7800
#define MCTRL0_REFR_CLKS_P_CNT	64

static unsigned long read_hbreg(unsigned long addr)
{
	unsigned long ret;

	__asm__ __volatile__("ldxa	[%1] %2, %0"
			     : "=&r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
	return ret;
}

static void write_hbreg(unsigned long addr, unsigned long val)
{
	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
			     "membar	#Sync"
			     : /* no outputs */
			     : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
			     : "memory");
	if (addr == HBIRD_ESTAR_MODE_ADDR) {
		/* Need to wait 16 clock cycles for the PLL to lock.  */
		udelay(1);
	}
}

static void self_refresh_ctl(int enable)
{
	unsigned long mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);

	if (enable)
		mctrl |= MCTRL0_SREFRESH_ENAB;
	else
		mctrl &= ~MCTRL0_SREFRESH_ENAB;
	write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl);
	(void) read_hbreg(HBIRD_MEM_CNTL0_ADDR);
}

static void frob_mem_refresh(int cpu_slowing_down,
			     unsigned long clock_tick,
			     unsigned long old_divisor, unsigned long divisor)
{
	unsigned long old_refr_count, refr_count, mctrl;

	refr_count  = (clock_tick * MCTRL0_REFR_INTERVAL);
	refr_count /= (MCTRL0_REFR_CLKS_P_CNT * divisor * 1000000000UL);

	mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
	old_refr_count = (mctrl & MCTRL0_REFR_COUNT_MASK)
		>> MCTRL0_REFR_COUNT_SHIFT;

	mctrl &= ~MCTRL0_REFR_COUNT_MASK;
	mctrl |= refr_count << MCTRL0_REFR_COUNT_SHIFT;
	write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl);
	mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);

	if (cpu_slowing_down && !(mctrl & MCTRL0_SREFRESH_ENAB)) {
		unsigned long usecs;

		/* We have to wait for both refresh counts (old
		 * and new) to go to zero.
		 */
		usecs = (MCTRL0_REFR_CLKS_P_CNT *
			 (refr_count + old_refr_count) *
			 1000000UL *
			 old_divisor) / clock_tick;
		udelay(usecs + 1UL);
	}
}

static void us2e_transition(unsigned long estar, unsigned long new_bits,
			    unsigned long clock_tick,
			    unsigned long old_divisor, unsigned long divisor)
{
	estar &= ~ESTAR_MODE_DIV_MASK;

	/* This is based upon the state transition diagram in the IIe manual.  */
	if (old_divisor == 2 && divisor == 1) {
		self_refresh_ctl(0);
		write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
		frob_mem_refresh(0, clock_tick, old_divisor, divisor);
	} else if (old_divisor == 1 && divisor == 2) {
		frob_mem_refresh(1, clock_tick, old_divisor, divisor);
		write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
		self_refresh_ctl(1);
	} else if (old_divisor == 1 && divisor > 2) {
		us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick,
				1, 2);
		us2e_transition(estar, new_bits, clock_tick,
				2, divisor);
	} else if (old_divisor > 2 && divisor == 1) {
		us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick,
				old_divisor, 2);
		us2e_transition(estar, new_bits, clock_tick,
				2, divisor);
	} else if (old_divisor < divisor) {
		frob_mem_refresh(0, clock_tick, old_divisor, divisor);
		write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
	} else if (old_divisor > divisor) {
		write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
		frob_mem_refresh(1, clock_tick, old_divisor, divisor);
	} else {
		BUG();
	}
}

static unsigned long index_to_estar_mode(unsigned int index)
{
	switch (index) {
	case 0:
		return ESTAR_MODE_DIV_1;

	case 1:
		return ESTAR_MODE_DIV_2;

	case 2:
		return ESTAR_MODE_DIV_4;

	case 3:
		return ESTAR_MODE_DIV_6;

	case 4:
		return ESTAR_MODE_DIV_8;

	default:
		BUG();
	}
}

static unsigned long index_to_divisor(unsigned int index)
{
	switch (index) {
	case 0:
		return 1;

	case 1:
		return 2;

	case 2:
		return 4;

	case 3:
		return 6;

	case 4:
		return 8;

	default:
		BUG();
	}
}

static unsigned long estar_to_divisor(unsigned long estar)
{
	unsigned long ret;

	switch (estar & ESTAR_MODE_DIV_MASK) {
	case ESTAR_MODE_DIV_1:
		ret = 1;
		break;
	case ESTAR_MODE_DIV_2:
		ret = 2;
		break;
	case ESTAR_MODE_DIV_4:
		ret = 4;
		break;
	case ESTAR_MODE_DIV_6:
		ret = 6;
		break;
	case ESTAR_MODE_DIV_8:
		ret = 8;
		break;
	default:
		BUG();
	}

	return ret;
}

static void __us2e_freq_get(void *arg)
{
	unsigned long *estar = arg;

	*estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR);
}

static unsigned int us2e_freq_get(unsigned int cpu)
{
	unsigned long clock_tick, estar;

	clock_tick = sparc64_get_clock_tick(cpu) / 1000;
	if (smp_call_function_single(cpu, __us2e_freq_get, &estar, 1))
		return 0;

	return clock_tick / estar_to_divisor(estar);
}

static void __us2e_freq_target(void *arg)
{
	unsigned int cpu = smp_processor_id();
	unsigned int *index = arg;
	unsigned long new_bits, new_freq;
	unsigned long clock_tick, divisor, old_divisor, estar;

	new_freq = clock_tick = sparc64_get_clock_tick(cpu) / 1000;
	new_bits = index_to_estar_mode(*index);
	divisor = index_to_divisor(*index);
	new_freq /= divisor;

	estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR);

	old_divisor = estar_to_divisor(estar);

	if (old_divisor != divisor) {
		us2e_transition(estar, new_bits, clock_tick * 1000,
				old_divisor, divisor);
	}
}

static int us2e_freq_target(struct cpufreq_policy *policy, unsigned int index)
{
	unsigned int cpu = policy->cpu;

	return smp_call_function_single(cpu, __us2e_freq_target, &index, 1);
}

static int __init us2e_freq_cpu_init(struct cpufreq_policy *policy)
{
	unsigned int cpu = policy->cpu;
	unsigned long clock_tick = sparc64_get_clock_tick(cpu) / 1000;
	struct cpufreq_frequency_table *table =
		&us2e_freq_table[cpu].table[0];

	table[0].driver_data = 0;
	table[0].frequency = clock_tick / 1;
	table[1].driver_data = 1;
	table[1].frequency = clock_tick / 2;
	table[2].driver_data = 2;
	table[2].frequency = clock_tick / 4;
	table[2].driver_data = 3;
	table[2].frequency = clock_tick / 6;
	table[2].driver_data = 4;
	table[2].frequency = clock_tick / 8;
	table[2].driver_data = 5;
	table[3].frequency = CPUFREQ_TABLE_END;

	policy->cpuinfo.transition_latency = 0;
	policy->cur = clock_tick;

	return cpufreq_table_validate_and_show(policy, table);
}

static int us2e_freq_cpu_exit(struct cpufreq_policy *policy)
{
	if (cpufreq_us2e_driver)
		us2e_freq_target(policy, 0);

	return 0;
}

static int __init us2e_freq_init(void)
{
	unsigned long manuf, impl, ver;
	int ret;

	if (tlb_type != spitfire)
		return -ENODEV;

	__asm__("rdpr %%ver, %0" : "=r" (ver));
	manuf = ((ver >> 48) & 0xffff);
	impl  = ((ver >> 32) & 0xffff);

	if (manuf == 0x17 && impl == 0x13) {
		struct cpufreq_driver *driver;

		ret = -ENOMEM;
		driver = kzalloc(sizeof(*driver), GFP_KERNEL);
		if (!driver)
			goto err_out;

		us2e_freq_table = kzalloc((NR_CPUS * sizeof(*us2e_freq_table)),
			GFP_KERNEL);
		if (!us2e_freq_table)
			goto err_out;

		driver->init = us2e_freq_cpu_init;
		driver->verify = cpufreq_generic_frequency_table_verify;
		driver->target_index = us2e_freq_target;
		driver->get = us2e_freq_get;
		driver->exit = us2e_freq_cpu_exit;
		strcpy(driver->name, "UltraSPARC-IIe");

		cpufreq_us2e_driver = driver;
		ret = cpufreq_register_driver(driver);
		if (ret)
			goto err_out;

		return 0;

err_out:
		if (driver) {
			kfree(driver);
			cpufreq_us2e_driver = NULL;
		}
		kfree(us2e_freq_table);
		us2e_freq_table = NULL;
		return ret;
	}

	return -ENODEV;
}

static void __exit us2e_freq_exit(void)
{
	if (cpufreq_us2e_driver) {
		cpufreq_unregister_driver(cpufreq_us2e_driver);
		kfree(cpufreq_us2e_driver);
		cpufreq_us2e_driver = NULL;
		kfree(us2e_freq_table);
		us2e_freq_table = NULL;
	}
}

MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
MODULE_DESCRIPTION("cpufreq driver for UltraSPARC-IIe");
MODULE_LICENSE("GPL");

module_init(us2e_freq_init);
module_exit(us2e_freq_exit);
Commit	Line	Data
1da177e4 LT	1	/* us2e_cpufreq.c: UltraSPARC-IIe cpu frequency support
	2	*
	3	* Copyright (C) 2003 David S. Miller (davem@redhat.com)
	4	*
	5	* Many thanks to Dominik Brodowski for fixing up the cpufreq
	6	* infrastructure in order to make this driver easier to implement.
	7	*/
	8
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/sched.h>
	12	#include <linux/smp.h>
	13	#include <linux/cpufreq.h>
	14	#include <linux/threads.h>
	15	#include <linux/slab.h>
	16	#include <linux/delay.h>
	17	#include <linux/init.h>
	18
	19	#include <asm/asi.h>
	20	#include <asm/timer.h>
	21
	22	static struct cpufreq_driver *cpufreq_us2e_driver;
	23
	24	struct us2e_freq_percpu_info {
	25	struct cpufreq_frequency_table table[6];
	26	};
	27
	28	/* Indexed by cpu number. */
	29	static struct us2e_freq_percpu_info *us2e_freq_table;
	30
	31	#define HBIRD_MEM_CNTL0_ADDR 0x1fe0000f010UL
	32	#define HBIRD_ESTAR_MODE_ADDR 0x1fe0000f080UL
	33
	34	/* UltraSPARC-IIe has five dividers: 1, 2, 4, 6, and 8. These are controlled
	35	* in the ESTAR mode control register.
	36	*/
	37	#define ESTAR_MODE_DIV_1 0x0000000000000000UL
	38	#define ESTAR_MODE_DIV_2 0x0000000000000001UL
	39	#define ESTAR_MODE_DIV_4 0x0000000000000003UL
	40	#define ESTAR_MODE_DIV_6 0x0000000000000002UL
	41	#define ESTAR_MODE_DIV_8 0x0000000000000004UL
	42	#define ESTAR_MODE_DIV_MASK 0x0000000000000007UL
	43
	44	#define MCTRL0_SREFRESH_ENAB 0x0000000000010000UL
	45	#define MCTRL0_REFR_COUNT_MASK 0x0000000000007f00UL
	46	#define MCTRL0_REFR_COUNT_SHIFT 8
	47	#define MCTRL0_REFR_INTERVAL 7800
	48	#define MCTRL0_REFR_CLKS_P_CNT 64
	49
	50	static unsigned long read_hbreg(unsigned long addr)
	51	{
	52	unsigned long ret;
	53
	54	__asm__ __volatile__("ldxa [%1] %2, %0"
	55	: "=&r" (ret)
	56	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
	57	return ret;
	58	}
	59
	60	static void write_hbreg(unsigned long addr, unsigned long val)
	61	{
	62	__asm__ __volatile__("stxa %0, [%1] %2\n\t"
	63	"membar #Sync"
	64	: /* no outputs */
65	: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
66	: "memory");
67	if (addr == HBIRD_ESTAR_MODE_ADDR) {
68	/* Need to wait 16 clock cycles for the PLL to lock. */
69	udelay(1);
70	}
71	}
72
73	static void self_refresh_ctl(int enable)
74	{
75	unsigned long mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
76
77	if (enable)
78	mctrl \|= MCTRL0_SREFRESH_ENAB;
79	else
80	mctrl &= ~MCTRL0_SREFRESH_ENAB;
81	write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl);
82	(void) read_hbreg(HBIRD_MEM_CNTL0_ADDR);
83	}
84
85	static void frob_mem_refresh(int cpu_slowing_down,
86	unsigned long clock_tick,
87	unsigned long old_divisor, unsigned long divisor)
88	{
89	unsigned long old_refr_count, refr_count, mctrl;
90
1da177e4 LT	91	refr_count = (clock_tick * MCTRL0_REFR_INTERVAL);
	92	refr_count /= (MCTRL0_REFR_CLKS_P_CNT * divisor * 1000000000UL);
	93
	94	mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
	95	old_refr_count = (mctrl & MCTRL0_REFR_COUNT_MASK)
	96	>> MCTRL0_REFR_COUNT_SHIFT;
	97
	98	mctrl &= ~MCTRL0_REFR_COUNT_MASK;
	99	mctrl \|= refr_count << MCTRL0_REFR_COUNT_SHIFT;
	100	write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl);
	101	mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
	102
	103	if (cpu_slowing_down && !(mctrl & MCTRL0_SREFRESH_ENAB)) {
	104	unsigned long usecs;
	105
	106	/* We have to wait for both refresh counts (old
	107	* and new) to go to zero.
	108	*/
	109	usecs = (MCTRL0_REFR_CLKS_P_CNT *
	110	(refr_count + old_refr_count) *
	111	1000000UL *
	112	old_divisor) / clock_tick;
	113	udelay(usecs + 1UL);
	114	}
	115	}
	116
	117	static void us2e_transition(unsigned long estar, unsigned long new_bits,
	118	unsigned long clock_tick,
	119	unsigned long old_divisor, unsigned long divisor)
	120	{
1da177e4 LT	121	estar &= ~ESTAR_MODE_DIV_MASK;
	122
	123	/* This is based upon the state transition diagram in the IIe manual. */
	124	if (old_divisor == 2 && divisor == 1) {
	125	self_refresh_ctl(0);
	126	write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar \| new_bits);
	127	frob_mem_refresh(0, clock_tick, old_divisor, divisor);
	128	} else if (old_divisor == 1 && divisor == 2) {
	129	frob_mem_refresh(1, clock_tick, old_divisor, divisor);
	130	write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar \| new_bits);
	131	self_refresh_ctl(1);
	132	} else if (old_divisor == 1 && divisor > 2) {
	133	us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick,
	134	1, 2);
	135	us2e_transition(estar, new_bits, clock_tick,
	136	2, divisor);
	137	} else if (old_divisor > 2 && divisor == 1) {
	138	us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick,
	139	old_divisor, 2);
	140	us2e_transition(estar, new_bits, clock_tick,
	141	2, divisor);
	142	} else if (old_divisor < divisor) {
	143	frob_mem_refresh(0, clock_tick, old_divisor, divisor);
	144	write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar \| new_bits);
	145	} else if (old_divisor > divisor) {
	146	write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar \| new_bits);
	147	frob_mem_refresh(1, clock_tick, old_divisor, divisor);
	148	} else {
	149	BUG();
	150	}
1da177e4 LT	151	}
	152
	153	static unsigned long index_to_estar_mode(unsigned int index)
	154	{
	155	switch (index) {
	156	case 0:
	157	return ESTAR_MODE_DIV_1;
	158
	159	case 1:
	160	return ESTAR_MODE_DIV_2;
	161
	162	case 2:
	163	return ESTAR_MODE_DIV_4;
	164
	165	case 3:
	166	return ESTAR_MODE_DIV_6;
	167
	168	case 4:
	169	return ESTAR_MODE_DIV_8;
	170
	171	default:
	172	BUG();
6cb79b3f	173	}
1da177e4 LT	174	}
	175
	176	static unsigned long index_to_divisor(unsigned int index)
	177	{
	178	switch (index) {
	179	case 0:
	180	return 1;
	181
	182	case 1:
	183	return 2;
	184
	185	case 2:
	186	return 4;
	187
	188	case 3:
	189	return 6;
	190
	191	case 4:
	192	return 8;
	193
	194	default:
	195	BUG();
6cb79b3f	196	}
1da177e4 LT	197	}
	198
	199	static unsigned long estar_to_divisor(unsigned long estar)
	200	{
	201	unsigned long ret;
	202
	203	switch (estar & ESTAR_MODE_DIV_MASK) {
	204	case ESTAR_MODE_DIV_1:
	205	ret = 1;
	206	break;
	207	case ESTAR_MODE_DIV_2:
	208	ret = 2;
	209	break;
	210	case ESTAR_MODE_DIV_4:
	211	ret = 4;
	212	break;
	213	case ESTAR_MODE_DIV_6:
	214	ret = 6;
	215	break;
	216	case ESTAR_MODE_DIV_8:
	217	ret = 8;
	218	break;
	219	default:
	220	BUG();
6cb79b3f	221	}
1da177e4 LT	222
	223	return ret;
	224	}
	225
12699ac5 TG	226	static void __us2e_freq_get(void *arg)
	227	{
	228	unsigned long *estar = arg;
	229
	230	*estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR);
	231	}
	232
2cab224d DM	233	static unsigned int us2e_freq_get(unsigned int cpu)
2cab224d DM	234	{
2cab224d DM	235	unsigned long clock_tick, estar;
2cab224d DM	236
2cab224d	237	clock_tick = sparc64_get_clock_tick(cpu) / 1000;
12699ac5 TG	238	if (smp_call_function_single(cpu, __us2e_freq_get, &estar, 1))
12699ac5 TG	239	return 0;
2cab224d DM	240
	241	return clock_tick / estar_to_divisor(estar);
	242	}
	243
12699ac5	244	static void __us2e_freq_target(void *arg)
1da177e4	245	{
12699ac5 TG	246	unsigned int cpu = smp_processor_id();
12699ac5 TG	247	unsigned int *index = arg;
1da177e4 LT	248	unsigned long new_bits, new_freq;
1da177e4 LT	249	unsigned long clock_tick, divisor, old_divisor, estar;
1da177e4	250
2cab224d	251	new_freq = clock_tick = sparc64_get_clock_tick(cpu) / 1000;
12699ac5 TG	252	new_bits = index_to_estar_mode(*index);
12699ac5 TG	253	divisor = index_to_divisor(*index);
1da177e4 LT	254	new_freq /= divisor;
	255
	256	estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR);
	257
	258	old_divisor = estar_to_divisor(estar);
	259
12699ac5	260	if (old_divisor != divisor) {
2cab224d DM	261	us2e_transition(estar, new_bits, clock_tick * 1000,
2cab224d DM	262	old_divisor, divisor);
12699ac5 TG	263	}
12699ac5 TG	264	}
1da177e4	265
12699ac5 TG	266	static int us2e_freq_target(struct cpufreq_policy *policy, unsigned int index)
	267	{
	268	unsigned int cpu = policy->cpu;
1da177e4	269
12699ac5	270	return smp_call_function_single(cpu, __us2e_freq_target, &index, 1);
1da177e4 LT	271	}
1da177e4 LT	272
1da177e4 LT	273	static int __init us2e_freq_cpu_init(struct cpufreq_policy *policy)
	274	{
	275	unsigned int cpu = policy->cpu;
2cab224d	276	unsigned long clock_tick = sparc64_get_clock_tick(cpu) / 1000;
1da177e4 LT	277	struct cpufreq_frequency_table *table =
	278	&us2e_freq_table[cpu].table[0];
	279
50701588	280	table[0].driver_data = 0;
1da177e4	281	table[0].frequency = clock_tick / 1;
50701588	282	table[1].driver_data = 1;
1da177e4	283	table[1].frequency = clock_tick / 2;
50701588	284	table[2].driver_data = 2;
1da177e4	285	table[2].frequency = clock_tick / 4;
50701588	286	table[2].driver_data = 3;
1da177e4	287	table[2].frequency = clock_tick / 6;
50701588	288	table[2].driver_data = 4;
1da177e4	289	table[2].frequency = clock_tick / 8;
50701588	290	table[2].driver_data = 5;
1da177e4 LT	291	table[3].frequency = CPUFREQ_TABLE_END;
1da177e4 LT	292
1da177e4 LT	293	policy->cpuinfo.transition_latency = 0;
	294	policy->cur = clock_tick;
	295
f1a707c0	296	return cpufreq_table_validate_and_show(policy, table);
1da177e4 LT	297	}
	298
	299	static int us2e_freq_cpu_exit(struct cpufreq_policy *policy)
	300	{
e0b3165b	301	if (cpufreq_us2e_driver)
9c0ebcf7	302	us2e_freq_target(policy, 0);
1da177e4 LT	303
	304	return 0;
	305	}
	306
	307	static int __init us2e_freq_init(void)
	308	{
	309	unsigned long manuf, impl, ver;
	310	int ret;
	311
d82ace7d DM	312	if (tlb_type != spitfire)
	313	return -ENODEV;
	314
1da177e4 LT	315	__asm__("rdpr %%ver, %0" : "=r" (ver));
	316	manuf = ((ver >> 48) & 0xffff);
	317	impl = ((ver >> 32) & 0xffff);
	318
	319	if (manuf == 0x17 && impl == 0x13) {
	320	struct cpufreq_driver *driver;
	321
	322	ret = -ENOMEM;
d5b73cd8	323	driver = kzalloc(sizeof(*driver), GFP_KERNEL);
1da177e4 LT	324	if (!driver)
1da177e4 LT	325	goto err_out;
1da177e4	326
d5b73cd8	327	us2e_freq_table = kzalloc((NR_CPUS * sizeof(*us2e_freq_table)),
1da177e4 LT	328	GFP_KERNEL);
	329	if (!us2e_freq_table)
	330	goto err_out;
	331
2cab224d	332	driver->init = us2e_freq_cpu_init;
7a1874a0	333	driver->verify = cpufreq_generic_frequency_table_verify;
9c0ebcf7	334	driver->target_index = us2e_freq_target;
2cab224d	335	driver->get = us2e_freq_get;
1da177e4	336	driver->exit = us2e_freq_cpu_exit;
1da177e4 LT	337	strcpy(driver->name, "UltraSPARC-IIe");
	338
	339	cpufreq_us2e_driver = driver;
	340	ret = cpufreq_register_driver(driver);
	341	if (ret)
	342	goto err_out;
	343
	344	return 0;
	345
	346	err_out:
	347	if (driver) {
	348	kfree(driver);
	349	cpufreq_us2e_driver = NULL;
	350	}
b2325fe1 JJ	351	kfree(us2e_freq_table);
b2325fe1 JJ	352	us2e_freq_table = NULL;
1da177e4 LT	353	return ret;
	354	}
	355
	356	return -ENODEV;
	357	}
	358
	359	static void __exit us2e_freq_exit(void)
	360	{
	361	if (cpufreq_us2e_driver) {
	362	cpufreq_unregister_driver(cpufreq_us2e_driver);
1da177e4 LT	363	kfree(cpufreq_us2e_driver);
	364	cpufreq_us2e_driver = NULL;
	365	kfree(us2e_freq_table);
	366	us2e_freq_table = NULL;
	367	}
	368	}
	369
	370	MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
	371	MODULE_DESCRIPTION("cpufreq driver for UltraSPARC-IIe");
	372	MODULE_LICENSE("GPL");
	373
	374	module_init(us2e_freq_init);
	375	module_exit(us2e_freq_exit);