[mirror_ubuntu-artful-kernel.git] / drivers / cpufreq / speedstep-ich.c

/*
 * (C) 2001  Dave Jones, Arjan van de ven.
 * (C) 2002 - 2003  Dominik Brodowski <linux@brodo.de>
 *
 *  Licensed under the terms of the GNU GPL License version 2.
 *  Based upon reverse engineered information, and on Intel documentation
 *  for chipsets ICH2-M and ICH3-M.
 *
 *  Many thanks to Ducrot Bruno for finding and fixing the last
 *  "missing link" for ICH2-M/ICH3-M support, and to Thomas Winkler
 *  for extensive testing.
 *
 *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
 */


/*********************************************************************
 *                        SPEEDSTEP - DEFINITIONS                    *
 *********************************************************************/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/pci.h>
#include <linux/sched.h>

#include <asm/cpu_device_id.h>

#include "speedstep-lib.h"


/* speedstep_chipset:
 *   It is necessary to know which chipset is used. As accesses to
 * this device occur at various places in this module, we need a
 * static struct pci_dev * pointing to that device.
 */
static struct pci_dev *speedstep_chipset_dev;


/* speedstep_processor
 */
static enum speedstep_processor speedstep_processor;

static u32 pmbase;

/*
 *   There are only two frequency states for each processor. Values
 * are in kHz for the time being.
 */
static struct cpufreq_frequency_table speedstep_freqs[] = {
	{SPEEDSTEP_HIGH,	0},
	{SPEEDSTEP_LOW,		0},
	{0,			CPUFREQ_TABLE_END},
};


/**
 * speedstep_find_register - read the PMBASE address
 *
 * Returns: -ENODEV if no register could be found
 */
static int speedstep_find_register(void)
{
	if (!speedstep_chipset_dev)
		return -ENODEV;

	/* get PMBASE */
	pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
	if (!(pmbase & 0x01)) {
		printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
		return -ENODEV;
	}

	pmbase &= 0xFFFFFFFE;
	if (!pmbase) {
		printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
		return -ENODEV;
	}

	pr_debug("pmbase is 0x%x\n", pmbase);
	return 0;
}

/**
 * speedstep_set_state - set the SpeedStep state
 * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
 *
 *   Tries to change the SpeedStep state.  Can be called from
 *   smp_call_function_single.
 */
static void speedstep_set_state(unsigned int state)
{
	u8 pm2_blk;
	u8 value;
	unsigned long flags;

	if (state > 0x1)
		return;

	/* Disable IRQs */
	local_irq_save(flags);

	/* read state */
	value = inb(pmbase + 0x50);

	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);

	/* write new state */
	value &= 0xFE;
	value |= state;

	pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);

	/* Disable bus master arbitration */
	pm2_blk = inb(pmbase + 0x20);
	pm2_blk |= 0x01;
	outb(pm2_blk, (pmbase + 0x20));

	/* Actual transition */
	outb(value, (pmbase + 0x50));

	/* Restore bus master arbitration */
	pm2_blk &= 0xfe;
	outb(pm2_blk, (pmbase + 0x20));

	/* check if transition was successful */
	value = inb(pmbase + 0x50);

	/* Enable IRQs */
	local_irq_restore(flags);

	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);

	if (state == (value & 0x1))
		pr_debug("change to %u MHz succeeded\n",
			speedstep_get_frequency(speedstep_processor) / 1000);
	else
		printk(KERN_ERR "cpufreq: change failed - I/O error\n");

	return;
}

/* Wrapper for smp_call_function_single. */
static void _speedstep_set_state(void *_state)
{
	speedstep_set_state(*(unsigned int *)_state);
}

/**
 * speedstep_activate - activate SpeedStep control in the chipset
 *
 *   Tries to activate the SpeedStep status and control registers.
 * Returns -EINVAL on an unsupported chipset, and zero on success.
 */
static int speedstep_activate(void)
{
	u16 value = 0;

	if (!speedstep_chipset_dev)
		return -EINVAL;

	pci_read_config_word(speedstep_chipset_dev, 0x00A0, &value);
	if (!(value & 0x08)) {
		value |= 0x08;
		pr_debug("activating SpeedStep (TM) registers\n");
		pci_write_config_word(speedstep_chipset_dev, 0x00A0, value);
	}

	return 0;
}


/**
 * speedstep_detect_chipset - detect the Southbridge which contains SpeedStep logic
 *
 *   Detects ICH2-M, ICH3-M and ICH4-M so far. The pci_dev points to
 * the LPC bridge / PM module which contains all power-management
 * functions. Returns the SPEEDSTEP_CHIPSET_-number for the detected
 * chipset, or zero on failure.
 */
static unsigned int speedstep_detect_chipset(void)
{
	speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
			      PCI_DEVICE_ID_INTEL_82801DB_12,
			      PCI_ANY_ID, PCI_ANY_ID,
			      NULL);
	if (speedstep_chipset_dev)
		return 4; /* 4-M */

	speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
			      PCI_DEVICE_ID_INTEL_82801CA_12,
			      PCI_ANY_ID, PCI_ANY_ID,
			      NULL);
	if (speedstep_chipset_dev)
		return 3; /* 3-M */


	speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
			      PCI_DEVICE_ID_INTEL_82801BA_10,
			      PCI_ANY_ID, PCI_ANY_ID,
			      NULL);
	if (speedstep_chipset_dev) {
		/* speedstep.c causes lockups on Dell Inspirons 8000 and
		 * 8100 which use a pretty old revision of the 82815
		 * host bridge. Abort on these systems.
		 */
		static struct pci_dev *hostbridge;

		hostbridge  = pci_get_subsys(PCI_VENDOR_ID_INTEL,
			      PCI_DEVICE_ID_INTEL_82815_MC,
			      PCI_ANY_ID, PCI_ANY_ID,
			      NULL);

		if (!hostbridge)
			return 2; /* 2-M */

		if (hostbridge->revision < 5) {
			pr_debug("hostbridge does not support speedstep\n");
			speedstep_chipset_dev = NULL;
			pci_dev_put(hostbridge);
			return 0;
		}

		pci_dev_put(hostbridge);
		return 2; /* 2-M */
	}

	return 0;
}

static void get_freq_data(void *_speed)
{
	unsigned int *speed = _speed;

	*speed = speedstep_get_frequency(speedstep_processor);
}

static unsigned int speedstep_get(unsigned int cpu)
{
	unsigned int speed;

	/* You're supposed to ensure CPU is online. */
	if (smp_call_function_single(cpu, get_freq_data, &speed, 1) != 0)
		BUG();

	pr_debug("detected %u kHz as current frequency\n", speed);
	return speed;
}

/**
 * speedstep_target - set a new CPUFreq policy
 * @policy: new policy
 * @target_freq: the target frequency
 * @relation: how that frequency relates to achieved frequency
 *	(CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 *
 * Sets a new CPUFreq policy.
 */
static int speedstep_target(struct cpufreq_policy *policy,
			     unsigned int target_freq,
			     unsigned int relation)
{
	unsigned int newstate = 0, policy_cpu;
	struct cpufreq_freqs freqs;

	if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0],
				target_freq, relation, &newstate))
		return -EINVAL;

	policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
	freqs.old = speedstep_get(policy_cpu);
	freqs.new = speedstep_freqs[newstate].frequency;

	pr_debug("transiting from %u to %u kHz\n", freqs.old, freqs.new);

	/* no transition necessary */
	if (freqs.old == freqs.new)
		return 0;

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);

	smp_call_function_single(policy_cpu, _speedstep_set_state, &newstate,
				 true);

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);

	return 0;
}


struct get_freqs {
	struct cpufreq_policy *policy;
	int ret;
};

static void get_freqs_on_cpu(void *_get_freqs)
{
	struct get_freqs *get_freqs = _get_freqs;

	get_freqs->ret =
		speedstep_get_freqs(speedstep_processor,
			    &speedstep_freqs[SPEEDSTEP_LOW].frequency,
			    &speedstep_freqs[SPEEDSTEP_HIGH].frequency,
			    &get_freqs->policy->cpuinfo.transition_latency,
			    &speedstep_set_state);
}

static int speedstep_cpu_init(struct cpufreq_policy *policy)
{
	unsigned int policy_cpu, speed;
	struct get_freqs gf;

	/* only run on CPU to be set, or on its sibling */
#ifdef CONFIG_SMP
	cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu));
#endif
	policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);

	/* detect low and high frequency and transition latency */
	gf.policy = policy;
	smp_call_function_single(policy_cpu, get_freqs_on_cpu, &gf, 1);
	if (gf.ret)
		return gf.ret;

	/* get current speed setting */
	speed = speedstep_get(policy_cpu);
	if (!speed)
		return -EIO;

	pr_debug("currently at %s speed setting - %i MHz\n",
		(speed == speedstep_freqs[SPEEDSTEP_LOW].frequency)
		? "low" : "high",
		(speed / 1000));

	/* cpuinfo and default policy values */
	policy->cur = speed;

	return cpufreq_table_validate_and_show(policy, speedstep_freqs);
}


static struct cpufreq_driver speedstep_driver = {
	.name	= "speedstep-ich",
	.verify	= cpufreq_generic_frequency_table_verify,
	.target	= speedstep_target,
	.init	= speedstep_cpu_init,
	.exit	= cpufreq_generic_exit,
	.get	= speedstep_get,
	.attr	= cpufreq_generic_attr,
};

static const struct x86_cpu_id ss_smi_ids[] = {
	{ X86_VENDOR_INTEL, 6, 0xb, },
	{ X86_VENDOR_INTEL, 6, 0x8, },
	{ X86_VENDOR_INTEL, 15, 2 },
	{}
};
#if 0
/* Autoload or not? Do not for now. */
MODULE_DEVICE_TABLE(x86cpu, ss_smi_ids);
#endif

/**
 * speedstep_init - initializes the SpeedStep CPUFreq driver
 *
 *   Initializes the SpeedStep support. Returns -ENODEV on unsupported
 * devices, -EINVAL on problems during initiatization, and zero on
 * success.
 */
static int __init speedstep_init(void)
{
	if (!x86_match_cpu(ss_smi_ids))
		return -ENODEV;

	/* detect processor */
	speedstep_processor = speedstep_detect_processor();
	if (!speedstep_processor) {
		pr_debug("Intel(R) SpeedStep(TM) capable processor "
				"not found\n");
		return -ENODEV;
	}

	/* detect chipset */
	if (!speedstep_detect_chipset()) {
		pr_debug("Intel(R) SpeedStep(TM) for this chipset not "
				"(yet) available.\n");
		return -ENODEV;
	}

	/* activate speedstep support */
	if (speedstep_activate()) {
		pci_dev_put(speedstep_chipset_dev);
		return -EINVAL;
	}

	if (speedstep_find_register())
		return -ENODEV;

	return cpufreq_register_driver(&speedstep_driver);
}


/**
 * speedstep_exit - unregisters SpeedStep support
 *
 *   Unregisters SpeedStep support.
 */
static void __exit speedstep_exit(void)
{
	pci_dev_put(speedstep_chipset_dev);
	cpufreq_unregister_driver(&speedstep_driver);
}


MODULE_AUTHOR("Dave Jones <davej@redhat.com>, "
		"Dominik Brodowski <linux@brodo.de>");
MODULE_DESCRIPTION("Speedstep driver for Intel mobile processors on chipsets "
		"with ICH-M southbridges.");
MODULE_LICENSE("GPL");

module_init(speedstep_init);
module_exit(speedstep_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* (C) 2001 Dave Jones, Arjan van de ven.
	3	* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
	4	*
	5	* Licensed under the terms of the GNU GPL License version 2.
	6	* Based upon reverse engineered information, and on Intel documentation
	7	* for chipsets ICH2-M and ICH3-M.
	8	*
	9	* Many thanks to Ducrot Bruno for finding and fixing the last
	10	* "missing link" for ICH2-M/ICH3-M support, and to Thomas Winkler
	11	* for extensive testing.
	12	*
	13	* BIG FAT DISCLAIMER: Work in progress code. Possibly dangerous
	14	*/
	15
	16
	17	/*********************************************************************
	18	* SPEEDSTEP - DEFINITIONS *
	19	*********************************************************************/
	20
	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/init.h>
	24	#include <linux/cpufreq.h>
	25	#include <linux/pci.h>
e8edc6e0	26	#include <linux/sched.h>
1da177e4	27
fa8031ae AK	28	#include <asm/cpu_device_id.h>
fa8031ae AK	29
1da177e4 LT	30	#include "speedstep-lib.h"
	31
	32
	33	/* speedstep_chipset:
	34	* It is necessary to know which chipset is used. As accesses to
	35	* this device occur at various places in this module, we need a
	36	* static struct pci_dev * pointing to that device.
	37	*/
	38	static struct pci_dev *speedstep_chipset_dev;
	39
	40
	41	/* speedstep_processor
	42	*/
1cce76c2	43	static enum speedstep_processor speedstep_processor;
1da177e4	44
9a7d82a8	45	static u32 pmbase;
1da177e4 LT	46
	47	/*
	48	* There are only two frequency states for each processor. Values
	49	* are in kHz for the time being.
	50	*/
	51	static struct cpufreq_frequency_table speedstep_freqs[] = {
	52	{SPEEDSTEP_HIGH, 0},
	53	{SPEEDSTEP_LOW, 0},
	54	{0, CPUFREQ_TABLE_END},
	55	};
	56
	57
1da177e4	58	/**
9a7d82a8	59	* speedstep_find_register - read the PMBASE address
1da177e4	60	*
9a7d82a8	61	* Returns: -ENODEV if no register could be found
1da177e4	62	*/
bbfebd66	63	static int speedstep_find_register(void)
1da177e4	64	{
9a7d82a8 MD	65	if (!speedstep_chipset_dev)
9a7d82a8 MD	66	return -ENODEV;
1da177e4 LT	67
	68	/* get PMBASE */
	69	pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
	70	if (!(pmbase & 0x01)) {
	71	printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
9a7d82a8	72	return -ENODEV;
1da177e4 LT	73	}
	74
	75	pmbase &= 0xFFFFFFFE;
	76	if (!pmbase) {
	77	printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
9a7d82a8	78	return -ENODEV;
1da177e4 LT	79	}
1da177e4 LT	80
2d06d8c4	81	pr_debug("pmbase is 0x%x\n", pmbase);
9a7d82a8 MD	82	return 0;
	83	}
	84
	85	/**
	86	* speedstep_set_state - set the SpeedStep state
	87	* @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
	88	*
394122ab RR	89	* Tries to change the SpeedStep state. Can be called from
394122ab RR	90	* smp_call_function_single.
9a7d82a8	91	*/
bbfebd66	92	static void speedstep_set_state(unsigned int state)
9a7d82a8 MD	93	{
	94	u8 pm2_blk;
	95	u8 value;
	96	unsigned long flags;
	97
	98	if (state > 0x1)
	99	return;
	100
1da177e4 LT	101	/* Disable IRQs */
	102	local_irq_save(flags);
	103
	104	/* read state */
	105	value = inb(pmbase + 0x50);
	106
2d06d8c4	107	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
1da177e4 LT	108
	109	/* write new state */
	110	value &= 0xFE;
	111	value \|= state;
	112
2d06d8c4	113	pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);
1da177e4 LT	114
	115	/* Disable bus master arbitration */
	116	pm2_blk = inb(pmbase + 0x20);
	117	pm2_blk \|= 0x01;
	118	outb(pm2_blk, (pmbase + 0x20));
	119
	120	/* Actual transition */
	121	outb(value, (pmbase + 0x50));
	122
	123	/* Restore bus master arbitration */
	124	pm2_blk &= 0xfe;
	125	outb(pm2_blk, (pmbase + 0x20));
	126
	127	/* check if transition was successful */
	128	value = inb(pmbase + 0x50);
	129
	130	/* Enable IRQs */
	131	local_irq_restore(flags);
	132
2d06d8c4	133	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
1da177e4	134
bbfebd66	135	if (state == (value & 0x1))
2d06d8c4	136	pr_debug("change to %u MHz succeeded\n",
bbfebd66 DJ	137	speedstep_get_frequency(speedstep_processor) / 1000);
	138	else
	139	printk(KERN_ERR "cpufreq: change failed - I/O error\n");
1da177e4 LT	140
	141	return;
	142	}
	143
394122ab RR	144	/* Wrapper for smp_call_function_single. */
	145	static void _speedstep_set_state(void *_state)
	146	{
	147	speedstep_set_state((unsigned int )_state);
	148	}
1da177e4 LT	149
	150	/**
	151	* speedstep_activate - activate SpeedStep control in the chipset
	152	*
	153	* Tries to activate the SpeedStep status and control registers.
	154	* Returns -EINVAL on an unsupported chipset, and zero on success.
	155	*/
bbfebd66	156	static int speedstep_activate(void)
1da177e4 LT	157	{
	158	u16 value = 0;
	159
	160	if (!speedstep_chipset_dev)
	161	return -EINVAL;
	162
	163	pci_read_config_word(speedstep_chipset_dev, 0x00A0, &value);
	164	if (!(value & 0x08)) {
	165	value \|= 0x08;
2d06d8c4	166	pr_debug("activating SpeedStep (TM) registers\n");
1da177e4 LT	167	pci_write_config_word(speedstep_chipset_dev, 0x00A0, value);
	168	}
	169
	170	return 0;
	171	}
	172
	173
	174	/**
	175	* speedstep_detect_chipset - detect the Southbridge which contains SpeedStep logic
	176	*
	177	* Detects ICH2-M, ICH3-M and ICH4-M so far. The pci_dev points to
	178	* the LPC bridge / PM module which contains all power-management
	179	* functions. Returns the SPEEDSTEP_CHIPSET_-number for the detected
	180	* chipset, or zero on failure.
	181	*/
bbfebd66	182	static unsigned int speedstep_detect_chipset(void)
1da177e4 LT	183	{
	184	speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
	185	PCI_DEVICE_ID_INTEL_82801DB_12,
bbfebd66	186	PCI_ANY_ID, PCI_ANY_ID,
1da177e4 LT	187	NULL);
	188	if (speedstep_chipset_dev)
	189	return 4; /* 4-M */
	190
	191	speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
	192	PCI_DEVICE_ID_INTEL_82801CA_12,
bbfebd66	193	PCI_ANY_ID, PCI_ANY_ID,
1da177e4 LT	194	NULL);
	195	if (speedstep_chipset_dev)
	196	return 3; /* 3-M */
	197
	198
	199	speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
	200	PCI_DEVICE_ID_INTEL_82801BA_10,
bbfebd66	201	PCI_ANY_ID, PCI_ANY_ID,
1da177e4 LT	202	NULL);
	203	if (speedstep_chipset_dev) {
	204	/* speedstep.c causes lockups on Dell Inspirons 8000 and
	205	* 8100 which use a pretty old revision of the 82815
c03c3013	206	* host bridge. Abort on these systems.
1da177e4 LT	207	*/
1da177e4 LT	208	static struct pci_dev *hostbridge;
1da177e4 LT	209
	210	hostbridge = pci_get_subsys(PCI_VENDOR_ID_INTEL,
	211	PCI_DEVICE_ID_INTEL_82815_MC,
bbfebd66	212	PCI_ANY_ID, PCI_ANY_ID,
1da177e4 LT	213	NULL);
	214
	215	if (!hostbridge)
	216	return 2; /* 2-M */
	217
44c10138	218	if (hostbridge->revision < 5) {
2d06d8c4	219	pr_debug("hostbridge does not support speedstep\n");
1da177e4 LT	220	speedstep_chipset_dev = NULL;
	221	pci_dev_put(hostbridge);
	222	return 0;
	223	}
	224
	225	pci_dev_put(hostbridge);
	226	return 2; /* 2-M */
	227	}
	228
	229	return 0;
	230	}
	231
8dca15e4	232	static void get_freq_data(void *_speed)
394122ab	233	{
8dca15e4	234	unsigned int *speed = _speed;
394122ab	235
8dca15e4	236	*speed = speedstep_get_frequency(speedstep_processor);
1da177e4 LT	237	}
	238
	239	static unsigned int speedstep_get(unsigned int cpu)
	240	{
8dca15e4	241	unsigned int speed;
394122ab RR	242
394122ab RR	243	/* You're supposed to ensure CPU is online. */
8dca15e4	244	if (smp_call_function_single(cpu, get_freq_data, &speed, 1) != 0)
394122ab RR	245	BUG();
394122ab RR	246
2d06d8c4	247	pr_debug("detected %u kHz as current frequency\n", speed);
8dca15e4	248	return speed;
1da177e4 LT	249	}
	250
	251	/**
	252	* speedstep_target - set a new CPUFreq policy
	253	* @policy: new policy
	254	* @target_freq: the target frequency
bbfebd66 DJ	255	* @relation: how that frequency relates to achieved frequency
bbfebd66 DJ	256	* (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
1da177e4 LT	257	*
	258	* Sets a new CPUFreq policy.
	259	*/
bbfebd66	260	static int speedstep_target(struct cpufreq_policy *policy,
1da177e4 LT	261	unsigned int target_freq,
	262	unsigned int relation)
	263	{
394122ab	264	unsigned int newstate = 0, policy_cpu;
1da177e4	265	struct cpufreq_freqs freqs;
1da177e4	266
bbfebd66 DJ	267	if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0],
bbfebd66 DJ	268	target_freq, relation, &newstate))
1da177e4 LT	269	return -EINVAL;
1da177e4 LT	270
394122ab RR	271	policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
394122ab RR	272	freqs.old = speedstep_get(policy_cpu);
1da177e4	273	freqs.new = speedstep_freqs[newstate].frequency;
1da177e4	274
2d06d8c4	275	pr_debug("transiting from %u to %u kHz\n", freqs.old, freqs.new);
1da177e4 LT	276
	277	/* no transition necessary */
	278	if (freqs.old == freqs.new)
	279	return 0;
	280
b43a7ffb	281	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
1da177e4	282
394122ab RR	283	smp_call_function_single(policy_cpu, _speedstep_set_state, &newstate,
394122ab RR	284	true);
1da177e4	285
b43a7ffb	286	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
1da177e4 LT	287
	288	return 0;
	289	}
	290
	291
394122ab RR	292	struct get_freqs {
	293	struct cpufreq_policy *policy;
	294	int ret;
	295	};
	296
	297	static void get_freqs_on_cpu(void *_get_freqs)
	298	{
	299	struct get_freqs *get_freqs = _get_freqs;
	300
	301	get_freqs->ret =
	302	speedstep_get_freqs(speedstep_processor,
	303	&speedstep_freqs[SPEEDSTEP_LOW].frequency,
	304	&speedstep_freqs[SPEEDSTEP_HIGH].frequency,
	305	&get_freqs->policy->cpuinfo.transition_latency,
	306	&speedstep_set_state);
	307	}
1da177e4 LT	308
	309	static int speedstep_cpu_init(struct cpufreq_policy *policy)
	310	{
394122ab RR	311	unsigned int policy_cpu, speed;
394122ab RR	312	struct get_freqs gf;
1da177e4 LT	313
	314	/* only run on CPU to be set, or on its sibling */
	315	#ifdef CONFIG_SMP
7ad728f9	316	cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu));
1da177e4	317	#endif
394122ab	318	policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
1da177e4	319
1a10760c	320	/* detect low and high frequency and transition latency */
394122ab RR	321	gf.policy = policy;
	322	smp_call_function_single(policy_cpu, get_freqs_on_cpu, &gf, 1);
	323	if (gf.ret)
	324	return gf.ret;
1da177e4 LT	325
1da177e4 LT	326	/* get current speed setting */
394122ab	327	speed = speedstep_get(policy_cpu);
1da177e4 LT	328	if (!speed)
	329	return -EIO;
	330
2d06d8c4	331	pr_debug("currently at %s speed setting - %i MHz\n",
bbfebd66 DJ	332	(speed == speedstep_freqs[SPEEDSTEP_LOW].frequency)
bbfebd66 DJ	333	? "low" : "high",
1da177e4 LT	334	(speed / 1000));
	335
	336	/* cpuinfo and default policy values */
1da177e4 LT	337	policy->cur = speed;
1da177e4 LT	338
5f3a2d39	339	return cpufreq_table_validate_and_show(policy, speedstep_freqs);
1da177e4 LT	340	}
	341
	342
221dee28	343	static struct cpufreq_driver speedstep_driver = {
1da177e4	344	.name = "speedstep-ich",
3be1394a	345	.verify = cpufreq_generic_frequency_table_verify,
1da177e4 LT	346	.target = speedstep_target,
1da177e4 LT	347	.init = speedstep_cpu_init,
3be1394a	348	.exit = cpufreq_generic_exit,
1da177e4	349	.get = speedstep_get,
3be1394a	350	.attr = cpufreq_generic_attr,
1da177e4 LT	351	};
1da177e4 LT	352
fa8031ae AK	353	static const struct x86_cpu_id ss_smi_ids[] = {
	354	{ X86_VENDOR_INTEL, 6, 0xb, },
	355	{ X86_VENDOR_INTEL, 6, 0x8, },
	356	{ X86_VENDOR_INTEL, 15, 2 },
	357	{}
	358	};
	359	#if 0
	360	/* Autoload or not? Do not for now. */
	361	MODULE_DEVICE_TABLE(x86cpu, ss_smi_ids);
	362	#endif
1da177e4 LT	363
	364	/**
	365	* speedstep_init - initializes the SpeedStep CPUFreq driver
	366	*
	367	* Initializes the SpeedStep support. Returns -ENODEV on unsupported
	368	* devices, -EINVAL on problems during initiatization, and zero on
	369	* success.
	370	*/
	371	static int __init speedstep_init(void)
	372	{
fa8031ae AK	373	if (!x86_match_cpu(ss_smi_ids))
	374	return -ENODEV;
	375
1da177e4 LT	376	/* detect processor */
	377	speedstep_processor = speedstep_detect_processor();
	378	if (!speedstep_processor) {
2d06d8c4	379	pr_debug("Intel(R) SpeedStep(TM) capable processor "
bbfebd66	380	"not found\n");
1da177e4 LT	381	return -ENODEV;
	382	}
	383
	384	/* detect chipset */
	385	if (!speedstep_detect_chipset()) {
2d06d8c4	386	pr_debug("Intel(R) SpeedStep(TM) for this chipset not "
bbfebd66	387	"(yet) available.\n");
1da177e4 LT	388	return -ENODEV;
	389	}
	390
	391	/* activate speedstep support */
	392	if (speedstep_activate()) {
	393	pci_dev_put(speedstep_chipset_dev);
	394	return -EINVAL;
	395	}
	396
9a7d82a8 MD	397	if (speedstep_find_register())
	398	return -ENODEV;
	399
1da177e4 LT	400	return cpufreq_register_driver(&speedstep_driver);
	401	}
	402
	403
	404	/**
	405	* speedstep_exit - unregisters SpeedStep support
	406	*
	407	* Unregisters SpeedStep support.
	408	*/
	409	static void __exit speedstep_exit(void)
	410	{
	411	pci_dev_put(speedstep_chipset_dev);
	412	cpufreq_unregister_driver(&speedstep_driver);
	413	}
	414
	415
bbfebd66 DJ	416	MODULE_AUTHOR("Dave Jones <davej@redhat.com>, "
	417	"Dominik Brodowski <linux@brodo.de>");
	418	MODULE_DESCRIPTION("Speedstep driver for Intel mobile processors on chipsets "
	419	"with ICH-M southbridges.");
	420	MODULE_LICENSE("GPL");
1da177e4 LT	421
	422	module_init(speedstep_init);
	423	module_exit(speedstep_exit);