[mirror_ubuntu-artful-kernel.git] / drivers / cpufreq / speedstep-lib.c

/*
 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
 *
 *  Licensed under the terms of the GNU GPL License version 2.
 *
 *  Library for common functions for Intel SpeedStep v.1 and v.2 support
 *
 *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/cpufreq.h>

#include <asm/msr.h>
#include <asm/tsc.h>
#include "speedstep-lib.h"

#define PFX "speedstep-lib: "

#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
static int relaxed_check;
#else
#define relaxed_check 0
#endif

/*********************************************************************
 *                   GET PROCESSOR CORE SPEED IN KHZ                 *
 *********************************************************************/

static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
{
	/* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
	struct {
		unsigned int ratio;	/* Frequency Multiplier (x10) */
		u8 bitmap;		/* power on configuration bits
					[27, 25:22] (in MSR 0x2a) */
	} msr_decode_mult[] = {
		{ 30, 0x01 },
		{ 35, 0x05 },
		{ 40, 0x02 },
		{ 45, 0x06 },
		{ 50, 0x00 },
		{ 55, 0x04 },
		{ 60, 0x0b },
		{ 65, 0x0f },
		{ 70, 0x09 },
		{ 75, 0x0d },
		{ 80, 0x0a },
		{ 85, 0x26 },
		{ 90, 0x20 },
		{ 100, 0x2b },
		{ 0, 0xff }	/* error or unknown value */
	};

	/* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
	struct {
		unsigned int value;	/* Front Side Bus speed in MHz */
		u8 bitmap;		/* power on configuration bits [18: 19]
					(in MSR 0x2a) */
	} msr_decode_fsb[] = {
		{  66, 0x0 },
		{ 100, 0x2 },
		{ 133, 0x1 },
		{   0, 0xff}
	};

	u32 msr_lo, msr_tmp;
	int i = 0, j = 0;

	/* read MSR 0x2a - we only need the low 32 bits */
	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
	msr_tmp = msr_lo;

	/* decode the FSB */
	msr_tmp &= 0x00c0000;
	msr_tmp >>= 18;
	while (msr_tmp != msr_decode_fsb[i].bitmap) {
		if (msr_decode_fsb[i].bitmap == 0xff)
			return 0;
		i++;
	}

	/* decode the multiplier */
	if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
		pr_debug("workaround for early PIIIs\n");
		msr_lo &= 0x03c00000;
	} else
		msr_lo &= 0x0bc00000;
	msr_lo >>= 22;
	while (msr_lo != msr_decode_mult[j].bitmap) {
		if (msr_decode_mult[j].bitmap == 0xff)
			return 0;
		j++;
	}

	pr_debug("speed is %u\n",
		(msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));

	return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
}


static unsigned int pentiumM_get_frequency(void)
{
	u32 msr_lo, msr_tmp;

	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);

	/* see table B-2 of 24547212.pdf */
	if (msr_lo & 0x00040000) {
		printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
				msr_lo, msr_tmp);
		return 0;
	}

	msr_tmp = (msr_lo >> 22) & 0x1f;
	pr_debug("bits 22-26 are 0x%x, speed is %u\n",
			msr_tmp, (msr_tmp * 100 * 1000));

	return msr_tmp * 100 * 1000;
}

static unsigned int pentium_core_get_frequency(void)
{
	u32 fsb = 0;
	u32 msr_lo, msr_tmp;
	int ret;

	rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
	/* see table B-2 of 25366920.pdf */
	switch (msr_lo & 0x07) {
	case 5:
		fsb = 100000;
		break;
	case 1:
		fsb = 133333;
		break;
	case 3:
		fsb = 166667;
		break;
	case 2:
		fsb = 200000;
		break;
	case 0:
		fsb = 266667;
		break;
	case 4:
		fsb = 333333;
		break;
	default:
		pr_err("PCORE - MSR_FSB_FREQ undefined value\n");
	}

	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
	pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
			msr_lo, msr_tmp);

	msr_tmp = (msr_lo >> 22) & 0x1f;
	pr_debug("bits 22-26 are 0x%x, speed is %u\n",
			msr_tmp, (msr_tmp * fsb));

	ret = (msr_tmp * fsb);
	return ret;
}


static unsigned int pentium4_get_frequency(void)
{
	struct cpuinfo_x86 *c = &boot_cpu_data;
	u32 msr_lo, msr_hi, mult;
	unsigned int fsb = 0;
	unsigned int ret;
	u8 fsb_code;

	/* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency
	 * to System Bus Frequency Ratio Field in the Processor Frequency
	 * Configuration Register of the MSR. Therefore the current
	 * frequency cannot be calculated and has to be measured.
	 */
	if (c->x86_model < 2)
		return cpu_khz;

	rdmsr(0x2c, msr_lo, msr_hi);

	pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);

	/* decode the FSB: see IA-32 Intel (C) Architecture Software
	 * Developer's Manual, Volume 3: System Prgramming Guide,
	 * revision #12 in Table B-1: MSRs in the Pentium 4 and
	 * Intel Xeon Processors, on page B-4 and B-5.
	 */
	fsb_code = (msr_lo >> 16) & 0x7;
	switch (fsb_code) {
	case 0:
		fsb = 100 * 1000;
		break;
	case 1:
		fsb = 13333 * 10;
		break;
	case 2:
		fsb = 200 * 1000;
		break;
	}

	if (!fsb)
		printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
				"Please send an e-mail to <linux@brodo.de>\n");

	/* Multiplier. */
	mult = msr_lo >> 24;

	pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
			fsb, mult, (fsb * mult));

	ret = (fsb * mult);
	return ret;
}


/* Warning: may get called from smp_call_function_single. */
unsigned int speedstep_get_frequency(enum speedstep_processor processor)
{
	switch (processor) {
	case SPEEDSTEP_CPU_PCORE:
		return pentium_core_get_frequency();
	case SPEEDSTEP_CPU_PM:
		return pentiumM_get_frequency();
	case SPEEDSTEP_CPU_P4D:
	case SPEEDSTEP_CPU_P4M:
		return pentium4_get_frequency();
	case SPEEDSTEP_CPU_PIII_T:
	case SPEEDSTEP_CPU_PIII_C:
	case SPEEDSTEP_CPU_PIII_C_EARLY:
		return pentium3_get_frequency(processor);
	default:
		return 0;
	};
	return 0;
}
EXPORT_SYMBOL_GPL(speedstep_get_frequency);


/*********************************************************************
 *                 DETECT SPEEDSTEP-CAPABLE PROCESSOR                *
 *********************************************************************/

/* Keep in sync with the x86_cpu_id tables in the different modules */
unsigned int speedstep_detect_processor(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);
	u32 ebx, msr_lo, msr_hi;

	pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model);

	if ((c->x86_vendor != X86_VENDOR_INTEL) ||
	    ((c->x86 != 6) && (c->x86 != 0xF)))
		return 0;

	if (c->x86 == 0xF) {
		/* Intel Mobile Pentium 4-M
		 * or Intel Mobile Pentium 4 with 533 MHz FSB */
		if (c->x86_model != 2)
			return 0;

		ebx = cpuid_ebx(0x00000001);
		ebx &= 0x000000FF;

		pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);

		switch (c->x86_mask) {
		case 4:
			/*
			 * B-stepping [M-P4-M]
			 * sample has ebx = 0x0f, production has 0x0e.
			 */
			if ((ebx == 0x0e) || (ebx == 0x0f))
				return SPEEDSTEP_CPU_P4M;
			break;
		case 7:
			/*
			 * C-stepping [M-P4-M]
			 * needs to have ebx=0x0e, else it's a celeron:
			 * cf. 25130917.pdf / page 7, footnote 5 even
			 * though 25072120.pdf / page 7 doesn't say
			 * samples are only of B-stepping...
			 */
			if (ebx == 0x0e)
				return SPEEDSTEP_CPU_P4M;
			break;
		case 9:
			/*
			 * D-stepping [M-P4-M or M-P4/533]
			 *
			 * this is totally strange: CPUID 0x0F29 is
			 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
			 * The latter need to be sorted out as they don't
			 * support speedstep.
			 * Celerons with CPUID 0x0F29 may have either
			 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
			 * specific.
			 * M-P4-Ms may have either ebx=0xe or 0xf [see above]
			 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
			 * also, M-P4M HTs have ebx=0x8, too
			 * For now, they are distinguished by the model_id
			 * string
			 */
			if ((ebx == 0x0e) ||
				(strstr(c->x86_model_id,
				    "Mobile Intel(R) Pentium(R) 4") != NULL))
				return SPEEDSTEP_CPU_P4M;
			break;
		default:
			break;
		}
		return 0;
	}

	switch (c->x86_model) {
	case 0x0B: /* Intel PIII [Tualatin] */
		/* cpuid_ebx(1) is 0x04 for desktop PIII,
		 * 0x06 for mobile PIII-M */
		ebx = cpuid_ebx(0x00000001);
		pr_debug("ebx is %x\n", ebx);

		ebx &= 0x000000FF;

		if (ebx != 0x06)
			return 0;

		/* So far all PIII-M processors support SpeedStep. See
		 * Intel's 24540640.pdf of June 2003
		 */
		return SPEEDSTEP_CPU_PIII_T;

	case 0x08: /* Intel PIII [Coppermine] */

		/* all mobile PIII Coppermines have FSB 100 MHz
		 * ==> sort out a few desktop PIIIs. */
		rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
		pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
				msr_lo, msr_hi);
		msr_lo &= 0x00c0000;
		if (msr_lo != 0x0080000)
			return 0;

		/*
		 * If the processor is a mobile version,
		 * platform ID has bit 50 set
		 * it has SpeedStep technology if either
		 * bit 56 or 57 is set
		 */
		rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
		pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
				msr_lo, msr_hi);
		if ((msr_hi & (1<<18)) &&
		    (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
			if (c->x86_mask == 0x01) {
				pr_debug("early PIII version\n");
				return SPEEDSTEP_CPU_PIII_C_EARLY;
			} else
				return SPEEDSTEP_CPU_PIII_C;
		}

	default:
		return 0;
	}
}
EXPORT_SYMBOL_GPL(speedstep_detect_processor);


/*********************************************************************
 *                     DETECT SPEEDSTEP SPEEDS                       *
 *********************************************************************/

unsigned int speedstep_get_freqs(enum speedstep_processor processor,
				  unsigned int *low_speed,
				  unsigned int *high_speed,
				  unsigned int *transition_latency,
				  void (*set_state) (unsigned int state))
{
	unsigned int prev_speed;
	unsigned int ret = 0;
	unsigned long flags;
	ktime_t tv1, tv2;

	if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
		return -EINVAL;

	pr_debug("trying to determine both speeds\n");

	/* get current speed */
	prev_speed = speedstep_get_frequency(processor);
	if (!prev_speed)
		return -EIO;

	pr_debug("previous speed is %u\n", prev_speed);

	preempt_disable();
	local_irq_save(flags);

	/* switch to low state */
	set_state(SPEEDSTEP_LOW);
	*low_speed = speedstep_get_frequency(processor);
	if (!*low_speed) {
		ret = -EIO;
		goto out;
	}

	pr_debug("low speed is %u\n", *low_speed);

	/* start latency measurement */
	if (transition_latency)
		tv1 = ktime_get();

	/* switch to high state */
	set_state(SPEEDSTEP_HIGH);

	/* end latency measurement */
	if (transition_latency)
		tv2 = ktime_get();

	*high_speed = speedstep_get_frequency(processor);
	if (!*high_speed) {
		ret = -EIO;
		goto out;
	}

	pr_debug("high speed is %u\n", *high_speed);

	if (*low_speed == *high_speed) {
		ret = -ENODEV;
		goto out;
	}

	/* switch to previous state, if necessary */
	if (*high_speed != prev_speed)
		set_state(SPEEDSTEP_LOW);

	if (transition_latency) {
		*transition_latency = ktime_to_us(ktime_sub(tv2, tv1));
		pr_debug("transition latency is %u uSec\n", *transition_latency);

		/* convert uSec to nSec and add 20% for safety reasons */
		*transition_latency *= 1200;

		/* check if the latency measurement is too high or too low
		 * and set it to a safe value (500uSec) in that case
		 */
		if (*transition_latency > 10000000 ||
		    *transition_latency < 50000) {
			pr_warn("frequency transition measured seems out of range (%u nSec), falling back to a safe one of %u nSec\n",
				*transition_latency, 500000);
			*transition_latency = 500000;
		}
	}

out:
	local_irq_restore(flags);
	preempt_enable();

	return ret;
}
EXPORT_SYMBOL_GPL(speedstep_get_freqs);

#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
module_param(relaxed_check, int, 0444);
MODULE_PARM_DESC(relaxed_check,
		"Don't do all checks for speedstep capability.");
#endif

MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
	3	*
	4	* Licensed under the terms of the GNU GPL License version 2.
	5	*
	6	* Library for common functions for Intel SpeedStep v.1 and v.2 support
	7	*
	8	* BIG FAT DISCLAIMER: Work in progress code. Possibly dangerous
	9	*/
	10
1c5864e2 JP	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
1c5864e2 JP	12
1da177e4	13	#include <linux/kernel.h>
32ee8c3e	14	#include <linux/module.h>
1da177e4 LT	15	#include <linux/moduleparam.h>
	16	#include <linux/init.h>
	17	#include <linux/cpufreq.h>
1da177e4 LT	18
1da177e4 LT	19	#include <asm/msr.h>
199785ea	20	#include <asm/tsc.h>
1da177e4 LT	21	#include "speedstep-lib.h"
1da177e4 LT	22
bbfebd66	23	#define PFX "speedstep-lib: "
1da177e4 LT	24
1da177e4 LT	25	#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
bbfebd66	26	static int relaxed_check;
1da177e4 LT	27	#else
	28	#define relaxed_check 0
	29	#endif
	30
	31	/*********************************************************************
	32	* GET PROCESSOR CORE SPEED IN KHZ *
	33	*********************************************************************/
	34
1cce76c2	35	static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
1da177e4	36	{
bbfebd66	37	/* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
1da177e4 LT	38	struct {
1da177e4 LT	39	unsigned int ratio; /* Frequency Multiplier (x10) */
32ee8c3e DJ	40	u8 bitmap; /* power on configuration bits
32ee8c3e DJ	41	[27, 25:22] (in MSR 0x2a) */
bbfebd66	42	} msr_decode_mult[] = {
1da177e4 LT	43	{ 30, 0x01 },
	44	{ 35, 0x05 },
	45	{ 40, 0x02 },
	46	{ 45, 0x06 },
	47	{ 50, 0x00 },
	48	{ 55, 0x04 },
	49	{ 60, 0x0b },
	50	{ 65, 0x0f },
	51	{ 70, 0x09 },
	52	{ 75, 0x0d },
	53	{ 80, 0x0a },
	54	{ 85, 0x26 },
	55	{ 90, 0x20 },
	56	{ 100, 0x2b },
bbfebd66	57	{ 0, 0xff } /* error or unknown value */
1da177e4 LT	58	};
	59
	60	/* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
	61	struct {
32ee8c3e DJ	62	unsigned int value; /* Front Side Bus speed in MHz */
	63	u8 bitmap; /* power on configuration bits [18: 19]
	64	(in MSR 0x2a) */
bbfebd66	65	} msr_decode_fsb[] = {
1da177e4 LT	66	{ 66, 0x0 },
	67	{ 100, 0x2 },
	68	{ 133, 0x1 },
	69	{ 0, 0xff}
	70	};
	71
32ee8c3e DJ	72	u32 msr_lo, msr_tmp;
32ee8c3e DJ	73	int i = 0, j = 0;
1da177e4 LT	74
	75	/* read MSR 0x2a - we only need the low 32 bits */
	76	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
2d06d8c4	77	pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
1da177e4 LT	78	msr_tmp = msr_lo;
	79
	80	/* decode the FSB */
	81	msr_tmp &= 0x00c0000;
	82	msr_tmp >>= 18;
	83	while (msr_tmp != msr_decode_fsb[i].bitmap) {
	84	if (msr_decode_fsb[i].bitmap == 0xff)
	85	return 0;
	86	i++;
	87	}
	88
	89	/* decode the multiplier */
bbfebd66	90	if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
2d06d8c4	91	pr_debug("workaround for early PIIIs\n");
1da177e4 LT	92	msr_lo &= 0x03c00000;
	93	} else
	94	msr_lo &= 0x0bc00000;
	95	msr_lo >>= 22;
	96	while (msr_lo != msr_decode_mult[j].bitmap) {
	97	if (msr_decode_mult[j].bitmap == 0xff)
	98	return 0;
	99	j++;
	100	}
	101
2d06d8c4	102	pr_debug("speed is %u\n",
bbfebd66	103	(msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
1da177e4	104
bbfebd66	105	return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
1da177e4 LT	106	}
	107
	108
	109	static unsigned int pentiumM_get_frequency(void)
	110	{
32ee8c3e	111	u32 msr_lo, msr_tmp;
1da177e4 LT	112
1da177e4 LT	113	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
2d06d8c4	114	pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
1da177e4 LT	115
	116	/* see table B-2 of 24547212.pdf */
	117	if (msr_lo & 0x00040000) {
bbfebd66 DJ	118	printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
bbfebd66 DJ	119	msr_lo, msr_tmp);
1da177e4 LT	120	return 0;
	121	}
	122
	123	msr_tmp = (msr_lo >> 22) & 0x1f;
2d06d8c4	124	pr_debug("bits 22-26 are 0x%x, speed is %u\n",
bbfebd66	125	msr_tmp, (msr_tmp * 100 * 1000));
1da177e4	126
bbfebd66	127	return msr_tmp * 100 * 1000;
1da177e4 LT	128	}
1da177e4 LT	129
4e74663c DB	130	static unsigned int pentium_core_get_frequency(void)
	131	{
	132	u32 fsb = 0;
	133	u32 msr_lo, msr_tmp;
bbfebd66	134	int ret;
4e74663c DB	135
4e74663c DB	136	rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
e11952b9	137	/* see table B-2 of 25366920.pdf */
4e74663c DB	138	switch (msr_lo & 0x07) {
4e74663c DB	139	case 5:
e11952b9	140	fsb = 100000;
4e74663c DB	141	break;
4e74663c DB	142	case 1:
e11952b9	143	fsb = 133333;
4e74663c DB	144	break;
4e74663c DB	145	case 3:
e11952b9	146	fsb = 166667;
4e74663c	147	break;
c60e19eb HRK	148	case 2:
	149	fsb = 200000;
	150	break;
	151	case 0:
	152	fsb = 266667;
	153	break;
	154	case 4:
	155	fsb = 333333;
	156	break;
4e74663c	157	default:
b49c22a6	158	pr_err("PCORE - MSR_FSB_FREQ undefined value\n");
4e74663c DB	159	}
	160
	161	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
2d06d8c4	162	pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
bbfebd66	163	msr_lo, msr_tmp);
4e74663c DB	164
4e74663c DB	165	msr_tmp = (msr_lo >> 22) & 0x1f;
2d06d8c4	166	pr_debug("bits 22-26 are 0x%x, speed is %u\n",
bbfebd66	167	msr_tmp, (msr_tmp * fsb));
4e74663c	168
bbfebd66 DJ	169	ret = (msr_tmp * fsb);
bbfebd66 DJ	170	return ret;
4e74663c	171	}
e11952b9	172
1da177e4 LT	173
	174	static unsigned int pentium4_get_frequency(void)
	175	{
	176	struct cpuinfo_x86 *c = &boot_cpu_data;
	177	u32 msr_lo, msr_hi, mult;
	178	unsigned int fsb = 0;
bbfebd66	179	unsigned int ret;
199785ea MCO	180	u8 fsb_code;
	181
	182	/* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency
	183	* to System Bus Frequency Ratio Field in the Processor Frequency
	184	* Configuration Register of the MSR. Therefore the current
	185	* frequency cannot be calculated and has to be measured.
	186	*/
	187	if (c->x86_model < 2)
	188	return cpu_khz;
1da177e4 LT	189
	190	rdmsr(0x2c, msr_lo, msr_hi);
	191
2d06d8c4	192	pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
1da177e4	193
32ee8c3e	194	/* decode the FSB: see IA-32 Intel (C) Architecture Software
1da177e4 LT	195	* Developer's Manual, Volume 3: System Prgramming Guide,
	196	* revision #12 in Table B-1: MSRs in the Pentium 4 and
	197	* Intel Xeon Processors, on page B-4 and B-5.
	198	*/
199785ea MCO	199	fsb_code = (msr_lo >> 16) & 0x7;
	200	switch (fsb_code) {
	201	case 0:
1da177e4	202	fsb = 100 * 1000;
199785ea MCO	203	break;
	204	case 1:
	205	fsb = 13333 * 10;
	206	break;
	207	case 2:
	208	fsb = 200 * 1000;
	209	break;
1da177e4 LT	210	}
	211
	212	if (!fsb)
bbfebd66 DJ	213	printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
bbfebd66 DJ	214	"Please send an e-mail to <linux@brodo.de>\n");
1da177e4 LT	215
1da177e4 LT	216	/* Multiplier. */
ed9cbcd4	217	mult = msr_lo >> 24;
1da177e4	218
2d06d8c4	219	pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
bbfebd66	220	fsb, mult, (fsb * mult));
1da177e4	221
bbfebd66 DJ	222	ret = (fsb * mult);
bbfebd66 DJ	223	return ret;
1da177e4 LT	224	}
1da177e4 LT	225
32ee8c3e	226
394122ab	227	/* Warning: may get called from smp_call_function_single. */
1cce76c2	228	unsigned int speedstep_get_frequency(enum speedstep_processor processor)
1da177e4 LT	229	{
1da177e4 LT	230	switch (processor) {
bbfebd66	231	case SPEEDSTEP_CPU_PCORE:
4e74663c	232	return pentium_core_get_frequency();
bbfebd66	233	case SPEEDSTEP_CPU_PM:
1da177e4	234	return pentiumM_get_frequency();
bbfebd66 DJ	235	case SPEEDSTEP_CPU_P4D:
bbfebd66 DJ	236	case SPEEDSTEP_CPU_P4M:
1da177e4	237	return pentium4_get_frequency();
bbfebd66 DJ	238	case SPEEDSTEP_CPU_PIII_T:
	239	case SPEEDSTEP_CPU_PIII_C:
	240	case SPEEDSTEP_CPU_PIII_C_EARLY:
1da177e4 LT	241	return pentium3_get_frequency(processor);
	242	default:
	243	return 0;
	244	};
	245	return 0;
	246	}
bbfebd66	247	EXPORT_SYMBOL_GPL(speedstep_get_frequency);
1da177e4 LT	248
	249
	250	/*********************************************************************
	251	* DETECT SPEEDSTEP-CAPABLE PROCESSOR *
	252	*********************************************************************/
	253
fa8031ae	254	/* Keep in sync with the x86_cpu_id tables in the different modules */
bbfebd66	255	unsigned int speedstep_detect_processor(void)
1da177e4	256	{
92cb7612	257	struct cpuinfo_x86 *c = &cpu_data(0);
32ee8c3e	258	u32 ebx, msr_lo, msr_hi;
1da177e4	259
2d06d8c4	260	pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model);
1da177e4	261
32ee8c3e	262	if ((c->x86_vendor != X86_VENDOR_INTEL) \|\|
1da177e4 LT	263	((c->x86 != 6) && (c->x86 != 0xF)))
	264	return 0;
	265
	266	if (c->x86 == 0xF) {
	267	/* Intel Mobile Pentium 4-M
	268	* or Intel Mobile Pentium 4 with 533 MHz FSB */
	269	if (c->x86_model != 2)
	270	return 0;
	271
	272	ebx = cpuid_ebx(0x00000001);
	273	ebx &= 0x000000FF;
	274
2d06d8c4	275	pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
1da177e4 LT	276
1da177e4 LT	277	switch (c->x86_mask) {
32ee8c3e	278	case 4:
1da177e4	279	/*
32ee8c3e	280	* B-stepping [M-P4-M]
1da177e4 LT	281	* sample has ebx = 0x0f, production has 0x0e.
	282	*/
	283	if ((ebx == 0x0e) \|\| (ebx == 0x0f))
bbfebd66	284	return SPEEDSTEP_CPU_P4M;
1da177e4	285	break;
32ee8c3e	286	case 7:
1da177e4 LT	287	/*
	288	* C-stepping [M-P4-M]
	289	* needs to have ebx=0x0e, else it's a celeron:
	290	* cf. 25130917.pdf / page 7, footnote 5 even
	291	* though 25072120.pdf / page 7 doesn't say
	292	* samples are only of B-stepping...
	293	*/
	294	if (ebx == 0x0e)
bbfebd66	295	return SPEEDSTEP_CPU_P4M;
1da177e4 LT	296	break;
	297	case 9:
	298	/*
	299	* D-stepping [M-P4-M or M-P4/533]
	300	*
	301	* this is totally strange: CPUID 0x0F29 is
	302	* used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
	303	* The latter need to be sorted out as they don't
	304	* support speedstep.
	305	* Celerons with CPUID 0x0F29 may have either
	306	* ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
	307	* specific.
	308	* M-P4-Ms may have either ebx=0xe or 0xf [see above]
	309	* M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
	310	* also, M-P4M HTs have ebx=0x8, too
bbfebd66 DJ	311	* For now, they are distinguished by the model_id
bbfebd66 DJ	312	* string
1da177e4	313	*/
bbfebd66 DJ	314	if ((ebx == 0x0e) \|\|
	315	(strstr(c->x86_model_id,
	316	"Mobile Intel(R) Pentium(R) 4") != NULL))
	317	return SPEEDSTEP_CPU_P4M;
1da177e4 LT	318	break;
	319	default:
	320	break;
	321	}
	322	return 0;
	323	}
	324
	325	switch (c->x86_model) {
	326	case 0x0B: /* Intel PIII [Tualatin] */
bbfebd66 DJ	327	/* cpuid_ebx(1) is 0x04 for desktop PIII,
bbfebd66 DJ	328	* 0x06 for mobile PIII-M */
1da177e4	329	ebx = cpuid_ebx(0x00000001);
2d06d8c4	330	pr_debug("ebx is %x\n", ebx);
1da177e4 LT	331
	332	ebx &= 0x000000FF;
	333
	334	if (ebx != 0x06)
	335	return 0;
	336
	337	/* So far all PIII-M processors support SpeedStep. See
32ee8c3e	338	* Intel's 24540640.pdf of June 2003
1da177e4	339	*/
bbfebd66	340	return SPEEDSTEP_CPU_PIII_T;
1da177e4 LT	341
	342	case 0x08: /* Intel PIII [Coppermine] */
	343
	344	/* all mobile PIII Coppermines have FSB 100 MHz
	345	* ==> sort out a few desktop PIIIs. */
	346	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
2d06d8c4	347	pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
bbfebd66	348	msr_lo, msr_hi);
1da177e4 LT	349	msr_lo &= 0x00c0000;
	350	if (msr_lo != 0x0080000)
	351	return 0;
	352
	353	/*
	354	* If the processor is a mobile version,
	355	* platform ID has bit 50 set
	356	* it has SpeedStep technology if either
	357	* bit 56 or 57 is set
	358	*/
	359	rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
2d06d8c4	360	pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
bbfebd66 DJ	361	msr_lo, msr_hi);
	362	if ((msr_hi & (1<<18)) &&
	363	(relaxed_check ? 1 : (msr_hi & (3<<24)))) {
1da177e4	364	if (c->x86_mask == 0x01) {
2d06d8c4	365	pr_debug("early PIII version\n");
bbfebd66	366	return SPEEDSTEP_CPU_PIII_C_EARLY;
1da177e4	367	} else
bbfebd66	368	return SPEEDSTEP_CPU_PIII_C;
1da177e4 LT	369	}
	370
	371	default:
	372	return 0;
	373	}
	374	}
	375	EXPORT_SYMBOL_GPL(speedstep_detect_processor);
	376
	377
	378	/*********************************************************************
	379	* DETECT SPEEDSTEP SPEEDS *
	380	*********************************************************************/
	381
1cce76c2	382	unsigned int speedstep_get_freqs(enum speedstep_processor processor,
1da177e4 LT	383	unsigned int *low_speed,
1da177e4 LT	384	unsigned int *high_speed,
1a10760c	385	unsigned int *transition_latency,
1da177e4 LT	386	void (*set_state) (unsigned int state))
	387	{
	388	unsigned int prev_speed;
	389	unsigned int ret = 0;
	390	unsigned long flags;
72e624de	391	ktime_t tv1, tv2;
1da177e4 LT	392
	393	if ((!processor) \|\| (!low_speed) \|\| (!high_speed) \|\| (!set_state))
	394	return -EINVAL;
	395
2d06d8c4	396	pr_debug("trying to determine both speeds\n");
1da177e4 LT	397
1da177e4 LT	398	/* get current speed */
bbfebd66	399	prev_speed = speedstep_get_frequency(processor);
1da177e4 LT	400	if (!prev_speed)
	401	return -EIO;
	402
2d06d8c4	403	pr_debug("previous speed is %u\n", prev_speed);
1a10760c	404
d4d4eda2	405	preempt_disable();
1da177e4 LT	406	local_irq_save(flags);
	407
	408	/* switch to low state */
	409	set_state(SPEEDSTEP_LOW);
bbfebd66	410	*low_speed = speedstep_get_frequency(processor);
1da177e4 LT	411	if (!*low_speed) {
	412	ret = -EIO;
	413	goto out;
	414	}
	415
2d06d8c4	416	pr_debug("low speed is %u\n", *low_speed);
1da177e4	417
1a10760c MD	418	/* start latency measurement */
1a10760c MD	419	if (transition_latency)
72e624de	420	tv1 = ktime_get();
1a10760c	421
1da177e4 LT	422	/* switch to high state */
1da177e4 LT	423	set_state(SPEEDSTEP_HIGH);
1a10760c MD	424
	425	/* end latency measurement */
	426	if (transition_latency)
72e624de	427	tv2 = ktime_get();
1a10760c	428
bbfebd66	429	*high_speed = speedstep_get_frequency(processor);
1da177e4 LT	430	if (!*high_speed) {
	431	ret = -EIO;
	432	goto out;
	433	}
	434
2d06d8c4	435	pr_debug("high speed is %u\n", *high_speed);
1da177e4 LT	436
	437	if (low_speed == high_speed) {
	438	ret = -ENODEV;
	439	goto out;
	440	}
	441
	442	/* switch to previous state, if necessary */
	443	if (*high_speed != prev_speed)
	444	set_state(SPEEDSTEP_LOW);
	445
1a10760c	446	if (transition_latency) {
72e624de	447	*transition_latency = ktime_to_us(ktime_sub(tv2, tv1));
2d06d8c4	448	pr_debug("transition latency is %u uSec\n", *transition_latency);
1a10760c MD	449
	450	/* convert uSec to nSec and add 20% for safety reasons */
	451	transition_latency = 1200;
	452
	453	/* check if the latency measurement is too high or too low
	454	* and set it to a safe value (500uSec) in that case
	455	*/
bbfebd66 DJ	456	if (*transition_latency > 10000000 \|\|
bbfebd66 DJ	457	*transition_latency < 50000) {
1c5864e2	458	pr_warn("frequency transition measured seems out of range (%u nSec), falling back to a safe one of %u nSec\n",
b49c22a6	459	*transition_latency, 500000);
1a10760c MD	460	*transition_latency = 500000;
	461	}
	462	}
	463
32ee8c3e	464	out:
1da177e4	465	local_irq_restore(flags);
d4d4eda2 MP	466	preempt_enable();
d4d4eda2 MP	467
bbfebd66	468	return ret;
1da177e4 LT	469	}
	470	EXPORT_SYMBOL_GPL(speedstep_get_freqs);
	471
	472	#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
	473	module_param(relaxed_check, int, 0444);
bbfebd66 DJ	474	MODULE_PARM_DESC(relaxed_check,
bbfebd66 DJ	475	"Don't do all checks for speedstep capability.");
1da177e4 LT	476	#endif
1da177e4 LT	477
bbfebd66 DJ	478	MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
	479	MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
	480	MODULE_LICENSE("GPL");