[mirror_ubuntu-bionic-kernel.git] / drivers / cpufreq / tegra-cpufreq.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *	Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>

static struct cpufreq_frequency_table freq_table[] = {
	{ .frequency = 216000 },
	{ .frequency = 312000 },
	{ .frequency = 456000 },
	{ .frequency = 608000 },
	{ .frequency = 760000 },
	{ .frequency = 816000 },
	{ .frequency = 912000 },
	{ .frequency = 1000000 },
	{ .frequency = CPUFREQ_TABLE_END },
};

#define NUM_CPUS	2

static struct clk *cpu_clk;
static struct clk *pll_x_clk;
static struct clk *pll_p_clk;
static struct clk *emc_clk;
static bool pll_x_prepared;

static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
					   unsigned int index)
{
	unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;

	/*
	 * Don't switch to intermediate freq if:
	 * - we are already at it, i.e. policy->cur == ifreq
	 * - index corresponds to ifreq
	 */
	if ((freq_table[index].frequency == ifreq) || (policy->cur == ifreq))
		return 0;

	return ifreq;
}

static int tegra_target_intermediate(struct cpufreq_policy *policy,
				     unsigned int index)
{
	int ret;

	/*
	 * Take an extra reference to the main pll so it doesn't turn
	 * off when we move the cpu off of it as enabling it again while we
	 * switch to it from tegra_target() would take additional time.
	 *
	 * When target-freq is equal to intermediate freq we don't need to
	 * switch to an intermediate freq and so this routine isn't called.
	 * Also, we wouldn't be using pll_x anymore and must not take extra
	 * reference to it, as it can be disabled now to save some power.
	 */
	clk_prepare_enable(pll_x_clk);

	ret = clk_set_parent(cpu_clk, pll_p_clk);
	if (ret)
		clk_disable_unprepare(pll_x_clk);
	else
		pll_x_prepared = true;

	return ret;
}

static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
{
	unsigned long rate = freq_table[index].frequency;
	unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
	int ret = 0;

	/*
	 * Vote on memory bus frequency based on cpu frequency
	 * This sets the minimum frequency, display or avp may request higher
	 */
	if (rate >= 816000)
		clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	else if (rate >= 456000)
		clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	else
		clk_set_rate(emc_clk, 100000000);  /* emc 50Mhz */

	/*
	 * target freq == pll_p, don't need to take extra reference to pll_x_clk
	 * as it isn't used anymore.
	 */
	if (rate == ifreq)
		return clk_set_parent(cpu_clk, pll_p_clk);

	ret = clk_set_rate(pll_x_clk, rate * 1000);
	/* Restore to earlier frequency on error, i.e. pll_x */
	if (ret)
		pr_err("Failed to change pll_x to %lu\n", rate);

	ret = clk_set_parent(cpu_clk, pll_x_clk);
	/* This shouldn't fail while changing or restoring */
	WARN_ON(ret);

	/*
	 * Drop count to pll_x clock only if we switched to intermediate freq
	 * earlier while transitioning to a target frequency.
	 */
	if (pll_x_prepared) {
		clk_disable_unprepare(pll_x_clk);
		pll_x_prepared = false;
	}

	return ret;
}

static int tegra_cpu_init(struct cpufreq_policy *policy)
{
	int ret;

	if (policy->cpu >= NUM_CPUS)
		return -EINVAL;

	clk_prepare_enable(emc_clk);
	clk_prepare_enable(cpu_clk);

	/* FIXME: what's the actual transition time? */
	ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
	if (ret) {
		clk_disable_unprepare(cpu_clk);
		clk_disable_unprepare(emc_clk);
		return ret;
	}

	policy->clk = cpu_clk;
	policy->suspend_freq = freq_table[0].frequency;
	return 0;
}

static int tegra_cpu_exit(struct cpufreq_policy *policy)
{
	clk_disable_unprepare(cpu_clk);
	clk_disable_unprepare(emc_clk);
	return 0;
}

static struct cpufreq_driver tegra_cpufreq_driver = {
	.flags			= CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify			= cpufreq_generic_frequency_table_verify,
	.get_intermediate	= tegra_get_intermediate,
	.target_intermediate	= tegra_target_intermediate,
	.target_index		= tegra_target,
	.get			= cpufreq_generic_get,
	.init			= tegra_cpu_init,
	.exit			= tegra_cpu_exit,
	.name			= "tegra",
	.attr			= cpufreq_generic_attr,
#ifdef CONFIG_PM
	.suspend		= cpufreq_generic_suspend,
#endif
};

static int __init tegra_cpufreq_init(void)
{
	cpu_clk = clk_get_sys(NULL, "cclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	pll_x_clk = clk_get_sys(NULL, "pll_x");
	if (IS_ERR(pll_x_clk))
		return PTR_ERR(pll_x_clk);

	pll_p_clk = clk_get_sys(NULL, "pll_p");
	if (IS_ERR(pll_p_clk))
		return PTR_ERR(pll_p_clk);

	emc_clk = clk_get_sys("cpu", "emc");
	if (IS_ERR(emc_clk)) {
		clk_put(cpu_clk);
		return PTR_ERR(emc_clk);
	}

	return cpufreq_register_driver(&tegra_cpufreq_driver);
}

static void __exit tegra_cpufreq_exit(void)
{
        cpufreq_unregister_driver(&tegra_cpufreq_driver);
	clk_put(emc_clk);
	clk_put(cpu_clk);
}


MODULE_AUTHOR("Colin Cross <ccross@android.com>");
MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
MODULE_LICENSE("GPL");
module_init(tegra_cpufreq_init);
module_exit(tegra_cpufreq_exit);
Commit	Line	Data
7056d423	1	/*
7056d423 CC	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* Author:
	5	* Colin Cross <ccross@google.com>
	6	* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/types.h>
	22	#include <linux/sched.h>
	23	#include <linux/cpufreq.h>
	24	#include <linux/delay.h>
	25	#include <linux/init.h>
	26	#include <linux/err.h>
	27	#include <linux/clk.h>
	28	#include <linux/io.h>
	29
7056d423	30	static struct cpufreq_frequency_table freq_table[] = {
5d69030d VK	31	{ .frequency = 216000 },
	32	{ .frequency = 312000 },
	33	{ .frequency = 456000 },
	34	{ .frequency = 608000 },
	35	{ .frequency = 760000 },
	36	{ .frequency = 816000 },
	37	{ .frequency = 912000 },
	38	{ .frequency = 1000000 },
	39	{ .frequency = CPUFREQ_TABLE_END },
7056d423 CC	40	};
	41
	42	#define NUM_CPUS 2
	43
	44	static struct clk *cpu_clk;
ce32ddaa SW	45	static struct clk *pll_x_clk;
ce32ddaa SW	46	static struct clk *pll_p_clk;
7a281284	47	static struct clk *emc_clk;
00917ddc	48	static bool pll_x_prepared;
7056d423	49
00917ddc VK	50	static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
	51	unsigned int index)
	52	{
	53	unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
	54
	55	/*
	56	* Don't switch to intermediate freq if:
	57	* - we are already at it, i.e. policy->cur == ifreq
	58	* - index corresponds to ifreq
	59	*/
	60	if ((freq_table[index].frequency == ifreq) \|\| (policy->cur == ifreq))
	61	return 0;
	62
	63	return ifreq;
	64	}
	65
	66	static int tegra_target_intermediate(struct cpufreq_policy *policy,
	67	unsigned int index)
ce32ddaa SW	68	{
	69	int ret;
	70
	71	/*
	72	* Take an extra reference to the main pll so it doesn't turn
00917ddc	73	* off when we move the cpu off of it as enabling it again while we
40cc5490 VK	74	* switch to it from tegra_target() would take additional time.
	75	*
	76	* When target-freq is equal to intermediate freq we don't need to
	77	* switch to an intermediate freq and so this routine isn't called.
	78	* Also, we wouldn't be using pll_x anymore and must not take extra
	79	* reference to it, as it can be disabled now to save some power.
ce32ddaa SW	80	*/
	81	clk_prepare_enable(pll_x_clk);
	82
	83	ret = clk_set_parent(cpu_clk, pll_p_clk);
00917ddc VK	84	if (ret)
	85	clk_disable_unprepare(pll_x_clk);
	86	else
	87	pll_x_prepared = true;
ce32ddaa	88
ce32ddaa SW	89	return ret;
	90	}
	91
e7b453d3	92	static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
7056d423	93	{
e7b453d3	94	unsigned long rate = freq_table[index].frequency;
00917ddc	95	unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
7056d423	96	int ret = 0;
7056d423	97
7a281284 CC	98	/*
	99	* Vote on memory bus frequency based on cpu frequency
	100	* This sets the minimum frequency, display or avp may request higher
	101	*/
	102	if (rate >= 816000)
	103	clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	104	else if (rate >= 456000)
	105	clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	106	else
	107	clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
	108
00917ddc VK	109	/*
	110	* target freq == pll_p, don't need to take extra reference to pll_x_clk
	111	* as it isn't used anymore.
	112	*/
	113	if (rate == ifreq)
	114	return clk_set_parent(cpu_clk, pll_p_clk);
	115
	116	ret = clk_set_rate(pll_x_clk, rate * 1000);
	117	/* Restore to earlier frequency on error, i.e. pll_x */
d4019f0a	118	if (ret)
00917ddc VK	119	pr_err("Failed to change pll_x to %lu\n", rate);
	120
	121	ret = clk_set_parent(cpu_clk, pll_x_clk);
	122	/* This shouldn't fail while changing or restoring */
	123	WARN_ON(ret);
	124
	125	/*
	126	* Drop count to pll_x clock only if we switched to intermediate freq
	127	* earlier while transitioning to a target frequency.
	128	*/
	129	if (pll_x_prepared) {
	130	clk_disable_unprepare(pll_x_clk);
	131	pll_x_prepared = false;
	132	}
7056d423	133
f56cc99e	134	return ret;
7056d423 CC	135	}
7056d423 CC	136
7056d423 CC	137	static int tegra_cpu_init(struct cpufreq_policy *policy)
7056d423 CC	138	{
99d428cf VK	139	int ret;
99d428cf VK	140
7056d423 CC	141	if (policy->cpu >= NUM_CPUS)
	142	return -EINVAL;
	143
6a5278d0 PG	144	clk_prepare_enable(emc_clk);
6a5278d0 PG	145	clk_prepare_enable(cpu_clk);
89a5fb84	146
7056d423	147	/* FIXME: what's the actual transition time? */
99d428cf VK	148	ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
	149	if (ret) {
	150	clk_disable_unprepare(cpu_clk);
	151	clk_disable_unprepare(emc_clk);
	152	return ret;
	153	}
7056d423	154
652ed95d	155	policy->clk = cpu_clk;
d351cb31	156	policy->suspend_freq = freq_table[0].frequency;
7056d423 CC	157	return 0;
	158	}
	159
	160	static int tegra_cpu_exit(struct cpufreq_policy *policy)
	161	{
99d428cf	162	clk_disable_unprepare(cpu_clk);
6a5278d0	163	clk_disable_unprepare(emc_clk);
7056d423 CC	164	return 0;
	165	}
	166
7056d423	167	static struct cpufreq_driver tegra_cpufreq_driver = {
00917ddc VK	168	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	169	.verify = cpufreq_generic_frequency_table_verify,
	170	.get_intermediate = tegra_get_intermediate,
	171	.target_intermediate = tegra_target_intermediate,
	172	.target_index = tegra_target,
	173	.get = cpufreq_generic_get,
	174	.init = tegra_cpu_init,
	175	.exit = tegra_cpu_exit,
	176	.name = "tegra",
	177	.attr = cpufreq_generic_attr,
d351cb31	178	#ifdef CONFIG_PM
00917ddc	179	.suspend = cpufreq_generic_suspend,
d351cb31	180	#endif
7056d423 CC	181	};
	182
	183	static int __init tegra_cpufreq_init(void)
	184	{
b192b910	185	cpu_clk = clk_get_sys(NULL, "cclk");
c26cefd0 RZ	186	if (IS_ERR(cpu_clk))
	187	return PTR_ERR(cpu_clk);
	188
	189	pll_x_clk = clk_get_sys(NULL, "pll_x");
	190	if (IS_ERR(pll_x_clk))
	191	return PTR_ERR(pll_x_clk);
	192
b192b910	193	pll_p_clk = clk_get_sys(NULL, "pll_p");
c26cefd0 RZ	194	if (IS_ERR(pll_p_clk))
	195	return PTR_ERR(pll_p_clk);
	196
	197	emc_clk = clk_get_sys("cpu", "emc");
	198	if (IS_ERR(emc_clk)) {
	199	clk_put(cpu_clk);
	200	return PTR_ERR(emc_clk);
	201	}
	202
7056d423 CC	203	return cpufreq_register_driver(&tegra_cpufreq_driver);
	204	}
	205
	206	static void __exit tegra_cpufreq_exit(void)
	207	{
	208	cpufreq_unregister_driver(&tegra_cpufreq_driver);
c26cefd0 RZ	209	clk_put(emc_clk);
c26cefd0 RZ	210	clk_put(cpu_clk);
7056d423 CC	211	}
	212
	213
	214	MODULE_AUTHOR("Colin Cross <ccross@android.com>");
	215	MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
	216	MODULE_LICENSE("GPL");
	217	module_init(tegra_cpufreq_init);
	218	module_exit(tegra_cpufreq_exit);