[mirror_ubuntu-jammy-kernel.git] / drivers / cpufreq / tegra186-cpufreq.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved
 */

#include <linux/cpufreq.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>

#include <soc/tegra/bpmp.h>
#include <soc/tegra/bpmp-abi.h>

#define TEGRA186_NUM_CLUSTERS		2
#define EDVD_OFFSET_A57(core)		((SZ_64K * 6) + (0x20 + (core) * 0x4))
#define EDVD_OFFSET_DENVER(core)	((SZ_64K * 7) + (0x20 + (core) * 0x4))
#define EDVD_CORE_VOLT_FREQ_F_SHIFT	0
#define EDVD_CORE_VOLT_FREQ_F_MASK	0xffff
#define EDVD_CORE_VOLT_FREQ_V_SHIFT	16

struct tegra186_cpufreq_cpu {
	unsigned int bpmp_cluster_id;
	unsigned int edvd_offset;
};

static const struct tegra186_cpufreq_cpu tegra186_cpus[] = {
	/* CPU0 - A57 Cluster */
	{
		.bpmp_cluster_id = 1,
		.edvd_offset = EDVD_OFFSET_A57(0)
	},
	/* CPU1 - Denver Cluster */
	{
		.bpmp_cluster_id = 0,
		.edvd_offset = EDVD_OFFSET_DENVER(0)
	},
	/* CPU2 - Denver Cluster */
	{
		.bpmp_cluster_id = 0,
		.edvd_offset = EDVD_OFFSET_DENVER(1)
	},
	/* CPU3 - A57 Cluster */
	{
		.bpmp_cluster_id = 1,
		.edvd_offset = EDVD_OFFSET_A57(1)
	},
	/* CPU4 - A57 Cluster */
	{
		.bpmp_cluster_id = 1,
		.edvd_offset = EDVD_OFFSET_A57(2)
	},
	/* CPU5 - A57 Cluster */
	{
		.bpmp_cluster_id = 1,
		.edvd_offset = EDVD_OFFSET_A57(3)
	},
};

struct tegra186_cpufreq_cluster {
	struct cpufreq_frequency_table *table;
	u32 ref_clk_khz;
	u32 div;
};

struct tegra186_cpufreq_data {
	void __iomem *regs;
	struct tegra186_cpufreq_cluster *clusters;
	const struct tegra186_cpufreq_cpu *cpus;
};

static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
{
	struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
	unsigned int cluster = data->cpus[policy->cpu].bpmp_cluster_id;

	policy->freq_table = data->clusters[cluster].table;
	policy->cpuinfo.transition_latency = 300 * 1000;
	policy->driver_data = NULL;

	return 0;
}

static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
				       unsigned int index)
{
	struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
	struct cpufreq_frequency_table *tbl = policy->freq_table + index;
	unsigned int edvd_offset = data->cpus[policy->cpu].edvd_offset;
	u32 edvd_val = tbl->driver_data;

	writel(edvd_val, data->regs + edvd_offset);

	return 0;
}

static unsigned int tegra186_cpufreq_get(unsigned int cpu)
{
	struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
	struct tegra186_cpufreq_cluster *cluster;
	struct cpufreq_policy *policy;
	unsigned int edvd_offset, cluster_id;
	u32 ndiv;

	policy = cpufreq_cpu_get(cpu);
	if (!policy)
		return 0;

	edvd_offset = data->cpus[policy->cpu].edvd_offset;
	ndiv = readl(data->regs + edvd_offset) & EDVD_CORE_VOLT_FREQ_F_MASK;
	cluster_id = data->cpus[policy->cpu].bpmp_cluster_id;
	cluster = &data->clusters[cluster_id];
	cpufreq_cpu_put(policy);

	return (cluster->ref_clk_khz * ndiv) / cluster->div;
}

static struct cpufreq_driver tegra186_cpufreq_driver = {
	.name = "tegra186",
	.flags = CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
			CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.get = tegra186_cpufreq_get,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = tegra186_cpufreq_set_target,
	.init = tegra186_cpufreq_init,
	.attr = cpufreq_generic_attr,
};

static struct cpufreq_frequency_table *init_vhint_table(
	struct platform_device *pdev, struct tegra_bpmp *bpmp,
	struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id)
{
	struct cpufreq_frequency_table *table;
	struct mrq_cpu_vhint_request req;
	struct tegra_bpmp_message msg;
	struct cpu_vhint_data *data;
	int err, i, j, num_rates = 0;
	dma_addr_t phys;
	void *virt;

	virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys,
				  GFP_KERNEL);
	if (!virt)
		return ERR_PTR(-ENOMEM);

	data = (struct cpu_vhint_data *)virt;

	memset(&req, 0, sizeof(req));
	req.addr = phys;
	req.cluster_id = cluster_id;

	memset(&msg, 0, sizeof(msg));
	msg.mrq = MRQ_CPU_VHINT;
	msg.tx.data = &req;
	msg.tx.size = sizeof(req);

	err = tegra_bpmp_transfer(bpmp, &msg);
	if (err) {
		table = ERR_PTR(err);
		goto free;
	}

	for (i = data->vfloor; i <= data->vceil; i++) {
		u16 ndiv = data->ndiv[i];

		if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
			continue;

		/* Only store lowest voltage index for each rate */
		if (i > 0 && ndiv == data->ndiv[i - 1])
			continue;

		num_rates++;
	}

	table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table),
			     GFP_KERNEL);
	if (!table) {
		table = ERR_PTR(-ENOMEM);
		goto free;
	}

	cluster->ref_clk_khz = data->ref_clk_hz / 1000;
	cluster->div = data->pdiv * data->mdiv;

	for (i = data->vfloor, j = 0; i <= data->vceil; i++) {
		struct cpufreq_frequency_table *point;
		u16 ndiv = data->ndiv[i];
		u32 edvd_val = 0;

		if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
			continue;

		/* Only store lowest voltage index for each rate */
		if (i > 0 && ndiv == data->ndiv[i - 1])
			continue;

		edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT;
		edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT;

		point = &table[j++];
		point->driver_data = edvd_val;
		point->frequency = (cluster->ref_clk_khz * ndiv) / cluster->div;
	}

	table[j].frequency = CPUFREQ_TABLE_END;

free:
	dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys);

	return table;
}

static int tegra186_cpufreq_probe(struct platform_device *pdev)
{
	struct tegra186_cpufreq_data *data;
	struct tegra_bpmp *bpmp;
	unsigned int i = 0, err;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->clusters = devm_kcalloc(&pdev->dev, TEGRA186_NUM_CLUSTERS,
				      sizeof(*data->clusters), GFP_KERNEL);
	if (!data->clusters)
		return -ENOMEM;

	data->cpus = tegra186_cpus;

	bpmp = tegra_bpmp_get(&pdev->dev);
	if (IS_ERR(bpmp))
		return PTR_ERR(bpmp);

	data->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(data->regs)) {
		err = PTR_ERR(data->regs);
		goto put_bpmp;
	}

	for (i = 0; i < TEGRA186_NUM_CLUSTERS; i++) {
		struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];

		cluster->table = init_vhint_table(pdev, bpmp, cluster, i);
		if (IS_ERR(cluster->table)) {
			err = PTR_ERR(cluster->table);
			goto put_bpmp;
		}
	}

	tegra186_cpufreq_driver.driver_data = data;

	err = cpufreq_register_driver(&tegra186_cpufreq_driver);

put_bpmp:
	tegra_bpmp_put(bpmp);

	return err;
}

static int tegra186_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&tegra186_cpufreq_driver);

	return 0;
}

static const struct of_device_id tegra186_cpufreq_of_match[] = {
	{ .compatible = "nvidia,tegra186-ccplex-cluster", },
	{ }
};
MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match);

static struct platform_driver tegra186_cpufreq_platform_driver = {
	.driver = {
		.name = "tegra186-cpufreq",
		.of_match_table = tegra186_cpufreq_of_match,
	},
	.probe = tegra186_cpufreq_probe,
	.remove = tegra186_cpufreq_remove,
};
module_platform_driver(tegra186_cpufreq_platform_driver);

MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2025cf9e	1	// SPDX-License-Identifier: GPL-2.0-only
939dc6f5 MP	2	/*
939dc6f5 MP	3	* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved
939dc6f5 MP	4	*/
	5
	6	#include <linux/cpufreq.h>
	7	#include <linux/dma-mapping.h>
	8	#include <linux/module.h>
	9	#include <linux/of.h>
	10	#include <linux/platform_device.h>
	11
	12	#include <soc/tegra/bpmp.h>
	13	#include <soc/tegra/bpmp-abi.h>
	14
cfef4bca	15	#define TEGRA186_NUM_CLUSTERS 2
b7b4e785 JH	16	#define EDVD_OFFSET_A57(core) ((SZ_64K * 6) + (0x20 + (core) * 0x4))
	17	#define EDVD_OFFSET_DENVER(core) ((SZ_64K * 7) + (0x20 + (core) * 0x4))
	18	#define EDVD_CORE_VOLT_FREQ_F_SHIFT 0
	19	#define EDVD_CORE_VOLT_FREQ_F_MASK 0xffff
	20	#define EDVD_CORE_VOLT_FREQ_V_SHIFT 16
	21
	22	struct tegra186_cpufreq_cpu {
cfef4bca	23	unsigned int bpmp_cluster_id;
b7b4e785 JH	24	unsigned int edvd_offset;
	25	};
	26
	27	static const struct tegra186_cpufreq_cpu tegra186_cpus[] = {
	28	/* CPU0 - A57 Cluster */
	29	{
cfef4bca	30	.bpmp_cluster_id = 1,
b7b4e785 JH	31	.edvd_offset = EDVD_OFFSET_A57(0)
	32	},
	33	/* CPU1 - Denver Cluster */
	34	{
cfef4bca	35	.bpmp_cluster_id = 0,
b7b4e785 JH	36	.edvd_offset = EDVD_OFFSET_DENVER(0)
	37	},
	38	/* CPU2 - Denver Cluster */
	39	{
cfef4bca	40	.bpmp_cluster_id = 0,
b7b4e785 JH	41	.edvd_offset = EDVD_OFFSET_DENVER(1)
	42	},
	43	/* CPU3 - A57 Cluster */
	44	{
cfef4bca	45	.bpmp_cluster_id = 1,
b7b4e785 JH	46	.edvd_offset = EDVD_OFFSET_A57(1)
	47	},
	48	/* CPU4 - A57 Cluster */
	49	{
cfef4bca	50	.bpmp_cluster_id = 1,
b7b4e785 JH	51	.edvd_offset = EDVD_OFFSET_A57(2)
	52	},
	53	/* CPU5 - A57 Cluster */
	54	{
939dc6f5	55	.bpmp_cluster_id = 1,
cfef4bca	56	.edvd_offset = EDVD_OFFSET_A57(3)
939dc6f5 MP	57	},
	58	};
	59
	60	struct tegra186_cpufreq_cluster {
939dc6f5	61	struct cpufreq_frequency_table *table;
e010d1d2 JH	62	u32 ref_clk_khz;
e010d1d2 JH	63	u32 div;
939dc6f5 MP	64	};
	65
	66	struct tegra186_cpufreq_data {
	67	void __iomem *regs;
939dc6f5	68	struct tegra186_cpufreq_cluster *clusters;
b7b4e785	69	const struct tegra186_cpufreq_cpu *cpus;
939dc6f5 MP	70	};
	71
	72	static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
	73	{
	74	struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
cfef4bca	75	unsigned int cluster = data->cpus[policy->cpu].bpmp_cluster_id;
939dc6f5	76
cfef4bca	77	policy->freq_table = data->clusters[cluster].table;
939dc6f5	78	policy->cpuinfo.transition_latency = 300 * 1000;
b7b4e785	79	policy->driver_data = NULL;
939dc6f5 MP	80
	81	return 0;
	82	}
	83
	84	static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
	85	unsigned int index)
	86	{
b7b4e785	87	struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
939dc6f5	88	struct cpufreq_frequency_table *tbl = policy->freq_table + index;
b7b4e785	89	unsigned int edvd_offset = data->cpus[policy->cpu].edvd_offset;
939dc6f5 MP	90	u32 edvd_val = tbl->driver_data;
939dc6f5 MP	91
b7b4e785	92	writel(edvd_val, data->regs + edvd_offset);
939dc6f5 MP	93
	94	return 0;
	95	}
	96
b89c01c9 JH	97	static unsigned int tegra186_cpufreq_get(unsigned int cpu)
b89c01c9 JH	98	{
e010d1d2	99	struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
cfef4bca	100	struct tegra186_cpufreq_cluster *cluster;
b89c01c9	101	struct cpufreq_policy *policy;
cfef4bca	102	unsigned int edvd_offset, cluster_id;
b89c01c9 JH	103	u32 ndiv;
	104
	105	policy = cpufreq_cpu_get(cpu);
	106	if (!policy)
	107	return 0;
	108
b7b4e785 JH	109	edvd_offset = data->cpus[policy->cpu].edvd_offset;
b7b4e785 JH	110	ndiv = readl(data->regs + edvd_offset) & EDVD_CORE_VOLT_FREQ_F_MASK;
cfef4bca JH	111	cluster_id = data->cpus[policy->cpu].bpmp_cluster_id;
cfef4bca JH	112	cluster = &data->clusters[cluster_id];
b89c01c9 JH	113	cpufreq_cpu_put(policy);
b89c01c9 JH	114
cfef4bca	115	return (cluster->ref_clk_khz * ndiv) / cluster->div;
b89c01c9 JH	116	}
b89c01c9 JH	117
939dc6f5 MP	118	static struct cpufreq_driver tegra186_cpufreq_driver = {
939dc6f5 MP	119	.name = "tegra186",
5ae4a4b4	120	.flags = CPUFREQ_HAVE_GOVERNOR_PER_POLICY \|
6cc3d0e9	121	CPUFREQ_NEED_INITIAL_FREQ_CHECK,
b89c01c9	122	.get = tegra186_cpufreq_get,
939dc6f5 MP	123	.verify = cpufreq_generic_frequency_table_verify,
	124	.target_index = tegra186_cpufreq_set_target,
	125	.init = tegra186_cpufreq_init,
	126	.attr = cpufreq_generic_attr,
	127	};
	128
	129	static struct cpufreq_frequency_table *init_vhint_table(
	130	struct platform_device pdev, struct tegra_bpmp bpmp,
cfef4bca	131	struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id)
939dc6f5 MP	132	{
	133	struct cpufreq_frequency_table *table;
	134	struct mrq_cpu_vhint_request req;
	135	struct tegra_bpmp_message msg;
	136	struct cpu_vhint_data *data;
	137	int err, i, j, num_rates = 0;
	138	dma_addr_t phys;
	139	void *virt;
	140
	141	virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys,
a3ade38d	142	GFP_KERNEL);
939dc6f5 MP	143	if (!virt)
	144	return ERR_PTR(-ENOMEM);
	145
	146	data = (struct cpu_vhint_data *)virt;
	147
	148	memset(&req, 0, sizeof(req));
	149	req.addr = phys;
cfef4bca	150	req.cluster_id = cluster_id;
939dc6f5 MP	151
	152	memset(&msg, 0, sizeof(msg));
	153	msg.mrq = MRQ_CPU_VHINT;
	154	msg.tx.data = &req;
	155	msg.tx.size = sizeof(req);
	156
	157	err = tegra_bpmp_transfer(bpmp, &msg);
	158	if (err) {
	159	table = ERR_PTR(err);
	160	goto free;
	161	}
	162
	163	for (i = data->vfloor; i <= data->vceil; i++) {
	164	u16 ndiv = data->ndiv[i];
	165
	166	if (ndiv < data->ndiv_min \|\| ndiv > data->ndiv_max)
	167	continue;
	168
	169	/* Only store lowest voltage index for each rate */
	170	if (i > 0 && ndiv == data->ndiv[i - 1])
	171	continue;
	172
	173	num_rates++;
	174	}
	175
	176	table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table),
	177	GFP_KERNEL);
	178	if (!table) {
	179	table = ERR_PTR(-ENOMEM);
	180	goto free;
	181	}
	182
e010d1d2 JH	183	cluster->ref_clk_khz = data->ref_clk_hz / 1000;
	184	cluster->div = data->pdiv * data->mdiv;
	185
939dc6f5 MP	186	for (i = data->vfloor, j = 0; i <= data->vceil; i++) {
	187	struct cpufreq_frequency_table *point;
	188	u16 ndiv = data->ndiv[i];
	189	u32 edvd_val = 0;
	190
	191	if (ndiv < data->ndiv_min \|\| ndiv > data->ndiv_max)
	192	continue;
	193
	194	/* Only store lowest voltage index for each rate */
	195	if (i > 0 && ndiv == data->ndiv[i - 1])
	196	continue;
	197
	198	edvd_val \|= i << EDVD_CORE_VOLT_FREQ_V_SHIFT;
	199	edvd_val \|= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT;
	200
	201	point = &table[j++];
	202	point->driver_data = edvd_val;
e010d1d2	203	point->frequency = (cluster->ref_clk_khz * ndiv) / cluster->div;
939dc6f5 MP	204	}
	205
	206	table[j].frequency = CPUFREQ_TABLE_END;
	207
	208	free:
	209	dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys);
	210
	211	return table;
	212	}
	213
	214	static int tegra186_cpufreq_probe(struct platform_device *pdev)
	215	{
	216	struct tegra186_cpufreq_data *data;
	217	struct tegra_bpmp *bpmp;
939dc6f5 MP	218	unsigned int i = 0, err;
	219
	220	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	221	if (!data)
	222	return -ENOMEM;
	223
cfef4bca	224	data->clusters = devm_kcalloc(&pdev->dev, TEGRA186_NUM_CLUSTERS,
939dc6f5 MP	225	sizeof(*data->clusters), GFP_KERNEL);
	226	if (!data->clusters)
	227	return -ENOMEM;
	228
b7b4e785	229	data->cpus = tegra186_cpus;
939dc6f5 MP	230
	231	bpmp = tegra_bpmp_get(&pdev->dev);
	232	if (IS_ERR(bpmp))
	233	return PTR_ERR(bpmp);
	234
308beafc	235	data->regs = devm_platform_ioremap_resource(pdev, 0);
939dc6f5 MP	236	if (IS_ERR(data->regs)) {
	237	err = PTR_ERR(data->regs);
	238	goto put_bpmp;
	239	}
	240
cfef4bca	241	for (i = 0; i < TEGRA186_NUM_CLUSTERS; i++) {
939dc6f5 MP	242	struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
939dc6f5 MP	243
cfef4bca	244	cluster->table = init_vhint_table(pdev, bpmp, cluster, i);
939dc6f5 MP	245	if (IS_ERR(cluster->table)) {
	246	err = PTR_ERR(cluster->table);
	247	goto put_bpmp;
	248	}
	249	}
	250
939dc6f5 MP	251	tegra186_cpufreq_driver.driver_data = data;
	252
	253	err = cpufreq_register_driver(&tegra186_cpufreq_driver);
939dc6f5 MP	254
	255	put_bpmp:
	256	tegra_bpmp_put(bpmp);
	257
	258	return err;
	259	}
	260
	261	static int tegra186_cpufreq_remove(struct platform_device *pdev)
	262	{
	263	cpufreq_unregister_driver(&tegra186_cpufreq_driver);
	264
	265	return 0;
	266	}
	267
	268	static const struct of_device_id tegra186_cpufreq_of_match[] = {
	269	{ .compatible = "nvidia,tegra186-ccplex-cluster", },
	270	{ }
	271	};
	272	MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match);
	273
	274	static struct platform_driver tegra186_cpufreq_platform_driver = {
	275	.driver = {
	276	.name = "tegra186-cpufreq",
	277	.of_match_table = tegra186_cpufreq_of_match,
	278	},
	279	.probe = tegra186_cpufreq_probe,
	280	.remove = tegra186_cpufreq_remove,
	281	};
	282	module_platform_driver(tegra186_cpufreq_platform_driver);
	283
	284	MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
	285	MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver");
	286	MODULE_LICENSE("GPL v2");