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Commit | Line | Data |
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b511431d JE |
1 | |
2 | menuconfig CRYPTO_HW | |
3 | bool "Hardware crypto devices" | |
4 | default y | |
06bfb7eb JE |
5 | ---help--- |
6 | Say Y here to get to see options for hardware crypto devices and | |
7 | processors. This option alone does not add any kernel code. | |
8 | ||
9 | If you say N, all options in this submenu will be skipped and disabled. | |
b511431d JE |
10 | |
11 | if CRYPTO_HW | |
1da177e4 LT |
12 | |
13 | config CRYPTO_DEV_PADLOCK | |
d158325e | 14 | tristate "Support for VIA PadLock ACE" |
2f817418 | 15 | depends on X86 && !UML |
1da177e4 LT |
16 | help |
17 | Some VIA processors come with an integrated crypto engine | |
18 | (so called VIA PadLock ACE, Advanced Cryptography Engine) | |
1191f0a4 ML |
19 | that provides instructions for very fast cryptographic |
20 | operations with supported algorithms. | |
1da177e4 LT |
21 | |
22 | The instructions are used only when the CPU supports them. | |
5644bda5 ML |
23 | Otherwise software encryption is used. |
24 | ||
1da177e4 | 25 | config CRYPTO_DEV_PADLOCK_AES |
1191f0a4 | 26 | tristate "PadLock driver for AES algorithm" |
1da177e4 | 27 | depends on CRYPTO_DEV_PADLOCK |
28ce728a | 28 | select CRYPTO_BLKCIPHER |
7dc748e4 | 29 | select CRYPTO_AES |
1da177e4 LT |
30 | help |
31 | Use VIA PadLock for AES algorithm. | |
32 | ||
1191f0a4 ML |
33 | Available in VIA C3 and newer CPUs. |
34 | ||
35 | If unsure say M. The compiled module will be | |
4737f097 | 36 | called padlock-aes. |
1191f0a4 | 37 | |
6c833275 ML |
38 | config CRYPTO_DEV_PADLOCK_SHA |
39 | tristate "PadLock driver for SHA1 and SHA256 algorithms" | |
40 | depends on CRYPTO_DEV_PADLOCK | |
bbbee467 | 41 | select CRYPTO_HASH |
6c833275 ML |
42 | select CRYPTO_SHA1 |
43 | select CRYPTO_SHA256 | |
6c833275 ML |
44 | help |
45 | Use VIA PadLock for SHA1/SHA256 algorithms. | |
46 | ||
47 | Available in VIA C7 and newer processors. | |
48 | ||
49 | If unsure say M. The compiled module will be | |
4737f097 | 50 | called padlock-sha. |
6c833275 | 51 | |
9fe757b0 JC |
52 | config CRYPTO_DEV_GEODE |
53 | tristate "Support for the Geode LX AES engine" | |
f6259dea | 54 | depends on X86_32 && PCI |
9fe757b0 JC |
55 | select CRYPTO_ALGAPI |
56 | select CRYPTO_BLKCIPHER | |
9fe757b0 JC |
57 | help |
58 | Say 'Y' here to use the AMD Geode LX processor on-board AES | |
3dde6ad8 | 59 | engine for the CryptoAPI AES algorithm. |
9fe757b0 JC |
60 | |
61 | To compile this driver as a module, choose M here: the module | |
62 | will be called geode-aes. | |
63 | ||
61d48c2c | 64 | config ZCRYPT |
a3358e3d | 65 | tristate "Support for s390 cryptographic adapters" |
61d48c2c | 66 | depends on S390 |
2f7c8bd6 | 67 | select HW_RANDOM |
61d48c2c | 68 | help |
a3358e3d HF |
69 | Select this option if you want to enable support for |
70 | s390 cryptographic adapters like: | |
61d48c2c | 71 | + PCI-X Cryptographic Coprocessor (PCIXCC) |
a3358e3d HF |
72 | + Crypto Express 2,3,4 or 5 Coprocessor (CEXxC) |
73 | + Crypto Express 2,3,4 or 5 Accelerator (CEXxA) | |
74 | + Crypto Express 4 or 5 EP11 Coprocessor (CEXxP) | |
61d48c2c | 75 | |
e80d4af0 HF |
76 | config PKEY |
77 | tristate "Kernel API for protected key handling" | |
78 | depends on S390 | |
79 | depends on ZCRYPT | |
80 | help | |
81 | With this option enabled the pkey kernel module provides an API | |
82 | for creation and handling of protected keys. Other parts of the | |
83 | kernel or userspace applications may use these functions. | |
84 | ||
85 | Select this option if you want to enable the kernel and userspace | |
86 | API for proteced key handling. | |
87 | ||
88 | Please note that creation of protected keys from secure keys | |
89 | requires to have at least one CEX card in coprocessor mode | |
90 | available at runtime. | |
61d48c2c | 91 | |
c4684f98 HF |
92 | config CRYPTO_PAES_S390 |
93 | tristate "PAES cipher algorithms" | |
94 | depends on S390 | |
95 | depends on ZCRYPT | |
96 | depends on PKEY | |
97 | select CRYPTO_ALGAPI | |
98 | select CRYPTO_BLKCIPHER | |
99 | help | |
100 | This is the s390 hardware accelerated implementation of the | |
101 | AES cipher algorithms for use with protected key. | |
102 | ||
103 | Select this option if you want to use the paes cipher | |
104 | for example to use protected key encrypted devices. | |
105 | ||
3f5615e0 JG |
106 | config CRYPTO_SHA1_S390 |
107 | tristate "SHA1 digest algorithm" | |
108 | depends on S390 | |
563f346d | 109 | select CRYPTO_HASH |
3f5615e0 JG |
110 | help |
111 | This is the s390 hardware accelerated implementation of the | |
112 | SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). | |
113 | ||
d393d9b8 JG |
114 | It is available as of z990. |
115 | ||
3f5615e0 JG |
116 | config CRYPTO_SHA256_S390 |
117 | tristate "SHA256 digest algorithm" | |
118 | depends on S390 | |
563f346d | 119 | select CRYPTO_HASH |
3f5615e0 JG |
120 | help |
121 | This is the s390 hardware accelerated implementation of the | |
122 | SHA256 secure hash standard (DFIPS 180-2). | |
123 | ||
d393d9b8 | 124 | It is available as of z9. |
3f5615e0 | 125 | |
291dc7c0 | 126 | config CRYPTO_SHA512_S390 |
4e2c6d7f | 127 | tristate "SHA384 and SHA512 digest algorithm" |
291dc7c0 | 128 | depends on S390 |
563f346d | 129 | select CRYPTO_HASH |
291dc7c0 JG |
130 | help |
131 | This is the s390 hardware accelerated implementation of the | |
132 | SHA512 secure hash standard. | |
133 | ||
d393d9b8 | 134 | It is available as of z10. |
291dc7c0 | 135 | |
3f5615e0 JG |
136 | config CRYPTO_DES_S390 |
137 | tristate "DES and Triple DES cipher algorithms" | |
138 | depends on S390 | |
139 | select CRYPTO_ALGAPI | |
140 | select CRYPTO_BLKCIPHER | |
63291d40 | 141 | select CRYPTO_DES |
3f5615e0 | 142 | help |
0200f3ec | 143 | This is the s390 hardware accelerated implementation of the |
3f5615e0 JG |
144 | DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). |
145 | ||
0200f3ec GS |
146 | As of z990 the ECB and CBC mode are hardware accelerated. |
147 | As of z196 the CTR mode is hardware accelerated. | |
148 | ||
3f5615e0 JG |
149 | config CRYPTO_AES_S390 |
150 | tristate "AES cipher algorithms" | |
151 | depends on S390 | |
152 | select CRYPTO_ALGAPI | |
153 | select CRYPTO_BLKCIPHER | |
154 | help | |
155 | This is the s390 hardware accelerated implementation of the | |
99d97222 GS |
156 | AES cipher algorithms (FIPS-197). |
157 | ||
158 | As of z9 the ECB and CBC modes are hardware accelerated | |
159 | for 128 bit keys. | |
160 | As of z10 the ECB and CBC modes are hardware accelerated | |
161 | for all AES key sizes. | |
0200f3ec GS |
162 | As of z196 the CTR mode is hardware accelerated for all AES |
163 | key sizes and XTS mode is hardware accelerated for 256 and | |
99d97222 | 164 | 512 bit keys. |
3f5615e0 JG |
165 | |
166 | config S390_PRNG | |
167 | tristate "Pseudo random number generator device driver" | |
168 | depends on S390 | |
169 | default "m" | |
170 | help | |
171 | Select this option if you want to use the s390 pseudo random number | |
172 | generator. The PRNG is part of the cryptographic processor functions | |
173 | and uses triple-DES to generate secure random numbers like the | |
d393d9b8 JG |
174 | ANSI X9.17 standard. User-space programs access the |
175 | pseudo-random-number device through the char device /dev/prandom. | |
176 | ||
177 | It is available as of z9. | |
3f5615e0 | 178 | |
df1309ce GS |
179 | config CRYPTO_GHASH_S390 |
180 | tristate "GHASH digest algorithm" | |
181 | depends on S390 | |
182 | select CRYPTO_HASH | |
183 | help | |
184 | This is the s390 hardware accelerated implementation of the | |
185 | GHASH message digest algorithm for GCM (Galois/Counter Mode). | |
186 | ||
187 | It is available as of z196. | |
188 | ||
f848dbd3 HB |
189 | config CRYPTO_CRC32_S390 |
190 | tristate "CRC-32 algorithms" | |
191 | depends on S390 | |
192 | select CRYPTO_HASH | |
193 | select CRC32 | |
194 | help | |
195 | Select this option if you want to use hardware accelerated | |
196 | implementations of CRC algorithms. With this option, you | |
197 | can optimize the computation of CRC-32 (IEEE 802.3 Ethernet) | |
198 | and CRC-32C (Castagnoli). | |
199 | ||
200 | It is available with IBM z13 or later. | |
201 | ||
f63601fd | 202 | config CRYPTO_DEV_MARVELL_CESA |
27b43fd9 | 203 | tristate "Marvell's Cryptographic Engine driver" |
fe55dfdc | 204 | depends on PLAT_ORION || ARCH_MVEBU |
f63601fd BB |
205 | select CRYPTO_AES |
206 | select CRYPTO_DES | |
207 | select CRYPTO_BLKCIPHER | |
208 | select CRYPTO_HASH | |
209 | select SRAM | |
210 | help | |
211 | This driver allows you to utilize the Cryptographic Engines and | |
27b43fd9 BB |
212 | Security Accelerator (CESA) which can be found on MVEBU and ORION |
213 | platforms. | |
db509a45 | 214 | This driver supports CPU offload through DMA transfers. |
f63601fd | 215 | |
0a625fd2 DM |
216 | config CRYPTO_DEV_NIAGARA2 |
217 | tristate "Niagara2 Stream Processing Unit driver" | |
50e78161 | 218 | select CRYPTO_DES |
596103cf HX |
219 | select CRYPTO_BLKCIPHER |
220 | select CRYPTO_HASH | |
8054b800 LC |
221 | select CRYPTO_MD5 |
222 | select CRYPTO_SHA1 | |
223 | select CRYPTO_SHA256 | |
0a625fd2 DM |
224 | depends on SPARC64 |
225 | help | |
226 | Each core of a Niagara2 processor contains a Stream | |
227 | Processing Unit, which itself contains several cryptographic | |
228 | sub-units. One set provides the Modular Arithmetic Unit, | |
229 | used for SSL offload. The other set provides the Cipher | |
230 | Group, which can perform encryption, decryption, hashing, | |
231 | checksumming, and raw copies. | |
232 | ||
f7d0561e EP |
233 | config CRYPTO_DEV_HIFN_795X |
234 | tristate "Driver HIFN 795x crypto accelerator chips" | |
c3041f9c | 235 | select CRYPTO_DES |
653ebd9c | 236 | select CRYPTO_BLKCIPHER |
946fef4e | 237 | select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG |
2707b937 | 238 | depends on PCI |
75b76625 | 239 | depends on !ARCH_DMA_ADDR_T_64BIT |
f7d0561e EP |
240 | help |
241 | This option allows you to have support for HIFN 795x crypto adapters. | |
242 | ||
946fef4e HX |
243 | config CRYPTO_DEV_HIFN_795X_RNG |
244 | bool "HIFN 795x random number generator" | |
245 | depends on CRYPTO_DEV_HIFN_795X | |
246 | help | |
247 | Select this option if you want to enable the random number generator | |
248 | on the HIFN 795x crypto adapters. | |
f7d0561e | 249 | |
8e8ec596 KP |
250 | source drivers/crypto/caam/Kconfig |
251 | ||
9c4a7965 KP |
252 | config CRYPTO_DEV_TALITOS |
253 | tristate "Talitos Freescale Security Engine (SEC)" | |
596103cf | 254 | select CRYPTO_AEAD |
9c4a7965 | 255 | select CRYPTO_AUTHENC |
596103cf HX |
256 | select CRYPTO_BLKCIPHER |
257 | select CRYPTO_HASH | |
9c4a7965 KP |
258 | select HW_RANDOM |
259 | depends on FSL_SOC | |
260 | help | |
261 | Say 'Y' here to use the Freescale Security Engine (SEC) | |
262 | to offload cryptographic algorithm computation. | |
263 | ||
264 | The Freescale SEC is present on PowerQUICC 'E' processors, such | |
265 | as the MPC8349E and MPC8548E. | |
266 | ||
267 | To compile this driver as a module, choose M here: the module | |
268 | will be called talitos. | |
269 | ||
5b841a65 LC |
270 | config CRYPTO_DEV_TALITOS1 |
271 | bool "SEC1 (SEC 1.0 and SEC Lite 1.2)" | |
272 | depends on CRYPTO_DEV_TALITOS | |
273 | depends on PPC_8xx || PPC_82xx | |
274 | default y | |
275 | help | |
276 | Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0 | |
277 | found on MPC82xx or the Freescale Security Engine (SEC Lite) | |
278 | version 1.2 found on MPC8xx | |
279 | ||
280 | config CRYPTO_DEV_TALITOS2 | |
281 | bool "SEC2+ (SEC version 2.0 or upper)" | |
282 | depends on CRYPTO_DEV_TALITOS | |
283 | default y if !PPC_8xx | |
284 | help | |
285 | Say 'Y' here to use the Freescale Security Engine (SEC) | |
286 | version 2 and following as found on MPC83xx, MPC85xx, etc ... | |
287 | ||
81bef015 CH |
288 | config CRYPTO_DEV_IXP4XX |
289 | tristate "Driver for IXP4xx crypto hardware acceleration" | |
9665c52b | 290 | depends on ARCH_IXP4XX && IXP4XX_QMGR && IXP4XX_NPE |
81bef015 | 291 | select CRYPTO_DES |
596103cf | 292 | select CRYPTO_AEAD |
090657e4 | 293 | select CRYPTO_AUTHENC |
81bef015 CH |
294 | select CRYPTO_BLKCIPHER |
295 | help | |
296 | Driver for the IXP4xx NPE crypto engine. | |
297 | ||
049359d6 JH |
298 | config CRYPTO_DEV_PPC4XX |
299 | tristate "Driver AMCC PPC4xx crypto accelerator" | |
300 | depends on PPC && 4xx | |
301 | select CRYPTO_HASH | |
a0aae821 CL |
302 | select CRYPTO_AEAD |
303 | select CRYPTO_AES | |
304 | select CRYPTO_CCM | |
305 | select CRYPTO_GCM | |
049359d6 JH |
306 | select CRYPTO_BLKCIPHER |
307 | help | |
308 | This option allows you to have support for AMCC crypto acceleration. | |
309 | ||
5343e674 CL |
310 | config HW_RANDOM_PPC4XX |
311 | bool "PowerPC 4xx generic true random number generator support" | |
312 | depends on CRYPTO_DEV_PPC4XX && HW_RANDOM | |
313 | default y | |
314 | ---help--- | |
315 | This option provides the kernel-side support for the TRNG hardware | |
316 | found in the security function of some PowerPC 4xx SoCs. | |
317 | ||
74ed87e7 TK |
318 | config CRYPTO_DEV_OMAP |
319 | tristate "Support for OMAP crypto HW accelerators" | |
320 | depends on ARCH_OMAP2PLUS | |
321 | help | |
322 | OMAP processors have various crypto HW accelerators. Select this if | |
323 | you want to use the OMAP modules for any of the crypto algorithms. | |
324 | ||
325 | if CRYPTO_DEV_OMAP | |
326 | ||
8628e7c8 | 327 | config CRYPTO_DEV_OMAP_SHAM |
eaef7e3f LV |
328 | tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator" |
329 | depends on ARCH_OMAP2PLUS | |
8628e7c8 DK |
330 | select CRYPTO_SHA1 |
331 | select CRYPTO_MD5 | |
eaef7e3f LV |
332 | select CRYPTO_SHA256 |
333 | select CRYPTO_SHA512 | |
334 | select CRYPTO_HMAC | |
8628e7c8 | 335 | help |
eaef7e3f LV |
336 | OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you |
337 | want to use the OMAP module for MD5/SHA1/SHA2 algorithms. | |
8628e7c8 | 338 | |
537559a5 DK |
339 | config CRYPTO_DEV_OMAP_AES |
340 | tristate "Support for OMAP AES hw engine" | |
1bbf6437 | 341 | depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP2PLUS |
537559a5 | 342 | select CRYPTO_AES |
596103cf | 343 | select CRYPTO_BLKCIPHER |
0529900a | 344 | select CRYPTO_ENGINE |
9fcb191a LV |
345 | select CRYPTO_CBC |
346 | select CRYPTO_ECB | |
347 | select CRYPTO_CTR | |
ad18cc9d | 348 | select CRYPTO_AEAD |
537559a5 DK |
349 | help |
350 | OMAP processors have AES module accelerator. Select this if you | |
351 | want to use the OMAP module for AES algorithms. | |
352 | ||
701d0f19 | 353 | config CRYPTO_DEV_OMAP_DES |
97ee7ed3 | 354 | tristate "Support for OMAP DES/3DES hw engine" |
701d0f19 JF |
355 | depends on ARCH_OMAP2PLUS |
356 | select CRYPTO_DES | |
596103cf | 357 | select CRYPTO_BLKCIPHER |
f1b77aac | 358 | select CRYPTO_ENGINE |
701d0f19 JF |
359 | help |
360 | OMAP processors have DES/3DES module accelerator. Select this if you | |
361 | want to use the OMAP module for DES and 3DES algorithms. Currently | |
97ee7ed3 PM |
362 | the ECB and CBC modes of operation are supported by the driver. Also |
363 | accesses made on unaligned boundaries are supported. | |
701d0f19 | 364 | |
74ed87e7 TK |
365 | endif # CRYPTO_DEV_OMAP |
366 | ||
ce921368 JI |
367 | config CRYPTO_DEV_PICOXCELL |
368 | tristate "Support for picoXcell IPSEC and Layer2 crypto engines" | |
4f44d86d | 369 | depends on (ARCH_PICOXCELL || COMPILE_TEST) && HAVE_CLK |
596103cf | 370 | select CRYPTO_AEAD |
ce921368 JI |
371 | select CRYPTO_AES |
372 | select CRYPTO_AUTHENC | |
596103cf | 373 | select CRYPTO_BLKCIPHER |
ce921368 JI |
374 | select CRYPTO_DES |
375 | select CRYPTO_CBC | |
376 | select CRYPTO_ECB | |
377 | select CRYPTO_SEQIV | |
378 | help | |
379 | This option enables support for the hardware offload engines in the | |
380 | Picochip picoXcell SoC devices. Select this for IPSEC ESP offload | |
381 | and for 3gpp Layer 2 ciphering support. | |
382 | ||
383 | Saying m here will build a module named pipcoxcell_crypto. | |
384 | ||
5de88752 JM |
385 | config CRYPTO_DEV_SAHARA |
386 | tristate "Support for SAHARA crypto accelerator" | |
74d24d83 | 387 | depends on ARCH_MXC && OF |
5de88752 JM |
388 | select CRYPTO_BLKCIPHER |
389 | select CRYPTO_AES | |
390 | select CRYPTO_ECB | |
391 | help | |
392 | This option enables support for the SAHARA HW crypto accelerator | |
393 | found in some Freescale i.MX chips. | |
394 | ||
d293b640 ST |
395 | config CRYPTO_DEV_MXC_SCC |
396 | tristate "Support for Freescale Security Controller (SCC)" | |
397 | depends on ARCH_MXC && OF | |
398 | select CRYPTO_BLKCIPHER | |
399 | select CRYPTO_DES | |
400 | help | |
401 | This option enables support for the Security Controller (SCC) | |
402 | found in Freescale i.MX25 chips. | |
403 | ||
c46ea13f KK |
404 | config CRYPTO_DEV_EXYNOS_RNG |
405 | tristate "EXYNOS HW pseudo random number generator support" | |
406 | depends on ARCH_EXYNOS || COMPILE_TEST | |
407 | depends on HAS_IOMEM | |
408 | select CRYPTO_RNG | |
409 | ---help--- | |
410 | This driver provides kernel-side support through the | |
411 | cryptographic API for the pseudo random number generator hardware | |
412 | found on Exynos SoCs. | |
413 | ||
414 | To compile this driver as a module, choose M here: the | |
415 | module will be called exynos-rng. | |
416 | ||
417 | If unsure, say Y. | |
418 | ||
a49e490c | 419 | config CRYPTO_DEV_S5P |
e922e96f | 420 | tristate "Support for Samsung S5PV210/Exynos crypto accelerator" |
dc1d9dee KK |
421 | depends on ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST |
422 | depends on HAS_IOMEM && HAS_DMA | |
a49e490c | 423 | select CRYPTO_AES |
a49e490c VZ |
424 | select CRYPTO_BLKCIPHER |
425 | help | |
426 | This option allows you to have support for S5P crypto acceleration. | |
e922e96f | 427 | Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES |
a49e490c VZ |
428 | algorithms execution. |
429 | ||
c2afad6c KK |
430 | config CRYPTO_DEV_EXYNOS_HASH |
431 | bool "Support for Samsung Exynos HASH accelerator" | |
432 | depends on CRYPTO_DEV_S5P | |
433 | depends on !CRYPTO_DEV_EXYNOS_RNG && CRYPTO_DEV_EXYNOS_RNG!=m | |
434 | select CRYPTO_SHA1 | |
435 | select CRYPTO_MD5 | |
436 | select CRYPTO_SHA256 | |
437 | help | |
438 | Select this to offload Exynos from HASH MD5/SHA1/SHA256. | |
439 | This will select software SHA1, MD5 and SHA256 as they are | |
440 | needed for small and zero-size messages. | |
441 | HASH algorithms will be disabled if EXYNOS_RNG | |
442 | is enabled due to hw conflict. | |
443 | ||
aef7b31c | 444 | config CRYPTO_DEV_NX |
7011a122 DS |
445 | bool "Support for IBM PowerPC Nest (NX) cryptographic acceleration" |
446 | depends on PPC64 | |
aef7b31c | 447 | help |
7011a122 DS |
448 | This enables support for the NX hardware cryptographic accelerator |
449 | coprocessor that is in IBM PowerPC P7+ or later processors. This | |
450 | does not actually enable any drivers, it only allows you to select | |
451 | which acceleration type (encryption and/or compression) to enable. | |
322cacce SJ |
452 | |
453 | if CRYPTO_DEV_NX | |
454 | source "drivers/crypto/nx/Kconfig" | |
455 | endif | |
aef7b31c | 456 | |
2789c08f AW |
457 | config CRYPTO_DEV_UX500 |
458 | tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration" | |
459 | depends on ARCH_U8500 | |
2789c08f AW |
460 | help |
461 | Driver for ST-Ericsson UX500 crypto engine. | |
462 | ||
463 | if CRYPTO_DEV_UX500 | |
464 | source "drivers/crypto/ux500/Kconfig" | |
465 | endif # if CRYPTO_DEV_UX500 | |
466 | ||
b8840098 SZ |
467 | config CRYPTO_DEV_BFIN_CRC |
468 | tristate "Support for Blackfin CRC hardware" | |
469 | depends on BF60x | |
470 | help | |
471 | Newer Blackfin processors have CRC hardware. Select this if you | |
472 | want to use the Blackfin CRC module. | |
473 | ||
89a82ef8 CP |
474 | config CRYPTO_DEV_ATMEL_AUTHENC |
475 | tristate "Support for Atmel IPSEC/SSL hw accelerator" | |
ceb4afb3 AB |
476 | depends on HAS_DMA |
477 | depends on ARCH_AT91 || COMPILE_TEST | |
89a82ef8 CP |
478 | select CRYPTO_AUTHENC |
479 | select CRYPTO_DEV_ATMEL_AES | |
480 | select CRYPTO_DEV_ATMEL_SHA | |
481 | help | |
482 | Some Atmel processors can combine the AES and SHA hw accelerators | |
483 | to enhance support of IPSEC/SSL. | |
484 | Select this if you want to use the Atmel modules for | |
485 | authenc(hmac(shaX),Y(cbc)) algorithms. | |
486 | ||
bd3c7b5c NR |
487 | config CRYPTO_DEV_ATMEL_AES |
488 | tristate "Support for Atmel AES hw accelerator" | |
cbafd643 | 489 | depends on HAS_DMA |
ceb4afb3 | 490 | depends on ARCH_AT91 || COMPILE_TEST |
bd3c7b5c | 491 | select CRYPTO_AES |
d4419548 | 492 | select CRYPTO_AEAD |
bd3c7b5c | 493 | select CRYPTO_BLKCIPHER |
bd3c7b5c NR |
494 | help |
495 | Some Atmel processors have AES hw accelerator. | |
496 | Select this if you want to use the Atmel module for | |
497 | AES algorithms. | |
498 | ||
499 | To compile this driver as a module, choose M here: the module | |
500 | will be called atmel-aes. | |
501 | ||
13802005 NR |
502 | config CRYPTO_DEV_ATMEL_TDES |
503 | tristate "Support for Atmel DES/TDES hw accelerator" | |
f7f9482e | 504 | depends on HAS_DMA |
ceb4afb3 | 505 | depends on ARCH_AT91 || COMPILE_TEST |
13802005 | 506 | select CRYPTO_DES |
13802005 NR |
507 | select CRYPTO_BLKCIPHER |
508 | help | |
509 | Some Atmel processors have DES/TDES hw accelerator. | |
510 | Select this if you want to use the Atmel module for | |
511 | DES/TDES algorithms. | |
512 | ||
513 | To compile this driver as a module, choose M here: the module | |
514 | will be called atmel-tdes. | |
515 | ||
ebc82efa | 516 | config CRYPTO_DEV_ATMEL_SHA |
d4905b38 | 517 | tristate "Support for Atmel SHA hw accelerator" |
f7f9482e | 518 | depends on HAS_DMA |
ceb4afb3 | 519 | depends on ARCH_AT91 || COMPILE_TEST |
596103cf | 520 | select CRYPTO_HASH |
ebc82efa | 521 | help |
d4905b38 NR |
522 | Some Atmel processors have SHA1/SHA224/SHA256/SHA384/SHA512 |
523 | hw accelerator. | |
ebc82efa | 524 | Select this if you want to use the Atmel module for |
d4905b38 | 525 | SHA1/SHA224/SHA256/SHA384/SHA512 algorithms. |
ebc82efa NR |
526 | |
527 | To compile this driver as a module, choose M here: the module | |
528 | will be called atmel-sha. | |
529 | ||
11105693 TDA |
530 | config CRYPTO_DEV_ATMEL_ECC |
531 | tristate "Support for Microchip / Atmel ECC hw accelerator" | |
532 | depends on ARCH_AT91 || COMPILE_TEST | |
533 | depends on I2C | |
534 | select CRYPTO_ECDH | |
535 | select CRC16 | |
536 | help | |
537 | Microhip / Atmel ECC hw accelerator. | |
538 | Select this if you want to use the Microchip / Atmel module for | |
539 | ECDH algorithm. | |
540 | ||
541 | To compile this driver as a module, choose M here: the module | |
542 | will be called atmel-ecc. | |
543 | ||
f1147660 | 544 | config CRYPTO_DEV_CCP |
720419f0 | 545 | bool "Support for AMD Secure Processor" |
6c506343 | 546 | depends on ((X86 && PCI) || (ARM64 && (OF_ADDRESS || ACPI))) && HAS_IOMEM |
f1147660 | 547 | help |
720419f0 BS |
548 | The AMD Secure Processor provides support for the Cryptographic Coprocessor |
549 | (CCP) and the Platform Security Processor (PSP) devices. | |
f1147660 TL |
550 | |
551 | if CRYPTO_DEV_CCP | |
552 | source "drivers/crypto/ccp/Kconfig" | |
553 | endif | |
554 | ||
15b59e7c MV |
555 | config CRYPTO_DEV_MXS_DCP |
556 | tristate "Support for Freescale MXS DCP" | |
a2712e6c | 557 | depends on (ARCH_MXS || ARCH_MXC) |
dc97fa02 | 558 | select STMP_DEVICE |
15b59e7c MV |
559 | select CRYPTO_CBC |
560 | select CRYPTO_ECB | |
561 | select CRYPTO_AES | |
562 | select CRYPTO_BLKCIPHER | |
596103cf | 563 | select CRYPTO_HASH |
15b59e7c MV |
564 | help |
565 | The Freescale i.MX23/i.MX28 has SHA1/SHA256 and AES128 CBC/ECB | |
566 | co-processor on the die. | |
567 | ||
568 | To compile this driver as a module, choose M here: the module | |
569 | will be called mxs-dcp. | |
570 | ||
cea4001a | 571 | source "drivers/crypto/qat/Kconfig" |
62ad8b5c | 572 | source "drivers/crypto/cavium/cpt/Kconfig" |
14fa93cd | 573 | source "drivers/crypto/cavium/nitrox/Kconfig" |
c672752d | 574 | |
640035a2 MC |
575 | config CRYPTO_DEV_CAVIUM_ZIP |
576 | tristate "Cavium ZIP driver" | |
577 | depends on PCI && 64BIT && (ARM64 || COMPILE_TEST) | |
578 | ---help--- | |
579 | Select this option if you want to enable compression/decompression | |
580 | acceleration on Cavium's ARM based SoCs | |
581 | ||
c672752d SV |
582 | config CRYPTO_DEV_QCE |
583 | tristate "Qualcomm crypto engine accelerator" | |
71d932d9 | 584 | depends on (ARCH_QCOM || COMPILE_TEST) && HAS_DMA && HAS_IOMEM |
c672752d SV |
585 | select CRYPTO_AES |
586 | select CRYPTO_DES | |
587 | select CRYPTO_ECB | |
588 | select CRYPTO_CBC | |
589 | select CRYPTO_XTS | |
590 | select CRYPTO_CTR | |
c672752d SV |
591 | select CRYPTO_BLKCIPHER |
592 | help | |
593 | This driver supports Qualcomm crypto engine accelerator | |
594 | hardware. To compile this driver as a module, choose M here. The | |
595 | module will be called qcrypto. | |
596 | ||
d2e3ae6f LB |
597 | config CRYPTO_DEV_VMX |
598 | bool "Support for VMX cryptographic acceleration instructions" | |
f1ab4287 | 599 | depends on PPC64 && VSX |
d2e3ae6f LB |
600 | help |
601 | Support for VMX cryptographic acceleration instructions. | |
602 | ||
603 | source "drivers/crypto/vmx/Kconfig" | |
604 | ||
d358f1ab | 605 | config CRYPTO_DEV_IMGTEC_HASH |
d358f1ab | 606 | tristate "Imagination Technologies hardware hash accelerator" |
8c98ebd7 GU |
607 | depends on MIPS || COMPILE_TEST |
608 | depends on HAS_DMA | |
d358f1ab JH |
609 | select CRYPTO_MD5 |
610 | select CRYPTO_SHA1 | |
d358f1ab JH |
611 | select CRYPTO_SHA256 |
612 | select CRYPTO_HASH | |
613 | help | |
614 | This driver interfaces with the Imagination Technologies | |
615 | hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256 | |
616 | hashing algorithms. | |
617 | ||
6298e948 LC |
618 | config CRYPTO_DEV_SUN4I_SS |
619 | tristate "Support for Allwinner Security System cryptographic accelerator" | |
f823ab93 | 620 | depends on ARCH_SUNXI && !64BIT |
6298e948 LC |
621 | select CRYPTO_MD5 |
622 | select CRYPTO_SHA1 | |
623 | select CRYPTO_AES | |
624 | select CRYPTO_DES | |
625 | select CRYPTO_BLKCIPHER | |
626 | help | |
627 | Some Allwinner SoC have a crypto accelerator named | |
628 | Security System. Select this if you want to use it. | |
629 | The Security System handle AES/DES/3DES ciphers in CBC mode | |
630 | and SHA1 and MD5 hash algorithms. | |
631 | ||
632 | To compile this driver as a module, choose M here: the module | |
633 | will be called sun4i-ss. | |
634 | ||
b8ae5c73 CL |
635 | config CRYPTO_DEV_SUN4I_SS_PRNG |
636 | bool "Support for Allwinner Security System PRNG" | |
637 | depends on CRYPTO_DEV_SUN4I_SS | |
638 | select CRYPTO_RNG | |
639 | help | |
640 | Select this option if you want to provide kernel-side support for | |
641 | the Pseudo-Random Number Generator found in the Security System. | |
642 | ||
433cd2c6 ZW |
643 | config CRYPTO_DEV_ROCKCHIP |
644 | tristate "Rockchip's Cryptographic Engine driver" | |
645 | depends on OF && ARCH_ROCKCHIP | |
646 | select CRYPTO_AES | |
647 | select CRYPTO_DES | |
bfd927ff ZW |
648 | select CRYPTO_MD5 |
649 | select CRYPTO_SHA1 | |
650 | select CRYPTO_SHA256 | |
651 | select CRYPTO_HASH | |
433cd2c6 ZW |
652 | select CRYPTO_BLKCIPHER |
653 | ||
654 | help | |
655 | This driver interfaces with the hardware crypto accelerator. | |
656 | Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode. | |
657 | ||
785e5c61 RL |
658 | config CRYPTO_DEV_MEDIATEK |
659 | tristate "MediaTek's EIP97 Cryptographic Engine driver" | |
c884b368 | 660 | depends on HAS_DMA |
7dee9f61 | 661 | depends on (ARM && ARCH_MEDIATEK) || COMPILE_TEST |
785e5c61 | 662 | select CRYPTO_AES |
d03f7b0d | 663 | select CRYPTO_AEAD |
785e5c61 | 664 | select CRYPTO_BLKCIPHER |
d03f7b0d | 665 | select CRYPTO_CTR |
7dee9f61 AB |
666 | select CRYPTO_SHA1 |
667 | select CRYPTO_SHA256 | |
668 | select CRYPTO_SHA512 | |
785e5c61 RL |
669 | select CRYPTO_HMAC |
670 | help | |
671 | This driver allows you to utilize the hardware crypto accelerator | |
672 | EIP97 which can be found on the MT7623 MT2701, MT8521p, etc .... | |
673 | Select this if you want to use it for AES/SHA1/SHA2 algorithms. | |
674 | ||
02038fd6 HS |
675 | source "drivers/crypto/chelsio/Kconfig" |
676 | ||
dbaf0624 G |
677 | source "drivers/crypto/virtio/Kconfig" |
678 | ||
9d12ba86 RR |
679 | config CRYPTO_DEV_BCM_SPU |
680 | tristate "Broadcom symmetric crypto/hash acceleration support" | |
681 | depends on ARCH_BCM_IPROC | |
efc856ed | 682 | depends on MAILBOX |
9d12ba86 RR |
683 | default m |
684 | select CRYPTO_DES | |
685 | select CRYPTO_MD5 | |
686 | select CRYPTO_SHA1 | |
687 | select CRYPTO_SHA256 | |
688 | select CRYPTO_SHA512 | |
689 | help | |
690 | This driver provides support for Broadcom crypto acceleration using the | |
691 | Secure Processing Unit (SPU). The SPU driver registers ablkcipher, | |
692 | ahash, and aead algorithms with the kernel cryptographic API. | |
693 | ||
b51dbe90 FD |
694 | source "drivers/crypto/stm32/Kconfig" |
695 | ||
1b44c5a6 AT |
696 | config CRYPTO_DEV_SAFEXCEL |
697 | tristate "Inside Secure's SafeXcel cryptographic engine driver" | |
698 | depends on HAS_DMA && OF | |
699 | depends on (ARM64 && ARCH_MVEBU) || (COMPILE_TEST && 64BIT) | |
700 | select CRYPTO_AES | |
701 | select CRYPTO_BLKCIPHER | |
702 | select CRYPTO_HASH | |
703 | select CRYPTO_HMAC | |
704 | select CRYPTO_SHA1 | |
705 | select CRYPTO_SHA256 | |
706 | select CRYPTO_SHA512 | |
707 | help | |
708 | This driver interfaces with the SafeXcel EIP-197 cryptographic engine | |
709 | designed by Inside Secure. Select this if you want to use CBC/ECB | |
710 | chain mode, AES cipher mode and SHA1/SHA224/SHA256/SHA512 hash | |
711 | algorithms. | |
712 | ||
a21eb94f LP |
713 | config CRYPTO_DEV_ARTPEC6 |
714 | tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration." | |
715 | depends on ARM && (ARCH_ARTPEC || COMPILE_TEST) | |
716 | depends on HAS_DMA | |
717 | depends on OF | |
718 | select CRYPTO_AEAD | |
719 | select CRYPTO_AES | |
720 | select CRYPTO_ALGAPI | |
721 | select CRYPTO_BLKCIPHER | |
722 | select CRYPTO_CTR | |
723 | select CRYPTO_HASH | |
724 | select CRYPTO_SHA1 | |
725 | select CRYPTO_SHA256 | |
a21eb94f LP |
726 | select CRYPTO_SHA512 |
727 | help | |
728 | Enables the driver for the on-chip crypto accelerator | |
729 | of Axis ARTPEC SoCs. | |
730 | ||
731 | To compile this driver as a module, choose M here. | |
732 | ||
b511431d | 733 | endif # CRYPTO_HW |