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Commit | Line | Data |
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b511431d JE |
1 | |
2 | menuconfig CRYPTO_HW | |
3 | bool "Hardware crypto devices" | |
4 | default y | |
06bfb7eb JE |
5 | ---help--- |
6 | Say Y here to get to see options for hardware crypto devices and | |
7 | processors. This option alone does not add any kernel code. | |
8 | ||
9 | If you say N, all options in this submenu will be skipped and disabled. | |
b511431d JE |
10 | |
11 | if CRYPTO_HW | |
1da177e4 LT |
12 | |
13 | config CRYPTO_DEV_PADLOCK | |
d158325e | 14 | tristate "Support for VIA PadLock ACE" |
2f817418 | 15 | depends on X86 && !UML |
1da177e4 LT |
16 | help |
17 | Some VIA processors come with an integrated crypto engine | |
18 | (so called VIA PadLock ACE, Advanced Cryptography Engine) | |
1191f0a4 ML |
19 | that provides instructions for very fast cryptographic |
20 | operations with supported algorithms. | |
1da177e4 LT |
21 | |
22 | The instructions are used only when the CPU supports them. | |
5644bda5 ML |
23 | Otherwise software encryption is used. |
24 | ||
1da177e4 | 25 | config CRYPTO_DEV_PADLOCK_AES |
1191f0a4 | 26 | tristate "PadLock driver for AES algorithm" |
1da177e4 | 27 | depends on CRYPTO_DEV_PADLOCK |
28ce728a | 28 | select CRYPTO_BLKCIPHER |
7dc748e4 | 29 | select CRYPTO_AES |
1da177e4 LT |
30 | help |
31 | Use VIA PadLock for AES algorithm. | |
32 | ||
1191f0a4 ML |
33 | Available in VIA C3 and newer CPUs. |
34 | ||
35 | If unsure say M. The compiled module will be | |
4737f097 | 36 | called padlock-aes. |
1191f0a4 | 37 | |
6c833275 ML |
38 | config CRYPTO_DEV_PADLOCK_SHA |
39 | tristate "PadLock driver for SHA1 and SHA256 algorithms" | |
40 | depends on CRYPTO_DEV_PADLOCK | |
bbbee467 | 41 | select CRYPTO_HASH |
6c833275 ML |
42 | select CRYPTO_SHA1 |
43 | select CRYPTO_SHA256 | |
6c833275 ML |
44 | help |
45 | Use VIA PadLock for SHA1/SHA256 algorithms. | |
46 | ||
47 | Available in VIA C7 and newer processors. | |
48 | ||
49 | If unsure say M. The compiled module will be | |
4737f097 | 50 | called padlock-sha. |
6c833275 | 51 | |
9fe757b0 JC |
52 | config CRYPTO_DEV_GEODE |
53 | tristate "Support for the Geode LX AES engine" | |
f6259dea | 54 | depends on X86_32 && PCI |
9fe757b0 JC |
55 | select CRYPTO_ALGAPI |
56 | select CRYPTO_BLKCIPHER | |
9fe757b0 JC |
57 | help |
58 | Say 'Y' here to use the AMD Geode LX processor on-board AES | |
3dde6ad8 | 59 | engine for the CryptoAPI AES algorithm. |
9fe757b0 JC |
60 | |
61 | To compile this driver as a module, choose M here: the module | |
62 | will be called geode-aes. | |
63 | ||
61d48c2c | 64 | config ZCRYPT |
a3358e3d | 65 | tristate "Support for s390 cryptographic adapters" |
61d48c2c | 66 | depends on S390 |
2f7c8bd6 | 67 | select HW_RANDOM |
61d48c2c | 68 | help |
a3358e3d HF |
69 | Select this option if you want to enable support for |
70 | s390 cryptographic adapters like: | |
61d48c2c | 71 | + PCI-X Cryptographic Coprocessor (PCIXCC) |
a3358e3d HF |
72 | + Crypto Express 2,3,4 or 5 Coprocessor (CEXxC) |
73 | + Crypto Express 2,3,4 or 5 Accelerator (CEXxA) | |
74 | + Crypto Express 4 or 5 EP11 Coprocessor (CEXxP) | |
61d48c2c | 75 | |
e80d4af0 HF |
76 | config PKEY |
77 | tristate "Kernel API for protected key handling" | |
78 | depends on S390 | |
79 | depends on ZCRYPT | |
80 | help | |
81 | With this option enabled the pkey kernel module provides an API | |
82 | for creation and handling of protected keys. Other parts of the | |
83 | kernel or userspace applications may use these functions. | |
84 | ||
85 | Select this option if you want to enable the kernel and userspace | |
86 | API for proteced key handling. | |
87 | ||
88 | Please note that creation of protected keys from secure keys | |
89 | requires to have at least one CEX card in coprocessor mode | |
90 | available at runtime. | |
61d48c2c | 91 | |
c4684f98 HF |
92 | config CRYPTO_PAES_S390 |
93 | tristate "PAES cipher algorithms" | |
94 | depends on S390 | |
95 | depends on ZCRYPT | |
96 | depends on PKEY | |
97 | select CRYPTO_ALGAPI | |
98 | select CRYPTO_BLKCIPHER | |
99 | help | |
100 | This is the s390 hardware accelerated implementation of the | |
101 | AES cipher algorithms for use with protected key. | |
102 | ||
103 | Select this option if you want to use the paes cipher | |
104 | for example to use protected key encrypted devices. | |
105 | ||
3f5615e0 JG |
106 | config CRYPTO_SHA1_S390 |
107 | tristate "SHA1 digest algorithm" | |
108 | depends on S390 | |
563f346d | 109 | select CRYPTO_HASH |
3f5615e0 JG |
110 | help |
111 | This is the s390 hardware accelerated implementation of the | |
112 | SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). | |
113 | ||
d393d9b8 JG |
114 | It is available as of z990. |
115 | ||
3f5615e0 JG |
116 | config CRYPTO_SHA256_S390 |
117 | tristate "SHA256 digest algorithm" | |
118 | depends on S390 | |
563f346d | 119 | select CRYPTO_HASH |
3f5615e0 JG |
120 | help |
121 | This is the s390 hardware accelerated implementation of the | |
122 | SHA256 secure hash standard (DFIPS 180-2). | |
123 | ||
d393d9b8 | 124 | It is available as of z9. |
3f5615e0 | 125 | |
291dc7c0 | 126 | config CRYPTO_SHA512_S390 |
4e2c6d7f | 127 | tristate "SHA384 and SHA512 digest algorithm" |
291dc7c0 | 128 | depends on S390 |
563f346d | 129 | select CRYPTO_HASH |
291dc7c0 JG |
130 | help |
131 | This is the s390 hardware accelerated implementation of the | |
132 | SHA512 secure hash standard. | |
133 | ||
d393d9b8 | 134 | It is available as of z10. |
291dc7c0 | 135 | |
3f5615e0 JG |
136 | config CRYPTO_DES_S390 |
137 | tristate "DES and Triple DES cipher algorithms" | |
138 | depends on S390 | |
139 | select CRYPTO_ALGAPI | |
140 | select CRYPTO_BLKCIPHER | |
63291d40 | 141 | select CRYPTO_DES |
3f5615e0 | 142 | help |
0200f3ec | 143 | This is the s390 hardware accelerated implementation of the |
3f5615e0 JG |
144 | DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). |
145 | ||
0200f3ec GS |
146 | As of z990 the ECB and CBC mode are hardware accelerated. |
147 | As of z196 the CTR mode is hardware accelerated. | |
148 | ||
3f5615e0 JG |
149 | config CRYPTO_AES_S390 |
150 | tristate "AES cipher algorithms" | |
151 | depends on S390 | |
152 | select CRYPTO_ALGAPI | |
153 | select CRYPTO_BLKCIPHER | |
154 | help | |
155 | This is the s390 hardware accelerated implementation of the | |
99d97222 GS |
156 | AES cipher algorithms (FIPS-197). |
157 | ||
158 | As of z9 the ECB and CBC modes are hardware accelerated | |
159 | for 128 bit keys. | |
160 | As of z10 the ECB and CBC modes are hardware accelerated | |
161 | for all AES key sizes. | |
0200f3ec GS |
162 | As of z196 the CTR mode is hardware accelerated for all AES |
163 | key sizes and XTS mode is hardware accelerated for 256 and | |
99d97222 | 164 | 512 bit keys. |
3f5615e0 JG |
165 | |
166 | config S390_PRNG | |
167 | tristate "Pseudo random number generator device driver" | |
168 | depends on S390 | |
169 | default "m" | |
170 | help | |
171 | Select this option if you want to use the s390 pseudo random number | |
172 | generator. The PRNG is part of the cryptographic processor functions | |
173 | and uses triple-DES to generate secure random numbers like the | |
d393d9b8 JG |
174 | ANSI X9.17 standard. User-space programs access the |
175 | pseudo-random-number device through the char device /dev/prandom. | |
176 | ||
177 | It is available as of z9. | |
3f5615e0 | 178 | |
df1309ce GS |
179 | config CRYPTO_GHASH_S390 |
180 | tristate "GHASH digest algorithm" | |
181 | depends on S390 | |
182 | select CRYPTO_HASH | |
183 | help | |
184 | This is the s390 hardware accelerated implementation of the | |
185 | GHASH message digest algorithm for GCM (Galois/Counter Mode). | |
186 | ||
187 | It is available as of z196. | |
188 | ||
f848dbd3 HB |
189 | config CRYPTO_CRC32_S390 |
190 | tristate "CRC-32 algorithms" | |
191 | depends on S390 | |
192 | select CRYPTO_HASH | |
193 | select CRC32 | |
194 | help | |
195 | Select this option if you want to use hardware accelerated | |
196 | implementations of CRC algorithms. With this option, you | |
197 | can optimize the computation of CRC-32 (IEEE 802.3 Ethernet) | |
198 | and CRC-32C (Castagnoli). | |
199 | ||
200 | It is available with IBM z13 or later. | |
201 | ||
85a7f0ac SAS |
202 | config CRYPTO_DEV_MV_CESA |
203 | tristate "Marvell's Cryptographic Engine" | |
204 | depends on PLAT_ORION | |
85a7f0ac | 205 | select CRYPTO_AES |
596103cf | 206 | select CRYPTO_BLKCIPHER |
1ebfefcf | 207 | select CRYPTO_HASH |
51b44fc8 | 208 | select SRAM |
85a7f0ac SAS |
209 | help |
210 | This driver allows you to utilize the Cryptographic Engines and | |
211 | Security Accelerator (CESA) which can be found on the Marvell Orion | |
212 | and Kirkwood SoCs, such as QNAP's TS-209. | |
213 | ||
214 | Currently the driver supports AES in ECB and CBC mode without DMA. | |
215 | ||
f63601fd BB |
216 | config CRYPTO_DEV_MARVELL_CESA |
217 | tristate "New Marvell's Cryptographic Engine driver" | |
fe55dfdc | 218 | depends on PLAT_ORION || ARCH_MVEBU |
f63601fd BB |
219 | select CRYPTO_AES |
220 | select CRYPTO_DES | |
221 | select CRYPTO_BLKCIPHER | |
222 | select CRYPTO_HASH | |
223 | select SRAM | |
224 | help | |
225 | This driver allows you to utilize the Cryptographic Engines and | |
226 | Security Accelerator (CESA) which can be found on the Armada 370. | |
db509a45 | 227 | This driver supports CPU offload through DMA transfers. |
f63601fd BB |
228 | |
229 | This driver is aimed at replacing the mv_cesa driver. This will only | |
230 | happen once it has received proper testing. | |
231 | ||
0a625fd2 DM |
232 | config CRYPTO_DEV_NIAGARA2 |
233 | tristate "Niagara2 Stream Processing Unit driver" | |
50e78161 | 234 | select CRYPTO_DES |
596103cf HX |
235 | select CRYPTO_BLKCIPHER |
236 | select CRYPTO_HASH | |
8054b800 LC |
237 | select CRYPTO_MD5 |
238 | select CRYPTO_SHA1 | |
239 | select CRYPTO_SHA256 | |
0a625fd2 DM |
240 | depends on SPARC64 |
241 | help | |
242 | Each core of a Niagara2 processor contains a Stream | |
243 | Processing Unit, which itself contains several cryptographic | |
244 | sub-units. One set provides the Modular Arithmetic Unit, | |
245 | used for SSL offload. The other set provides the Cipher | |
246 | Group, which can perform encryption, decryption, hashing, | |
247 | checksumming, and raw copies. | |
248 | ||
f7d0561e EP |
249 | config CRYPTO_DEV_HIFN_795X |
250 | tristate "Driver HIFN 795x crypto accelerator chips" | |
c3041f9c | 251 | select CRYPTO_DES |
653ebd9c | 252 | select CRYPTO_BLKCIPHER |
946fef4e | 253 | select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG |
2707b937 | 254 | depends on PCI |
75b76625 | 255 | depends on !ARCH_DMA_ADDR_T_64BIT |
f7d0561e EP |
256 | help |
257 | This option allows you to have support for HIFN 795x crypto adapters. | |
258 | ||
946fef4e HX |
259 | config CRYPTO_DEV_HIFN_795X_RNG |
260 | bool "HIFN 795x random number generator" | |
261 | depends on CRYPTO_DEV_HIFN_795X | |
262 | help | |
263 | Select this option if you want to enable the random number generator | |
264 | on the HIFN 795x crypto adapters. | |
f7d0561e | 265 | |
8e8ec596 KP |
266 | source drivers/crypto/caam/Kconfig |
267 | ||
9c4a7965 KP |
268 | config CRYPTO_DEV_TALITOS |
269 | tristate "Talitos Freescale Security Engine (SEC)" | |
596103cf | 270 | select CRYPTO_AEAD |
9c4a7965 | 271 | select CRYPTO_AUTHENC |
596103cf HX |
272 | select CRYPTO_BLKCIPHER |
273 | select CRYPTO_HASH | |
9c4a7965 KP |
274 | select HW_RANDOM |
275 | depends on FSL_SOC | |
276 | help | |
277 | Say 'Y' here to use the Freescale Security Engine (SEC) | |
278 | to offload cryptographic algorithm computation. | |
279 | ||
280 | The Freescale SEC is present on PowerQUICC 'E' processors, such | |
281 | as the MPC8349E and MPC8548E. | |
282 | ||
283 | To compile this driver as a module, choose M here: the module | |
284 | will be called talitos. | |
285 | ||
5b841a65 LC |
286 | config CRYPTO_DEV_TALITOS1 |
287 | bool "SEC1 (SEC 1.0 and SEC Lite 1.2)" | |
288 | depends on CRYPTO_DEV_TALITOS | |
289 | depends on PPC_8xx || PPC_82xx | |
290 | default y | |
291 | help | |
292 | Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0 | |
293 | found on MPC82xx or the Freescale Security Engine (SEC Lite) | |
294 | version 1.2 found on MPC8xx | |
295 | ||
296 | config CRYPTO_DEV_TALITOS2 | |
297 | bool "SEC2+ (SEC version 2.0 or upper)" | |
298 | depends on CRYPTO_DEV_TALITOS | |
299 | default y if !PPC_8xx | |
300 | help | |
301 | Say 'Y' here to use the Freescale Security Engine (SEC) | |
302 | version 2 and following as found on MPC83xx, MPC85xx, etc ... | |
303 | ||
81bef015 CH |
304 | config CRYPTO_DEV_IXP4XX |
305 | tristate "Driver for IXP4xx crypto hardware acceleration" | |
9665c52b | 306 | depends on ARCH_IXP4XX && IXP4XX_QMGR && IXP4XX_NPE |
81bef015 | 307 | select CRYPTO_DES |
596103cf | 308 | select CRYPTO_AEAD |
090657e4 | 309 | select CRYPTO_AUTHENC |
81bef015 CH |
310 | select CRYPTO_BLKCIPHER |
311 | help | |
312 | Driver for the IXP4xx NPE crypto engine. | |
313 | ||
049359d6 JH |
314 | config CRYPTO_DEV_PPC4XX |
315 | tristate "Driver AMCC PPC4xx crypto accelerator" | |
316 | depends on PPC && 4xx | |
317 | select CRYPTO_HASH | |
049359d6 JH |
318 | select CRYPTO_BLKCIPHER |
319 | help | |
320 | This option allows you to have support for AMCC crypto acceleration. | |
321 | ||
5343e674 CL |
322 | config HW_RANDOM_PPC4XX |
323 | bool "PowerPC 4xx generic true random number generator support" | |
324 | depends on CRYPTO_DEV_PPC4XX && HW_RANDOM | |
325 | default y | |
326 | ---help--- | |
327 | This option provides the kernel-side support for the TRNG hardware | |
328 | found in the security function of some PowerPC 4xx SoCs. | |
329 | ||
74ed87e7 TK |
330 | config CRYPTO_DEV_OMAP |
331 | tristate "Support for OMAP crypto HW accelerators" | |
332 | depends on ARCH_OMAP2PLUS | |
333 | help | |
334 | OMAP processors have various crypto HW accelerators. Select this if | |
335 | you want to use the OMAP modules for any of the crypto algorithms. | |
336 | ||
337 | if CRYPTO_DEV_OMAP | |
338 | ||
8628e7c8 | 339 | config CRYPTO_DEV_OMAP_SHAM |
eaef7e3f LV |
340 | tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator" |
341 | depends on ARCH_OMAP2PLUS | |
8628e7c8 DK |
342 | select CRYPTO_SHA1 |
343 | select CRYPTO_MD5 | |
eaef7e3f LV |
344 | select CRYPTO_SHA256 |
345 | select CRYPTO_SHA512 | |
346 | select CRYPTO_HMAC | |
8628e7c8 | 347 | help |
eaef7e3f LV |
348 | OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you |
349 | want to use the OMAP module for MD5/SHA1/SHA2 algorithms. | |
8628e7c8 | 350 | |
537559a5 DK |
351 | config CRYPTO_DEV_OMAP_AES |
352 | tristate "Support for OMAP AES hw engine" | |
1bbf6437 | 353 | depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP2PLUS |
537559a5 | 354 | select CRYPTO_AES |
596103cf | 355 | select CRYPTO_BLKCIPHER |
0529900a | 356 | select CRYPTO_ENGINE |
9fcb191a LV |
357 | select CRYPTO_CBC |
358 | select CRYPTO_ECB | |
359 | select CRYPTO_CTR | |
ad18cc9d | 360 | select CRYPTO_AEAD |
537559a5 DK |
361 | help |
362 | OMAP processors have AES module accelerator. Select this if you | |
363 | want to use the OMAP module for AES algorithms. | |
364 | ||
701d0f19 | 365 | config CRYPTO_DEV_OMAP_DES |
97ee7ed3 | 366 | tristate "Support for OMAP DES/3DES hw engine" |
701d0f19 JF |
367 | depends on ARCH_OMAP2PLUS |
368 | select CRYPTO_DES | |
596103cf | 369 | select CRYPTO_BLKCIPHER |
f1b77aac | 370 | select CRYPTO_ENGINE |
701d0f19 JF |
371 | help |
372 | OMAP processors have DES/3DES module accelerator. Select this if you | |
373 | want to use the OMAP module for DES and 3DES algorithms. Currently | |
97ee7ed3 PM |
374 | the ECB and CBC modes of operation are supported by the driver. Also |
375 | accesses made on unaligned boundaries are supported. | |
701d0f19 | 376 | |
74ed87e7 TK |
377 | endif # CRYPTO_DEV_OMAP |
378 | ||
ce921368 JI |
379 | config CRYPTO_DEV_PICOXCELL |
380 | tristate "Support for picoXcell IPSEC and Layer2 crypto engines" | |
4f44d86d | 381 | depends on (ARCH_PICOXCELL || COMPILE_TEST) && HAVE_CLK |
596103cf | 382 | select CRYPTO_AEAD |
ce921368 JI |
383 | select CRYPTO_AES |
384 | select CRYPTO_AUTHENC | |
596103cf | 385 | select CRYPTO_BLKCIPHER |
ce921368 JI |
386 | select CRYPTO_DES |
387 | select CRYPTO_CBC | |
388 | select CRYPTO_ECB | |
389 | select CRYPTO_SEQIV | |
390 | help | |
391 | This option enables support for the hardware offload engines in the | |
392 | Picochip picoXcell SoC devices. Select this for IPSEC ESP offload | |
393 | and for 3gpp Layer 2 ciphering support. | |
394 | ||
395 | Saying m here will build a module named pipcoxcell_crypto. | |
396 | ||
5de88752 JM |
397 | config CRYPTO_DEV_SAHARA |
398 | tristate "Support for SAHARA crypto accelerator" | |
74d24d83 | 399 | depends on ARCH_MXC && OF |
5de88752 JM |
400 | select CRYPTO_BLKCIPHER |
401 | select CRYPTO_AES | |
402 | select CRYPTO_ECB | |
403 | help | |
404 | This option enables support for the SAHARA HW crypto accelerator | |
405 | found in some Freescale i.MX chips. | |
406 | ||
d293b640 ST |
407 | config CRYPTO_DEV_MXC_SCC |
408 | tristate "Support for Freescale Security Controller (SCC)" | |
409 | depends on ARCH_MXC && OF | |
410 | select CRYPTO_BLKCIPHER | |
411 | select CRYPTO_DES | |
412 | help | |
413 | This option enables support for the Security Controller (SCC) | |
414 | found in Freescale i.MX25 chips. | |
415 | ||
c46ea13f KK |
416 | config CRYPTO_DEV_EXYNOS_RNG |
417 | tristate "EXYNOS HW pseudo random number generator support" | |
418 | depends on ARCH_EXYNOS || COMPILE_TEST | |
419 | depends on HAS_IOMEM | |
420 | select CRYPTO_RNG | |
421 | ---help--- | |
422 | This driver provides kernel-side support through the | |
423 | cryptographic API for the pseudo random number generator hardware | |
424 | found on Exynos SoCs. | |
425 | ||
426 | To compile this driver as a module, choose M here: the | |
427 | module will be called exynos-rng. | |
428 | ||
429 | If unsure, say Y. | |
430 | ||
a49e490c | 431 | config CRYPTO_DEV_S5P |
e922e96f | 432 | tristate "Support for Samsung S5PV210/Exynos crypto accelerator" |
dc1d9dee KK |
433 | depends on ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST |
434 | depends on HAS_IOMEM && HAS_DMA | |
a49e490c | 435 | select CRYPTO_AES |
a49e490c VZ |
436 | select CRYPTO_BLKCIPHER |
437 | help | |
438 | This option allows you to have support for S5P crypto acceleration. | |
e922e96f | 439 | Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES |
a49e490c VZ |
440 | algorithms execution. |
441 | ||
aef7b31c | 442 | config CRYPTO_DEV_NX |
7011a122 DS |
443 | bool "Support for IBM PowerPC Nest (NX) cryptographic acceleration" |
444 | depends on PPC64 | |
aef7b31c | 445 | help |
7011a122 DS |
446 | This enables support for the NX hardware cryptographic accelerator |
447 | coprocessor that is in IBM PowerPC P7+ or later processors. This | |
448 | does not actually enable any drivers, it only allows you to select | |
449 | which acceleration type (encryption and/or compression) to enable. | |
322cacce SJ |
450 | |
451 | if CRYPTO_DEV_NX | |
452 | source "drivers/crypto/nx/Kconfig" | |
453 | endif | |
aef7b31c | 454 | |
2789c08f AW |
455 | config CRYPTO_DEV_UX500 |
456 | tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration" | |
457 | depends on ARCH_U8500 | |
2789c08f AW |
458 | help |
459 | Driver for ST-Ericsson UX500 crypto engine. | |
460 | ||
461 | if CRYPTO_DEV_UX500 | |
462 | source "drivers/crypto/ux500/Kconfig" | |
463 | endif # if CRYPTO_DEV_UX500 | |
464 | ||
b8840098 SZ |
465 | config CRYPTO_DEV_BFIN_CRC |
466 | tristate "Support for Blackfin CRC hardware" | |
467 | depends on BF60x | |
468 | help | |
469 | Newer Blackfin processors have CRC hardware. Select this if you | |
470 | want to use the Blackfin CRC module. | |
471 | ||
89a82ef8 CP |
472 | config CRYPTO_DEV_ATMEL_AUTHENC |
473 | tristate "Support for Atmel IPSEC/SSL hw accelerator" | |
ceb4afb3 AB |
474 | depends on HAS_DMA |
475 | depends on ARCH_AT91 || COMPILE_TEST | |
89a82ef8 CP |
476 | select CRYPTO_AUTHENC |
477 | select CRYPTO_DEV_ATMEL_AES | |
478 | select CRYPTO_DEV_ATMEL_SHA | |
479 | help | |
480 | Some Atmel processors can combine the AES and SHA hw accelerators | |
481 | to enhance support of IPSEC/SSL. | |
482 | Select this if you want to use the Atmel modules for | |
483 | authenc(hmac(shaX),Y(cbc)) algorithms. | |
484 | ||
bd3c7b5c NR |
485 | config CRYPTO_DEV_ATMEL_AES |
486 | tristate "Support for Atmel AES hw accelerator" | |
cbafd643 | 487 | depends on HAS_DMA |
ceb4afb3 | 488 | depends on ARCH_AT91 || COMPILE_TEST |
bd3c7b5c | 489 | select CRYPTO_AES |
d4419548 | 490 | select CRYPTO_AEAD |
bd3c7b5c | 491 | select CRYPTO_BLKCIPHER |
bd3c7b5c NR |
492 | help |
493 | Some Atmel processors have AES hw accelerator. | |
494 | Select this if you want to use the Atmel module for | |
495 | AES algorithms. | |
496 | ||
497 | To compile this driver as a module, choose M here: the module | |
498 | will be called atmel-aes. | |
499 | ||
13802005 NR |
500 | config CRYPTO_DEV_ATMEL_TDES |
501 | tristate "Support for Atmel DES/TDES hw accelerator" | |
f7f9482e | 502 | depends on HAS_DMA |
ceb4afb3 | 503 | depends on ARCH_AT91 || COMPILE_TEST |
13802005 | 504 | select CRYPTO_DES |
13802005 NR |
505 | select CRYPTO_BLKCIPHER |
506 | help | |
507 | Some Atmel processors have DES/TDES hw accelerator. | |
508 | Select this if you want to use the Atmel module for | |
509 | DES/TDES algorithms. | |
510 | ||
511 | To compile this driver as a module, choose M here: the module | |
512 | will be called atmel-tdes. | |
513 | ||
ebc82efa | 514 | config CRYPTO_DEV_ATMEL_SHA |
d4905b38 | 515 | tristate "Support for Atmel SHA hw accelerator" |
f7f9482e | 516 | depends on HAS_DMA |
ceb4afb3 | 517 | depends on ARCH_AT91 || COMPILE_TEST |
596103cf | 518 | select CRYPTO_HASH |
ebc82efa | 519 | help |
d4905b38 NR |
520 | Some Atmel processors have SHA1/SHA224/SHA256/SHA384/SHA512 |
521 | hw accelerator. | |
ebc82efa | 522 | Select this if you want to use the Atmel module for |
d4905b38 | 523 | SHA1/SHA224/SHA256/SHA384/SHA512 algorithms. |
ebc82efa NR |
524 | |
525 | To compile this driver as a module, choose M here: the module | |
526 | will be called atmel-sha. | |
527 | ||
f1147660 TL |
528 | config CRYPTO_DEV_CCP |
529 | bool "Support for AMD Cryptographic Coprocessor" | |
6c506343 | 530 | depends on ((X86 && PCI) || (ARM64 && (OF_ADDRESS || ACPI))) && HAS_IOMEM |
f1147660 | 531 | help |
21dc9e8f | 532 | The AMD Cryptographic Coprocessor provides hardware offload support |
f1147660 TL |
533 | for encryption, hashing and related operations. |
534 | ||
535 | if CRYPTO_DEV_CCP | |
536 | source "drivers/crypto/ccp/Kconfig" | |
537 | endif | |
538 | ||
15b59e7c MV |
539 | config CRYPTO_DEV_MXS_DCP |
540 | tristate "Support for Freescale MXS DCP" | |
a2712e6c | 541 | depends on (ARCH_MXS || ARCH_MXC) |
dc97fa02 | 542 | select STMP_DEVICE |
15b59e7c MV |
543 | select CRYPTO_CBC |
544 | select CRYPTO_ECB | |
545 | select CRYPTO_AES | |
546 | select CRYPTO_BLKCIPHER | |
596103cf | 547 | select CRYPTO_HASH |
15b59e7c MV |
548 | help |
549 | The Freescale i.MX23/i.MX28 has SHA1/SHA256 and AES128 CBC/ECB | |
550 | co-processor on the die. | |
551 | ||
552 | To compile this driver as a module, choose M here: the module | |
553 | will be called mxs-dcp. | |
554 | ||
cea4001a | 555 | source "drivers/crypto/qat/Kconfig" |
62ad8b5c | 556 | source "drivers/crypto/cavium/cpt/Kconfig" |
14fa93cd | 557 | source "drivers/crypto/cavium/nitrox/Kconfig" |
c672752d | 558 | |
640035a2 MC |
559 | config CRYPTO_DEV_CAVIUM_ZIP |
560 | tristate "Cavium ZIP driver" | |
561 | depends on PCI && 64BIT && (ARM64 || COMPILE_TEST) | |
562 | ---help--- | |
563 | Select this option if you want to enable compression/decompression | |
564 | acceleration on Cavium's ARM based SoCs | |
565 | ||
c672752d SV |
566 | config CRYPTO_DEV_QCE |
567 | tristate "Qualcomm crypto engine accelerator" | |
71d932d9 | 568 | depends on (ARCH_QCOM || COMPILE_TEST) && HAS_DMA && HAS_IOMEM |
c672752d SV |
569 | select CRYPTO_AES |
570 | select CRYPTO_DES | |
571 | select CRYPTO_ECB | |
572 | select CRYPTO_CBC | |
573 | select CRYPTO_XTS | |
574 | select CRYPTO_CTR | |
c672752d SV |
575 | select CRYPTO_BLKCIPHER |
576 | help | |
577 | This driver supports Qualcomm crypto engine accelerator | |
578 | hardware. To compile this driver as a module, choose M here. The | |
579 | module will be called qcrypto. | |
580 | ||
d2e3ae6f LB |
581 | config CRYPTO_DEV_VMX |
582 | bool "Support for VMX cryptographic acceleration instructions" | |
f1ab4287 | 583 | depends on PPC64 && VSX |
d2e3ae6f LB |
584 | help |
585 | Support for VMX cryptographic acceleration instructions. | |
586 | ||
587 | source "drivers/crypto/vmx/Kconfig" | |
588 | ||
d358f1ab | 589 | config CRYPTO_DEV_IMGTEC_HASH |
d358f1ab | 590 | tristate "Imagination Technologies hardware hash accelerator" |
8c98ebd7 GU |
591 | depends on MIPS || COMPILE_TEST |
592 | depends on HAS_DMA | |
d358f1ab JH |
593 | select CRYPTO_MD5 |
594 | select CRYPTO_SHA1 | |
d358f1ab JH |
595 | select CRYPTO_SHA256 |
596 | select CRYPTO_HASH | |
597 | help | |
598 | This driver interfaces with the Imagination Technologies | |
599 | hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256 | |
600 | hashing algorithms. | |
601 | ||
6298e948 LC |
602 | config CRYPTO_DEV_SUN4I_SS |
603 | tristate "Support for Allwinner Security System cryptographic accelerator" | |
f823ab93 | 604 | depends on ARCH_SUNXI && !64BIT |
6298e948 LC |
605 | select CRYPTO_MD5 |
606 | select CRYPTO_SHA1 | |
607 | select CRYPTO_AES | |
608 | select CRYPTO_DES | |
609 | select CRYPTO_BLKCIPHER | |
610 | help | |
611 | Some Allwinner SoC have a crypto accelerator named | |
612 | Security System. Select this if you want to use it. | |
613 | The Security System handle AES/DES/3DES ciphers in CBC mode | |
614 | and SHA1 and MD5 hash algorithms. | |
615 | ||
616 | To compile this driver as a module, choose M here: the module | |
617 | will be called sun4i-ss. | |
618 | ||
433cd2c6 ZW |
619 | config CRYPTO_DEV_ROCKCHIP |
620 | tristate "Rockchip's Cryptographic Engine driver" | |
621 | depends on OF && ARCH_ROCKCHIP | |
622 | select CRYPTO_AES | |
623 | select CRYPTO_DES | |
bfd927ff ZW |
624 | select CRYPTO_MD5 |
625 | select CRYPTO_SHA1 | |
626 | select CRYPTO_SHA256 | |
627 | select CRYPTO_HASH | |
433cd2c6 ZW |
628 | select CRYPTO_BLKCIPHER |
629 | ||
630 | help | |
631 | This driver interfaces with the hardware crypto accelerator. | |
632 | Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode. | |
633 | ||
785e5c61 RL |
634 | config CRYPTO_DEV_MEDIATEK |
635 | tristate "MediaTek's EIP97 Cryptographic Engine driver" | |
c884b368 | 636 | depends on HAS_DMA |
7dee9f61 | 637 | depends on (ARM && ARCH_MEDIATEK) || COMPILE_TEST |
785e5c61 | 638 | select CRYPTO_AES |
d03f7b0d | 639 | select CRYPTO_AEAD |
785e5c61 | 640 | select CRYPTO_BLKCIPHER |
d03f7b0d | 641 | select CRYPTO_CTR |
7dee9f61 AB |
642 | select CRYPTO_SHA1 |
643 | select CRYPTO_SHA256 | |
644 | select CRYPTO_SHA512 | |
785e5c61 RL |
645 | select CRYPTO_HMAC |
646 | help | |
647 | This driver allows you to utilize the hardware crypto accelerator | |
648 | EIP97 which can be found on the MT7623 MT2701, MT8521p, etc .... | |
649 | Select this if you want to use it for AES/SHA1/SHA2 algorithms. | |
650 | ||
02038fd6 HS |
651 | source "drivers/crypto/chelsio/Kconfig" |
652 | ||
dbaf0624 G |
653 | source "drivers/crypto/virtio/Kconfig" |
654 | ||
9d12ba86 RR |
655 | config CRYPTO_DEV_BCM_SPU |
656 | tristate "Broadcom symmetric crypto/hash acceleration support" | |
657 | depends on ARCH_BCM_IPROC | |
efc856ed | 658 | depends on MAILBOX |
9d12ba86 RR |
659 | default m |
660 | select CRYPTO_DES | |
661 | select CRYPTO_MD5 | |
662 | select CRYPTO_SHA1 | |
663 | select CRYPTO_SHA256 | |
664 | select CRYPTO_SHA512 | |
665 | help | |
666 | This driver provides support for Broadcom crypto acceleration using the | |
667 | Secure Processing Unit (SPU). The SPU driver registers ablkcipher, | |
668 | ahash, and aead algorithms with the kernel cryptographic API. | |
669 | ||
b51dbe90 FD |
670 | source "drivers/crypto/stm32/Kconfig" |
671 | ||
1b44c5a6 AT |
672 | config CRYPTO_DEV_SAFEXCEL |
673 | tristate "Inside Secure's SafeXcel cryptographic engine driver" | |
674 | depends on HAS_DMA && OF | |
675 | depends on (ARM64 && ARCH_MVEBU) || (COMPILE_TEST && 64BIT) | |
676 | select CRYPTO_AES | |
677 | select CRYPTO_BLKCIPHER | |
678 | select CRYPTO_HASH | |
679 | select CRYPTO_HMAC | |
680 | select CRYPTO_SHA1 | |
681 | select CRYPTO_SHA256 | |
682 | select CRYPTO_SHA512 | |
683 | help | |
684 | This driver interfaces with the SafeXcel EIP-197 cryptographic engine | |
685 | designed by Inside Secure. Select this if you want to use CBC/ECB | |
686 | chain mode, AES cipher mode and SHA1/SHA224/SHA256/SHA512 hash | |
687 | algorithms. | |
688 | ||
b511431d | 689 | endif # CRYPTO_HW |