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ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
b511431d JE |
2 | |
3 | menuconfig CRYPTO_HW | |
4 | bool "Hardware crypto devices" | |
5 | default y | |
a7f7f624 | 6 | help |
06bfb7eb JE |
7 | Say Y here to get to see options for hardware crypto devices and |
8 | processors. This option alone does not add any kernel code. | |
9 | ||
10 | If you say N, all options in this submenu will be skipped and disabled. | |
b511431d JE |
11 | |
12 | if CRYPTO_HW | |
1da177e4 | 13 | |
3914b931 CL |
14 | source "drivers/crypto/allwinner/Kconfig" |
15 | ||
1da177e4 | 16 | config CRYPTO_DEV_PADLOCK |
d158325e | 17 | tristate "Support for VIA PadLock ACE" |
2f817418 | 18 | depends on X86 && !UML |
1da177e4 LT |
19 | help |
20 | Some VIA processors come with an integrated crypto engine | |
21 | (so called VIA PadLock ACE, Advanced Cryptography Engine) | |
1191f0a4 ML |
22 | that provides instructions for very fast cryptographic |
23 | operations with supported algorithms. | |
1da177e4 LT |
24 | |
25 | The instructions are used only when the CPU supports them. | |
5644bda5 ML |
26 | Otherwise software encryption is used. |
27 | ||
1da177e4 | 28 | config CRYPTO_DEV_PADLOCK_AES |
1191f0a4 | 29 | tristate "PadLock driver for AES algorithm" |
1da177e4 | 30 | depends on CRYPTO_DEV_PADLOCK |
b95bba5d | 31 | select CRYPTO_SKCIPHER |
8131878d | 32 | select CRYPTO_LIB_AES |
1da177e4 LT |
33 | help |
34 | Use VIA PadLock for AES algorithm. | |
35 | ||
1191f0a4 ML |
36 | Available in VIA C3 and newer CPUs. |
37 | ||
38 | If unsure say M. The compiled module will be | |
4737f097 | 39 | called padlock-aes. |
1191f0a4 | 40 | |
6c833275 ML |
41 | config CRYPTO_DEV_PADLOCK_SHA |
42 | tristate "PadLock driver for SHA1 and SHA256 algorithms" | |
43 | depends on CRYPTO_DEV_PADLOCK | |
bbbee467 | 44 | select CRYPTO_HASH |
6c833275 ML |
45 | select CRYPTO_SHA1 |
46 | select CRYPTO_SHA256 | |
6c833275 ML |
47 | help |
48 | Use VIA PadLock for SHA1/SHA256 algorithms. | |
49 | ||
50 | Available in VIA C7 and newer processors. | |
51 | ||
52 | If unsure say M. The compiled module will be | |
4737f097 | 53 | called padlock-sha. |
6c833275 | 54 | |
9fe757b0 JC |
55 | config CRYPTO_DEV_GEODE |
56 | tristate "Support for the Geode LX AES engine" | |
f6259dea | 57 | depends on X86_32 && PCI |
9fe757b0 | 58 | select CRYPTO_ALGAPI |
b95bba5d | 59 | select CRYPTO_SKCIPHER |
9fe757b0 JC |
60 | help |
61 | Say 'Y' here to use the AMD Geode LX processor on-board AES | |
3dde6ad8 | 62 | engine for the CryptoAPI AES algorithm. |
9fe757b0 JC |
63 | |
64 | To compile this driver as a module, choose M here: the module | |
65 | will be called geode-aes. | |
66 | ||
61d48c2c | 67 | config ZCRYPT |
a3358e3d | 68 | tristate "Support for s390 cryptographic adapters" |
61d48c2c | 69 | depends on S390 |
2f7c8bd6 | 70 | select HW_RANDOM |
61d48c2c | 71 | help |
a3358e3d HF |
72 | Select this option if you want to enable support for |
73 | s390 cryptographic adapters like: | |
0ae88ccf HF |
74 | + Crypto Express 2 up to 7 Coprocessor (CEXxC) |
75 | + Crypto Express 2 up to 7 Accelerator (CEXxA) | |
76 | + Crypto Express 4 up to 7 EP11 Coprocessor (CEXxP) | |
77 | ||
78 | config ZCRYPT_DEBUG | |
79 | bool "Enable debug features for s390 cryptographic adapters" | |
80 | default n | |
81 | depends on DEBUG_KERNEL | |
82 | depends on ZCRYPT | |
83 | help | |
84 | Say 'Y' here to enable some additional debug features on the | |
85 | s390 cryptographic adapters driver. | |
86 | ||
87 | There will be some more sysfs attributes displayed for ap cards | |
88 | and queues and some flags on crypto requests are interpreted as | |
89 | debugging messages to force error injection. | |
90 | ||
91 | Do not enable on production level kernel build. | |
92 | ||
93 | If unsure, say N. | |
61d48c2c | 94 | |
00fab235 HF |
95 | config ZCRYPT_MULTIDEVNODES |
96 | bool "Support for multiple zcrypt device nodes" | |
97 | default y | |
98 | depends on S390 | |
99 | depends on ZCRYPT | |
100 | help | |
101 | With this option enabled the zcrypt device driver can | |
102 | provide multiple devices nodes in /dev. Each device | |
103 | node can get customized to limit access and narrow | |
104 | down the use of the available crypto hardware. | |
105 | ||
e80d4af0 HF |
106 | config PKEY |
107 | tristate "Kernel API for protected key handling" | |
108 | depends on S390 | |
109 | depends on ZCRYPT | |
110 | help | |
111 | With this option enabled the pkey kernel module provides an API | |
112 | for creation and handling of protected keys. Other parts of the | |
113 | kernel or userspace applications may use these functions. | |
114 | ||
115 | Select this option if you want to enable the kernel and userspace | |
116 | API for proteced key handling. | |
117 | ||
118 | Please note that creation of protected keys from secure keys | |
119 | requires to have at least one CEX card in coprocessor mode | |
120 | available at runtime. | |
61d48c2c | 121 | |
c4684f98 HF |
122 | config CRYPTO_PAES_S390 |
123 | tristate "PAES cipher algorithms" | |
124 | depends on S390 | |
125 | depends on ZCRYPT | |
126 | depends on PKEY | |
127 | select CRYPTO_ALGAPI | |
b95bba5d | 128 | select CRYPTO_SKCIPHER |
c4684f98 HF |
129 | help |
130 | This is the s390 hardware accelerated implementation of the | |
131 | AES cipher algorithms for use with protected key. | |
132 | ||
133 | Select this option if you want to use the paes cipher | |
134 | for example to use protected key encrypted devices. | |
135 | ||
3f5615e0 JG |
136 | config CRYPTO_SHA1_S390 |
137 | tristate "SHA1 digest algorithm" | |
138 | depends on S390 | |
563f346d | 139 | select CRYPTO_HASH |
3f5615e0 JG |
140 | help |
141 | This is the s390 hardware accelerated implementation of the | |
142 | SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). | |
143 | ||
d393d9b8 JG |
144 | It is available as of z990. |
145 | ||
3f5615e0 JG |
146 | config CRYPTO_SHA256_S390 |
147 | tristate "SHA256 digest algorithm" | |
148 | depends on S390 | |
563f346d | 149 | select CRYPTO_HASH |
3f5615e0 JG |
150 | help |
151 | This is the s390 hardware accelerated implementation of the | |
152 | SHA256 secure hash standard (DFIPS 180-2). | |
153 | ||
d393d9b8 | 154 | It is available as of z9. |
3f5615e0 | 155 | |
291dc7c0 | 156 | config CRYPTO_SHA512_S390 |
4e2c6d7f | 157 | tristate "SHA384 and SHA512 digest algorithm" |
291dc7c0 | 158 | depends on S390 |
563f346d | 159 | select CRYPTO_HASH |
291dc7c0 JG |
160 | help |
161 | This is the s390 hardware accelerated implementation of the | |
162 | SHA512 secure hash standard. | |
163 | ||
d393d9b8 | 164 | It is available as of z10. |
291dc7c0 | 165 | |
3c2eb6b7 JS |
166 | config CRYPTO_SHA3_256_S390 |
167 | tristate "SHA3_224 and SHA3_256 digest algorithm" | |
168 | depends on S390 | |
169 | select CRYPTO_HASH | |
170 | help | |
171 | This is the s390 hardware accelerated implementation of the | |
172 | SHA3_256 secure hash standard. | |
173 | ||
174 | It is available as of z14. | |
175 | ||
176 | config CRYPTO_SHA3_512_S390 | |
177 | tristate "SHA3_384 and SHA3_512 digest algorithm" | |
178 | depends on S390 | |
179 | select CRYPTO_HASH | |
180 | help | |
181 | This is the s390 hardware accelerated implementation of the | |
182 | SHA3_512 secure hash standard. | |
183 | ||
184 | It is available as of z14. | |
185 | ||
3f5615e0 JG |
186 | config CRYPTO_DES_S390 |
187 | tristate "DES and Triple DES cipher algorithms" | |
188 | depends on S390 | |
189 | select CRYPTO_ALGAPI | |
b95bba5d | 190 | select CRYPTO_SKCIPHER |
04007b0e | 191 | select CRYPTO_LIB_DES |
3f5615e0 | 192 | help |
0200f3ec | 193 | This is the s390 hardware accelerated implementation of the |
3f5615e0 JG |
194 | DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). |
195 | ||
0200f3ec GS |
196 | As of z990 the ECB and CBC mode are hardware accelerated. |
197 | As of z196 the CTR mode is hardware accelerated. | |
198 | ||
3f5615e0 JG |
199 | config CRYPTO_AES_S390 |
200 | tristate "AES cipher algorithms" | |
201 | depends on S390 | |
202 | select CRYPTO_ALGAPI | |
b95bba5d | 203 | select CRYPTO_SKCIPHER |
3f5615e0 JG |
204 | help |
205 | This is the s390 hardware accelerated implementation of the | |
99d97222 GS |
206 | AES cipher algorithms (FIPS-197). |
207 | ||
208 | As of z9 the ECB and CBC modes are hardware accelerated | |
209 | for 128 bit keys. | |
210 | As of z10 the ECB and CBC modes are hardware accelerated | |
211 | for all AES key sizes. | |
0200f3ec GS |
212 | As of z196 the CTR mode is hardware accelerated for all AES |
213 | key sizes and XTS mode is hardware accelerated for 256 and | |
99d97222 | 214 | 512 bit keys. |
3f5615e0 | 215 | |
ecc8b558 PS |
216 | config CRYPTO_CHACHA_S390 |
217 | tristate "ChaCha20 stream cipher" | |
218 | depends on S390 | |
219 | select CRYPTO_ALGAPI | |
220 | select CRYPTO_SKCIPHER | |
221 | select CRYPTO_CHACHA20 | |
222 | help | |
223 | This is the s390 SIMD implementation of the ChaCha20 stream | |
224 | cipher (RFC 7539). | |
225 | ||
226 | It is available as of z13. | |
227 | ||
3f5615e0 JG |
228 | config S390_PRNG |
229 | tristate "Pseudo random number generator device driver" | |
230 | depends on S390 | |
231 | default "m" | |
232 | help | |
233 | Select this option if you want to use the s390 pseudo random number | |
234 | generator. The PRNG is part of the cryptographic processor functions | |
235 | and uses triple-DES to generate secure random numbers like the | |
d393d9b8 JG |
236 | ANSI X9.17 standard. User-space programs access the |
237 | pseudo-random-number device through the char device /dev/prandom. | |
238 | ||
239 | It is available as of z9. | |
3f5615e0 | 240 | |
df1309ce | 241 | config CRYPTO_GHASH_S390 |
8dfa20fc | 242 | tristate "GHASH hash function" |
df1309ce GS |
243 | depends on S390 |
244 | select CRYPTO_HASH | |
245 | help | |
8dfa20fc EB |
246 | This is the s390 hardware accelerated implementation of GHASH, |
247 | the hash function used in GCM (Galois/Counter mode). | |
df1309ce GS |
248 | |
249 | It is available as of z196. | |
250 | ||
f848dbd3 HB |
251 | config CRYPTO_CRC32_S390 |
252 | tristate "CRC-32 algorithms" | |
253 | depends on S390 | |
254 | select CRYPTO_HASH | |
255 | select CRC32 | |
256 | help | |
257 | Select this option if you want to use hardware accelerated | |
258 | implementations of CRC algorithms. With this option, you | |
259 | can optimize the computation of CRC-32 (IEEE 802.3 Ethernet) | |
260 | and CRC-32C (Castagnoli). | |
261 | ||
262 | It is available with IBM z13 or later. | |
263 | ||
0a625fd2 | 264 | config CRYPTO_DEV_NIAGARA2 |
2452cfdf KK |
265 | tristate "Niagara2 Stream Processing Unit driver" |
266 | select CRYPTO_LIB_DES | |
267 | select CRYPTO_SKCIPHER | |
268 | select CRYPTO_HASH | |
269 | select CRYPTO_MD5 | |
270 | select CRYPTO_SHA1 | |
271 | select CRYPTO_SHA256 | |
272 | depends on SPARC64 | |
273 | help | |
0a625fd2 DM |
274 | Each core of a Niagara2 processor contains a Stream |
275 | Processing Unit, which itself contains several cryptographic | |
276 | sub-units. One set provides the Modular Arithmetic Unit, | |
277 | used for SSL offload. The other set provides the Cipher | |
278 | Group, which can perform encryption, decryption, hashing, | |
279 | checksumming, and raw copies. | |
280 | ||
46c5338d | 281 | config CRYPTO_DEV_SL3516 |
df941fdd | 282 | tristate "Storlink SL3516 crypto offloader" |
e29dd5c8 GU |
283 | depends on ARCH_GEMINI || COMPILE_TEST |
284 | depends on HAS_IOMEM && PM | |
46c5338d CL |
285 | select CRYPTO_SKCIPHER |
286 | select CRYPTO_ENGINE | |
287 | select CRYPTO_ECB | |
288 | select CRYPTO_AES | |
289 | select HW_RANDOM | |
290 | help | |
291 | This option allows you to have support for SL3516 crypto offloader. | |
292 | ||
293 | config CRYPTO_DEV_SL3516_DEBUG | |
294 | bool "Enable SL3516 stats" | |
295 | depends on CRYPTO_DEV_SL3516 | |
296 | depends on DEBUG_FS | |
297 | help | |
298 | Say y to enable SL3516 debug stats. | |
299 | This will create /sys/kernel/debug/sl3516/stats for displaying | |
300 | the number of requests per algorithm and other internal stats. | |
301 | ||
f7d0561e EP |
302 | config CRYPTO_DEV_HIFN_795X |
303 | tristate "Driver HIFN 795x crypto accelerator chips" | |
04007b0e | 304 | select CRYPTO_LIB_DES |
b95bba5d | 305 | select CRYPTO_SKCIPHER |
946fef4e | 306 | select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG |
2707b937 | 307 | depends on PCI |
75b76625 | 308 | depends on !ARCH_DMA_ADDR_T_64BIT |
f7d0561e EP |
309 | help |
310 | This option allows you to have support for HIFN 795x crypto adapters. | |
311 | ||
946fef4e HX |
312 | config CRYPTO_DEV_HIFN_795X_RNG |
313 | bool "HIFN 795x random number generator" | |
314 | depends on CRYPTO_DEV_HIFN_795X | |
315 | help | |
316 | Select this option if you want to enable the random number generator | |
317 | on the HIFN 795x crypto adapters. | |
f7d0561e | 318 | |
8636a1f9 | 319 | source "drivers/crypto/caam/Kconfig" |
8e8ec596 | 320 | |
9c4a7965 KP |
321 | config CRYPTO_DEV_TALITOS |
322 | tristate "Talitos Freescale Security Engine (SEC)" | |
596103cf | 323 | select CRYPTO_AEAD |
9c4a7965 | 324 | select CRYPTO_AUTHENC |
b95bba5d | 325 | select CRYPTO_SKCIPHER |
596103cf | 326 | select CRYPTO_HASH |
dbc2e87b | 327 | select CRYPTO_LIB_DES |
9c4a7965 KP |
328 | select HW_RANDOM |
329 | depends on FSL_SOC | |
330 | help | |
331 | Say 'Y' here to use the Freescale Security Engine (SEC) | |
332 | to offload cryptographic algorithm computation. | |
333 | ||
334 | The Freescale SEC is present on PowerQUICC 'E' processors, such | |
335 | as the MPC8349E and MPC8548E. | |
336 | ||
337 | To compile this driver as a module, choose M here: the module | |
338 | will be called talitos. | |
339 | ||
5b841a65 LC |
340 | config CRYPTO_DEV_TALITOS1 |
341 | bool "SEC1 (SEC 1.0 and SEC Lite 1.2)" | |
342 | depends on CRYPTO_DEV_TALITOS | |
343 | depends on PPC_8xx || PPC_82xx | |
344 | default y | |
345 | help | |
346 | Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0 | |
347 | found on MPC82xx or the Freescale Security Engine (SEC Lite) | |
348 | version 1.2 found on MPC8xx | |
349 | ||
350 | config CRYPTO_DEV_TALITOS2 | |
351 | bool "SEC2+ (SEC version 2.0 or upper)" | |
352 | depends on CRYPTO_DEV_TALITOS | |
353 | default y if !PPC_8xx | |
354 | help | |
355 | Say 'Y' here to use the Freescale Security Engine (SEC) | |
356 | version 2 and following as found on MPC83xx, MPC85xx, etc ... | |
357 | ||
81bef015 CH |
358 | config CRYPTO_DEV_IXP4XX |
359 | tristate "Driver for IXP4xx crypto hardware acceleration" | |
9665c52b | 360 | depends on ARCH_IXP4XX && IXP4XX_QMGR && IXP4XX_NPE |
dfb098d6 CL |
361 | select CRYPTO_AES |
362 | select CRYPTO_DES | |
363 | select CRYPTO_ECB | |
364 | select CRYPTO_CBC | |
365 | select CRYPTO_CTR | |
04007b0e | 366 | select CRYPTO_LIB_DES |
596103cf | 367 | select CRYPTO_AEAD |
090657e4 | 368 | select CRYPTO_AUTHENC |
b95bba5d | 369 | select CRYPTO_SKCIPHER |
81bef015 CH |
370 | help |
371 | Driver for the IXP4xx NPE crypto engine. | |
372 | ||
049359d6 JH |
373 | config CRYPTO_DEV_PPC4XX |
374 | tristate "Driver AMCC PPC4xx crypto accelerator" | |
375 | depends on PPC && 4xx | |
376 | select CRYPTO_HASH | |
a0aae821 | 377 | select CRYPTO_AEAD |
298b4c60 | 378 | select CRYPTO_AES |
da3e7a97 | 379 | select CRYPTO_LIB_AES |
a0aae821 | 380 | select CRYPTO_CCM |
98e87e3d | 381 | select CRYPTO_CTR |
a0aae821 | 382 | select CRYPTO_GCM |
b95bba5d | 383 | select CRYPTO_SKCIPHER |
049359d6 JH |
384 | help |
385 | This option allows you to have support for AMCC crypto acceleration. | |
386 | ||
5343e674 CL |
387 | config HW_RANDOM_PPC4XX |
388 | bool "PowerPC 4xx generic true random number generator support" | |
63b8ee4f | 389 | depends on CRYPTO_DEV_PPC4XX && HW_RANDOM=y |
5343e674 | 390 | default y |
a7f7f624 | 391 | help |
5343e674 CL |
392 | This option provides the kernel-side support for the TRNG hardware |
393 | found in the security function of some PowerPC 4xx SoCs. | |
394 | ||
74ed87e7 TK |
395 | config CRYPTO_DEV_OMAP |
396 | tristate "Support for OMAP crypto HW accelerators" | |
397 | depends on ARCH_OMAP2PLUS | |
398 | help | |
399 | OMAP processors have various crypto HW accelerators. Select this if | |
2452cfdf | 400 | you want to use the OMAP modules for any of the crypto algorithms. |
74ed87e7 TK |
401 | |
402 | if CRYPTO_DEV_OMAP | |
403 | ||
8628e7c8 | 404 | config CRYPTO_DEV_OMAP_SHAM |
eaef7e3f LV |
405 | tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator" |
406 | depends on ARCH_OMAP2PLUS | |
38281194 | 407 | select CRYPTO_ENGINE |
8628e7c8 DK |
408 | select CRYPTO_SHA1 |
409 | select CRYPTO_MD5 | |
eaef7e3f LV |
410 | select CRYPTO_SHA256 |
411 | select CRYPTO_SHA512 | |
412 | select CRYPTO_HMAC | |
8628e7c8 | 413 | help |
eaef7e3f LV |
414 | OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you |
415 | want to use the OMAP module for MD5/SHA1/SHA2 algorithms. | |
8628e7c8 | 416 | |
537559a5 DK |
417 | config CRYPTO_DEV_OMAP_AES |
418 | tristate "Support for OMAP AES hw engine" | |
1bbf6437 | 419 | depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP2PLUS |
537559a5 | 420 | select CRYPTO_AES |
b95bba5d | 421 | select CRYPTO_SKCIPHER |
0529900a | 422 | select CRYPTO_ENGINE |
9fcb191a LV |
423 | select CRYPTO_CBC |
424 | select CRYPTO_ECB | |
425 | select CRYPTO_CTR | |
ad18cc9d | 426 | select CRYPTO_AEAD |
537559a5 DK |
427 | help |
428 | OMAP processors have AES module accelerator. Select this if you | |
429 | want to use the OMAP module for AES algorithms. | |
430 | ||
701d0f19 | 431 | config CRYPTO_DEV_OMAP_DES |
97ee7ed3 | 432 | tristate "Support for OMAP DES/3DES hw engine" |
701d0f19 | 433 | depends on ARCH_OMAP2PLUS |
04007b0e | 434 | select CRYPTO_LIB_DES |
b95bba5d | 435 | select CRYPTO_SKCIPHER |
f1b77aac | 436 | select CRYPTO_ENGINE |
701d0f19 JF |
437 | help |
438 | OMAP processors have DES/3DES module accelerator. Select this if you | |
439 | want to use the OMAP module for DES and 3DES algorithms. Currently | |
97ee7ed3 PM |
440 | the ECB and CBC modes of operation are supported by the driver. Also |
441 | accesses made on unaligned boundaries are supported. | |
701d0f19 | 442 | |
74ed87e7 TK |
443 | endif # CRYPTO_DEV_OMAP |
444 | ||
5de88752 JM |
445 | config CRYPTO_DEV_SAHARA |
446 | tristate "Support for SAHARA crypto accelerator" | |
74d24d83 | 447 | depends on ARCH_MXC && OF |
b95bba5d | 448 | select CRYPTO_SKCIPHER |
5de88752 JM |
449 | select CRYPTO_AES |
450 | select CRYPTO_ECB | |
451 | help | |
452 | This option enables support for the SAHARA HW crypto accelerator | |
453 | found in some Freescale i.MX chips. | |
454 | ||
c46ea13f | 455 | config CRYPTO_DEV_EXYNOS_RNG |
b279997f | 456 | tristate "Exynos HW pseudo random number generator support" |
c46ea13f KK |
457 | depends on ARCH_EXYNOS || COMPILE_TEST |
458 | depends on HAS_IOMEM | |
459 | select CRYPTO_RNG | |
a7f7f624 | 460 | help |
c46ea13f KK |
461 | This driver provides kernel-side support through the |
462 | cryptographic API for the pseudo random number generator hardware | |
463 | found on Exynos SoCs. | |
464 | ||
465 | To compile this driver as a module, choose M here: the | |
466 | module will be called exynos-rng. | |
467 | ||
468 | If unsure, say Y. | |
469 | ||
a49e490c | 470 | config CRYPTO_DEV_S5P |
e922e96f | 471 | tristate "Support for Samsung S5PV210/Exynos crypto accelerator" |
dc1d9dee | 472 | depends on ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST |
ee1b23d1 | 473 | depends on HAS_IOMEM |
a49e490c | 474 | select CRYPTO_AES |
b95bba5d | 475 | select CRYPTO_SKCIPHER |
a49e490c VZ |
476 | help |
477 | This option allows you to have support for S5P crypto acceleration. | |
e922e96f | 478 | Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES |
a49e490c VZ |
479 | algorithms execution. |
480 | ||
c2afad6c KK |
481 | config CRYPTO_DEV_EXYNOS_HASH |
482 | bool "Support for Samsung Exynos HASH accelerator" | |
483 | depends on CRYPTO_DEV_S5P | |
484 | depends on !CRYPTO_DEV_EXYNOS_RNG && CRYPTO_DEV_EXYNOS_RNG!=m | |
485 | select CRYPTO_SHA1 | |
486 | select CRYPTO_MD5 | |
487 | select CRYPTO_SHA256 | |
488 | help | |
489 | Select this to offload Exynos from HASH MD5/SHA1/SHA256. | |
490 | This will select software SHA1, MD5 and SHA256 as they are | |
491 | needed for small and zero-size messages. | |
492 | HASH algorithms will be disabled if EXYNOS_RNG | |
493 | is enabled due to hw conflict. | |
494 | ||
aef7b31c | 495 | config CRYPTO_DEV_NX |
7011a122 DS |
496 | bool "Support for IBM PowerPC Nest (NX) cryptographic acceleration" |
497 | depends on PPC64 | |
aef7b31c | 498 | help |
7011a122 DS |
499 | This enables support for the NX hardware cryptographic accelerator |
500 | coprocessor that is in IBM PowerPC P7+ or later processors. This | |
501 | does not actually enable any drivers, it only allows you to select | |
502 | which acceleration type (encryption and/or compression) to enable. | |
322cacce SJ |
503 | |
504 | if CRYPTO_DEV_NX | |
505 | source "drivers/crypto/nx/Kconfig" | |
506 | endif | |
aef7b31c | 507 | |
2789c08f AW |
508 | config CRYPTO_DEV_UX500 |
509 | tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration" | |
510 | depends on ARCH_U8500 | |
2789c08f AW |
511 | help |
512 | Driver for ST-Ericsson UX500 crypto engine. | |
513 | ||
514 | if CRYPTO_DEV_UX500 | |
515 | source "drivers/crypto/ux500/Kconfig" | |
516 | endif # if CRYPTO_DEV_UX500 | |
517 | ||
89a82ef8 | 518 | config CRYPTO_DEV_ATMEL_AUTHENC |
aee1f9f3 | 519 | bool "Support for Atmel IPSEC/SSL hw accelerator" |
ceb4afb3 | 520 | depends on ARCH_AT91 || COMPILE_TEST |
aee1f9f3 | 521 | depends on CRYPTO_DEV_ATMEL_AES |
89a82ef8 CP |
522 | help |
523 | Some Atmel processors can combine the AES and SHA hw accelerators | |
524 | to enhance support of IPSEC/SSL. | |
525 | Select this if you want to use the Atmel modules for | |
526 | authenc(hmac(shaX),Y(cbc)) algorithms. | |
527 | ||
bd3c7b5c NR |
528 | config CRYPTO_DEV_ATMEL_AES |
529 | tristate "Support for Atmel AES hw accelerator" | |
ceb4afb3 | 530 | depends on ARCH_AT91 || COMPILE_TEST |
bd3c7b5c | 531 | select CRYPTO_AES |
d4419548 | 532 | select CRYPTO_AEAD |
b95bba5d | 533 | select CRYPTO_SKCIPHER |
aee1f9f3 Y |
534 | select CRYPTO_AUTHENC if CRYPTO_DEV_ATMEL_AUTHENC |
535 | select CRYPTO_DEV_ATMEL_SHA if CRYPTO_DEV_ATMEL_AUTHENC | |
bd3c7b5c NR |
536 | help |
537 | Some Atmel processors have AES hw accelerator. | |
538 | Select this if you want to use the Atmel module for | |
539 | AES algorithms. | |
540 | ||
541 | To compile this driver as a module, choose M here: the module | |
542 | will be called atmel-aes. | |
543 | ||
13802005 NR |
544 | config CRYPTO_DEV_ATMEL_TDES |
545 | tristate "Support for Atmel DES/TDES hw accelerator" | |
ceb4afb3 | 546 | depends on ARCH_AT91 || COMPILE_TEST |
04007b0e | 547 | select CRYPTO_LIB_DES |
b95bba5d | 548 | select CRYPTO_SKCIPHER |
13802005 NR |
549 | help |
550 | Some Atmel processors have DES/TDES hw accelerator. | |
551 | Select this if you want to use the Atmel module for | |
552 | DES/TDES algorithms. | |
553 | ||
554 | To compile this driver as a module, choose M here: the module | |
555 | will be called atmel-tdes. | |
556 | ||
ebc82efa | 557 | config CRYPTO_DEV_ATMEL_SHA |
d4905b38 | 558 | tristate "Support for Atmel SHA hw accelerator" |
ceb4afb3 | 559 | depends on ARCH_AT91 || COMPILE_TEST |
596103cf | 560 | select CRYPTO_HASH |
ebc82efa | 561 | help |
d4905b38 NR |
562 | Some Atmel processors have SHA1/SHA224/SHA256/SHA384/SHA512 |
563 | hw accelerator. | |
ebc82efa | 564 | Select this if you want to use the Atmel module for |
d4905b38 | 565 | SHA1/SHA224/SHA256/SHA384/SHA512 algorithms. |
ebc82efa NR |
566 | |
567 | To compile this driver as a module, choose M here: the module | |
568 | will be called atmel-sha. | |
569 | ||
c34a3201 AB |
570 | config CRYPTO_DEV_ATMEL_I2C |
571 | tristate | |
d33a23b0 | 572 | select BITREVERSE |
c34a3201 | 573 | |
11105693 TDA |
574 | config CRYPTO_DEV_ATMEL_ECC |
575 | tristate "Support for Microchip / Atmel ECC hw accelerator" | |
11105693 | 576 | depends on I2C |
c34a3201 | 577 | select CRYPTO_DEV_ATMEL_I2C |
11105693 TDA |
578 | select CRYPTO_ECDH |
579 | select CRC16 | |
580 | help | |
581 | Microhip / Atmel ECC hw accelerator. | |
582 | Select this if you want to use the Microchip / Atmel module for | |
583 | ECDH algorithm. | |
584 | ||
585 | To compile this driver as a module, choose M here: the module | |
586 | will be called atmel-ecc. | |
587 | ||
da001fb6 AB |
588 | config CRYPTO_DEV_ATMEL_SHA204A |
589 | tristate "Support for Microchip / Atmel SHA accelerator and RNG" | |
590 | depends on I2C | |
591 | select CRYPTO_DEV_ATMEL_I2C | |
592 | select HW_RANDOM | |
4bb02dbd | 593 | select CRC16 |
da001fb6 AB |
594 | help |
595 | Microhip / Atmel SHA accelerator and RNG. | |
596 | Select this if you want to use the Microchip / Atmel SHA204A | |
597 | module as a random number generator. (Other functions of the | |
598 | chip are currently not exposed by this driver) | |
599 | ||
600 | To compile this driver as a module, choose M here: the module | |
601 | will be called atmel-sha204a. | |
602 | ||
f1147660 | 603 | config CRYPTO_DEV_CCP |
720419f0 | 604 | bool "Support for AMD Secure Processor" |
6c506343 | 605 | depends on ((X86 && PCI) || (ARM64 && (OF_ADDRESS || ACPI))) && HAS_IOMEM |
f1147660 | 606 | help |
720419f0 BS |
607 | The AMD Secure Processor provides support for the Cryptographic Coprocessor |
608 | (CCP) and the Platform Security Processor (PSP) devices. | |
f1147660 TL |
609 | |
610 | if CRYPTO_DEV_CCP | |
611 | source "drivers/crypto/ccp/Kconfig" | |
612 | endif | |
613 | ||
15b59e7c MV |
614 | config CRYPTO_DEV_MXS_DCP |
615 | tristate "Support for Freescale MXS DCP" | |
a2712e6c | 616 | depends on (ARCH_MXS || ARCH_MXC) |
dc97fa02 | 617 | select STMP_DEVICE |
15b59e7c MV |
618 | select CRYPTO_CBC |
619 | select CRYPTO_ECB | |
620 | select CRYPTO_AES | |
b95bba5d | 621 | select CRYPTO_SKCIPHER |
596103cf | 622 | select CRYPTO_HASH |
15b59e7c MV |
623 | help |
624 | The Freescale i.MX23/i.MX28 has SHA1/SHA256 and AES128 CBC/ECB | |
625 | co-processor on the die. | |
626 | ||
627 | To compile this driver as a module, choose M here: the module | |
628 | will be called mxs-dcp. | |
629 | ||
cea4001a | 630 | source "drivers/crypto/qat/Kconfig" |
62ad8b5c | 631 | source "drivers/crypto/cavium/cpt/Kconfig" |
14fa93cd | 632 | source "drivers/crypto/cavium/nitrox/Kconfig" |
655ff1a1 | 633 | source "drivers/crypto/marvell/Kconfig" |
c672752d | 634 | |
640035a2 MC |
635 | config CRYPTO_DEV_CAVIUM_ZIP |
636 | tristate "Cavium ZIP driver" | |
637 | depends on PCI && 64BIT && (ARM64 || COMPILE_TEST) | |
a7f7f624 | 638 | help |
640035a2 MC |
639 | Select this option if you want to enable compression/decompression |
640 | acceleration on Cavium's ARM based SoCs | |
641 | ||
c672752d SV |
642 | config CRYPTO_DEV_QCE |
643 | tristate "Qualcomm crypto engine accelerator" | |
ee1b23d1 GU |
644 | depends on ARCH_QCOM || COMPILE_TEST |
645 | depends on HAS_IOMEM | |
59e056cd EQ |
646 | help |
647 | This driver supports Qualcomm crypto engine accelerator | |
648 | hardware. To compile this driver as a module, choose M here. The | |
649 | module will be called qcrypto. | |
650 | ||
651 | config CRYPTO_DEV_QCE_SKCIPHER | |
652 | bool | |
653 | depends on CRYPTO_DEV_QCE | |
c672752d | 654 | select CRYPTO_AES |
04007b0e | 655 | select CRYPTO_LIB_DES |
c672752d SV |
656 | select CRYPTO_ECB |
657 | select CRYPTO_CBC | |
658 | select CRYPTO_XTS | |
659 | select CRYPTO_CTR | |
b95bba5d | 660 | select CRYPTO_SKCIPHER |
59e056cd EQ |
661 | |
662 | config CRYPTO_DEV_QCE_SHA | |
663 | bool | |
664 | depends on CRYPTO_DEV_QCE | |
8ac1b9cc SM |
665 | select CRYPTO_SHA1 |
666 | select CRYPTO_SHA256 | |
59e056cd | 667 | |
9363efb4 TG |
668 | config CRYPTO_DEV_QCE_AEAD |
669 | bool | |
670 | depends on CRYPTO_DEV_QCE | |
671 | select CRYPTO_AUTHENC | |
672 | select CRYPTO_LIB_DES | |
673 | ||
59e056cd EQ |
674 | choice |
675 | prompt "Algorithms enabled for QCE acceleration" | |
676 | default CRYPTO_DEV_QCE_ENABLE_ALL | |
677 | depends on CRYPTO_DEV_QCE | |
678 | help | |
2e0e386a | 679 | This option allows to choose whether to build support for all algorithms |
59e056cd EQ |
680 | (default), hashes-only, or skciphers-only. |
681 | ||
682 | The QCE engine does not appear to scale as well as the CPU to handle | |
683 | multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the | |
684 | QCE handles only 2 requests in parallel. | |
685 | ||
686 | Ipsec throughput seems to improve when disabling either family of | |
687 | algorithms, sharing the load with the CPU. Enabling skciphers-only | |
688 | appears to work best. | |
689 | ||
690 | config CRYPTO_DEV_QCE_ENABLE_ALL | |
691 | bool "All supported algorithms" | |
692 | select CRYPTO_DEV_QCE_SKCIPHER | |
693 | select CRYPTO_DEV_QCE_SHA | |
9363efb4 | 694 | select CRYPTO_DEV_QCE_AEAD |
59e056cd EQ |
695 | help |
696 | Enable all supported algorithms: | |
697 | - AES (CBC, CTR, ECB, XTS) | |
698 | - 3DES (CBC, ECB) | |
699 | - DES (CBC, ECB) | |
700 | - SHA1, HMAC-SHA1 | |
701 | - SHA256, HMAC-SHA256 | |
702 | ||
703 | config CRYPTO_DEV_QCE_ENABLE_SKCIPHER | |
704 | bool "Symmetric-key ciphers only" | |
705 | select CRYPTO_DEV_QCE_SKCIPHER | |
706 | help | |
707 | Enable symmetric-key ciphers only: | |
708 | - AES (CBC, CTR, ECB, XTS) | |
709 | - 3DES (ECB, CBC) | |
710 | - DES (ECB, CBC) | |
711 | ||
712 | config CRYPTO_DEV_QCE_ENABLE_SHA | |
713 | bool "Hash/HMAC only" | |
714 | select CRYPTO_DEV_QCE_SHA | |
715 | help | |
716 | Enable hashes/HMAC algorithms only: | |
717 | - SHA1, HMAC-SHA1 | |
718 | - SHA256, HMAC-SHA256 | |
719 | ||
9363efb4 TG |
720 | config CRYPTO_DEV_QCE_ENABLE_AEAD |
721 | bool "AEAD algorithms only" | |
722 | select CRYPTO_DEV_QCE_AEAD | |
723 | help | |
724 | Enable AEAD algorithms only: | |
725 | - authenc() | |
726 | - ccm(aes) | |
727 | - rfc4309(ccm(aes)) | |
59e056cd | 728 | endchoice |
c672752d | 729 | |
ce163ba0 EQ |
730 | config CRYPTO_DEV_QCE_SW_MAX_LEN |
731 | int "Default maximum request size to use software for AES" | |
732 | depends on CRYPTO_DEV_QCE && CRYPTO_DEV_QCE_SKCIPHER | |
733 | default 512 | |
734 | help | |
735 | This sets the default maximum request size to perform AES requests | |
736 | using software instead of the crypto engine. It can be changed by | |
737 | setting the aes_sw_max_len parameter. | |
738 | ||
739 | Small blocks are processed faster in software than hardware. | |
740 | Considering the 256-bit ciphers, software is 2-3 times faster than | |
741 | qce at 256-bytes, 30% faster at 512, and about even at 768-bytes. | |
742 | With 128-bit keys, the break-even point would be around 1024-bytes. | |
743 | ||
744 | The default is set a little lower, to 512 bytes, to balance the | |
745 | cost in CPU usage. The minimum recommended setting is 16-bytes | |
746 | (1 AES block), since AES-GCM will fail if you set it lower. | |
747 | Setting this to zero will send all requests to the hardware. | |
748 | ||
749 | Note that 192-bit keys are not supported by the hardware and are | |
750 | always processed by the software fallback, and all DES requests | |
751 | are done by the hardware. | |
752 | ||
ceec5f5b VK |
753 | config CRYPTO_DEV_QCOM_RNG |
754 | tristate "Qualcomm Random Number Generator Driver" | |
755 | depends on ARCH_QCOM || COMPILE_TEST | |
756 | select CRYPTO_RNG | |
757 | help | |
758 | This driver provides support for the Random Number | |
759 | Generator hardware found on Qualcomm SoCs. | |
760 | ||
761 | To compile this driver as a module, choose M here. The | |
2452cfdf | 762 | module will be called qcom-rng. If unsure, say N. |
ceec5f5b | 763 | |
d2e3ae6f LB |
764 | config CRYPTO_DEV_VMX |
765 | bool "Support for VMX cryptographic acceleration instructions" | |
f1ab4287 | 766 | depends on PPC64 && VSX |
d2e3ae6f LB |
767 | help |
768 | Support for VMX cryptographic acceleration instructions. | |
769 | ||
770 | source "drivers/crypto/vmx/Kconfig" | |
771 | ||
d358f1ab | 772 | config CRYPTO_DEV_IMGTEC_HASH |
d358f1ab | 773 | tristate "Imagination Technologies hardware hash accelerator" |
8c98ebd7 | 774 | depends on MIPS || COMPILE_TEST |
d358f1ab JH |
775 | select CRYPTO_MD5 |
776 | select CRYPTO_SHA1 | |
d358f1ab JH |
777 | select CRYPTO_SHA256 |
778 | select CRYPTO_HASH | |
779 | help | |
780 | This driver interfaces with the Imagination Technologies | |
781 | hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256 | |
782 | hashing algorithms. | |
783 | ||
433cd2c6 ZW |
784 | config CRYPTO_DEV_ROCKCHIP |
785 | tristate "Rockchip's Cryptographic Engine driver" | |
786 | depends on OF && ARCH_ROCKCHIP | |
787 | select CRYPTO_AES | |
04007b0e | 788 | select CRYPTO_LIB_DES |
bfd927ff ZW |
789 | select CRYPTO_MD5 |
790 | select CRYPTO_SHA1 | |
791 | select CRYPTO_SHA256 | |
792 | select CRYPTO_HASH | |
b95bba5d | 793 | select CRYPTO_SKCIPHER |
433cd2c6 ZW |
794 | |
795 | help | |
796 | This driver interfaces with the hardware crypto accelerator. | |
797 | Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode. | |
798 | ||
4d96f7d4 KA |
799 | config CRYPTO_DEV_ZYNQMP_AES |
800 | tristate "Support for Xilinx ZynqMP AES hw accelerator" | |
801 | depends on ZYNQMP_FIRMWARE || COMPILE_TEST | |
802 | select CRYPTO_AES | |
803 | select CRYPTO_ENGINE | |
804 | select CRYPTO_AEAD | |
805 | help | |
806 | Xilinx ZynqMP has AES-GCM engine used for symmetric key | |
807 | encryption and decryption. This driver interfaces with AES hw | |
808 | accelerator. Select this if you want to use the ZynqMP module | |
809 | for AES algorithms. | |
810 | ||
02038fd6 HS |
811 | source "drivers/crypto/chelsio/Kconfig" |
812 | ||
dbaf0624 G |
813 | source "drivers/crypto/virtio/Kconfig" |
814 | ||
9d12ba86 RR |
815 | config CRYPTO_DEV_BCM_SPU |
816 | tristate "Broadcom symmetric crypto/hash acceleration support" | |
817 | depends on ARCH_BCM_IPROC | |
efc856ed | 818 | depends on MAILBOX |
9d12ba86 | 819 | default m |
ab57b335 | 820 | select CRYPTO_AUTHENC |
04007b0e | 821 | select CRYPTO_LIB_DES |
9d12ba86 RR |
822 | select CRYPTO_MD5 |
823 | select CRYPTO_SHA1 | |
824 | select CRYPTO_SHA256 | |
825 | select CRYPTO_SHA512 | |
826 | help | |
827 | This driver provides support for Broadcom crypto acceleration using the | |
a9c01cd6 | 828 | Secure Processing Unit (SPU). The SPU driver registers skcipher, |
9d12ba86 RR |
829 | ahash, and aead algorithms with the kernel cryptographic API. |
830 | ||
b51dbe90 FD |
831 | source "drivers/crypto/stm32/Kconfig" |
832 | ||
1b44c5a6 AT |
833 | config CRYPTO_DEV_SAFEXCEL |
834 | tristate "Inside Secure's SafeXcel cryptographic engine driver" | |
6dc0e310 | 835 | depends on (OF || PCI || COMPILE_TEST) && HAS_IOMEM |
363a90c2 | 836 | select CRYPTO_LIB_AES |
f6beaea3 | 837 | select CRYPTO_AUTHENC |
b95bba5d | 838 | select CRYPTO_SKCIPHER |
04007b0e | 839 | select CRYPTO_LIB_DES |
1b44c5a6 AT |
840 | select CRYPTO_HASH |
841 | select CRYPTO_HMAC | |
293f89cf | 842 | select CRYPTO_MD5 |
1b44c5a6 AT |
843 | select CRYPTO_SHA1 |
844 | select CRYPTO_SHA256 | |
845 | select CRYPTO_SHA512 | |
fc0f82b1 | 846 | select CRYPTO_CHACHA20POLY1305 |
1d448f27 | 847 | select CRYPTO_SHA3 |
1b44c5a6 | 848 | help |
0f6e5c82 PL |
849 | This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic |
850 | engines designed by Inside Secure. It currently accelerates DES, 3DES and | |
851 | AES block ciphers in ECB and CBC mode, as well as SHA1, SHA224, SHA256, | |
852 | SHA384 and SHA512 hash algorithms for both basic hash and HMAC. | |
853 | Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations. | |
1b44c5a6 | 854 | |
a21eb94f LP |
855 | config CRYPTO_DEV_ARTPEC6 |
856 | tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration." | |
857 | depends on ARM && (ARCH_ARTPEC || COMPILE_TEST) | |
a21eb94f LP |
858 | depends on OF |
859 | select CRYPTO_AEAD | |
860 | select CRYPTO_AES | |
861 | select CRYPTO_ALGAPI | |
b95bba5d | 862 | select CRYPTO_SKCIPHER |
a21eb94f LP |
863 | select CRYPTO_CTR |
864 | select CRYPTO_HASH | |
865 | select CRYPTO_SHA1 | |
866 | select CRYPTO_SHA256 | |
a21eb94f LP |
867 | select CRYPTO_SHA512 |
868 | help | |
869 | Enables the driver for the on-chip crypto accelerator | |
870 | of Axis ARTPEC SoCs. | |
871 | ||
872 | To compile this driver as a module, choose M here. | |
873 | ||
4c3f9727 GBY |
874 | config CRYPTO_DEV_CCREE |
875 | tristate "Support for ARM TrustZone CryptoCell family of security processors" | |
876 | depends on CRYPTO && CRYPTO_HW && OF && HAS_DMA | |
877 | default n | |
878 | select CRYPTO_HASH | |
b95bba5d | 879 | select CRYPTO_SKCIPHER |
04007b0e | 880 | select CRYPTO_LIB_DES |
4c3f9727 GBY |
881 | select CRYPTO_AEAD |
882 | select CRYPTO_AUTHENC | |
883 | select CRYPTO_SHA1 | |
884 | select CRYPTO_MD5 | |
885 | select CRYPTO_SHA256 | |
886 | select CRYPTO_SHA512 | |
887 | select CRYPTO_HMAC | |
888 | select CRYPTO_AES | |
889 | select CRYPTO_CBC | |
890 | select CRYPTO_ECB | |
891 | select CRYPTO_CTR | |
892 | select CRYPTO_XTS | |
9b8d51f8 | 893 | select CRYPTO_SM4 |
927574e0 | 894 | select CRYPTO_SM3 |
4c3f9727 | 895 | help |
27b3b22d GBY |
896 | Say 'Y' to enable a driver for the REE interface of the Arm |
897 | TrustZone CryptoCell family of processors. Currently the | |
1c876a90 | 898 | CryptoCell 713, 703, 712, 710 and 630 are supported. |
4c3f9727 GBY |
899 | Choose this if you wish to use hardware acceleration of |
900 | cryptographic operations on the system REE. | |
901 | If unsure say Y. | |
902 | ||
915e4e84 JC |
903 | source "drivers/crypto/hisilicon/Kconfig" |
904 | ||
48fe583f CL |
905 | source "drivers/crypto/amlogic/Kconfig" |
906 | ||
7694b6ca K |
907 | config CRYPTO_DEV_SA2UL |
908 | tristate "Support for TI security accelerator" | |
909 | depends on ARCH_K3 || COMPILE_TEST | |
910 | select ARM64_CRYPTO | |
911 | select CRYPTO_AES | |
912 | select CRYPTO_AES_ARM64 | |
913 | select CRYPTO_ALGAPI | |
61f033ba | 914 | select CRYPTO_AUTHENC |
bfe8fe93 RD |
915 | select CRYPTO_SHA1 |
916 | select CRYPTO_SHA256 | |
917 | select CRYPTO_SHA512 | |
7694b6ca K |
918 | select HW_RANDOM |
919 | select SG_SPLIT | |
920 | help | |
921 | K3 devices include a security accelerator engine that may be | |
922 | used for crypto offload. Select this if you want to use hardware | |
923 | acceleration for cryptographic algorithms on these devices. | |
924 | ||
88574332 MH |
925 | source "drivers/crypto/keembay/Kconfig" |
926 | ||
b511431d | 927 | endif # CRYPTO_HW |