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Commit | Line | Data |
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b511431d JE |
1 | |
2 | menuconfig CRYPTO_HW | |
3 | bool "Hardware crypto devices" | |
4 | default y | |
06bfb7eb JE |
5 | ---help--- |
6 | Say Y here to get to see options for hardware crypto devices and | |
7 | processors. This option alone does not add any kernel code. | |
8 | ||
9 | If you say N, all options in this submenu will be skipped and disabled. | |
b511431d JE |
10 | |
11 | if CRYPTO_HW | |
1da177e4 LT |
12 | |
13 | config CRYPTO_DEV_PADLOCK | |
d158325e | 14 | tristate "Support for VIA PadLock ACE" |
2f817418 | 15 | depends on X86 && !UML |
1da177e4 LT |
16 | help |
17 | Some VIA processors come with an integrated crypto engine | |
18 | (so called VIA PadLock ACE, Advanced Cryptography Engine) | |
1191f0a4 ML |
19 | that provides instructions for very fast cryptographic |
20 | operations with supported algorithms. | |
1da177e4 LT |
21 | |
22 | The instructions are used only when the CPU supports them. | |
5644bda5 ML |
23 | Otherwise software encryption is used. |
24 | ||
1da177e4 | 25 | config CRYPTO_DEV_PADLOCK_AES |
1191f0a4 | 26 | tristate "PadLock driver for AES algorithm" |
1da177e4 | 27 | depends on CRYPTO_DEV_PADLOCK |
28ce728a | 28 | select CRYPTO_BLKCIPHER |
7dc748e4 | 29 | select CRYPTO_AES |
1da177e4 LT |
30 | help |
31 | Use VIA PadLock for AES algorithm. | |
32 | ||
1191f0a4 ML |
33 | Available in VIA C3 and newer CPUs. |
34 | ||
35 | If unsure say M. The compiled module will be | |
4737f097 | 36 | called padlock-aes. |
1191f0a4 | 37 | |
6c833275 ML |
38 | config CRYPTO_DEV_PADLOCK_SHA |
39 | tristate "PadLock driver for SHA1 and SHA256 algorithms" | |
40 | depends on CRYPTO_DEV_PADLOCK | |
bbbee467 | 41 | select CRYPTO_HASH |
6c833275 ML |
42 | select CRYPTO_SHA1 |
43 | select CRYPTO_SHA256 | |
6c833275 ML |
44 | help |
45 | Use VIA PadLock for SHA1/SHA256 algorithms. | |
46 | ||
47 | Available in VIA C7 and newer processors. | |
48 | ||
49 | If unsure say M. The compiled module will be | |
4737f097 | 50 | called padlock-sha. |
6c833275 | 51 | |
9fe757b0 JC |
52 | config CRYPTO_DEV_GEODE |
53 | tristate "Support for the Geode LX AES engine" | |
f6259dea | 54 | depends on X86_32 && PCI |
9fe757b0 JC |
55 | select CRYPTO_ALGAPI |
56 | select CRYPTO_BLKCIPHER | |
9fe757b0 JC |
57 | help |
58 | Say 'Y' here to use the AMD Geode LX processor on-board AES | |
3dde6ad8 | 59 | engine for the CryptoAPI AES algorithm. |
9fe757b0 JC |
60 | |
61 | To compile this driver as a module, choose M here: the module | |
62 | will be called geode-aes. | |
63 | ||
61d48c2c | 64 | config ZCRYPT |
a3358e3d | 65 | tristate "Support for s390 cryptographic adapters" |
61d48c2c | 66 | depends on S390 |
2f7c8bd6 | 67 | select HW_RANDOM |
61d48c2c | 68 | help |
a3358e3d HF |
69 | Select this option if you want to enable support for |
70 | s390 cryptographic adapters like: | |
61d48c2c | 71 | + PCI-X Cryptographic Coprocessor (PCIXCC) |
a3358e3d HF |
72 | + Crypto Express 2,3,4 or 5 Coprocessor (CEXxC) |
73 | + Crypto Express 2,3,4 or 5 Accelerator (CEXxA) | |
74 | + Crypto Express 4 or 5 EP11 Coprocessor (CEXxP) | |
61d48c2c | 75 | |
e80d4af0 HF |
76 | config PKEY |
77 | tristate "Kernel API for protected key handling" | |
78 | depends on S390 | |
79 | depends on ZCRYPT | |
80 | help | |
81 | With this option enabled the pkey kernel module provides an API | |
82 | for creation and handling of protected keys. Other parts of the | |
83 | kernel or userspace applications may use these functions. | |
84 | ||
85 | Select this option if you want to enable the kernel and userspace | |
86 | API for proteced key handling. | |
87 | ||
88 | Please note that creation of protected keys from secure keys | |
89 | requires to have at least one CEX card in coprocessor mode | |
90 | available at runtime. | |
61d48c2c | 91 | |
3f5615e0 JG |
92 | config CRYPTO_SHA1_S390 |
93 | tristate "SHA1 digest algorithm" | |
94 | depends on S390 | |
563f346d | 95 | select CRYPTO_HASH |
3f5615e0 JG |
96 | help |
97 | This is the s390 hardware accelerated implementation of the | |
98 | SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). | |
99 | ||
d393d9b8 JG |
100 | It is available as of z990. |
101 | ||
3f5615e0 JG |
102 | config CRYPTO_SHA256_S390 |
103 | tristate "SHA256 digest algorithm" | |
104 | depends on S390 | |
563f346d | 105 | select CRYPTO_HASH |
3f5615e0 JG |
106 | help |
107 | This is the s390 hardware accelerated implementation of the | |
108 | SHA256 secure hash standard (DFIPS 180-2). | |
109 | ||
d393d9b8 | 110 | It is available as of z9. |
3f5615e0 | 111 | |
291dc7c0 | 112 | config CRYPTO_SHA512_S390 |
4e2c6d7f | 113 | tristate "SHA384 and SHA512 digest algorithm" |
291dc7c0 | 114 | depends on S390 |
563f346d | 115 | select CRYPTO_HASH |
291dc7c0 JG |
116 | help |
117 | This is the s390 hardware accelerated implementation of the | |
118 | SHA512 secure hash standard. | |
119 | ||
d393d9b8 | 120 | It is available as of z10. |
291dc7c0 | 121 | |
3f5615e0 JG |
122 | config CRYPTO_DES_S390 |
123 | tristate "DES and Triple DES cipher algorithms" | |
124 | depends on S390 | |
125 | select CRYPTO_ALGAPI | |
126 | select CRYPTO_BLKCIPHER | |
63291d40 | 127 | select CRYPTO_DES |
3f5615e0 | 128 | help |
0200f3ec | 129 | This is the s390 hardware accelerated implementation of the |
3f5615e0 JG |
130 | DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). |
131 | ||
0200f3ec GS |
132 | As of z990 the ECB and CBC mode are hardware accelerated. |
133 | As of z196 the CTR mode is hardware accelerated. | |
134 | ||
3f5615e0 JG |
135 | config CRYPTO_AES_S390 |
136 | tristate "AES cipher algorithms" | |
137 | depends on S390 | |
138 | select CRYPTO_ALGAPI | |
139 | select CRYPTO_BLKCIPHER | |
27937843 | 140 | select PKEY |
3f5615e0 JG |
141 | help |
142 | This is the s390 hardware accelerated implementation of the | |
99d97222 GS |
143 | AES cipher algorithms (FIPS-197). |
144 | ||
145 | As of z9 the ECB and CBC modes are hardware accelerated | |
146 | for 128 bit keys. | |
147 | As of z10 the ECB and CBC modes are hardware accelerated | |
148 | for all AES key sizes. | |
0200f3ec GS |
149 | As of z196 the CTR mode is hardware accelerated for all AES |
150 | key sizes and XTS mode is hardware accelerated for 256 and | |
99d97222 | 151 | 512 bit keys. |
3f5615e0 JG |
152 | |
153 | config S390_PRNG | |
154 | tristate "Pseudo random number generator device driver" | |
155 | depends on S390 | |
156 | default "m" | |
157 | help | |
158 | Select this option if you want to use the s390 pseudo random number | |
159 | generator. The PRNG is part of the cryptographic processor functions | |
160 | and uses triple-DES to generate secure random numbers like the | |
d393d9b8 JG |
161 | ANSI X9.17 standard. User-space programs access the |
162 | pseudo-random-number device through the char device /dev/prandom. | |
163 | ||
164 | It is available as of z9. | |
3f5615e0 | 165 | |
df1309ce GS |
166 | config CRYPTO_GHASH_S390 |
167 | tristate "GHASH digest algorithm" | |
168 | depends on S390 | |
169 | select CRYPTO_HASH | |
170 | help | |
171 | This is the s390 hardware accelerated implementation of the | |
172 | GHASH message digest algorithm for GCM (Galois/Counter Mode). | |
173 | ||
174 | It is available as of z196. | |
175 | ||
f848dbd3 HB |
176 | config CRYPTO_CRC32_S390 |
177 | tristate "CRC-32 algorithms" | |
178 | depends on S390 | |
179 | select CRYPTO_HASH | |
180 | select CRC32 | |
181 | help | |
182 | Select this option if you want to use hardware accelerated | |
183 | implementations of CRC algorithms. With this option, you | |
184 | can optimize the computation of CRC-32 (IEEE 802.3 Ethernet) | |
185 | and CRC-32C (Castagnoli). | |
186 | ||
187 | It is available with IBM z13 or later. | |
188 | ||
85a7f0ac SAS |
189 | config CRYPTO_DEV_MV_CESA |
190 | tristate "Marvell's Cryptographic Engine" | |
191 | depends on PLAT_ORION | |
85a7f0ac | 192 | select CRYPTO_AES |
596103cf | 193 | select CRYPTO_BLKCIPHER |
1ebfefcf | 194 | select CRYPTO_HASH |
51b44fc8 | 195 | select SRAM |
85a7f0ac SAS |
196 | help |
197 | This driver allows you to utilize the Cryptographic Engines and | |
198 | Security Accelerator (CESA) which can be found on the Marvell Orion | |
199 | and Kirkwood SoCs, such as QNAP's TS-209. | |
200 | ||
201 | Currently the driver supports AES in ECB and CBC mode without DMA. | |
202 | ||
f63601fd BB |
203 | config CRYPTO_DEV_MARVELL_CESA |
204 | tristate "New Marvell's Cryptographic Engine driver" | |
fe55dfdc | 205 | depends on PLAT_ORION || ARCH_MVEBU |
f63601fd BB |
206 | select CRYPTO_AES |
207 | select CRYPTO_DES | |
208 | select CRYPTO_BLKCIPHER | |
209 | select CRYPTO_HASH | |
210 | select SRAM | |
211 | help | |
212 | This driver allows you to utilize the Cryptographic Engines and | |
213 | Security Accelerator (CESA) which can be found on the Armada 370. | |
db509a45 | 214 | This driver supports CPU offload through DMA transfers. |
f63601fd BB |
215 | |
216 | This driver is aimed at replacing the mv_cesa driver. This will only | |
217 | happen once it has received proper testing. | |
218 | ||
0a625fd2 DM |
219 | config CRYPTO_DEV_NIAGARA2 |
220 | tristate "Niagara2 Stream Processing Unit driver" | |
50e78161 | 221 | select CRYPTO_DES |
596103cf HX |
222 | select CRYPTO_BLKCIPHER |
223 | select CRYPTO_HASH | |
8054b800 LC |
224 | select CRYPTO_MD5 |
225 | select CRYPTO_SHA1 | |
226 | select CRYPTO_SHA256 | |
0a625fd2 DM |
227 | depends on SPARC64 |
228 | help | |
229 | Each core of a Niagara2 processor contains a Stream | |
230 | Processing Unit, which itself contains several cryptographic | |
231 | sub-units. One set provides the Modular Arithmetic Unit, | |
232 | used for SSL offload. The other set provides the Cipher | |
233 | Group, which can perform encryption, decryption, hashing, | |
234 | checksumming, and raw copies. | |
235 | ||
f7d0561e EP |
236 | config CRYPTO_DEV_HIFN_795X |
237 | tristate "Driver HIFN 795x crypto accelerator chips" | |
c3041f9c | 238 | select CRYPTO_DES |
653ebd9c | 239 | select CRYPTO_BLKCIPHER |
946fef4e | 240 | select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG |
2707b937 | 241 | depends on PCI |
75b76625 | 242 | depends on !ARCH_DMA_ADDR_T_64BIT |
f7d0561e EP |
243 | help |
244 | This option allows you to have support for HIFN 795x crypto adapters. | |
245 | ||
946fef4e HX |
246 | config CRYPTO_DEV_HIFN_795X_RNG |
247 | bool "HIFN 795x random number generator" | |
248 | depends on CRYPTO_DEV_HIFN_795X | |
249 | help | |
250 | Select this option if you want to enable the random number generator | |
251 | on the HIFN 795x crypto adapters. | |
f7d0561e | 252 | |
8e8ec596 KP |
253 | source drivers/crypto/caam/Kconfig |
254 | ||
9c4a7965 KP |
255 | config CRYPTO_DEV_TALITOS |
256 | tristate "Talitos Freescale Security Engine (SEC)" | |
596103cf | 257 | select CRYPTO_AEAD |
9c4a7965 | 258 | select CRYPTO_AUTHENC |
596103cf HX |
259 | select CRYPTO_BLKCIPHER |
260 | select CRYPTO_HASH | |
9c4a7965 KP |
261 | select HW_RANDOM |
262 | depends on FSL_SOC | |
263 | help | |
264 | Say 'Y' here to use the Freescale Security Engine (SEC) | |
265 | to offload cryptographic algorithm computation. | |
266 | ||
267 | The Freescale SEC is present on PowerQUICC 'E' processors, such | |
268 | as the MPC8349E and MPC8548E. | |
269 | ||
270 | To compile this driver as a module, choose M here: the module | |
271 | will be called talitos. | |
272 | ||
5b841a65 LC |
273 | config CRYPTO_DEV_TALITOS1 |
274 | bool "SEC1 (SEC 1.0 and SEC Lite 1.2)" | |
275 | depends on CRYPTO_DEV_TALITOS | |
276 | depends on PPC_8xx || PPC_82xx | |
277 | default y | |
278 | help | |
279 | Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0 | |
280 | found on MPC82xx or the Freescale Security Engine (SEC Lite) | |
281 | version 1.2 found on MPC8xx | |
282 | ||
283 | config CRYPTO_DEV_TALITOS2 | |
284 | bool "SEC2+ (SEC version 2.0 or upper)" | |
285 | depends on CRYPTO_DEV_TALITOS | |
286 | default y if !PPC_8xx | |
287 | help | |
288 | Say 'Y' here to use the Freescale Security Engine (SEC) | |
289 | version 2 and following as found on MPC83xx, MPC85xx, etc ... | |
290 | ||
81bef015 CH |
291 | config CRYPTO_DEV_IXP4XX |
292 | tristate "Driver for IXP4xx crypto hardware acceleration" | |
9665c52b | 293 | depends on ARCH_IXP4XX && IXP4XX_QMGR && IXP4XX_NPE |
81bef015 | 294 | select CRYPTO_DES |
596103cf | 295 | select CRYPTO_AEAD |
090657e4 | 296 | select CRYPTO_AUTHENC |
81bef015 CH |
297 | select CRYPTO_BLKCIPHER |
298 | help | |
299 | Driver for the IXP4xx NPE crypto engine. | |
300 | ||
049359d6 JH |
301 | config CRYPTO_DEV_PPC4XX |
302 | tristate "Driver AMCC PPC4xx crypto accelerator" | |
303 | depends on PPC && 4xx | |
304 | select CRYPTO_HASH | |
049359d6 JH |
305 | select CRYPTO_BLKCIPHER |
306 | help | |
307 | This option allows you to have support for AMCC crypto acceleration. | |
308 | ||
5343e674 CL |
309 | config HW_RANDOM_PPC4XX |
310 | bool "PowerPC 4xx generic true random number generator support" | |
311 | depends on CRYPTO_DEV_PPC4XX && HW_RANDOM | |
312 | default y | |
313 | ---help--- | |
314 | This option provides the kernel-side support for the TRNG hardware | |
315 | found in the security function of some PowerPC 4xx SoCs. | |
316 | ||
8628e7c8 | 317 | config CRYPTO_DEV_OMAP_SHAM |
eaef7e3f LV |
318 | tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator" |
319 | depends on ARCH_OMAP2PLUS | |
8628e7c8 DK |
320 | select CRYPTO_SHA1 |
321 | select CRYPTO_MD5 | |
eaef7e3f LV |
322 | select CRYPTO_SHA256 |
323 | select CRYPTO_SHA512 | |
324 | select CRYPTO_HMAC | |
8628e7c8 | 325 | help |
eaef7e3f LV |
326 | OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you |
327 | want to use the OMAP module for MD5/SHA1/SHA2 algorithms. | |
8628e7c8 | 328 | |
537559a5 DK |
329 | config CRYPTO_DEV_OMAP_AES |
330 | tristate "Support for OMAP AES hw engine" | |
1bbf6437 | 331 | depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP2PLUS |
537559a5 | 332 | select CRYPTO_AES |
596103cf | 333 | select CRYPTO_BLKCIPHER |
0529900a | 334 | select CRYPTO_ENGINE |
9fcb191a LV |
335 | select CRYPTO_CBC |
336 | select CRYPTO_ECB | |
337 | select CRYPTO_CTR | |
537559a5 DK |
338 | help |
339 | OMAP processors have AES module accelerator. Select this if you | |
340 | want to use the OMAP module for AES algorithms. | |
341 | ||
701d0f19 | 342 | config CRYPTO_DEV_OMAP_DES |
97ee7ed3 | 343 | tristate "Support for OMAP DES/3DES hw engine" |
701d0f19 JF |
344 | depends on ARCH_OMAP2PLUS |
345 | select CRYPTO_DES | |
596103cf | 346 | select CRYPTO_BLKCIPHER |
f1b77aac | 347 | select CRYPTO_ENGINE |
701d0f19 JF |
348 | help |
349 | OMAP processors have DES/3DES module accelerator. Select this if you | |
350 | want to use the OMAP module for DES and 3DES algorithms. Currently | |
97ee7ed3 PM |
351 | the ECB and CBC modes of operation are supported by the driver. Also |
352 | accesses made on unaligned boundaries are supported. | |
701d0f19 | 353 | |
ce921368 JI |
354 | config CRYPTO_DEV_PICOXCELL |
355 | tristate "Support for picoXcell IPSEC and Layer2 crypto engines" | |
4f44d86d | 356 | depends on (ARCH_PICOXCELL || COMPILE_TEST) && HAVE_CLK |
596103cf | 357 | select CRYPTO_AEAD |
ce921368 JI |
358 | select CRYPTO_AES |
359 | select CRYPTO_AUTHENC | |
596103cf | 360 | select CRYPTO_BLKCIPHER |
ce921368 JI |
361 | select CRYPTO_DES |
362 | select CRYPTO_CBC | |
363 | select CRYPTO_ECB | |
364 | select CRYPTO_SEQIV | |
365 | help | |
366 | This option enables support for the hardware offload engines in the | |
367 | Picochip picoXcell SoC devices. Select this for IPSEC ESP offload | |
368 | and for 3gpp Layer 2 ciphering support. | |
369 | ||
370 | Saying m here will build a module named pipcoxcell_crypto. | |
371 | ||
5de88752 JM |
372 | config CRYPTO_DEV_SAHARA |
373 | tristate "Support for SAHARA crypto accelerator" | |
74d24d83 | 374 | depends on ARCH_MXC && OF |
5de88752 JM |
375 | select CRYPTO_BLKCIPHER |
376 | select CRYPTO_AES | |
377 | select CRYPTO_ECB | |
378 | help | |
379 | This option enables support for the SAHARA HW crypto accelerator | |
380 | found in some Freescale i.MX chips. | |
381 | ||
d293b640 ST |
382 | config CRYPTO_DEV_MXC_SCC |
383 | tristate "Support for Freescale Security Controller (SCC)" | |
384 | depends on ARCH_MXC && OF | |
385 | select CRYPTO_BLKCIPHER | |
386 | select CRYPTO_DES | |
387 | help | |
388 | This option enables support for the Security Controller (SCC) | |
389 | found in Freescale i.MX25 chips. | |
390 | ||
a49e490c | 391 | config CRYPTO_DEV_S5P |
e922e96f | 392 | tristate "Support for Samsung S5PV210/Exynos crypto accelerator" |
dc1d9dee KK |
393 | depends on ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST |
394 | depends on HAS_IOMEM && HAS_DMA | |
a49e490c | 395 | select CRYPTO_AES |
a49e490c VZ |
396 | select CRYPTO_BLKCIPHER |
397 | help | |
398 | This option allows you to have support for S5P crypto acceleration. | |
e922e96f | 399 | Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES |
a49e490c VZ |
400 | algorithms execution. |
401 | ||
aef7b31c | 402 | config CRYPTO_DEV_NX |
7011a122 DS |
403 | bool "Support for IBM PowerPC Nest (NX) cryptographic acceleration" |
404 | depends on PPC64 | |
aef7b31c | 405 | help |
7011a122 DS |
406 | This enables support for the NX hardware cryptographic accelerator |
407 | coprocessor that is in IBM PowerPC P7+ or later processors. This | |
408 | does not actually enable any drivers, it only allows you to select | |
409 | which acceleration type (encryption and/or compression) to enable. | |
322cacce SJ |
410 | |
411 | if CRYPTO_DEV_NX | |
412 | source "drivers/crypto/nx/Kconfig" | |
413 | endif | |
aef7b31c | 414 | |
2789c08f AW |
415 | config CRYPTO_DEV_UX500 |
416 | tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration" | |
417 | depends on ARCH_U8500 | |
2789c08f AW |
418 | help |
419 | Driver for ST-Ericsson UX500 crypto engine. | |
420 | ||
421 | if CRYPTO_DEV_UX500 | |
422 | source "drivers/crypto/ux500/Kconfig" | |
423 | endif # if CRYPTO_DEV_UX500 | |
424 | ||
b8840098 SZ |
425 | config CRYPTO_DEV_BFIN_CRC |
426 | tristate "Support for Blackfin CRC hardware" | |
427 | depends on BF60x | |
428 | help | |
429 | Newer Blackfin processors have CRC hardware. Select this if you | |
430 | want to use the Blackfin CRC module. | |
431 | ||
89a82ef8 CP |
432 | config CRYPTO_DEV_ATMEL_AUTHENC |
433 | tristate "Support for Atmel IPSEC/SSL hw accelerator" | |
ceb4afb3 AB |
434 | depends on HAS_DMA |
435 | depends on ARCH_AT91 || COMPILE_TEST | |
89a82ef8 CP |
436 | select CRYPTO_AUTHENC |
437 | select CRYPTO_DEV_ATMEL_AES | |
438 | select CRYPTO_DEV_ATMEL_SHA | |
439 | help | |
440 | Some Atmel processors can combine the AES and SHA hw accelerators | |
441 | to enhance support of IPSEC/SSL. | |
442 | Select this if you want to use the Atmel modules for | |
443 | authenc(hmac(shaX),Y(cbc)) algorithms. | |
444 | ||
bd3c7b5c NR |
445 | config CRYPTO_DEV_ATMEL_AES |
446 | tristate "Support for Atmel AES hw accelerator" | |
cbafd643 | 447 | depends on HAS_DMA |
ceb4afb3 | 448 | depends on ARCH_AT91 || COMPILE_TEST |
bd3c7b5c | 449 | select CRYPTO_AES |
d4419548 | 450 | select CRYPTO_AEAD |
bd3c7b5c | 451 | select CRYPTO_BLKCIPHER |
bd3c7b5c NR |
452 | help |
453 | Some Atmel processors have AES hw accelerator. | |
454 | Select this if you want to use the Atmel module for | |
455 | AES algorithms. | |
456 | ||
457 | To compile this driver as a module, choose M here: the module | |
458 | will be called atmel-aes. | |
459 | ||
13802005 NR |
460 | config CRYPTO_DEV_ATMEL_TDES |
461 | tristate "Support for Atmel DES/TDES hw accelerator" | |
f7f9482e | 462 | depends on HAS_DMA |
ceb4afb3 | 463 | depends on ARCH_AT91 || COMPILE_TEST |
13802005 | 464 | select CRYPTO_DES |
13802005 NR |
465 | select CRYPTO_BLKCIPHER |
466 | help | |
467 | Some Atmel processors have DES/TDES hw accelerator. | |
468 | Select this if you want to use the Atmel module for | |
469 | DES/TDES algorithms. | |
470 | ||
471 | To compile this driver as a module, choose M here: the module | |
472 | will be called atmel-tdes. | |
473 | ||
ebc82efa | 474 | config CRYPTO_DEV_ATMEL_SHA |
d4905b38 | 475 | tristate "Support for Atmel SHA hw accelerator" |
f7f9482e | 476 | depends on HAS_DMA |
ceb4afb3 | 477 | depends on ARCH_AT91 || COMPILE_TEST |
596103cf | 478 | select CRYPTO_HASH |
ebc82efa | 479 | help |
d4905b38 NR |
480 | Some Atmel processors have SHA1/SHA224/SHA256/SHA384/SHA512 |
481 | hw accelerator. | |
ebc82efa | 482 | Select this if you want to use the Atmel module for |
d4905b38 | 483 | SHA1/SHA224/SHA256/SHA384/SHA512 algorithms. |
ebc82efa NR |
484 | |
485 | To compile this driver as a module, choose M here: the module | |
486 | will be called atmel-sha. | |
487 | ||
f1147660 TL |
488 | config CRYPTO_DEV_CCP |
489 | bool "Support for AMD Cryptographic Coprocessor" | |
6c506343 | 490 | depends on ((X86 && PCI) || (ARM64 && (OF_ADDRESS || ACPI))) && HAS_IOMEM |
f1147660 | 491 | help |
21dc9e8f | 492 | The AMD Cryptographic Coprocessor provides hardware offload support |
f1147660 TL |
493 | for encryption, hashing and related operations. |
494 | ||
495 | if CRYPTO_DEV_CCP | |
496 | source "drivers/crypto/ccp/Kconfig" | |
497 | endif | |
498 | ||
15b59e7c MV |
499 | config CRYPTO_DEV_MXS_DCP |
500 | tristate "Support for Freescale MXS DCP" | |
a2712e6c | 501 | depends on (ARCH_MXS || ARCH_MXC) |
dc97fa02 | 502 | select STMP_DEVICE |
15b59e7c MV |
503 | select CRYPTO_CBC |
504 | select CRYPTO_ECB | |
505 | select CRYPTO_AES | |
506 | select CRYPTO_BLKCIPHER | |
596103cf | 507 | select CRYPTO_HASH |
15b59e7c MV |
508 | help |
509 | The Freescale i.MX23/i.MX28 has SHA1/SHA256 and AES128 CBC/ECB | |
510 | co-processor on the die. | |
511 | ||
512 | To compile this driver as a module, choose M here: the module | |
513 | will be called mxs-dcp. | |
514 | ||
cea4001a | 515 | source "drivers/crypto/qat/Kconfig" |
62ad8b5c | 516 | source "drivers/crypto/cavium/cpt/Kconfig" |
c672752d | 517 | |
640035a2 MC |
518 | config CRYPTO_DEV_CAVIUM_ZIP |
519 | tristate "Cavium ZIP driver" | |
520 | depends on PCI && 64BIT && (ARM64 || COMPILE_TEST) | |
521 | ---help--- | |
522 | Select this option if you want to enable compression/decompression | |
523 | acceleration on Cavium's ARM based SoCs | |
524 | ||
c672752d SV |
525 | config CRYPTO_DEV_QCE |
526 | tristate "Qualcomm crypto engine accelerator" | |
71d932d9 | 527 | depends on (ARCH_QCOM || COMPILE_TEST) && HAS_DMA && HAS_IOMEM |
c672752d SV |
528 | select CRYPTO_AES |
529 | select CRYPTO_DES | |
530 | select CRYPTO_ECB | |
531 | select CRYPTO_CBC | |
532 | select CRYPTO_XTS | |
533 | select CRYPTO_CTR | |
c672752d SV |
534 | select CRYPTO_BLKCIPHER |
535 | help | |
536 | This driver supports Qualcomm crypto engine accelerator | |
537 | hardware. To compile this driver as a module, choose M here. The | |
538 | module will be called qcrypto. | |
539 | ||
d2e3ae6f LB |
540 | config CRYPTO_DEV_VMX |
541 | bool "Support for VMX cryptographic acceleration instructions" | |
f1ab4287 | 542 | depends on PPC64 && VSX |
d2e3ae6f LB |
543 | help |
544 | Support for VMX cryptographic acceleration instructions. | |
545 | ||
546 | source "drivers/crypto/vmx/Kconfig" | |
547 | ||
d358f1ab | 548 | config CRYPTO_DEV_IMGTEC_HASH |
d358f1ab | 549 | tristate "Imagination Technologies hardware hash accelerator" |
8c98ebd7 GU |
550 | depends on MIPS || COMPILE_TEST |
551 | depends on HAS_DMA | |
d358f1ab JH |
552 | select CRYPTO_MD5 |
553 | select CRYPTO_SHA1 | |
d358f1ab JH |
554 | select CRYPTO_SHA256 |
555 | select CRYPTO_HASH | |
556 | help | |
557 | This driver interfaces with the Imagination Technologies | |
558 | hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256 | |
559 | hashing algorithms. | |
560 | ||
6298e948 LC |
561 | config CRYPTO_DEV_SUN4I_SS |
562 | tristate "Support for Allwinner Security System cryptographic accelerator" | |
f823ab93 | 563 | depends on ARCH_SUNXI && !64BIT |
6298e948 LC |
564 | select CRYPTO_MD5 |
565 | select CRYPTO_SHA1 | |
566 | select CRYPTO_AES | |
567 | select CRYPTO_DES | |
568 | select CRYPTO_BLKCIPHER | |
569 | help | |
570 | Some Allwinner SoC have a crypto accelerator named | |
571 | Security System. Select this if you want to use it. | |
572 | The Security System handle AES/DES/3DES ciphers in CBC mode | |
573 | and SHA1 and MD5 hash algorithms. | |
574 | ||
575 | To compile this driver as a module, choose M here: the module | |
576 | will be called sun4i-ss. | |
577 | ||
433cd2c6 ZW |
578 | config CRYPTO_DEV_ROCKCHIP |
579 | tristate "Rockchip's Cryptographic Engine driver" | |
580 | depends on OF && ARCH_ROCKCHIP | |
581 | select CRYPTO_AES | |
582 | select CRYPTO_DES | |
bfd927ff ZW |
583 | select CRYPTO_MD5 |
584 | select CRYPTO_SHA1 | |
585 | select CRYPTO_SHA256 | |
586 | select CRYPTO_HASH | |
433cd2c6 ZW |
587 | select CRYPTO_BLKCIPHER |
588 | ||
589 | help | |
590 | This driver interfaces with the hardware crypto accelerator. | |
591 | Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode. | |
592 | ||
785e5c61 RL |
593 | config CRYPTO_DEV_MEDIATEK |
594 | tristate "MediaTek's EIP97 Cryptographic Engine driver" | |
c884b368 | 595 | depends on HAS_DMA |
7dee9f61 | 596 | depends on (ARM && ARCH_MEDIATEK) || COMPILE_TEST |
785e5c61 | 597 | select CRYPTO_AES |
d03f7b0d | 598 | select CRYPTO_AEAD |
785e5c61 | 599 | select CRYPTO_BLKCIPHER |
d03f7b0d | 600 | select CRYPTO_CTR |
7dee9f61 AB |
601 | select CRYPTO_SHA1 |
602 | select CRYPTO_SHA256 | |
603 | select CRYPTO_SHA512 | |
785e5c61 RL |
604 | select CRYPTO_HMAC |
605 | help | |
606 | This driver allows you to utilize the hardware crypto accelerator | |
607 | EIP97 which can be found on the MT7623 MT2701, MT8521p, etc .... | |
608 | Select this if you want to use it for AES/SHA1/SHA2 algorithms. | |
609 | ||
02038fd6 HS |
610 | source "drivers/crypto/chelsio/Kconfig" |
611 | ||
dbaf0624 G |
612 | source "drivers/crypto/virtio/Kconfig" |
613 | ||
9d12ba86 RR |
614 | config CRYPTO_DEV_BCM_SPU |
615 | tristate "Broadcom symmetric crypto/hash acceleration support" | |
616 | depends on ARCH_BCM_IPROC | |
617 | depends on BCM_PDC_MBOX | |
618 | default m | |
619 | select CRYPTO_DES | |
620 | select CRYPTO_MD5 | |
621 | select CRYPTO_SHA1 | |
622 | select CRYPTO_SHA256 | |
623 | select CRYPTO_SHA512 | |
624 | help | |
625 | This driver provides support for Broadcom crypto acceleration using the | |
626 | Secure Processing Unit (SPU). The SPU driver registers ablkcipher, | |
627 | ahash, and aead algorithms with the kernel cryptographic API. | |
628 | ||
b51dbe90 FD |
629 | source "drivers/crypto/stm32/Kconfig" |
630 | ||
b511431d | 631 | endif # CRYPTO_HW |