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Commit | Line | Data |
---|---|---|
bd3c7b5c NR |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for ATMEL AES HW acceleration. | |
5 | * | |
6 | * Copyright (c) 2012 Eukréa Electromatique - ATMEL | |
7 | * Author: Nicolas Royer <nicolas@eukrea.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as published | |
11 | * by the Free Software Foundation. | |
12 | * | |
13 | * Some ideas are from omap-aes.c driver. | |
14 | */ | |
15 | ||
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/hw_random.h> | |
24 | #include <linux/platform_device.h> | |
25 | ||
26 | #include <linux/device.h> | |
bd3c7b5c NR |
27 | #include <linux/init.h> |
28 | #include <linux/errno.h> | |
29 | #include <linux/interrupt.h> | |
bd3c7b5c | 30 | #include <linux/irq.h> |
bd3c7b5c NR |
31 | #include <linux/scatterlist.h> |
32 | #include <linux/dma-mapping.h> | |
be943c7d | 33 | #include <linux/of_device.h> |
bd3c7b5c NR |
34 | #include <linux/delay.h> |
35 | #include <linux/crypto.h> | |
bd3c7b5c NR |
36 | #include <crypto/scatterwalk.h> |
37 | #include <crypto/algapi.h> | |
38 | #include <crypto/aes.h> | |
d4419548 | 39 | #include <crypto/internal/aead.h> |
cadc4ab8 | 40 | #include <linux/platform_data/crypto-atmel.h> |
be943c7d | 41 | #include <dt-bindings/dma/at91.h> |
bd3c7b5c NR |
42 | #include "atmel-aes-regs.h" |
43 | ||
88efd9a9 CP |
44 | #define ATMEL_AES_PRIORITY 300 |
45 | ||
bbe628ed CP |
46 | #define ATMEL_AES_BUFFER_ORDER 2 |
47 | #define ATMEL_AES_BUFFER_SIZE (PAGE_SIZE << ATMEL_AES_BUFFER_ORDER) | |
48 | ||
bd3c7b5c NR |
49 | #define CFB8_BLOCK_SIZE 1 |
50 | #define CFB16_BLOCK_SIZE 2 | |
51 | #define CFB32_BLOCK_SIZE 4 | |
52 | #define CFB64_BLOCK_SIZE 8 | |
53 | ||
bbe628ed CP |
54 | #define SIZE_IN_WORDS(x) ((x) >> 2) |
55 | ||
bd3c7b5c | 56 | /* AES flags */ |
d4419548 | 57 | /* Reserve bits [18:16] [14:12] [1:0] for mode (same as for AES_MR) */ |
77dacf5f | 58 | #define AES_FLAGS_ENCRYPT AES_MR_CYPHER_ENC |
d4419548 | 59 | #define AES_FLAGS_GTAGEN AES_MR_GTAGEN |
77dacf5f CP |
60 | #define AES_FLAGS_OPMODE_MASK (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK) |
61 | #define AES_FLAGS_ECB AES_MR_OPMOD_ECB | |
62 | #define AES_FLAGS_CBC AES_MR_OPMOD_CBC | |
63 | #define AES_FLAGS_OFB AES_MR_OPMOD_OFB | |
64 | #define AES_FLAGS_CFB128 (AES_MR_OPMOD_CFB | AES_MR_CFBS_128b) | |
65 | #define AES_FLAGS_CFB64 (AES_MR_OPMOD_CFB | AES_MR_CFBS_64b) | |
66 | #define AES_FLAGS_CFB32 (AES_MR_OPMOD_CFB | AES_MR_CFBS_32b) | |
67 | #define AES_FLAGS_CFB16 (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b) | |
68 | #define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b) | |
69 | #define AES_FLAGS_CTR AES_MR_OPMOD_CTR | |
d4419548 | 70 | #define AES_FLAGS_GCM AES_MR_OPMOD_GCM |
77dacf5f CP |
71 | |
72 | #define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \ | |
d4419548 CP |
73 | AES_FLAGS_ENCRYPT | \ |
74 | AES_FLAGS_GTAGEN) | |
77dacf5f CP |
75 | |
76 | #define AES_FLAGS_INIT BIT(2) | |
77 | #define AES_FLAGS_BUSY BIT(3) | |
77dacf5f CP |
78 | |
79 | #define AES_FLAGS_PERSISTENT (AES_FLAGS_INIT | AES_FLAGS_BUSY) | |
bd3c7b5c | 80 | |
cadc4ab8 | 81 | #define ATMEL_AES_QUEUE_LENGTH 50 |
bd3c7b5c | 82 | |
129f8bb6 | 83 | #define ATMEL_AES_DMA_THRESHOLD 256 |
bd3c7b5c NR |
84 | |
85 | ||
cadc4ab8 | 86 | struct atmel_aes_caps { |
afbac17e CP |
87 | bool has_dualbuff; |
88 | bool has_cfb64; | |
fcac8365 | 89 | bool has_ctr32; |
d4419548 | 90 | bool has_gcm; |
afbac17e | 91 | u32 max_burst_size; |
cadc4ab8 NR |
92 | }; |
93 | ||
bd3c7b5c NR |
94 | struct atmel_aes_dev; |
95 | ||
ccbf7298 CP |
96 | |
97 | typedef int (*atmel_aes_fn_t)(struct atmel_aes_dev *); | |
98 | ||
99 | ||
100 | struct atmel_aes_base_ctx { | |
afbac17e CP |
101 | struct atmel_aes_dev *dd; |
102 | atmel_aes_fn_t start; | |
103 | int keylen; | |
104 | u32 key[AES_KEYSIZE_256 / sizeof(u32)]; | |
105 | u16 block_size; | |
bd3c7b5c NR |
106 | }; |
107 | ||
ccbf7298 CP |
108 | struct atmel_aes_ctx { |
109 | struct atmel_aes_base_ctx base; | |
110 | }; | |
111 | ||
fcac8365 CP |
112 | struct atmel_aes_ctr_ctx { |
113 | struct atmel_aes_base_ctx base; | |
114 | ||
115 | u32 iv[AES_BLOCK_SIZE / sizeof(u32)]; | |
116 | size_t offset; | |
117 | struct scatterlist src[2]; | |
118 | struct scatterlist dst[2]; | |
119 | }; | |
120 | ||
d4419548 CP |
121 | struct atmel_aes_gcm_ctx { |
122 | struct atmel_aes_base_ctx base; | |
123 | ||
124 | struct scatterlist src[2]; | |
125 | struct scatterlist dst[2]; | |
126 | ||
127 | u32 j0[AES_BLOCK_SIZE / sizeof(u32)]; | |
128 | u32 tag[AES_BLOCK_SIZE / sizeof(u32)]; | |
129 | u32 ghash[AES_BLOCK_SIZE / sizeof(u32)]; | |
130 | size_t textlen; | |
131 | ||
132 | const u32 *ghash_in; | |
133 | u32 *ghash_out; | |
134 | atmel_aes_fn_t ghash_resume; | |
135 | }; | |
136 | ||
bd3c7b5c | 137 | struct atmel_aes_reqctx { |
afbac17e | 138 | unsigned long mode; |
bd3c7b5c NR |
139 | }; |
140 | ||
141 | struct atmel_aes_dma { | |
bbe628ed CP |
142 | struct dma_chan *chan; |
143 | struct scatterlist *sg; | |
144 | int nents; | |
145 | unsigned int remainder; | |
146 | unsigned int sg_len; | |
bd3c7b5c NR |
147 | }; |
148 | ||
149 | struct atmel_aes_dev { | |
150 | struct list_head list; | |
151 | unsigned long phys_base; | |
152 | void __iomem *io_base; | |
153 | ||
ccbf7298 CP |
154 | struct crypto_async_request *areq; |
155 | struct atmel_aes_base_ctx *ctx; | |
156 | ||
10f12c1b CP |
157 | bool is_async; |
158 | atmel_aes_fn_t resume; | |
bbe628ed | 159 | atmel_aes_fn_t cpu_transfer_complete; |
10f12c1b | 160 | |
bd3c7b5c NR |
161 | struct device *dev; |
162 | struct clk *iclk; | |
afbac17e | 163 | int irq; |
bd3c7b5c NR |
164 | |
165 | unsigned long flags; | |
bd3c7b5c NR |
166 | |
167 | spinlock_t lock; | |
168 | struct crypto_queue queue; | |
169 | ||
170 | struct tasklet_struct done_task; | |
171 | struct tasklet_struct queue_task; | |
172 | ||
bbe628ed CP |
173 | size_t total; |
174 | size_t datalen; | |
175 | u32 *data; | |
bd3c7b5c | 176 | |
bbe628ed CP |
177 | struct atmel_aes_dma src; |
178 | struct atmel_aes_dma dst; | |
bd3c7b5c | 179 | |
bbe628ed CP |
180 | size_t buflen; |
181 | void *buf; | |
182 | struct scatterlist aligned_sg; | |
183 | struct scatterlist *real_dst; | |
bd3c7b5c | 184 | |
cadc4ab8 NR |
185 | struct atmel_aes_caps caps; |
186 | ||
afbac17e | 187 | u32 hw_version; |
bd3c7b5c NR |
188 | }; |
189 | ||
190 | struct atmel_aes_drv { | |
191 | struct list_head dev_list; | |
192 | spinlock_t lock; | |
193 | }; | |
194 | ||
195 | static struct atmel_aes_drv atmel_aes = { | |
196 | .dev_list = LIST_HEAD_INIT(atmel_aes.dev_list), | |
197 | .lock = __SPIN_LOCK_UNLOCKED(atmel_aes.lock), | |
198 | }; | |
199 | ||
e37a7e55 | 200 | /* Shared functions */ |
cadc4ab8 | 201 | |
bd3c7b5c NR |
202 | static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset) |
203 | { | |
204 | return readl_relaxed(dd->io_base + offset); | |
205 | } | |
206 | ||
207 | static inline void atmel_aes_write(struct atmel_aes_dev *dd, | |
208 | u32 offset, u32 value) | |
209 | { | |
210 | writel_relaxed(value, dd->io_base + offset); | |
211 | } | |
212 | ||
213 | static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset, | |
214 | u32 *value, int count) | |
215 | { | |
216 | for (; count--; value++, offset += 4) | |
217 | *value = atmel_aes_read(dd, offset); | |
218 | } | |
219 | ||
220 | static void atmel_aes_write_n(struct atmel_aes_dev *dd, u32 offset, | |
c0b28d8c | 221 | const u32 *value, int count) |
bd3c7b5c NR |
222 | { |
223 | for (; count--; value++, offset += 4) | |
224 | atmel_aes_write(dd, offset, *value); | |
225 | } | |
226 | ||
bbe628ed CP |
227 | static inline void atmel_aes_read_block(struct atmel_aes_dev *dd, u32 offset, |
228 | u32 *value) | |
229 | { | |
230 | atmel_aes_read_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE)); | |
231 | } | |
232 | ||
233 | static inline void atmel_aes_write_block(struct atmel_aes_dev *dd, u32 offset, | |
234 | const u32 *value) | |
235 | { | |
236 | atmel_aes_write_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE)); | |
237 | } | |
238 | ||
239 | static inline int atmel_aes_wait_for_data_ready(struct atmel_aes_dev *dd, | |
240 | atmel_aes_fn_t resume) | |
241 | { | |
242 | u32 isr = atmel_aes_read(dd, AES_ISR); | |
243 | ||
244 | if (unlikely(isr & AES_INT_DATARDY)) | |
245 | return resume(dd); | |
246 | ||
247 | dd->resume = resume; | |
248 | atmel_aes_write(dd, AES_IER, AES_INT_DATARDY); | |
249 | return -EINPROGRESS; | |
250 | } | |
251 | ||
252 | static inline size_t atmel_aes_padlen(size_t len, size_t block_size) | |
253 | { | |
254 | len &= block_size - 1; | |
255 | return len ? block_size - len : 0; | |
256 | } | |
257 | ||
d4419548 CP |
258 | static inline struct aead_request * |
259 | aead_request_cast(struct crypto_async_request *req) | |
260 | { | |
261 | return container_of(req, struct aead_request, base); | |
262 | } | |
263 | ||
ccbf7298 | 264 | static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_base_ctx *ctx) |
bd3c7b5c NR |
265 | { |
266 | struct atmel_aes_dev *aes_dd = NULL; | |
267 | struct atmel_aes_dev *tmp; | |
268 | ||
269 | spin_lock_bh(&atmel_aes.lock); | |
270 | if (!ctx->dd) { | |
271 | list_for_each_entry(tmp, &atmel_aes.dev_list, list) { | |
272 | aes_dd = tmp; | |
273 | break; | |
274 | } | |
275 | ctx->dd = aes_dd; | |
276 | } else { | |
277 | aes_dd = ctx->dd; | |
278 | } | |
279 | ||
280 | spin_unlock_bh(&atmel_aes.lock); | |
281 | ||
282 | return aes_dd; | |
283 | } | |
284 | ||
285 | static int atmel_aes_hw_init(struct atmel_aes_dev *dd) | |
286 | { | |
9d83d299 LC |
287 | int err; |
288 | ||
289 | err = clk_prepare_enable(dd->iclk); | |
290 | if (err) | |
291 | return err; | |
bd3c7b5c NR |
292 | |
293 | if (!(dd->flags & AES_FLAGS_INIT)) { | |
294 | atmel_aes_write(dd, AES_CR, AES_CR_SWRST); | |
cadc4ab8 | 295 | atmel_aes_write(dd, AES_MR, 0xE << AES_MR_CKEY_OFFSET); |
bd3c7b5c | 296 | dd->flags |= AES_FLAGS_INIT; |
bd3c7b5c NR |
297 | } |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
cadc4ab8 NR |
302 | static inline unsigned int atmel_aes_get_version(struct atmel_aes_dev *dd) |
303 | { | |
304 | return atmel_aes_read(dd, AES_HW_VERSION) & 0x00000fff; | |
305 | } | |
306 | ||
aab0a39b | 307 | static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd) |
bd3c7b5c | 308 | { |
aab0a39b CP |
309 | int err; |
310 | ||
311 | err = atmel_aes_hw_init(dd); | |
312 | if (err) | |
313 | return err; | |
bd3c7b5c | 314 | |
cadc4ab8 NR |
315 | dd->hw_version = atmel_aes_get_version(dd); |
316 | ||
aab0a39b | 317 | dev_info(dd->dev, "version: 0x%x\n", dd->hw_version); |
bd3c7b5c NR |
318 | |
319 | clk_disable_unprepare(dd->iclk); | |
aab0a39b | 320 | return 0; |
bd3c7b5c NR |
321 | } |
322 | ||
77dacf5f CP |
323 | static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd, |
324 | const struct atmel_aes_reqctx *rctx) | |
325 | { | |
326 | /* Clear all but persistent flags and set request flags. */ | |
327 | dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode; | |
328 | } | |
329 | ||
d4419548 CP |
330 | static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd) |
331 | { | |
332 | return (dd->flags & AES_FLAGS_ENCRYPT); | |
333 | } | |
334 | ||
10f12c1b | 335 | static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err) |
bd3c7b5c | 336 | { |
bd3c7b5c NR |
337 | clk_disable_unprepare(dd->iclk); |
338 | dd->flags &= ~AES_FLAGS_BUSY; | |
339 | ||
10f12c1b CP |
340 | if (dd->is_async) |
341 | dd->areq->complete(dd->areq, err); | |
342 | ||
343 | tasklet_schedule(&dd->queue_task); | |
344 | ||
345 | return err; | |
bd3c7b5c NR |
346 | } |
347 | ||
e37a7e55 CP |
348 | static void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma, |
349 | const u32 *iv) | |
350 | { | |
351 | u32 valmr = 0; | |
352 | ||
353 | /* MR register must be set before IV registers */ | |
354 | if (dd->ctx->keylen == AES_KEYSIZE_128) | |
355 | valmr |= AES_MR_KEYSIZE_128; | |
356 | else if (dd->ctx->keylen == AES_KEYSIZE_192) | |
357 | valmr |= AES_MR_KEYSIZE_192; | |
358 | else | |
359 | valmr |= AES_MR_KEYSIZE_256; | |
360 | ||
361 | valmr |= dd->flags & AES_FLAGS_MODE_MASK; | |
362 | ||
363 | if (use_dma) { | |
364 | valmr |= AES_MR_SMOD_IDATAR0; | |
365 | if (dd->caps.has_dualbuff) | |
366 | valmr |= AES_MR_DUALBUFF; | |
367 | } else { | |
368 | valmr |= AES_MR_SMOD_AUTO; | |
369 | } | |
370 | ||
371 | atmel_aes_write(dd, AES_MR, valmr); | |
372 | ||
373 | atmel_aes_write_n(dd, AES_KEYWR(0), dd->ctx->key, | |
374 | SIZE_IN_WORDS(dd->ctx->keylen)); | |
375 | ||
376 | if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB) | |
377 | atmel_aes_write_block(dd, AES_IVR(0), iv); | |
378 | } | |
379 | ||
bbe628ed CP |
380 | |
381 | /* CPU transfer */ | |
382 | ||
383 | static int atmel_aes_cpu_transfer(struct atmel_aes_dev *dd) | |
bd3c7b5c | 384 | { |
bbe628ed CP |
385 | int err = 0; |
386 | u32 isr; | |
bd3c7b5c | 387 | |
bbe628ed CP |
388 | for (;;) { |
389 | atmel_aes_read_block(dd, AES_ODATAR(0), dd->data); | |
390 | dd->data += 4; | |
391 | dd->datalen -= AES_BLOCK_SIZE; | |
392 | ||
393 | if (dd->datalen < AES_BLOCK_SIZE) | |
394 | break; | |
395 | ||
396 | atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); | |
397 | ||
398 | isr = atmel_aes_read(dd, AES_ISR); | |
399 | if (!(isr & AES_INT_DATARDY)) { | |
400 | dd->resume = atmel_aes_cpu_transfer; | |
401 | atmel_aes_write(dd, AES_IER, AES_INT_DATARDY); | |
402 | return -EINPROGRESS; | |
403 | } | |
404 | } | |
405 | ||
406 | if (!sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst), | |
407 | dd->buf, dd->total)) | |
408 | err = -EINVAL; | |
409 | ||
410 | if (err) | |
411 | return atmel_aes_complete(dd, err); | |
412 | ||
413 | return dd->cpu_transfer_complete(dd); | |
bd3c7b5c NR |
414 | } |
415 | ||
bbe628ed CP |
416 | static int atmel_aes_cpu_start(struct atmel_aes_dev *dd, |
417 | struct scatterlist *src, | |
418 | struct scatterlist *dst, | |
419 | size_t len, | |
420 | atmel_aes_fn_t resume) | |
bd3c7b5c | 421 | { |
bbe628ed | 422 | size_t padlen = atmel_aes_padlen(len, AES_BLOCK_SIZE); |
77dacf5f | 423 | |
bbe628ed CP |
424 | if (unlikely(len == 0)) |
425 | return -EINVAL; | |
77dacf5f | 426 | |
bbe628ed | 427 | sg_copy_to_buffer(src, sg_nents(src), dd->buf, len); |
77dacf5f | 428 | |
bbe628ed CP |
429 | dd->total = len; |
430 | dd->real_dst = dst; | |
431 | dd->cpu_transfer_complete = resume; | |
432 | dd->datalen = len + padlen; | |
433 | dd->data = (u32 *)dd->buf; | |
434 | atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); | |
435 | return atmel_aes_wait_for_data_ready(dd, atmel_aes_cpu_transfer); | |
436 | } | |
77dacf5f | 437 | |
77dacf5f | 438 | |
bbe628ed CP |
439 | /* DMA transfer */ |
440 | ||
441 | static void atmel_aes_dma_callback(void *data); | |
442 | ||
443 | static bool atmel_aes_check_aligned(struct atmel_aes_dev *dd, | |
444 | struct scatterlist *sg, | |
445 | size_t len, | |
446 | struct atmel_aes_dma *dma) | |
447 | { | |
448 | int nents; | |
449 | ||
450 | if (!IS_ALIGNED(len, dd->ctx->block_size)) | |
451 | return false; | |
452 | ||
453 | for (nents = 0; sg; sg = sg_next(sg), ++nents) { | |
454 | if (!IS_ALIGNED(sg->offset, sizeof(u32))) | |
455 | return false; | |
456 | ||
457 | if (len <= sg->length) { | |
458 | if (!IS_ALIGNED(len, dd->ctx->block_size)) | |
459 | return false; | |
460 | ||
461 | dma->nents = nents+1; | |
462 | dma->remainder = sg->length - len; | |
463 | sg->length = len; | |
464 | return true; | |
465 | } | |
466 | ||
467 | if (!IS_ALIGNED(sg->length, dd->ctx->block_size)) | |
468 | return false; | |
469 | ||
470 | len -= sg->length; | |
77dacf5f | 471 | } |
bd3c7b5c | 472 | |
bbe628ed CP |
473 | return false; |
474 | } | |
bd3c7b5c | 475 | |
bbe628ed CP |
476 | static inline void atmel_aes_restore_sg(const struct atmel_aes_dma *dma) |
477 | { | |
478 | struct scatterlist *sg = dma->sg; | |
479 | int nents = dma->nents; | |
bd3c7b5c | 480 | |
bbe628ed CP |
481 | if (!dma->remainder) |
482 | return; | |
bd3c7b5c | 483 | |
bbe628ed CP |
484 | while (--nents > 0 && sg) |
485 | sg = sg_next(sg); | |
bd3c7b5c | 486 | |
bbe628ed CP |
487 | if (!sg) |
488 | return; | |
bd3c7b5c | 489 | |
bbe628ed CP |
490 | sg->length += dma->remainder; |
491 | } | |
bd3c7b5c | 492 | |
bbe628ed CP |
493 | static int atmel_aes_map(struct atmel_aes_dev *dd, |
494 | struct scatterlist *src, | |
495 | struct scatterlist *dst, | |
496 | size_t len) | |
497 | { | |
498 | bool src_aligned, dst_aligned; | |
499 | size_t padlen; | |
cadc4ab8 | 500 | |
bbe628ed CP |
501 | dd->total = len; |
502 | dd->src.sg = src; | |
503 | dd->dst.sg = dst; | |
504 | dd->real_dst = dst; | |
bd3c7b5c | 505 | |
bbe628ed CP |
506 | src_aligned = atmel_aes_check_aligned(dd, src, len, &dd->src); |
507 | if (src == dst) | |
508 | dst_aligned = src_aligned; | |
509 | else | |
510 | dst_aligned = atmel_aes_check_aligned(dd, dst, len, &dd->dst); | |
511 | if (!src_aligned || !dst_aligned) { | |
512 | padlen = atmel_aes_padlen(len, dd->ctx->block_size); | |
513 | ||
514 | if (dd->buflen < len + padlen) | |
515 | return -ENOMEM; | |
516 | ||
517 | if (!src_aligned) { | |
518 | sg_copy_to_buffer(src, sg_nents(src), dd->buf, len); | |
519 | dd->src.sg = &dd->aligned_sg; | |
520 | dd->src.nents = 1; | |
521 | dd->src.remainder = 0; | |
522 | } | |
bd3c7b5c | 523 | |
bbe628ed CP |
524 | if (!dst_aligned) { |
525 | dd->dst.sg = &dd->aligned_sg; | |
526 | dd->dst.nents = 1; | |
527 | dd->dst.remainder = 0; | |
528 | } | |
bd3c7b5c | 529 | |
bbe628ed CP |
530 | sg_init_table(&dd->aligned_sg, 1); |
531 | sg_set_buf(&dd->aligned_sg, dd->buf, len + padlen); | |
532 | } | |
bd3c7b5c | 533 | |
bbe628ed CP |
534 | if (dd->src.sg == dd->dst.sg) { |
535 | dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents, | |
536 | DMA_BIDIRECTIONAL); | |
537 | dd->dst.sg_len = dd->src.sg_len; | |
538 | if (!dd->src.sg_len) | |
539 | return -EFAULT; | |
540 | } else { | |
541 | dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents, | |
542 | DMA_TO_DEVICE); | |
543 | if (!dd->src.sg_len) | |
544 | return -EFAULT; | |
545 | ||
546 | dd->dst.sg_len = dma_map_sg(dd->dev, dd->dst.sg, dd->dst.nents, | |
547 | DMA_FROM_DEVICE); | |
548 | if (!dd->dst.sg_len) { | |
549 | dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents, | |
550 | DMA_TO_DEVICE); | |
551 | return -EFAULT; | |
552 | } | |
553 | } | |
bd3c7b5c NR |
554 | |
555 | return 0; | |
bd3c7b5c NR |
556 | } |
557 | ||
bbe628ed | 558 | static void atmel_aes_unmap(struct atmel_aes_dev *dd) |
bd3c7b5c | 559 | { |
bbe628ed CP |
560 | if (dd->src.sg == dd->dst.sg) { |
561 | dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents, | |
562 | DMA_BIDIRECTIONAL); | |
ccbf7298 | 563 | |
bbe628ed CP |
564 | if (dd->src.sg != &dd->aligned_sg) |
565 | atmel_aes_restore_sg(&dd->src); | |
566 | } else { | |
567 | dma_unmap_sg(dd->dev, dd->dst.sg, dd->dst.nents, | |
568 | DMA_FROM_DEVICE); | |
289b2623 | 569 | |
bbe628ed CP |
570 | if (dd->dst.sg != &dd->aligned_sg) |
571 | atmel_aes_restore_sg(&dd->dst); | |
bd3c7b5c | 572 | |
bbe628ed CP |
573 | dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents, |
574 | DMA_TO_DEVICE); | |
575 | ||
576 | if (dd->src.sg != &dd->aligned_sg) | |
577 | atmel_aes_restore_sg(&dd->src); | |
578 | } | |
579 | ||
580 | if (dd->dst.sg == &dd->aligned_sg) | |
581 | sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst), | |
582 | dd->buf, dd->total); | |
583 | } | |
bd3c7b5c | 584 | |
bbe628ed CP |
585 | static int atmel_aes_dma_transfer_start(struct atmel_aes_dev *dd, |
586 | enum dma_slave_buswidth addr_width, | |
587 | enum dma_transfer_direction dir, | |
588 | u32 maxburst) | |
589 | { | |
590 | struct dma_async_tx_descriptor *desc; | |
591 | struct dma_slave_config config; | |
592 | dma_async_tx_callback callback; | |
593 | struct atmel_aes_dma *dma; | |
594 | int err; | |
595 | ||
596 | memset(&config, 0, sizeof(config)); | |
597 | config.direction = dir; | |
598 | config.src_addr_width = addr_width; | |
599 | config.dst_addr_width = addr_width; | |
600 | config.src_maxburst = maxburst; | |
601 | config.dst_maxburst = maxburst; | |
602 | ||
603 | switch (dir) { | |
604 | case DMA_MEM_TO_DEV: | |
605 | dma = &dd->src; | |
606 | callback = NULL; | |
607 | config.dst_addr = dd->phys_base + AES_IDATAR(0); | |
608 | break; | |
bd3c7b5c | 609 | |
bbe628ed CP |
610 | case DMA_DEV_TO_MEM: |
611 | dma = &dd->dst; | |
612 | callback = atmel_aes_dma_callback; | |
613 | config.src_addr = dd->phys_base + AES_ODATAR(0); | |
614 | break; | |
615 | ||
616 | default: | |
bd3c7b5c | 617 | return -EINVAL; |
bbe628ed | 618 | } |
bd3c7b5c | 619 | |
bbe628ed CP |
620 | err = dmaengine_slave_config(dma->chan, &config); |
621 | if (err) | |
622 | return err; | |
bd3c7b5c | 623 | |
bbe628ed CP |
624 | desc = dmaengine_prep_slave_sg(dma->chan, dma->sg, dma->sg_len, dir, |
625 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
626 | if (!desc) | |
627 | return -ENOMEM; | |
bd3c7b5c | 628 | |
bbe628ed CP |
629 | desc->callback = callback; |
630 | desc->callback_param = dd; | |
631 | dmaengine_submit(desc); | |
632 | dma_async_issue_pending(dma->chan); | |
bd3c7b5c | 633 | |
bbe628ed CP |
634 | return 0; |
635 | } | |
10f12c1b | 636 | |
bbe628ed CP |
637 | static void atmel_aes_dma_transfer_stop(struct atmel_aes_dev *dd, |
638 | enum dma_transfer_direction dir) | |
bd3c7b5c | 639 | { |
bbe628ed | 640 | struct atmel_aes_dma *dma; |
cadc4ab8 | 641 | |
bbe628ed CP |
642 | switch (dir) { |
643 | case DMA_MEM_TO_DEV: | |
644 | dma = &dd->src; | |
645 | break; | |
646 | ||
647 | case DMA_DEV_TO_MEM: | |
648 | dma = &dd->dst; | |
649 | break; | |
cadc4ab8 | 650 | |
bbe628ed CP |
651 | default: |
652 | return; | |
cadc4ab8 NR |
653 | } |
654 | ||
bbe628ed CP |
655 | dmaengine_terminate_all(dma->chan); |
656 | } | |
cadc4ab8 | 657 | |
bbe628ed CP |
658 | static int atmel_aes_dma_start(struct atmel_aes_dev *dd, |
659 | struct scatterlist *src, | |
660 | struct scatterlist *dst, | |
661 | size_t len, | |
662 | atmel_aes_fn_t resume) | |
663 | { | |
664 | enum dma_slave_buswidth addr_width; | |
665 | u32 maxburst; | |
666 | int err; | |
cadc4ab8 | 667 | |
bbe628ed CP |
668 | switch (dd->ctx->block_size) { |
669 | case CFB8_BLOCK_SIZE: | |
670 | addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
671 | maxburst = 1; | |
672 | break; | |
cadc4ab8 | 673 | |
bbe628ed CP |
674 | case CFB16_BLOCK_SIZE: |
675 | addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
676 | maxburst = 1; | |
677 | break; | |
cadc4ab8 | 678 | |
bbe628ed CP |
679 | case CFB32_BLOCK_SIZE: |
680 | case CFB64_BLOCK_SIZE: | |
681 | addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
682 | maxburst = 1; | |
683 | break; | |
cadc4ab8 | 684 | |
bbe628ed CP |
685 | case AES_BLOCK_SIZE: |
686 | addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
687 | maxburst = dd->caps.max_burst_size; | |
688 | break; | |
bd3c7b5c | 689 | |
bbe628ed CP |
690 | default: |
691 | err = -EINVAL; | |
692 | goto exit; | |
693 | } | |
289b2623 | 694 | |
bbe628ed CP |
695 | err = atmel_aes_map(dd, src, dst, len); |
696 | if (err) | |
697 | goto exit; | |
cadc4ab8 | 698 | |
bbe628ed | 699 | dd->resume = resume; |
cadc4ab8 | 700 | |
bbe628ed CP |
701 | /* Set output DMA transfer first */ |
702 | err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_DEV_TO_MEM, | |
703 | maxburst); | |
704 | if (err) | |
705 | goto unmap; | |
bd3c7b5c | 706 | |
bbe628ed CP |
707 | /* Then set input DMA transfer */ |
708 | err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_MEM_TO_DEV, | |
709 | maxburst); | |
710 | if (err) | |
711 | goto output_transfer_stop; | |
bd3c7b5c | 712 | |
bbe628ed | 713 | return -EINPROGRESS; |
cadc4ab8 | 714 | |
bbe628ed CP |
715 | output_transfer_stop: |
716 | atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM); | |
717 | unmap: | |
718 | atmel_aes_unmap(dd); | |
719 | exit: | |
720 | return atmel_aes_complete(dd, err); | |
721 | } | |
bd3c7b5c | 722 | |
bbe628ed CP |
723 | static void atmel_aes_dma_stop(struct atmel_aes_dev *dd) |
724 | { | |
725 | atmel_aes_dma_transfer_stop(dd, DMA_MEM_TO_DEV); | |
726 | atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM); | |
727 | atmel_aes_unmap(dd); | |
728 | } | |
729 | ||
730 | static void atmel_aes_dma_callback(void *data) | |
731 | { | |
732 | struct atmel_aes_dev *dd = data; | |
733 | ||
734 | atmel_aes_dma_stop(dd); | |
735 | dd->is_async = true; | |
736 | (void)dd->resume(dd); | |
bd3c7b5c NR |
737 | } |
738 | ||
bd3c7b5c | 739 | static int atmel_aes_handle_queue(struct atmel_aes_dev *dd, |
ccbf7298 | 740 | struct crypto_async_request *new_areq) |
bd3c7b5c | 741 | { |
ccbf7298 CP |
742 | struct crypto_async_request *areq, *backlog; |
743 | struct atmel_aes_base_ctx *ctx; | |
bd3c7b5c NR |
744 | unsigned long flags; |
745 | int err, ret = 0; | |
746 | ||
747 | spin_lock_irqsave(&dd->lock, flags); | |
ccbf7298 CP |
748 | if (new_areq) |
749 | ret = crypto_enqueue_request(&dd->queue, new_areq); | |
bd3c7b5c NR |
750 | if (dd->flags & AES_FLAGS_BUSY) { |
751 | spin_unlock_irqrestore(&dd->lock, flags); | |
752 | return ret; | |
753 | } | |
754 | backlog = crypto_get_backlog(&dd->queue); | |
ccbf7298 CP |
755 | areq = crypto_dequeue_request(&dd->queue); |
756 | if (areq) | |
bd3c7b5c NR |
757 | dd->flags |= AES_FLAGS_BUSY; |
758 | spin_unlock_irqrestore(&dd->lock, flags); | |
759 | ||
ccbf7298 | 760 | if (!areq) |
bd3c7b5c NR |
761 | return ret; |
762 | ||
763 | if (backlog) | |
764 | backlog->complete(backlog, -EINPROGRESS); | |
765 | ||
ccbf7298 CP |
766 | ctx = crypto_tfm_ctx(areq->tfm); |
767 | ||
768 | dd->areq = areq; | |
769 | dd->ctx = ctx; | |
10f12c1b | 770 | dd->is_async = (areq != new_areq); |
ccbf7298 CP |
771 | |
772 | err = ctx->start(dd); | |
10f12c1b | 773 | return (dd->is_async) ? ret : err; |
ccbf7298 CP |
774 | } |
775 | ||
e37a7e55 CP |
776 | |
777 | /* AES async block ciphers */ | |
778 | ||
bbe628ed CP |
779 | static int atmel_aes_transfer_complete(struct atmel_aes_dev *dd) |
780 | { | |
781 | return atmel_aes_complete(dd, 0); | |
782 | } | |
783 | ||
ccbf7298 CP |
784 | static int atmel_aes_start(struct atmel_aes_dev *dd) |
785 | { | |
786 | struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq); | |
bbe628ed CP |
787 | struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req); |
788 | bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD || | |
789 | dd->ctx->block_size != AES_BLOCK_SIZE); | |
ccbf7298 | 790 | int err; |
bd3c7b5c | 791 | |
77dacf5f | 792 | atmel_aes_set_mode(dd, rctx); |
bd3c7b5c | 793 | |
cdfab4a7 | 794 | err = atmel_aes_hw_init(dd); |
bbe628ed | 795 | if (err) |
10f12c1b | 796 | return atmel_aes_complete(dd, err); |
bd3c7b5c | 797 | |
bbe628ed CP |
798 | atmel_aes_write_ctrl(dd, use_dma, req->info); |
799 | if (use_dma) | |
800 | return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes, | |
801 | atmel_aes_transfer_complete); | |
bd3c7b5c | 802 | |
bbe628ed CP |
803 | return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes, |
804 | atmel_aes_transfer_complete); | |
bd3c7b5c NR |
805 | } |
806 | ||
fcac8365 CP |
807 | static inline struct atmel_aes_ctr_ctx * |
808 | atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx *ctx) | |
809 | { | |
810 | return container_of(ctx, struct atmel_aes_ctr_ctx, base); | |
811 | } | |
812 | ||
813 | static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd) | |
814 | { | |
815 | struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx); | |
816 | struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq); | |
817 | struct scatterlist *src, *dst; | |
818 | u32 ctr, blocks; | |
819 | size_t datalen; | |
820 | bool use_dma, fragmented = false; | |
821 | ||
822 | /* Check for transfer completion. */ | |
823 | ctx->offset += dd->total; | |
824 | if (ctx->offset >= req->nbytes) | |
825 | return atmel_aes_transfer_complete(dd); | |
826 | ||
827 | /* Compute data length. */ | |
828 | datalen = req->nbytes - ctx->offset; | |
829 | blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE); | |
830 | ctr = be32_to_cpu(ctx->iv[3]); | |
831 | if (dd->caps.has_ctr32) { | |
832 | /* Check 32bit counter overflow. */ | |
833 | u32 start = ctr; | |
834 | u32 end = start + blocks - 1; | |
835 | ||
836 | if (end < start) { | |
837 | ctr |= 0xffffffff; | |
838 | datalen = AES_BLOCK_SIZE * -start; | |
839 | fragmented = true; | |
840 | } | |
841 | } else { | |
842 | /* Check 16bit counter overflow. */ | |
843 | u16 start = ctr & 0xffff; | |
844 | u16 end = start + (u16)blocks - 1; | |
845 | ||
846 | if (blocks >> 16 || end < start) { | |
847 | ctr |= 0xffff; | |
848 | datalen = AES_BLOCK_SIZE * (0x10000-start); | |
849 | fragmented = true; | |
850 | } | |
851 | } | |
852 | use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD); | |
853 | ||
854 | /* Jump to offset. */ | |
855 | src = scatterwalk_ffwd(ctx->src, req->src, ctx->offset); | |
856 | dst = ((req->src == req->dst) ? src : | |
857 | scatterwalk_ffwd(ctx->dst, req->dst, ctx->offset)); | |
858 | ||
859 | /* Configure hardware. */ | |
860 | atmel_aes_write_ctrl(dd, use_dma, ctx->iv); | |
861 | if (unlikely(fragmented)) { | |
862 | /* | |
863 | * Increment the counter manually to cope with the hardware | |
864 | * counter overflow. | |
865 | */ | |
866 | ctx->iv[3] = cpu_to_be32(ctr); | |
867 | crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE); | |
868 | } | |
869 | ||
870 | if (use_dma) | |
871 | return atmel_aes_dma_start(dd, src, dst, datalen, | |
872 | atmel_aes_ctr_transfer); | |
873 | ||
874 | return atmel_aes_cpu_start(dd, src, dst, datalen, | |
875 | atmel_aes_ctr_transfer); | |
876 | } | |
877 | ||
878 | static int atmel_aes_ctr_start(struct atmel_aes_dev *dd) | |
879 | { | |
880 | struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx); | |
881 | struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq); | |
882 | struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req); | |
883 | int err; | |
884 | ||
885 | atmel_aes_set_mode(dd, rctx); | |
886 | ||
887 | err = atmel_aes_hw_init(dd); | |
888 | if (err) | |
889 | return atmel_aes_complete(dd, err); | |
890 | ||
891 | memcpy(ctx->iv, req->info, AES_BLOCK_SIZE); | |
892 | ctx->offset = 0; | |
893 | dd->total = 0; | |
894 | return atmel_aes_ctr_transfer(dd); | |
895 | } | |
896 | ||
bd3c7b5c NR |
897 | static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode) |
898 | { | |
afbac17e CP |
899 | struct atmel_aes_base_ctx *ctx; |
900 | struct atmel_aes_reqctx *rctx; | |
bd3c7b5c NR |
901 | struct atmel_aes_dev *dd; |
902 | ||
afbac17e | 903 | ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req)); |
77dacf5f CP |
904 | switch (mode & AES_FLAGS_OPMODE_MASK) { |
905 | case AES_FLAGS_CFB8: | |
cadc4ab8 | 906 | ctx->block_size = CFB8_BLOCK_SIZE; |
77dacf5f CP |
907 | break; |
908 | ||
909 | case AES_FLAGS_CFB16: | |
cadc4ab8 | 910 | ctx->block_size = CFB16_BLOCK_SIZE; |
77dacf5f CP |
911 | break; |
912 | ||
913 | case AES_FLAGS_CFB32: | |
cadc4ab8 | 914 | ctx->block_size = CFB32_BLOCK_SIZE; |
77dacf5f CP |
915 | break; |
916 | ||
917 | case AES_FLAGS_CFB64: | |
9f84951f | 918 | ctx->block_size = CFB64_BLOCK_SIZE; |
77dacf5f CP |
919 | break; |
920 | ||
921 | default: | |
cadc4ab8 | 922 | ctx->block_size = AES_BLOCK_SIZE; |
77dacf5f | 923 | break; |
bd3c7b5c NR |
924 | } |
925 | ||
926 | dd = atmel_aes_find_dev(ctx); | |
927 | if (!dd) | |
928 | return -ENODEV; | |
929 | ||
afbac17e | 930 | rctx = ablkcipher_request_ctx(req); |
bd3c7b5c NR |
931 | rctx->mode = mode; |
932 | ||
ccbf7298 | 933 | return atmel_aes_handle_queue(dd, &req->base); |
bd3c7b5c NR |
934 | } |
935 | ||
bd3c7b5c NR |
936 | static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, |
937 | unsigned int keylen) | |
938 | { | |
ccbf7298 | 939 | struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(tfm); |
bd3c7b5c | 940 | |
afbac17e CP |
941 | if (keylen != AES_KEYSIZE_128 && |
942 | keylen != AES_KEYSIZE_192 && | |
943 | keylen != AES_KEYSIZE_256) { | |
bd3c7b5c NR |
944 | crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); |
945 | return -EINVAL; | |
946 | } | |
947 | ||
948 | memcpy(ctx->key, key, keylen); | |
949 | ctx->keylen = keylen; | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
954 | static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req) | |
955 | { | |
77dacf5f | 956 | return atmel_aes_crypt(req, AES_FLAGS_ECB | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
957 | } |
958 | ||
959 | static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req) | |
960 | { | |
77dacf5f | 961 | return atmel_aes_crypt(req, AES_FLAGS_ECB); |
bd3c7b5c NR |
962 | } |
963 | ||
964 | static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req) | |
965 | { | |
afbac17e | 966 | return atmel_aes_crypt(req, AES_FLAGS_CBC | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
967 | } |
968 | ||
969 | static int atmel_aes_cbc_decrypt(struct ablkcipher_request *req) | |
970 | { | |
afbac17e | 971 | return atmel_aes_crypt(req, AES_FLAGS_CBC); |
bd3c7b5c NR |
972 | } |
973 | ||
974 | static int atmel_aes_ofb_encrypt(struct ablkcipher_request *req) | |
975 | { | |
afbac17e | 976 | return atmel_aes_crypt(req, AES_FLAGS_OFB | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
977 | } |
978 | ||
979 | static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req) | |
980 | { | |
afbac17e | 981 | return atmel_aes_crypt(req, AES_FLAGS_OFB); |
bd3c7b5c NR |
982 | } |
983 | ||
984 | static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req) | |
985 | { | |
77dacf5f | 986 | return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
987 | } |
988 | ||
989 | static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req) | |
990 | { | |
77dacf5f | 991 | return atmel_aes_crypt(req, AES_FLAGS_CFB128); |
bd3c7b5c NR |
992 | } |
993 | ||
994 | static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req) | |
995 | { | |
77dacf5f | 996 | return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
997 | } |
998 | ||
999 | static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req) | |
1000 | { | |
77dacf5f | 1001 | return atmel_aes_crypt(req, AES_FLAGS_CFB64); |
bd3c7b5c NR |
1002 | } |
1003 | ||
1004 | static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req) | |
1005 | { | |
77dacf5f | 1006 | return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1007 | } |
1008 | ||
1009 | static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req) | |
1010 | { | |
77dacf5f | 1011 | return atmel_aes_crypt(req, AES_FLAGS_CFB32); |
bd3c7b5c NR |
1012 | } |
1013 | ||
1014 | static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req) | |
1015 | { | |
77dacf5f | 1016 | return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1017 | } |
1018 | ||
1019 | static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req) | |
1020 | { | |
77dacf5f | 1021 | return atmel_aes_crypt(req, AES_FLAGS_CFB16); |
bd3c7b5c NR |
1022 | } |
1023 | ||
1024 | static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req) | |
1025 | { | |
77dacf5f | 1026 | return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1027 | } |
1028 | ||
1029 | static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req) | |
1030 | { | |
77dacf5f | 1031 | return atmel_aes_crypt(req, AES_FLAGS_CFB8); |
bd3c7b5c NR |
1032 | } |
1033 | ||
1034 | static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req) | |
1035 | { | |
afbac17e | 1036 | return atmel_aes_crypt(req, AES_FLAGS_CTR | AES_FLAGS_ENCRYPT); |
bd3c7b5c NR |
1037 | } |
1038 | ||
1039 | static int atmel_aes_ctr_decrypt(struct ablkcipher_request *req) | |
1040 | { | |
afbac17e | 1041 | return atmel_aes_crypt(req, AES_FLAGS_CTR); |
bd3c7b5c NR |
1042 | } |
1043 | ||
1044 | static int atmel_aes_cra_init(struct crypto_tfm *tfm) | |
1045 | { | |
ccbf7298 CP |
1046 | struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm); |
1047 | ||
bd3c7b5c | 1048 | tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx); |
ccbf7298 | 1049 | ctx->base.start = atmel_aes_start; |
bd3c7b5c NR |
1050 | |
1051 | return 0; | |
1052 | } | |
1053 | ||
fcac8365 CP |
1054 | static int atmel_aes_ctr_cra_init(struct crypto_tfm *tfm) |
1055 | { | |
1056 | struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm); | |
1057 | ||
1058 | tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx); | |
1059 | ctx->base.start = atmel_aes_ctr_start; | |
1060 | ||
1061 | return 0; | |
1062 | } | |
1063 | ||
bd3c7b5c NR |
1064 | static void atmel_aes_cra_exit(struct crypto_tfm *tfm) |
1065 | { | |
1066 | } | |
1067 | ||
1068 | static struct crypto_alg aes_algs[] = { | |
1069 | { | |
1070 | .cra_name = "ecb(aes)", | |
1071 | .cra_driver_name = "atmel-ecb-aes", | |
88efd9a9 | 1072 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1073 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1074 | .cra_blocksize = AES_BLOCK_SIZE, | |
1075 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1076 | .cra_alignmask = 0xf, |
bd3c7b5c NR |
1077 | .cra_type = &crypto_ablkcipher_type, |
1078 | .cra_module = THIS_MODULE, | |
1079 | .cra_init = atmel_aes_cra_init, | |
1080 | .cra_exit = atmel_aes_cra_exit, | |
1081 | .cra_u.ablkcipher = { | |
1082 | .min_keysize = AES_MIN_KEY_SIZE, | |
1083 | .max_keysize = AES_MAX_KEY_SIZE, | |
1084 | .setkey = atmel_aes_setkey, | |
1085 | .encrypt = atmel_aes_ecb_encrypt, | |
1086 | .decrypt = atmel_aes_ecb_decrypt, | |
1087 | } | |
1088 | }, | |
1089 | { | |
1090 | .cra_name = "cbc(aes)", | |
1091 | .cra_driver_name = "atmel-cbc-aes", | |
88efd9a9 | 1092 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1093 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1094 | .cra_blocksize = AES_BLOCK_SIZE, | |
1095 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1096 | .cra_alignmask = 0xf, |
bd3c7b5c NR |
1097 | .cra_type = &crypto_ablkcipher_type, |
1098 | .cra_module = THIS_MODULE, | |
1099 | .cra_init = atmel_aes_cra_init, | |
1100 | .cra_exit = atmel_aes_cra_exit, | |
1101 | .cra_u.ablkcipher = { | |
1102 | .min_keysize = AES_MIN_KEY_SIZE, | |
1103 | .max_keysize = AES_MAX_KEY_SIZE, | |
1104 | .ivsize = AES_BLOCK_SIZE, | |
1105 | .setkey = atmel_aes_setkey, | |
1106 | .encrypt = atmel_aes_cbc_encrypt, | |
1107 | .decrypt = atmel_aes_cbc_decrypt, | |
1108 | } | |
1109 | }, | |
1110 | { | |
1111 | .cra_name = "ofb(aes)", | |
1112 | .cra_driver_name = "atmel-ofb-aes", | |
88efd9a9 | 1113 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1114 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1115 | .cra_blocksize = AES_BLOCK_SIZE, | |
1116 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1117 | .cra_alignmask = 0xf, |
bd3c7b5c NR |
1118 | .cra_type = &crypto_ablkcipher_type, |
1119 | .cra_module = THIS_MODULE, | |
1120 | .cra_init = atmel_aes_cra_init, | |
1121 | .cra_exit = atmel_aes_cra_exit, | |
1122 | .cra_u.ablkcipher = { | |
1123 | .min_keysize = AES_MIN_KEY_SIZE, | |
1124 | .max_keysize = AES_MAX_KEY_SIZE, | |
1125 | .ivsize = AES_BLOCK_SIZE, | |
1126 | .setkey = atmel_aes_setkey, | |
1127 | .encrypt = atmel_aes_ofb_encrypt, | |
1128 | .decrypt = atmel_aes_ofb_decrypt, | |
1129 | } | |
1130 | }, | |
1131 | { | |
1132 | .cra_name = "cfb(aes)", | |
1133 | .cra_driver_name = "atmel-cfb-aes", | |
88efd9a9 | 1134 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1135 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1136 | .cra_blocksize = AES_BLOCK_SIZE, | |
1137 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1138 | .cra_alignmask = 0xf, |
bd3c7b5c NR |
1139 | .cra_type = &crypto_ablkcipher_type, |
1140 | .cra_module = THIS_MODULE, | |
1141 | .cra_init = atmel_aes_cra_init, | |
1142 | .cra_exit = atmel_aes_cra_exit, | |
1143 | .cra_u.ablkcipher = { | |
1144 | .min_keysize = AES_MIN_KEY_SIZE, | |
1145 | .max_keysize = AES_MAX_KEY_SIZE, | |
1146 | .ivsize = AES_BLOCK_SIZE, | |
1147 | .setkey = atmel_aes_setkey, | |
1148 | .encrypt = atmel_aes_cfb_encrypt, | |
1149 | .decrypt = atmel_aes_cfb_decrypt, | |
1150 | } | |
1151 | }, | |
1152 | { | |
1153 | .cra_name = "cfb32(aes)", | |
1154 | .cra_driver_name = "atmel-cfb32-aes", | |
88efd9a9 | 1155 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1156 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1157 | .cra_blocksize = CFB32_BLOCK_SIZE, | |
1158 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1159 | .cra_alignmask = 0x3, |
bd3c7b5c NR |
1160 | .cra_type = &crypto_ablkcipher_type, |
1161 | .cra_module = THIS_MODULE, | |
1162 | .cra_init = atmel_aes_cra_init, | |
1163 | .cra_exit = atmel_aes_cra_exit, | |
1164 | .cra_u.ablkcipher = { | |
1165 | .min_keysize = AES_MIN_KEY_SIZE, | |
1166 | .max_keysize = AES_MAX_KEY_SIZE, | |
1167 | .ivsize = AES_BLOCK_SIZE, | |
1168 | .setkey = atmel_aes_setkey, | |
1169 | .encrypt = atmel_aes_cfb32_encrypt, | |
1170 | .decrypt = atmel_aes_cfb32_decrypt, | |
1171 | } | |
1172 | }, | |
1173 | { | |
1174 | .cra_name = "cfb16(aes)", | |
1175 | .cra_driver_name = "atmel-cfb16-aes", | |
88efd9a9 | 1176 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1177 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1178 | .cra_blocksize = CFB16_BLOCK_SIZE, | |
1179 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1180 | .cra_alignmask = 0x1, |
bd3c7b5c NR |
1181 | .cra_type = &crypto_ablkcipher_type, |
1182 | .cra_module = THIS_MODULE, | |
1183 | .cra_init = atmel_aes_cra_init, | |
1184 | .cra_exit = atmel_aes_cra_exit, | |
1185 | .cra_u.ablkcipher = { | |
1186 | .min_keysize = AES_MIN_KEY_SIZE, | |
1187 | .max_keysize = AES_MAX_KEY_SIZE, | |
1188 | .ivsize = AES_BLOCK_SIZE, | |
1189 | .setkey = atmel_aes_setkey, | |
1190 | .encrypt = atmel_aes_cfb16_encrypt, | |
1191 | .decrypt = atmel_aes_cfb16_decrypt, | |
1192 | } | |
1193 | }, | |
1194 | { | |
1195 | .cra_name = "cfb8(aes)", | |
1196 | .cra_driver_name = "atmel-cfb8-aes", | |
88efd9a9 | 1197 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c | 1198 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
e5d8c961 | 1199 | .cra_blocksize = CFB8_BLOCK_SIZE, |
bd3c7b5c NR |
1200 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), |
1201 | .cra_alignmask = 0x0, | |
1202 | .cra_type = &crypto_ablkcipher_type, | |
1203 | .cra_module = THIS_MODULE, | |
1204 | .cra_init = atmel_aes_cra_init, | |
1205 | .cra_exit = atmel_aes_cra_exit, | |
1206 | .cra_u.ablkcipher = { | |
1207 | .min_keysize = AES_MIN_KEY_SIZE, | |
1208 | .max_keysize = AES_MAX_KEY_SIZE, | |
1209 | .ivsize = AES_BLOCK_SIZE, | |
1210 | .setkey = atmel_aes_setkey, | |
1211 | .encrypt = atmel_aes_cfb8_encrypt, | |
1212 | .decrypt = atmel_aes_cfb8_decrypt, | |
1213 | } | |
1214 | }, | |
1215 | { | |
1216 | .cra_name = "ctr(aes)", | |
1217 | .cra_driver_name = "atmel-ctr-aes", | |
88efd9a9 | 1218 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c | 1219 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
da7b850e | 1220 | .cra_blocksize = 1, |
fcac8365 | 1221 | .cra_ctxsize = sizeof(struct atmel_aes_ctr_ctx), |
cadc4ab8 | 1222 | .cra_alignmask = 0xf, |
bd3c7b5c NR |
1223 | .cra_type = &crypto_ablkcipher_type, |
1224 | .cra_module = THIS_MODULE, | |
fcac8365 | 1225 | .cra_init = atmel_aes_ctr_cra_init, |
bd3c7b5c NR |
1226 | .cra_exit = atmel_aes_cra_exit, |
1227 | .cra_u.ablkcipher = { | |
1228 | .min_keysize = AES_MIN_KEY_SIZE, | |
1229 | .max_keysize = AES_MAX_KEY_SIZE, | |
1230 | .ivsize = AES_BLOCK_SIZE, | |
1231 | .setkey = atmel_aes_setkey, | |
1232 | .encrypt = atmel_aes_ctr_encrypt, | |
1233 | .decrypt = atmel_aes_ctr_decrypt, | |
1234 | } | |
1235 | }, | |
1236 | }; | |
1237 | ||
cadc4ab8 | 1238 | static struct crypto_alg aes_cfb64_alg = { |
bd3c7b5c NR |
1239 | .cra_name = "cfb64(aes)", |
1240 | .cra_driver_name = "atmel-cfb64-aes", | |
88efd9a9 | 1241 | .cra_priority = ATMEL_AES_PRIORITY, |
bd3c7b5c NR |
1242 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, |
1243 | .cra_blocksize = CFB64_BLOCK_SIZE, | |
1244 | .cra_ctxsize = sizeof(struct atmel_aes_ctx), | |
cadc4ab8 | 1245 | .cra_alignmask = 0x7, |
bd3c7b5c NR |
1246 | .cra_type = &crypto_ablkcipher_type, |
1247 | .cra_module = THIS_MODULE, | |
1248 | .cra_init = atmel_aes_cra_init, | |
1249 | .cra_exit = atmel_aes_cra_exit, | |
1250 | .cra_u.ablkcipher = { | |
1251 | .min_keysize = AES_MIN_KEY_SIZE, | |
1252 | .max_keysize = AES_MAX_KEY_SIZE, | |
1253 | .ivsize = AES_BLOCK_SIZE, | |
1254 | .setkey = atmel_aes_setkey, | |
1255 | .encrypt = atmel_aes_cfb64_encrypt, | |
1256 | .decrypt = atmel_aes_cfb64_decrypt, | |
1257 | } | |
bd3c7b5c NR |
1258 | }; |
1259 | ||
e37a7e55 | 1260 | |
d4419548 CP |
1261 | /* gcm aead functions */ |
1262 | ||
1263 | static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd, | |
1264 | const u32 *data, size_t datalen, | |
1265 | const u32 *ghash_in, u32 *ghash_out, | |
1266 | atmel_aes_fn_t resume); | |
1267 | static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd); | |
1268 | static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd); | |
1269 | ||
1270 | static int atmel_aes_gcm_start(struct atmel_aes_dev *dd); | |
1271 | static int atmel_aes_gcm_process(struct atmel_aes_dev *dd); | |
1272 | static int atmel_aes_gcm_length(struct atmel_aes_dev *dd); | |
1273 | static int atmel_aes_gcm_data(struct atmel_aes_dev *dd); | |
1274 | static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd); | |
1275 | static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd); | |
1276 | static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd); | |
1277 | ||
1278 | static inline struct atmel_aes_gcm_ctx * | |
1279 | atmel_aes_gcm_ctx_cast(struct atmel_aes_base_ctx *ctx) | |
1280 | { | |
1281 | return container_of(ctx, struct atmel_aes_gcm_ctx, base); | |
1282 | } | |
1283 | ||
1284 | static int atmel_aes_gcm_ghash(struct atmel_aes_dev *dd, | |
1285 | const u32 *data, size_t datalen, | |
1286 | const u32 *ghash_in, u32 *ghash_out, | |
1287 | atmel_aes_fn_t resume) | |
1288 | { | |
1289 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1290 | ||
1291 | dd->data = (u32 *)data; | |
1292 | dd->datalen = datalen; | |
1293 | ctx->ghash_in = ghash_in; | |
1294 | ctx->ghash_out = ghash_out; | |
1295 | ctx->ghash_resume = resume; | |
1296 | ||
1297 | atmel_aes_write_ctrl(dd, false, NULL); | |
1298 | return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_ghash_init); | |
1299 | } | |
1300 | ||
1301 | static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd) | |
1302 | { | |
1303 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1304 | ||
1305 | /* Set the data length. */ | |
1306 | atmel_aes_write(dd, AES_AADLENR, dd->total); | |
1307 | atmel_aes_write(dd, AES_CLENR, 0); | |
1308 | ||
1309 | /* If needed, overwrite the GCM Intermediate Hash Word Registers */ | |
1310 | if (ctx->ghash_in) | |
1311 | atmel_aes_write_block(dd, AES_GHASHR(0), ctx->ghash_in); | |
1312 | ||
1313 | return atmel_aes_gcm_ghash_finalize(dd); | |
1314 | } | |
1315 | ||
1316 | static int atmel_aes_gcm_ghash_finalize(struct atmel_aes_dev *dd) | |
1317 | { | |
1318 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1319 | u32 isr; | |
1320 | ||
1321 | /* Write data into the Input Data Registers. */ | |
1322 | while (dd->datalen > 0) { | |
1323 | atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); | |
1324 | dd->data += 4; | |
1325 | dd->datalen -= AES_BLOCK_SIZE; | |
1326 | ||
1327 | isr = atmel_aes_read(dd, AES_ISR); | |
1328 | if (!(isr & AES_INT_DATARDY)) { | |
1329 | dd->resume = atmel_aes_gcm_ghash_finalize; | |
1330 | atmel_aes_write(dd, AES_IER, AES_INT_DATARDY); | |
1331 | return -EINPROGRESS; | |
1332 | } | |
1333 | } | |
1334 | ||
1335 | /* Read the computed hash from GHASHRx. */ | |
1336 | atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash_out); | |
1337 | ||
1338 | return ctx->ghash_resume(dd); | |
1339 | } | |
1340 | ||
1341 | ||
1342 | static int atmel_aes_gcm_start(struct atmel_aes_dev *dd) | |
1343 | { | |
1344 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1345 | struct aead_request *req = aead_request_cast(dd->areq); | |
1346 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | |
1347 | struct atmel_aes_reqctx *rctx = aead_request_ctx(req); | |
1348 | size_t ivsize = crypto_aead_ivsize(tfm); | |
1349 | size_t datalen, padlen; | |
1350 | const void *iv = req->iv; | |
1351 | u8 *data = dd->buf; | |
1352 | int err; | |
1353 | ||
1354 | atmel_aes_set_mode(dd, rctx); | |
1355 | ||
1356 | err = atmel_aes_hw_init(dd); | |
1357 | if (err) | |
1358 | return atmel_aes_complete(dd, err); | |
1359 | ||
1360 | if (likely(ivsize == 12)) { | |
1361 | memcpy(ctx->j0, iv, ivsize); | |
1362 | ctx->j0[3] = cpu_to_be32(1); | |
1363 | return atmel_aes_gcm_process(dd); | |
1364 | } | |
1365 | ||
1366 | padlen = atmel_aes_padlen(ivsize, AES_BLOCK_SIZE); | |
1367 | datalen = ivsize + padlen + AES_BLOCK_SIZE; | |
1368 | if (datalen > dd->buflen) | |
1369 | return atmel_aes_complete(dd, -EINVAL); | |
1370 | ||
1371 | memcpy(data, iv, ivsize); | |
1372 | memset(data + ivsize, 0, padlen + sizeof(u64)); | |
1373 | ((u64 *)(data + datalen))[-1] = cpu_to_be64(ivsize * 8); | |
1374 | ||
1375 | return atmel_aes_gcm_ghash(dd, (const u32 *)data, datalen, | |
1376 | NULL, ctx->j0, atmel_aes_gcm_process); | |
1377 | } | |
1378 | ||
1379 | static int atmel_aes_gcm_process(struct atmel_aes_dev *dd) | |
1380 | { | |
1381 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1382 | struct aead_request *req = aead_request_cast(dd->areq); | |
1383 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | |
1384 | bool enc = atmel_aes_is_encrypt(dd); | |
1385 | u32 authsize; | |
1386 | ||
1387 | /* Compute text length. */ | |
1388 | authsize = crypto_aead_authsize(tfm); | |
1389 | ctx->textlen = req->cryptlen - (enc ? 0 : authsize); | |
1390 | ||
1391 | /* | |
1392 | * According to tcrypt test suite, the GCM Automatic Tag Generation | |
1393 | * fails when both the message and its associated data are empty. | |
1394 | */ | |
1395 | if (likely(req->assoclen != 0 || ctx->textlen != 0)) | |
1396 | dd->flags |= AES_FLAGS_GTAGEN; | |
1397 | ||
1398 | atmel_aes_write_ctrl(dd, false, NULL); | |
1399 | return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_length); | |
1400 | } | |
1401 | ||
1402 | static int atmel_aes_gcm_length(struct atmel_aes_dev *dd) | |
1403 | { | |
1404 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1405 | struct aead_request *req = aead_request_cast(dd->areq); | |
1406 | u32 j0_lsw, *j0 = ctx->j0; | |
1407 | size_t padlen; | |
1408 | ||
1409 | /* Write incr32(J0) into IV. */ | |
1410 | j0_lsw = j0[3]; | |
1411 | j0[3] = cpu_to_be32(be32_to_cpu(j0[3]) + 1); | |
1412 | atmel_aes_write_block(dd, AES_IVR(0), j0); | |
1413 | j0[3] = j0_lsw; | |
1414 | ||
1415 | /* Set aad and text lengths. */ | |
1416 | atmel_aes_write(dd, AES_AADLENR, req->assoclen); | |
1417 | atmel_aes_write(dd, AES_CLENR, ctx->textlen); | |
1418 | ||
1419 | /* Check whether AAD are present. */ | |
1420 | if (unlikely(req->assoclen == 0)) { | |
1421 | dd->datalen = 0; | |
1422 | return atmel_aes_gcm_data(dd); | |
1423 | } | |
1424 | ||
1425 | /* Copy assoc data and add padding. */ | |
1426 | padlen = atmel_aes_padlen(req->assoclen, AES_BLOCK_SIZE); | |
1427 | if (unlikely(req->assoclen + padlen > dd->buflen)) | |
1428 | return atmel_aes_complete(dd, -EINVAL); | |
1429 | sg_copy_to_buffer(req->src, sg_nents(req->src), dd->buf, req->assoclen); | |
1430 | ||
1431 | /* Write assoc data into the Input Data register. */ | |
1432 | dd->data = (u32 *)dd->buf; | |
1433 | dd->datalen = req->assoclen + padlen; | |
1434 | return atmel_aes_gcm_data(dd); | |
1435 | } | |
1436 | ||
1437 | static int atmel_aes_gcm_data(struct atmel_aes_dev *dd) | |
1438 | { | |
1439 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1440 | struct aead_request *req = aead_request_cast(dd->areq); | |
1441 | bool use_dma = (ctx->textlen >= ATMEL_AES_DMA_THRESHOLD); | |
1442 | struct scatterlist *src, *dst; | |
1443 | u32 isr, mr; | |
1444 | ||
1445 | /* Write AAD first. */ | |
1446 | while (dd->datalen > 0) { | |
1447 | atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); | |
1448 | dd->data += 4; | |
1449 | dd->datalen -= AES_BLOCK_SIZE; | |
1450 | ||
1451 | isr = atmel_aes_read(dd, AES_ISR); | |
1452 | if (!(isr & AES_INT_DATARDY)) { | |
1453 | dd->resume = atmel_aes_gcm_data; | |
1454 | atmel_aes_write(dd, AES_IER, AES_INT_DATARDY); | |
1455 | return -EINPROGRESS; | |
1456 | } | |
1457 | } | |
1458 | ||
1459 | /* GMAC only. */ | |
1460 | if (unlikely(ctx->textlen == 0)) | |
1461 | return atmel_aes_gcm_tag_init(dd); | |
1462 | ||
1463 | /* Prepare src and dst scatter lists to transfer cipher/plain texts */ | |
1464 | src = scatterwalk_ffwd(ctx->src, req->src, req->assoclen); | |
1465 | dst = ((req->src == req->dst) ? src : | |
1466 | scatterwalk_ffwd(ctx->dst, req->dst, req->assoclen)); | |
1467 | ||
1468 | if (use_dma) { | |
1469 | /* Update the Mode Register for DMA transfers. */ | |
1470 | mr = atmel_aes_read(dd, AES_MR); | |
1471 | mr &= ~(AES_MR_SMOD_MASK | AES_MR_DUALBUFF); | |
1472 | mr |= AES_MR_SMOD_IDATAR0; | |
1473 | if (dd->caps.has_dualbuff) | |
1474 | mr |= AES_MR_DUALBUFF; | |
1475 | atmel_aes_write(dd, AES_MR, mr); | |
1476 | ||
1477 | return atmel_aes_dma_start(dd, src, dst, ctx->textlen, | |
1478 | atmel_aes_gcm_tag_init); | |
1479 | } | |
1480 | ||
1481 | return atmel_aes_cpu_start(dd, src, dst, ctx->textlen, | |
1482 | atmel_aes_gcm_tag_init); | |
1483 | } | |
1484 | ||
1485 | static int atmel_aes_gcm_tag_init(struct atmel_aes_dev *dd) | |
1486 | { | |
1487 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1488 | struct aead_request *req = aead_request_cast(dd->areq); | |
1489 | u64 *data = dd->buf; | |
1490 | ||
1491 | if (likely(dd->flags & AES_FLAGS_GTAGEN)) { | |
1492 | if (!(atmel_aes_read(dd, AES_ISR) & AES_INT_TAGRDY)) { | |
1493 | dd->resume = atmel_aes_gcm_tag_init; | |
1494 | atmel_aes_write(dd, AES_IER, AES_INT_TAGRDY); | |
1495 | return -EINPROGRESS; | |
1496 | } | |
1497 | ||
1498 | return atmel_aes_gcm_finalize(dd); | |
1499 | } | |
1500 | ||
1501 | /* Read the GCM Intermediate Hash Word Registers. */ | |
1502 | atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash); | |
1503 | ||
1504 | data[0] = cpu_to_be64(req->assoclen * 8); | |
1505 | data[1] = cpu_to_be64(ctx->textlen * 8); | |
1506 | ||
1507 | return atmel_aes_gcm_ghash(dd, (const u32 *)data, AES_BLOCK_SIZE, | |
1508 | ctx->ghash, ctx->ghash, atmel_aes_gcm_tag); | |
1509 | } | |
1510 | ||
1511 | static int atmel_aes_gcm_tag(struct atmel_aes_dev *dd) | |
1512 | { | |
1513 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1514 | unsigned long flags; | |
1515 | ||
1516 | /* | |
1517 | * Change mode to CTR to complete the tag generation. | |
1518 | * Use J0 as Initialization Vector. | |
1519 | */ | |
1520 | flags = dd->flags; | |
1521 | dd->flags &= ~(AES_FLAGS_OPMODE_MASK | AES_FLAGS_GTAGEN); | |
1522 | dd->flags |= AES_FLAGS_CTR; | |
1523 | atmel_aes_write_ctrl(dd, false, ctx->j0); | |
1524 | dd->flags = flags; | |
1525 | ||
1526 | atmel_aes_write_block(dd, AES_IDATAR(0), ctx->ghash); | |
1527 | return atmel_aes_wait_for_data_ready(dd, atmel_aes_gcm_finalize); | |
1528 | } | |
1529 | ||
1530 | static int atmel_aes_gcm_finalize(struct atmel_aes_dev *dd) | |
1531 | { | |
1532 | struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); | |
1533 | struct aead_request *req = aead_request_cast(dd->areq); | |
1534 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | |
1535 | bool enc = atmel_aes_is_encrypt(dd); | |
1536 | u32 offset, authsize, itag[4], *otag = ctx->tag; | |
1537 | int err; | |
1538 | ||
1539 | /* Read the computed tag. */ | |
1540 | if (likely(dd->flags & AES_FLAGS_GTAGEN)) | |
1541 | atmel_aes_read_block(dd, AES_TAGR(0), ctx->tag); | |
1542 | else | |
1543 | atmel_aes_read_block(dd, AES_ODATAR(0), ctx->tag); | |
1544 | ||
1545 | offset = req->assoclen + ctx->textlen; | |
1546 | authsize = crypto_aead_authsize(tfm); | |
1547 | if (enc) { | |
1548 | scatterwalk_map_and_copy(otag, req->dst, offset, authsize, 1); | |
1549 | err = 0; | |
1550 | } else { | |
1551 | scatterwalk_map_and_copy(itag, req->src, offset, authsize, 0); | |
1552 | err = crypto_memneq(itag, otag, authsize) ? -EBADMSG : 0; | |
1553 | } | |
1554 | ||
1555 | return atmel_aes_complete(dd, err); | |
1556 | } | |
1557 | ||
1558 | static int atmel_aes_gcm_crypt(struct aead_request *req, | |
1559 | unsigned long mode) | |
1560 | { | |
1561 | struct atmel_aes_base_ctx *ctx; | |
1562 | struct atmel_aes_reqctx *rctx; | |
1563 | struct atmel_aes_dev *dd; | |
1564 | ||
1565 | ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); | |
1566 | ctx->block_size = AES_BLOCK_SIZE; | |
1567 | ||
1568 | dd = atmel_aes_find_dev(ctx); | |
1569 | if (!dd) | |
1570 | return -ENODEV; | |
1571 | ||
1572 | rctx = aead_request_ctx(req); | |
1573 | rctx->mode = AES_FLAGS_GCM | mode; | |
1574 | ||
1575 | return atmel_aes_handle_queue(dd, &req->base); | |
1576 | } | |
1577 | ||
1578 | static int atmel_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key, | |
1579 | unsigned int keylen) | |
1580 | { | |
1581 | struct atmel_aes_base_ctx *ctx = crypto_aead_ctx(tfm); | |
1582 | ||
1583 | if (keylen != AES_KEYSIZE_256 && | |
1584 | keylen != AES_KEYSIZE_192 && | |
1585 | keylen != AES_KEYSIZE_128) { | |
1586 | crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
1587 | return -EINVAL; | |
1588 | } | |
1589 | ||
1590 | memcpy(ctx->key, key, keylen); | |
1591 | ctx->keylen = keylen; | |
1592 | ||
1593 | return 0; | |
1594 | } | |
1595 | ||
1596 | static int atmel_aes_gcm_setauthsize(struct crypto_aead *tfm, | |
1597 | unsigned int authsize) | |
1598 | { | |
1599 | /* Same as crypto_gcm_authsize() from crypto/gcm.c */ | |
1600 | switch (authsize) { | |
1601 | case 4: | |
1602 | case 8: | |
1603 | case 12: | |
1604 | case 13: | |
1605 | case 14: | |
1606 | case 15: | |
1607 | case 16: | |
1608 | break; | |
1609 | default: | |
1610 | return -EINVAL; | |
1611 | } | |
1612 | ||
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | static int atmel_aes_gcm_encrypt(struct aead_request *req) | |
1617 | { | |
1618 | return atmel_aes_gcm_crypt(req, AES_FLAGS_ENCRYPT); | |
1619 | } | |
1620 | ||
1621 | static int atmel_aes_gcm_decrypt(struct aead_request *req) | |
1622 | { | |
1623 | return atmel_aes_gcm_crypt(req, 0); | |
1624 | } | |
1625 | ||
1626 | static int atmel_aes_gcm_init(struct crypto_aead *tfm) | |
1627 | { | |
1628 | struct atmel_aes_gcm_ctx *ctx = crypto_aead_ctx(tfm); | |
1629 | ||
1630 | crypto_aead_set_reqsize(tfm, sizeof(struct atmel_aes_reqctx)); | |
1631 | ctx->base.start = atmel_aes_gcm_start; | |
1632 | ||
1633 | return 0; | |
1634 | } | |
1635 | ||
1636 | static void atmel_aes_gcm_exit(struct crypto_aead *tfm) | |
1637 | { | |
1638 | ||
1639 | } | |
1640 | ||
1641 | static struct aead_alg aes_gcm_alg = { | |
1642 | .setkey = atmel_aes_gcm_setkey, | |
1643 | .setauthsize = atmel_aes_gcm_setauthsize, | |
1644 | .encrypt = atmel_aes_gcm_encrypt, | |
1645 | .decrypt = atmel_aes_gcm_decrypt, | |
1646 | .init = atmel_aes_gcm_init, | |
1647 | .exit = atmel_aes_gcm_exit, | |
1648 | .ivsize = 12, | |
1649 | .maxauthsize = AES_BLOCK_SIZE, | |
1650 | ||
1651 | .base = { | |
1652 | .cra_name = "gcm(aes)", | |
1653 | .cra_driver_name = "atmel-gcm-aes", | |
1654 | .cra_priority = ATMEL_AES_PRIORITY, | |
1655 | .cra_flags = CRYPTO_ALG_ASYNC, | |
1656 | .cra_blocksize = 1, | |
1657 | .cra_ctxsize = sizeof(struct atmel_aes_gcm_ctx), | |
1658 | .cra_alignmask = 0xf, | |
1659 | .cra_module = THIS_MODULE, | |
1660 | }, | |
1661 | }; | |
1662 | ||
1663 | ||
e37a7e55 CP |
1664 | /* Probe functions */ |
1665 | ||
1666 | static int atmel_aes_buff_init(struct atmel_aes_dev *dd) | |
1667 | { | |
1668 | dd->buf = (void *)__get_free_pages(GFP_KERNEL, ATMEL_AES_BUFFER_ORDER); | |
1669 | dd->buflen = ATMEL_AES_BUFFER_SIZE; | |
1670 | dd->buflen &= ~(AES_BLOCK_SIZE - 1); | |
1671 | ||
1672 | if (!dd->buf) { | |
1673 | dev_err(dd->dev, "unable to alloc pages.\n"); | |
1674 | return -ENOMEM; | |
1675 | } | |
1676 | ||
1677 | return 0; | |
1678 | } | |
1679 | ||
1680 | static void atmel_aes_buff_cleanup(struct atmel_aes_dev *dd) | |
1681 | { | |
1682 | free_page((unsigned long)dd->buf); | |
1683 | } | |
1684 | ||
1685 | static bool atmel_aes_filter(struct dma_chan *chan, void *slave) | |
1686 | { | |
1687 | struct at_dma_slave *sl = slave; | |
1688 | ||
1689 | if (sl && sl->dma_dev == chan->device->dev) { | |
1690 | chan->private = sl; | |
1691 | return true; | |
1692 | } else { | |
1693 | return false; | |
1694 | } | |
1695 | } | |
1696 | ||
1697 | static int atmel_aes_dma_init(struct atmel_aes_dev *dd, | |
1698 | struct crypto_platform_data *pdata) | |
1699 | { | |
1700 | struct at_dma_slave *slave; | |
1701 | int err = -ENOMEM; | |
1702 | dma_cap_mask_t mask; | |
1703 | ||
1704 | dma_cap_zero(mask); | |
1705 | dma_cap_set(DMA_SLAVE, mask); | |
1706 | ||
1707 | /* Try to grab 2 DMA channels */ | |
1708 | slave = &pdata->dma_slave->rxdata; | |
1709 | dd->src.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter, | |
1710 | slave, dd->dev, "tx"); | |
1711 | if (!dd->src.chan) | |
1712 | goto err_dma_in; | |
1713 | ||
1714 | slave = &pdata->dma_slave->txdata; | |
1715 | dd->dst.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter, | |
1716 | slave, dd->dev, "rx"); | |
1717 | if (!dd->dst.chan) | |
1718 | goto err_dma_out; | |
1719 | ||
1720 | return 0; | |
1721 | ||
1722 | err_dma_out: | |
1723 | dma_release_channel(dd->src.chan); | |
1724 | err_dma_in: | |
1725 | dev_warn(dd->dev, "no DMA channel available\n"); | |
1726 | return err; | |
1727 | } | |
1728 | ||
1729 | static void atmel_aes_dma_cleanup(struct atmel_aes_dev *dd) | |
1730 | { | |
1731 | dma_release_channel(dd->dst.chan); | |
1732 | dma_release_channel(dd->src.chan); | |
1733 | } | |
1734 | ||
bd3c7b5c NR |
1735 | static void atmel_aes_queue_task(unsigned long data) |
1736 | { | |
1737 | struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data; | |
1738 | ||
1739 | atmel_aes_handle_queue(dd, NULL); | |
1740 | } | |
1741 | ||
1742 | static void atmel_aes_done_task(unsigned long data) | |
1743 | { | |
afbac17e | 1744 | struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data; |
bd3c7b5c | 1745 | |
10f12c1b CP |
1746 | dd->is_async = true; |
1747 | (void)dd->resume(dd); | |
1748 | } | |
bd3c7b5c | 1749 | |
bd3c7b5c NR |
1750 | static irqreturn_t atmel_aes_irq(int irq, void *dev_id) |
1751 | { | |
1752 | struct atmel_aes_dev *aes_dd = dev_id; | |
1753 | u32 reg; | |
1754 | ||
1755 | reg = atmel_aes_read(aes_dd, AES_ISR); | |
1756 | if (reg & atmel_aes_read(aes_dd, AES_IMR)) { | |
1757 | atmel_aes_write(aes_dd, AES_IDR, reg); | |
1758 | if (AES_FLAGS_BUSY & aes_dd->flags) | |
1759 | tasklet_schedule(&aes_dd->done_task); | |
1760 | else | |
1761 | dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n"); | |
1762 | return IRQ_HANDLED; | |
1763 | } | |
1764 | ||
1765 | return IRQ_NONE; | |
1766 | } | |
1767 | ||
1768 | static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd) | |
1769 | { | |
1770 | int i; | |
1771 | ||
d4419548 CP |
1772 | if (dd->caps.has_gcm) |
1773 | crypto_unregister_aead(&aes_gcm_alg); | |
1774 | ||
cadc4ab8 NR |
1775 | if (dd->caps.has_cfb64) |
1776 | crypto_unregister_alg(&aes_cfb64_alg); | |
924a8bc7 CP |
1777 | |
1778 | for (i = 0; i < ARRAY_SIZE(aes_algs); i++) | |
1779 | crypto_unregister_alg(&aes_algs[i]); | |
bd3c7b5c NR |
1780 | } |
1781 | ||
1782 | static int atmel_aes_register_algs(struct atmel_aes_dev *dd) | |
1783 | { | |
1784 | int err, i, j; | |
1785 | ||
1786 | for (i = 0; i < ARRAY_SIZE(aes_algs); i++) { | |
bd3c7b5c NR |
1787 | err = crypto_register_alg(&aes_algs[i]); |
1788 | if (err) | |
1789 | goto err_aes_algs; | |
1790 | } | |
1791 | ||
cadc4ab8 NR |
1792 | if (dd->caps.has_cfb64) { |
1793 | err = crypto_register_alg(&aes_cfb64_alg); | |
bd3c7b5c NR |
1794 | if (err) |
1795 | goto err_aes_cfb64_alg; | |
1796 | } | |
1797 | ||
d4419548 CP |
1798 | if (dd->caps.has_gcm) { |
1799 | err = crypto_register_aead(&aes_gcm_alg); | |
1800 | if (err) | |
1801 | goto err_aes_gcm_alg; | |
1802 | } | |
1803 | ||
bd3c7b5c NR |
1804 | return 0; |
1805 | ||
d4419548 CP |
1806 | err_aes_gcm_alg: |
1807 | crypto_unregister_alg(&aes_cfb64_alg); | |
bd3c7b5c NR |
1808 | err_aes_cfb64_alg: |
1809 | i = ARRAY_SIZE(aes_algs); | |
1810 | err_aes_algs: | |
1811 | for (j = 0; j < i; j++) | |
1812 | crypto_unregister_alg(&aes_algs[j]); | |
1813 | ||
1814 | return err; | |
1815 | } | |
1816 | ||
cadc4ab8 NR |
1817 | static void atmel_aes_get_cap(struct atmel_aes_dev *dd) |
1818 | { | |
1819 | dd->caps.has_dualbuff = 0; | |
1820 | dd->caps.has_cfb64 = 0; | |
fcac8365 | 1821 | dd->caps.has_ctr32 = 0; |
d4419548 | 1822 | dd->caps.has_gcm = 0; |
cadc4ab8 NR |
1823 | dd->caps.max_burst_size = 1; |
1824 | ||
1825 | /* keep only major version number */ | |
1826 | switch (dd->hw_version & 0xff0) { | |
973e209d LZ |
1827 | case 0x500: |
1828 | dd->caps.has_dualbuff = 1; | |
1829 | dd->caps.has_cfb64 = 1; | |
fcac8365 | 1830 | dd->caps.has_ctr32 = 1; |
d4419548 | 1831 | dd->caps.has_gcm = 1; |
973e209d LZ |
1832 | dd->caps.max_burst_size = 4; |
1833 | break; | |
cf1f0d12 LZ |
1834 | case 0x200: |
1835 | dd->caps.has_dualbuff = 1; | |
1836 | dd->caps.has_cfb64 = 1; | |
fcac8365 | 1837 | dd->caps.has_ctr32 = 1; |
d4419548 | 1838 | dd->caps.has_gcm = 1; |
cf1f0d12 LZ |
1839 | dd->caps.max_burst_size = 4; |
1840 | break; | |
cadc4ab8 NR |
1841 | case 0x130: |
1842 | dd->caps.has_dualbuff = 1; | |
1843 | dd->caps.has_cfb64 = 1; | |
1844 | dd->caps.max_burst_size = 4; | |
1845 | break; | |
1846 | case 0x120: | |
1847 | break; | |
1848 | default: | |
1849 | dev_warn(dd->dev, | |
1850 | "Unmanaged aes version, set minimum capabilities\n"); | |
1851 | break; | |
1852 | } | |
1853 | } | |
1854 | ||
be943c7d NF |
1855 | #if defined(CONFIG_OF) |
1856 | static const struct of_device_id atmel_aes_dt_ids[] = { | |
1857 | { .compatible = "atmel,at91sam9g46-aes" }, | |
1858 | { /* sentinel */ } | |
1859 | }; | |
1860 | MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids); | |
1861 | ||
1862 | static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev) | |
1863 | { | |
1864 | struct device_node *np = pdev->dev.of_node; | |
1865 | struct crypto_platform_data *pdata; | |
1866 | ||
1867 | if (!np) { | |
1868 | dev_err(&pdev->dev, "device node not found\n"); | |
1869 | return ERR_PTR(-EINVAL); | |
1870 | } | |
1871 | ||
1872 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1873 | if (!pdata) { | |
1874 | dev_err(&pdev->dev, "could not allocate memory for pdata\n"); | |
1875 | return ERR_PTR(-ENOMEM); | |
1876 | } | |
1877 | ||
1878 | pdata->dma_slave = devm_kzalloc(&pdev->dev, | |
1879 | sizeof(*(pdata->dma_slave)), | |
1880 | GFP_KERNEL); | |
1881 | if (!pdata->dma_slave) { | |
1882 | dev_err(&pdev->dev, "could not allocate memory for dma_slave\n"); | |
1883 | devm_kfree(&pdev->dev, pdata); | |
1884 | return ERR_PTR(-ENOMEM); | |
1885 | } | |
1886 | ||
1887 | return pdata; | |
1888 | } | |
1889 | #else | |
1890 | static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev) | |
1891 | { | |
1892 | return ERR_PTR(-EINVAL); | |
1893 | } | |
1894 | #endif | |
1895 | ||
49cfe4db | 1896 | static int atmel_aes_probe(struct platform_device *pdev) |
bd3c7b5c NR |
1897 | { |
1898 | struct atmel_aes_dev *aes_dd; | |
cadc4ab8 | 1899 | struct crypto_platform_data *pdata; |
bd3c7b5c NR |
1900 | struct device *dev = &pdev->dev; |
1901 | struct resource *aes_res; | |
bd3c7b5c NR |
1902 | int err; |
1903 | ||
1904 | pdata = pdev->dev.platform_data; | |
1905 | if (!pdata) { | |
be943c7d NF |
1906 | pdata = atmel_aes_of_init(pdev); |
1907 | if (IS_ERR(pdata)) { | |
1908 | err = PTR_ERR(pdata); | |
1909 | goto aes_dd_err; | |
1910 | } | |
1911 | } | |
1912 | ||
1913 | if (!pdata->dma_slave) { | |
bd3c7b5c NR |
1914 | err = -ENXIO; |
1915 | goto aes_dd_err; | |
1916 | } | |
1917 | ||
b0e8b341 | 1918 | aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL); |
bd3c7b5c NR |
1919 | if (aes_dd == NULL) { |
1920 | dev_err(dev, "unable to alloc data struct.\n"); | |
1921 | err = -ENOMEM; | |
1922 | goto aes_dd_err; | |
1923 | } | |
1924 | ||
1925 | aes_dd->dev = dev; | |
1926 | ||
1927 | platform_set_drvdata(pdev, aes_dd); | |
1928 | ||
1929 | INIT_LIST_HEAD(&aes_dd->list); | |
8a10eb8d | 1930 | spin_lock_init(&aes_dd->lock); |
bd3c7b5c NR |
1931 | |
1932 | tasklet_init(&aes_dd->done_task, atmel_aes_done_task, | |
1933 | (unsigned long)aes_dd); | |
1934 | tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task, | |
1935 | (unsigned long)aes_dd); | |
1936 | ||
1937 | crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH); | |
1938 | ||
1939 | aes_dd->irq = -1; | |
1940 | ||
1941 | /* Get the base address */ | |
1942 | aes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1943 | if (!aes_res) { | |
1944 | dev_err(dev, "no MEM resource info\n"); | |
1945 | err = -ENODEV; | |
1946 | goto res_err; | |
1947 | } | |
1948 | aes_dd->phys_base = aes_res->start; | |
bd3c7b5c NR |
1949 | |
1950 | /* Get the IRQ */ | |
1951 | aes_dd->irq = platform_get_irq(pdev, 0); | |
1952 | if (aes_dd->irq < 0) { | |
1953 | dev_err(dev, "no IRQ resource info\n"); | |
1954 | err = aes_dd->irq; | |
b0e8b341 | 1955 | goto res_err; |
bd3c7b5c NR |
1956 | } |
1957 | ||
b0e8b341 LC |
1958 | err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq, |
1959 | IRQF_SHARED, "atmel-aes", aes_dd); | |
bd3c7b5c NR |
1960 | if (err) { |
1961 | dev_err(dev, "unable to request aes irq.\n"); | |
b0e8b341 | 1962 | goto res_err; |
bd3c7b5c NR |
1963 | } |
1964 | ||
1965 | /* Initializing the clock */ | |
b0e8b341 | 1966 | aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk"); |
bd3c7b5c | 1967 | if (IS_ERR(aes_dd->iclk)) { |
be208356 | 1968 | dev_err(dev, "clock initialization failed.\n"); |
bd3c7b5c | 1969 | err = PTR_ERR(aes_dd->iclk); |
b0e8b341 | 1970 | goto res_err; |
bd3c7b5c NR |
1971 | } |
1972 | ||
b0e8b341 | 1973 | aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res); |
bd3c7b5c NR |
1974 | if (!aes_dd->io_base) { |
1975 | dev_err(dev, "can't ioremap\n"); | |
1976 | err = -ENOMEM; | |
b0e8b341 | 1977 | goto res_err; |
bd3c7b5c NR |
1978 | } |
1979 | ||
aab0a39b CP |
1980 | err = atmel_aes_hw_version_init(aes_dd); |
1981 | if (err) | |
1982 | goto res_err; | |
cadc4ab8 NR |
1983 | |
1984 | atmel_aes_get_cap(aes_dd); | |
1985 | ||
1986 | err = atmel_aes_buff_init(aes_dd); | |
1987 | if (err) | |
1988 | goto err_aes_buff; | |
1989 | ||
1990 | err = atmel_aes_dma_init(aes_dd, pdata); | |
bd3c7b5c NR |
1991 | if (err) |
1992 | goto err_aes_dma; | |
1993 | ||
1994 | spin_lock(&atmel_aes.lock); | |
1995 | list_add_tail(&aes_dd->list, &atmel_aes.dev_list); | |
1996 | spin_unlock(&atmel_aes.lock); | |
1997 | ||
1998 | err = atmel_aes_register_algs(aes_dd); | |
1999 | if (err) | |
2000 | goto err_algs; | |
2001 | ||
be943c7d | 2002 | dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n", |
bbe628ed CP |
2003 | dma_chan_name(aes_dd->src.chan), |
2004 | dma_chan_name(aes_dd->dst.chan)); | |
bd3c7b5c NR |
2005 | |
2006 | return 0; | |
2007 | ||
2008 | err_algs: | |
2009 | spin_lock(&atmel_aes.lock); | |
2010 | list_del(&aes_dd->list); | |
2011 | spin_unlock(&atmel_aes.lock); | |
2012 | atmel_aes_dma_cleanup(aes_dd); | |
2013 | err_aes_dma: | |
cadc4ab8 NR |
2014 | atmel_aes_buff_cleanup(aes_dd); |
2015 | err_aes_buff: | |
bd3c7b5c NR |
2016 | res_err: |
2017 | tasklet_kill(&aes_dd->done_task); | |
2018 | tasklet_kill(&aes_dd->queue_task); | |
bd3c7b5c NR |
2019 | aes_dd_err: |
2020 | dev_err(dev, "initialization failed.\n"); | |
2021 | ||
2022 | return err; | |
2023 | } | |
2024 | ||
49cfe4db | 2025 | static int atmel_aes_remove(struct platform_device *pdev) |
bd3c7b5c NR |
2026 | { |
2027 | static struct atmel_aes_dev *aes_dd; | |
2028 | ||
2029 | aes_dd = platform_get_drvdata(pdev); | |
2030 | if (!aes_dd) | |
2031 | return -ENODEV; | |
2032 | spin_lock(&atmel_aes.lock); | |
2033 | list_del(&aes_dd->list); | |
2034 | spin_unlock(&atmel_aes.lock); | |
2035 | ||
2036 | atmel_aes_unregister_algs(aes_dd); | |
2037 | ||
2038 | tasklet_kill(&aes_dd->done_task); | |
2039 | tasklet_kill(&aes_dd->queue_task); | |
2040 | ||
2041 | atmel_aes_dma_cleanup(aes_dd); | |
2a377828 | 2042 | atmel_aes_buff_cleanup(aes_dd); |
bd3c7b5c | 2043 | |
bd3c7b5c NR |
2044 | return 0; |
2045 | } | |
2046 | ||
2047 | static struct platform_driver atmel_aes_driver = { | |
2048 | .probe = atmel_aes_probe, | |
49cfe4db | 2049 | .remove = atmel_aes_remove, |
bd3c7b5c NR |
2050 | .driver = { |
2051 | .name = "atmel_aes", | |
be943c7d | 2052 | .of_match_table = of_match_ptr(atmel_aes_dt_ids), |
bd3c7b5c NR |
2053 | }, |
2054 | }; | |
2055 | ||
2056 | module_platform_driver(atmel_aes_driver); | |
2057 | ||
2058 | MODULE_DESCRIPTION("Atmel AES hw acceleration support."); | |
2059 | MODULE_LICENSE("GPL v2"); | |
2060 | MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique"); |