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Commit | Line | Data |
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ebc82efa NR |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for ATMEL SHA1/SHA256 HW acceleration. | |
5 | * | |
6 | * Copyright (c) 2012 Eukréa Electromatique - ATMEL | |
7 | * Author: Nicolas Royer <nicolas@eukrea.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as published | |
11 | * by the Free Software Foundation. | |
12 | * | |
13 | * Some ideas are from omap-sham.c drivers. | |
14 | */ | |
15 | ||
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/hw_random.h> | |
24 | #include <linux/platform_device.h> | |
25 | ||
26 | #include <linux/device.h> | |
ebc82efa NR |
27 | #include <linux/init.h> |
28 | #include <linux/errno.h> | |
29 | #include <linux/interrupt.h> | |
ebc82efa | 30 | #include <linux/irq.h> |
ebc82efa NR |
31 | #include <linux/scatterlist.h> |
32 | #include <linux/dma-mapping.h> | |
abfe7ae4 | 33 | #include <linux/of_device.h> |
ebc82efa NR |
34 | #include <linux/delay.h> |
35 | #include <linux/crypto.h> | |
36 | #include <linux/cryptohash.h> | |
37 | #include <crypto/scatterwalk.h> | |
38 | #include <crypto/algapi.h> | |
39 | #include <crypto/sha.h> | |
40 | #include <crypto/hash.h> | |
41 | #include <crypto/internal/hash.h> | |
d4905b38 | 42 | #include <linux/platform_data/crypto-atmel.h> |
ebc82efa NR |
43 | #include "atmel-sha-regs.h" |
44 | ||
45 | /* SHA flags */ | |
46 | #define SHA_FLAGS_BUSY BIT(0) | |
47 | #define SHA_FLAGS_FINAL BIT(1) | |
48 | #define SHA_FLAGS_DMA_ACTIVE BIT(2) | |
49 | #define SHA_FLAGS_OUTPUT_READY BIT(3) | |
50 | #define SHA_FLAGS_INIT BIT(4) | |
51 | #define SHA_FLAGS_CPU BIT(5) | |
52 | #define SHA_FLAGS_DMA_READY BIT(6) | |
53 | ||
f07cebad CP |
54 | /* bits[10:8] are reserved. */ |
55 | #define SHA_FLAGS_ALGO_MASK SHA_MR_ALGO_MASK | |
56 | #define SHA_FLAGS_SHA1 SHA_MR_ALGO_SHA1 | |
57 | #define SHA_FLAGS_SHA256 SHA_MR_ALGO_SHA256 | |
58 | #define SHA_FLAGS_SHA384 SHA_MR_ALGO_SHA384 | |
59 | #define SHA_FLAGS_SHA512 SHA_MR_ALGO_SHA512 | |
60 | #define SHA_FLAGS_SHA224 SHA_MR_ALGO_SHA224 | |
61 | ||
ebc82efa NR |
62 | #define SHA_FLAGS_FINUP BIT(16) |
63 | #define SHA_FLAGS_SG BIT(17) | |
d4905b38 NR |
64 | #define SHA_FLAGS_ERROR BIT(23) |
65 | #define SHA_FLAGS_PAD BIT(24) | |
7cee3508 | 66 | #define SHA_FLAGS_RESTORE BIT(25) |
ebc82efa NR |
67 | |
68 | #define SHA_OP_UPDATE 1 | |
69 | #define SHA_OP_FINAL 2 | |
70 | ||
cc831d32 | 71 | #define SHA_BUFFER_LEN (PAGE_SIZE / 16) |
ebc82efa NR |
72 | |
73 | #define ATMEL_SHA_DMA_THRESHOLD 56 | |
74 | ||
d4905b38 NR |
75 | struct atmel_sha_caps { |
76 | bool has_dma; | |
77 | bool has_dualbuff; | |
78 | bool has_sha224; | |
79 | bool has_sha_384_512; | |
7cee3508 | 80 | bool has_uihv; |
d4905b38 | 81 | }; |
ebc82efa NR |
82 | |
83 | struct atmel_sha_dev; | |
84 | ||
cc831d32 | 85 | /* |
9c4274d9 | 86 | * .statesize = sizeof(struct atmel_sha_reqctx) must be <= PAGE_SIZE / 8 as |
cc831d32 CP |
87 | * tested by the ahash_prepare_alg() function. |
88 | */ | |
ebc82efa NR |
89 | struct atmel_sha_reqctx { |
90 | struct atmel_sha_dev *dd; | |
91 | unsigned long flags; | |
92 | unsigned long op; | |
93 | ||
d4905b38 NR |
94 | u8 digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32)); |
95 | u64 digcnt[2]; | |
ebc82efa NR |
96 | size_t bufcnt; |
97 | size_t buflen; | |
98 | dma_addr_t dma_addr; | |
99 | ||
100 | /* walk state */ | |
101 | struct scatterlist *sg; | |
102 | unsigned int offset; /* offset in current sg */ | |
103 | unsigned int total; /* total request */ | |
104 | ||
d4905b38 NR |
105 | size_t block_size; |
106 | ||
9c4274d9 | 107 | u8 buffer[SHA_BUFFER_LEN + SHA512_BLOCK_SIZE] __aligned(sizeof(u32)); |
ebc82efa NR |
108 | }; |
109 | ||
a29af939 CP |
110 | typedef int (*atmel_sha_fn_t)(struct atmel_sha_dev *); |
111 | ||
ebc82efa NR |
112 | struct atmel_sha_ctx { |
113 | struct atmel_sha_dev *dd; | |
a29af939 | 114 | atmel_sha_fn_t start; |
ebc82efa NR |
115 | |
116 | unsigned long flags; | |
ebc82efa NR |
117 | }; |
118 | ||
d4905b38 NR |
119 | #define ATMEL_SHA_QUEUE_LENGTH 50 |
120 | ||
121 | struct atmel_sha_dma { | |
122 | struct dma_chan *chan; | |
123 | struct dma_slave_config dma_conf; | |
124 | }; | |
ebc82efa NR |
125 | |
126 | struct atmel_sha_dev { | |
127 | struct list_head list; | |
128 | unsigned long phys_base; | |
129 | struct device *dev; | |
130 | struct clk *iclk; | |
131 | int irq; | |
132 | void __iomem *io_base; | |
133 | ||
134 | spinlock_t lock; | |
135 | int err; | |
136 | struct tasklet_struct done_task; | |
f56809c3 | 137 | struct tasklet_struct queue_task; |
ebc82efa NR |
138 | |
139 | unsigned long flags; | |
140 | struct crypto_queue queue; | |
141 | struct ahash_request *req; | |
a29af939 | 142 | bool is_async; |
b5ce82a7 | 143 | atmel_sha_fn_t resume; |
d4905b38 NR |
144 | |
145 | struct atmel_sha_dma dma_lch_in; | |
146 | ||
147 | struct atmel_sha_caps caps; | |
148 | ||
149 | u32 hw_version; | |
ebc82efa NR |
150 | }; |
151 | ||
152 | struct atmel_sha_drv { | |
153 | struct list_head dev_list; | |
154 | spinlock_t lock; | |
155 | }; | |
156 | ||
157 | static struct atmel_sha_drv atmel_sha = { | |
158 | .dev_list = LIST_HEAD_INIT(atmel_sha.dev_list), | |
159 | .lock = __SPIN_LOCK_UNLOCKED(atmel_sha.lock), | |
160 | }; | |
161 | ||
162 | static inline u32 atmel_sha_read(struct atmel_sha_dev *dd, u32 offset) | |
163 | { | |
164 | return readl_relaxed(dd->io_base + offset); | |
165 | } | |
166 | ||
167 | static inline void atmel_sha_write(struct atmel_sha_dev *dd, | |
168 | u32 offset, u32 value) | |
169 | { | |
170 | writel_relaxed(value, dd->io_base + offset); | |
171 | } | |
172 | ||
a29af939 CP |
173 | static inline int atmel_sha_complete(struct atmel_sha_dev *dd, int err) |
174 | { | |
175 | struct ahash_request *req = dd->req; | |
176 | ||
177 | dd->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL | SHA_FLAGS_CPU | | |
178 | SHA_FLAGS_DMA_READY | SHA_FLAGS_OUTPUT_READY); | |
179 | ||
180 | clk_disable(dd->iclk); | |
181 | ||
182 | if (dd->is_async && req->base.complete) | |
183 | req->base.complete(&req->base, err); | |
184 | ||
185 | /* handle new request */ | |
186 | tasklet_schedule(&dd->queue_task); | |
187 | ||
188 | return err; | |
189 | } | |
190 | ||
ebc82efa NR |
191 | static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx) |
192 | { | |
193 | size_t count; | |
194 | ||
195 | while ((ctx->bufcnt < ctx->buflen) && ctx->total) { | |
196 | count = min(ctx->sg->length - ctx->offset, ctx->total); | |
197 | count = min(count, ctx->buflen - ctx->bufcnt); | |
198 | ||
803eeae8 LZ |
199 | if (count <= 0) { |
200 | /* | |
201 | * Check if count <= 0 because the buffer is full or | |
202 | * because the sg length is 0. In the latest case, | |
203 | * check if there is another sg in the list, a 0 length | |
204 | * sg doesn't necessarily mean the end of the sg list. | |
205 | */ | |
206 | if ((ctx->sg->length == 0) && !sg_is_last(ctx->sg)) { | |
207 | ctx->sg = sg_next(ctx->sg); | |
208 | continue; | |
209 | } else { | |
210 | break; | |
211 | } | |
212 | } | |
ebc82efa NR |
213 | |
214 | scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, ctx->sg, | |
215 | ctx->offset, count, 0); | |
216 | ||
217 | ctx->bufcnt += count; | |
218 | ctx->offset += count; | |
219 | ctx->total -= count; | |
220 | ||
221 | if (ctx->offset == ctx->sg->length) { | |
222 | ctx->sg = sg_next(ctx->sg); | |
223 | if (ctx->sg) | |
224 | ctx->offset = 0; | |
225 | else | |
226 | ctx->total = 0; | |
227 | } | |
228 | } | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
233 | /* | |
d4905b38 NR |
234 | * The purpose of this padding is to ensure that the padded message is a |
235 | * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512). | |
236 | * The bit "1" is appended at the end of the message followed by | |
237 | * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or | |
238 | * 128 bits block (SHA384/SHA512) equals to the message length in bits | |
239 | * is appended. | |
ebc82efa | 240 | * |
d4905b38 | 241 | * For SHA1/SHA224/SHA256, padlen is calculated as followed: |
ebc82efa NR |
242 | * - if message length < 56 bytes then padlen = 56 - message length |
243 | * - else padlen = 64 + 56 - message length | |
d4905b38 NR |
244 | * |
245 | * For SHA384/SHA512, padlen is calculated as followed: | |
246 | * - if message length < 112 bytes then padlen = 112 - message length | |
247 | * - else padlen = 128 + 112 - message length | |
ebc82efa NR |
248 | */ |
249 | static void atmel_sha_fill_padding(struct atmel_sha_reqctx *ctx, int length) | |
250 | { | |
251 | unsigned int index, padlen; | |
d4905b38 NR |
252 | u64 bits[2]; |
253 | u64 size[2]; | |
254 | ||
255 | size[0] = ctx->digcnt[0]; | |
256 | size[1] = ctx->digcnt[1]; | |
257 | ||
258 | size[0] += ctx->bufcnt; | |
259 | if (size[0] < ctx->bufcnt) | |
260 | size[1]++; | |
261 | ||
262 | size[0] += length; | |
263 | if (size[0] < length) | |
264 | size[1]++; | |
265 | ||
266 | bits[1] = cpu_to_be64(size[0] << 3); | |
267 | bits[0] = cpu_to_be64(size[1] << 3 | size[0] >> 61); | |
268 | ||
f07cebad CP |
269 | switch (ctx->flags & SHA_FLAGS_ALGO_MASK) { |
270 | case SHA_FLAGS_SHA384: | |
271 | case SHA_FLAGS_SHA512: | |
d4905b38 NR |
272 | index = ctx->bufcnt & 0x7f; |
273 | padlen = (index < 112) ? (112 - index) : ((128+112) - index); | |
274 | *(ctx->buffer + ctx->bufcnt) = 0x80; | |
275 | memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1); | |
276 | memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16); | |
277 | ctx->bufcnt += padlen + 16; | |
278 | ctx->flags |= SHA_FLAGS_PAD; | |
f07cebad CP |
279 | break; |
280 | ||
281 | default: | |
d4905b38 NR |
282 | index = ctx->bufcnt & 0x3f; |
283 | padlen = (index < 56) ? (56 - index) : ((64+56) - index); | |
284 | *(ctx->buffer + ctx->bufcnt) = 0x80; | |
285 | memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1); | |
286 | memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8); | |
287 | ctx->bufcnt += padlen + 8; | |
288 | ctx->flags |= SHA_FLAGS_PAD; | |
f07cebad | 289 | break; |
d4905b38 | 290 | } |
ebc82efa NR |
291 | } |
292 | ||
8340c7fd | 293 | static struct atmel_sha_dev *atmel_sha_find_dev(struct atmel_sha_ctx *tctx) |
ebc82efa | 294 | { |
ebc82efa NR |
295 | struct atmel_sha_dev *dd = NULL; |
296 | struct atmel_sha_dev *tmp; | |
297 | ||
298 | spin_lock_bh(&atmel_sha.lock); | |
299 | if (!tctx->dd) { | |
300 | list_for_each_entry(tmp, &atmel_sha.dev_list, list) { | |
301 | dd = tmp; | |
302 | break; | |
303 | } | |
304 | tctx->dd = dd; | |
305 | } else { | |
306 | dd = tctx->dd; | |
307 | } | |
308 | ||
309 | spin_unlock_bh(&atmel_sha.lock); | |
310 | ||
8340c7fd CP |
311 | return dd; |
312 | } | |
313 | ||
314 | static int atmel_sha_init(struct ahash_request *req) | |
315 | { | |
316 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
317 | struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm); | |
318 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
319 | struct atmel_sha_dev *dd = atmel_sha_find_dev(tctx); | |
320 | ||
ebc82efa NR |
321 | ctx->dd = dd; |
322 | ||
323 | ctx->flags = 0; | |
324 | ||
325 | dev_dbg(dd->dev, "init: digest size: %d\n", | |
326 | crypto_ahash_digestsize(tfm)); | |
327 | ||
d4905b38 NR |
328 | switch (crypto_ahash_digestsize(tfm)) { |
329 | case SHA1_DIGEST_SIZE: | |
ebc82efa | 330 | ctx->flags |= SHA_FLAGS_SHA1; |
d4905b38 NR |
331 | ctx->block_size = SHA1_BLOCK_SIZE; |
332 | break; | |
333 | case SHA224_DIGEST_SIZE: | |
334 | ctx->flags |= SHA_FLAGS_SHA224; | |
335 | ctx->block_size = SHA224_BLOCK_SIZE; | |
336 | break; | |
337 | case SHA256_DIGEST_SIZE: | |
ebc82efa | 338 | ctx->flags |= SHA_FLAGS_SHA256; |
d4905b38 NR |
339 | ctx->block_size = SHA256_BLOCK_SIZE; |
340 | break; | |
341 | case SHA384_DIGEST_SIZE: | |
342 | ctx->flags |= SHA_FLAGS_SHA384; | |
343 | ctx->block_size = SHA384_BLOCK_SIZE; | |
344 | break; | |
345 | case SHA512_DIGEST_SIZE: | |
346 | ctx->flags |= SHA_FLAGS_SHA512; | |
347 | ctx->block_size = SHA512_BLOCK_SIZE; | |
348 | break; | |
349 | default: | |
350 | return -EINVAL; | |
351 | break; | |
352 | } | |
ebc82efa NR |
353 | |
354 | ctx->bufcnt = 0; | |
d4905b38 NR |
355 | ctx->digcnt[0] = 0; |
356 | ctx->digcnt[1] = 0; | |
ebc82efa NR |
357 | ctx->buflen = SHA_BUFFER_LEN; |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma) | |
363 | { | |
364 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
7cee3508 CP |
365 | u32 valmr = SHA_MR_MODE_AUTO; |
366 | unsigned int i, hashsize = 0; | |
ebc82efa NR |
367 | |
368 | if (likely(dma)) { | |
d4905b38 NR |
369 | if (!dd->caps.has_dma) |
370 | atmel_sha_write(dd, SHA_IER, SHA_INT_TXBUFE); | |
ebc82efa | 371 | valmr = SHA_MR_MODE_PDC; |
d4905b38 NR |
372 | if (dd->caps.has_dualbuff) |
373 | valmr |= SHA_MR_DUALBUFF; | |
ebc82efa NR |
374 | } else { |
375 | atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY); | |
376 | } | |
377 | ||
7cee3508 CP |
378 | switch (ctx->flags & SHA_FLAGS_ALGO_MASK) { |
379 | case SHA_FLAGS_SHA1: | |
d4905b38 | 380 | valmr |= SHA_MR_ALGO_SHA1; |
7cee3508 CP |
381 | hashsize = SHA1_DIGEST_SIZE; |
382 | break; | |
383 | ||
384 | case SHA_FLAGS_SHA224: | |
d4905b38 | 385 | valmr |= SHA_MR_ALGO_SHA224; |
7cee3508 CP |
386 | hashsize = SHA256_DIGEST_SIZE; |
387 | break; | |
388 | ||
389 | case SHA_FLAGS_SHA256: | |
ebc82efa | 390 | valmr |= SHA_MR_ALGO_SHA256; |
7cee3508 CP |
391 | hashsize = SHA256_DIGEST_SIZE; |
392 | break; | |
393 | ||
394 | case SHA_FLAGS_SHA384: | |
d4905b38 | 395 | valmr |= SHA_MR_ALGO_SHA384; |
7cee3508 CP |
396 | hashsize = SHA512_DIGEST_SIZE; |
397 | break; | |
398 | ||
399 | case SHA_FLAGS_SHA512: | |
d4905b38 | 400 | valmr |= SHA_MR_ALGO_SHA512; |
7cee3508 CP |
401 | hashsize = SHA512_DIGEST_SIZE; |
402 | break; | |
403 | ||
404 | default: | |
405 | break; | |
406 | } | |
ebc82efa NR |
407 | |
408 | /* Setting CR_FIRST only for the first iteration */ | |
7cee3508 CP |
409 | if (!(ctx->digcnt[0] || ctx->digcnt[1])) { |
410 | atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST); | |
411 | } else if (dd->caps.has_uihv && (ctx->flags & SHA_FLAGS_RESTORE)) { | |
412 | const u32 *hash = (const u32 *)ctx->digest; | |
413 | ||
414 | /* | |
415 | * Restore the hardware context: update the User Initialize | |
416 | * Hash Value (UIHV) with the value saved when the latest | |
417 | * 'update' operation completed on this very same crypto | |
418 | * request. | |
419 | */ | |
420 | ctx->flags &= ~SHA_FLAGS_RESTORE; | |
421 | atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV); | |
422 | for (i = 0; i < hashsize / sizeof(u32); ++i) | |
423 | atmel_sha_write(dd, SHA_REG_DIN(i), hash[i]); | |
424 | atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST); | |
425 | valmr |= SHA_MR_UIHV; | |
426 | } | |
427 | /* | |
428 | * WARNING: If the UIHV feature is not available, the hardware CANNOT | |
429 | * process concurrent requests: the internal registers used to store | |
430 | * the hash/digest are still set to the partial digest output values | |
431 | * computed during the latest round. | |
432 | */ | |
ebc82efa | 433 | |
ebc82efa NR |
434 | atmel_sha_write(dd, SHA_MR, valmr); |
435 | } | |
436 | ||
437 | static int atmel_sha_xmit_cpu(struct atmel_sha_dev *dd, const u8 *buf, | |
438 | size_t length, int final) | |
439 | { | |
440 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
441 | int count, len32; | |
442 | const u32 *buffer = (const u32 *)buf; | |
443 | ||
d4905b38 NR |
444 | dev_dbg(dd->dev, "xmit_cpu: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n", |
445 | ctx->digcnt[1], ctx->digcnt[0], length, final); | |
ebc82efa NR |
446 | |
447 | atmel_sha_write_ctrl(dd, 0); | |
448 | ||
449 | /* should be non-zero before next lines to disable clocks later */ | |
d4905b38 NR |
450 | ctx->digcnt[0] += length; |
451 | if (ctx->digcnt[0] < length) | |
452 | ctx->digcnt[1]++; | |
ebc82efa NR |
453 | |
454 | if (final) | |
455 | dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ | |
456 | ||
457 | len32 = DIV_ROUND_UP(length, sizeof(u32)); | |
458 | ||
459 | dd->flags |= SHA_FLAGS_CPU; | |
460 | ||
461 | for (count = 0; count < len32; count++) | |
462 | atmel_sha_write(dd, SHA_REG_DIN(count), buffer[count]); | |
463 | ||
464 | return -EINPROGRESS; | |
465 | } | |
466 | ||
467 | static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, | |
468 | size_t length1, dma_addr_t dma_addr2, size_t length2, int final) | |
469 | { | |
470 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
471 | int len32; | |
472 | ||
d4905b38 NR |
473 | dev_dbg(dd->dev, "xmit_pdc: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n", |
474 | ctx->digcnt[1], ctx->digcnt[0], length1, final); | |
ebc82efa NR |
475 | |
476 | len32 = DIV_ROUND_UP(length1, sizeof(u32)); | |
477 | atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTDIS); | |
478 | atmel_sha_write(dd, SHA_TPR, dma_addr1); | |
479 | atmel_sha_write(dd, SHA_TCR, len32); | |
480 | ||
481 | len32 = DIV_ROUND_UP(length2, sizeof(u32)); | |
482 | atmel_sha_write(dd, SHA_TNPR, dma_addr2); | |
483 | atmel_sha_write(dd, SHA_TNCR, len32); | |
484 | ||
485 | atmel_sha_write_ctrl(dd, 1); | |
486 | ||
487 | /* should be non-zero before next lines to disable clocks later */ | |
d4905b38 NR |
488 | ctx->digcnt[0] += length1; |
489 | if (ctx->digcnt[0] < length1) | |
490 | ctx->digcnt[1]++; | |
ebc82efa NR |
491 | |
492 | if (final) | |
493 | dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ | |
494 | ||
495 | dd->flags |= SHA_FLAGS_DMA_ACTIVE; | |
496 | ||
497 | /* Start DMA transfer */ | |
498 | atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTEN); | |
499 | ||
500 | return -EINPROGRESS; | |
501 | } | |
502 | ||
d4905b38 NR |
503 | static void atmel_sha_dma_callback(void *data) |
504 | { | |
505 | struct atmel_sha_dev *dd = data; | |
506 | ||
a29af939 CP |
507 | dd->is_async = true; |
508 | ||
d4905b38 NR |
509 | /* dma_lch_in - completed - wait DATRDY */ |
510 | atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY); | |
511 | } | |
512 | ||
513 | static int atmel_sha_xmit_dma(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, | |
514 | size_t length1, dma_addr_t dma_addr2, size_t length2, int final) | |
515 | { | |
516 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
517 | struct dma_async_tx_descriptor *in_desc; | |
518 | struct scatterlist sg[2]; | |
519 | ||
520 | dev_dbg(dd->dev, "xmit_dma: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n", | |
521 | ctx->digcnt[1], ctx->digcnt[0], length1, final); | |
522 | ||
3f1992c0 LZ |
523 | dd->dma_lch_in.dma_conf.src_maxburst = 16; |
524 | dd->dma_lch_in.dma_conf.dst_maxburst = 16; | |
d4905b38 NR |
525 | |
526 | dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf); | |
527 | ||
528 | if (length2) { | |
529 | sg_init_table(sg, 2); | |
530 | sg_dma_address(&sg[0]) = dma_addr1; | |
531 | sg_dma_len(&sg[0]) = length1; | |
532 | sg_dma_address(&sg[1]) = dma_addr2; | |
533 | sg_dma_len(&sg[1]) = length2; | |
534 | in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 2, | |
535 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
536 | } else { | |
537 | sg_init_table(sg, 1); | |
538 | sg_dma_address(&sg[0]) = dma_addr1; | |
539 | sg_dma_len(&sg[0]) = length1; | |
540 | in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 1, | |
541 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
542 | } | |
543 | if (!in_desc) | |
a29af939 | 544 | atmel_sha_complete(dd, -EINVAL); |
d4905b38 NR |
545 | |
546 | in_desc->callback = atmel_sha_dma_callback; | |
547 | in_desc->callback_param = dd; | |
548 | ||
549 | atmel_sha_write_ctrl(dd, 1); | |
550 | ||
551 | /* should be non-zero before next lines to disable clocks later */ | |
552 | ctx->digcnt[0] += length1; | |
553 | if (ctx->digcnt[0] < length1) | |
554 | ctx->digcnt[1]++; | |
555 | ||
556 | if (final) | |
557 | dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ | |
558 | ||
559 | dd->flags |= SHA_FLAGS_DMA_ACTIVE; | |
560 | ||
561 | /* Start DMA transfer */ | |
562 | dmaengine_submit(in_desc); | |
563 | dma_async_issue_pending(dd->dma_lch_in.chan); | |
564 | ||
565 | return -EINPROGRESS; | |
566 | } | |
567 | ||
568 | static int atmel_sha_xmit_start(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, | |
569 | size_t length1, dma_addr_t dma_addr2, size_t length2, int final) | |
570 | { | |
571 | if (dd->caps.has_dma) | |
572 | return atmel_sha_xmit_dma(dd, dma_addr1, length1, | |
573 | dma_addr2, length2, final); | |
574 | else | |
575 | return atmel_sha_xmit_pdc(dd, dma_addr1, length1, | |
576 | dma_addr2, length2, final); | |
577 | } | |
578 | ||
ebc82efa NR |
579 | static int atmel_sha_update_cpu(struct atmel_sha_dev *dd) |
580 | { | |
581 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
582 | int bufcnt; | |
583 | ||
584 | atmel_sha_append_sg(ctx); | |
585 | atmel_sha_fill_padding(ctx, 0); | |
ebc82efa NR |
586 | bufcnt = ctx->bufcnt; |
587 | ctx->bufcnt = 0; | |
588 | ||
589 | return atmel_sha_xmit_cpu(dd, ctx->buffer, bufcnt, 1); | |
590 | } | |
591 | ||
592 | static int atmel_sha_xmit_dma_map(struct atmel_sha_dev *dd, | |
593 | struct atmel_sha_reqctx *ctx, | |
594 | size_t length, int final) | |
595 | { | |
596 | ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, | |
d4905b38 | 597 | ctx->buflen + ctx->block_size, DMA_TO_DEVICE); |
ebc82efa NR |
598 | if (dma_mapping_error(dd->dev, ctx->dma_addr)) { |
599 | dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen + | |
d4905b38 | 600 | ctx->block_size); |
a29af939 | 601 | atmel_sha_complete(dd, -EINVAL); |
ebc82efa NR |
602 | } |
603 | ||
604 | ctx->flags &= ~SHA_FLAGS_SG; | |
605 | ||
606 | /* next call does not fail... so no unmap in the case of error */ | |
d4905b38 | 607 | return atmel_sha_xmit_start(dd, ctx->dma_addr, length, 0, 0, final); |
ebc82efa NR |
608 | } |
609 | ||
610 | static int atmel_sha_update_dma_slow(struct atmel_sha_dev *dd) | |
611 | { | |
612 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
613 | unsigned int final; | |
614 | size_t count; | |
615 | ||
616 | atmel_sha_append_sg(ctx); | |
617 | ||
618 | final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total; | |
619 | ||
d4905b38 NR |
620 | dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: 0x%llx 0x%llx, final: %d\n", |
621 | ctx->bufcnt, ctx->digcnt[1], ctx->digcnt[0], final); | |
ebc82efa NR |
622 | |
623 | if (final) | |
624 | atmel_sha_fill_padding(ctx, 0); | |
625 | ||
0099286b | 626 | if (final || (ctx->bufcnt == ctx->buflen)) { |
ebc82efa NR |
627 | count = ctx->bufcnt; |
628 | ctx->bufcnt = 0; | |
629 | return atmel_sha_xmit_dma_map(dd, ctx, count, final); | |
630 | } | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd) | |
636 | { | |
637 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
638 | unsigned int length, final, tail; | |
639 | struct scatterlist *sg; | |
640 | unsigned int count; | |
641 | ||
642 | if (!ctx->total) | |
643 | return 0; | |
644 | ||
645 | if (ctx->bufcnt || ctx->offset) | |
646 | return atmel_sha_update_dma_slow(dd); | |
647 | ||
d4905b38 NR |
648 | dev_dbg(dd->dev, "fast: digcnt: 0x%llx 0x%llx, bufcnt: %u, total: %u\n", |
649 | ctx->digcnt[1], ctx->digcnt[0], ctx->bufcnt, ctx->total); | |
ebc82efa NR |
650 | |
651 | sg = ctx->sg; | |
652 | ||
653 | if (!IS_ALIGNED(sg->offset, sizeof(u32))) | |
654 | return atmel_sha_update_dma_slow(dd); | |
655 | ||
d4905b38 NR |
656 | if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->block_size)) |
657 | /* size is not ctx->block_size aligned */ | |
ebc82efa NR |
658 | return atmel_sha_update_dma_slow(dd); |
659 | ||
660 | length = min(ctx->total, sg->length); | |
661 | ||
662 | if (sg_is_last(sg)) { | |
663 | if (!(ctx->flags & SHA_FLAGS_FINUP)) { | |
d4905b38 NR |
664 | /* not last sg must be ctx->block_size aligned */ |
665 | tail = length & (ctx->block_size - 1); | |
ebc82efa | 666 | length -= tail; |
ebc82efa NR |
667 | } |
668 | } | |
669 | ||
670 | ctx->total -= length; | |
671 | ctx->offset = length; /* offset where to start slow */ | |
672 | ||
673 | final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total; | |
674 | ||
675 | /* Add padding */ | |
676 | if (final) { | |
d4905b38 | 677 | tail = length & (ctx->block_size - 1); |
ebc82efa NR |
678 | length -= tail; |
679 | ctx->total += tail; | |
680 | ctx->offset = length; /* offset where to start slow */ | |
681 | ||
682 | sg = ctx->sg; | |
683 | atmel_sha_append_sg(ctx); | |
684 | ||
685 | atmel_sha_fill_padding(ctx, length); | |
686 | ||
687 | ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, | |
d4905b38 | 688 | ctx->buflen + ctx->block_size, DMA_TO_DEVICE); |
ebc82efa NR |
689 | if (dma_mapping_error(dd->dev, ctx->dma_addr)) { |
690 | dev_err(dd->dev, "dma %u bytes error\n", | |
d4905b38 | 691 | ctx->buflen + ctx->block_size); |
a29af939 | 692 | atmel_sha_complete(dd, -EINVAL); |
ebc82efa NR |
693 | } |
694 | ||
695 | if (length == 0) { | |
696 | ctx->flags &= ~SHA_FLAGS_SG; | |
697 | count = ctx->bufcnt; | |
698 | ctx->bufcnt = 0; | |
d4905b38 | 699 | return atmel_sha_xmit_start(dd, ctx->dma_addr, count, 0, |
ebc82efa NR |
700 | 0, final); |
701 | } else { | |
702 | ctx->sg = sg; | |
703 | if (!dma_map_sg(dd->dev, ctx->sg, 1, | |
704 | DMA_TO_DEVICE)) { | |
705 | dev_err(dd->dev, "dma_map_sg error\n"); | |
a29af939 | 706 | atmel_sha_complete(dd, -EINVAL); |
ebc82efa NR |
707 | } |
708 | ||
709 | ctx->flags |= SHA_FLAGS_SG; | |
710 | ||
711 | count = ctx->bufcnt; | |
712 | ctx->bufcnt = 0; | |
d4905b38 | 713 | return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), |
ebc82efa NR |
714 | length, ctx->dma_addr, count, final); |
715 | } | |
716 | } | |
717 | ||
718 | if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) { | |
719 | dev_err(dd->dev, "dma_map_sg error\n"); | |
a29af939 | 720 | atmel_sha_complete(dd, -EINVAL); |
ebc82efa NR |
721 | } |
722 | ||
723 | ctx->flags |= SHA_FLAGS_SG; | |
724 | ||
725 | /* next call does not fail... so no unmap in the case of error */ | |
d4905b38 | 726 | return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), length, 0, |
ebc82efa NR |
727 | 0, final); |
728 | } | |
729 | ||
730 | static int atmel_sha_update_dma_stop(struct atmel_sha_dev *dd) | |
731 | { | |
732 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); | |
733 | ||
734 | if (ctx->flags & SHA_FLAGS_SG) { | |
735 | dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); | |
736 | if (ctx->sg->length == ctx->offset) { | |
737 | ctx->sg = sg_next(ctx->sg); | |
738 | if (ctx->sg) | |
739 | ctx->offset = 0; | |
740 | } | |
d4905b38 | 741 | if (ctx->flags & SHA_FLAGS_PAD) { |
ebc82efa | 742 | dma_unmap_single(dd->dev, ctx->dma_addr, |
d4905b38 NR |
743 | ctx->buflen + ctx->block_size, DMA_TO_DEVICE); |
744 | } | |
ebc82efa NR |
745 | } else { |
746 | dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen + | |
d4905b38 | 747 | ctx->block_size, DMA_TO_DEVICE); |
ebc82efa NR |
748 | } |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
753 | static int atmel_sha_update_req(struct atmel_sha_dev *dd) | |
754 | { | |
755 | struct ahash_request *req = dd->req; | |
756 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
757 | int err; | |
758 | ||
d4905b38 NR |
759 | dev_dbg(dd->dev, "update_req: total: %u, digcnt: 0x%llx 0x%llx\n", |
760 | ctx->total, ctx->digcnt[1], ctx->digcnt[0]); | |
ebc82efa NR |
761 | |
762 | if (ctx->flags & SHA_FLAGS_CPU) | |
763 | err = atmel_sha_update_cpu(dd); | |
764 | else | |
765 | err = atmel_sha_update_dma_start(dd); | |
766 | ||
767 | /* wait for dma completion before can take more data */ | |
d4905b38 NR |
768 | dev_dbg(dd->dev, "update: err: %d, digcnt: 0x%llx 0%llx\n", |
769 | err, ctx->digcnt[1], ctx->digcnt[0]); | |
ebc82efa NR |
770 | |
771 | return err; | |
772 | } | |
773 | ||
774 | static int atmel_sha_final_req(struct atmel_sha_dev *dd) | |
775 | { | |
776 | struct ahash_request *req = dd->req; | |
777 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
778 | int err = 0; | |
779 | int count; | |
780 | ||
781 | if (ctx->bufcnt >= ATMEL_SHA_DMA_THRESHOLD) { | |
782 | atmel_sha_fill_padding(ctx, 0); | |
783 | count = ctx->bufcnt; | |
784 | ctx->bufcnt = 0; | |
785 | err = atmel_sha_xmit_dma_map(dd, ctx, count, 1); | |
786 | } | |
787 | /* faster to handle last block with cpu */ | |
788 | else { | |
789 | atmel_sha_fill_padding(ctx, 0); | |
790 | count = ctx->bufcnt; | |
791 | ctx->bufcnt = 0; | |
792 | err = atmel_sha_xmit_cpu(dd, ctx->buffer, count, 1); | |
793 | } | |
794 | ||
795 | dev_dbg(dd->dev, "final_req: err: %d\n", err); | |
796 | ||
797 | return err; | |
798 | } | |
799 | ||
800 | static void atmel_sha_copy_hash(struct ahash_request *req) | |
801 | { | |
802 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
803 | u32 *hash = (u32 *)ctx->digest; | |
7cee3508 | 804 | unsigned int i, hashsize; |
ebc82efa | 805 | |
7cee3508 CP |
806 | switch (ctx->flags & SHA_FLAGS_ALGO_MASK) { |
807 | case SHA_FLAGS_SHA1: | |
808 | hashsize = SHA1_DIGEST_SIZE; | |
809 | break; | |
810 | ||
811 | case SHA_FLAGS_SHA224: | |
812 | case SHA_FLAGS_SHA256: | |
813 | hashsize = SHA256_DIGEST_SIZE; | |
814 | break; | |
815 | ||
816 | case SHA_FLAGS_SHA384: | |
817 | case SHA_FLAGS_SHA512: | |
818 | hashsize = SHA512_DIGEST_SIZE; | |
819 | break; | |
820 | ||
821 | default: | |
822 | /* Should not happen... */ | |
823 | return; | |
824 | } | |
825 | ||
826 | for (i = 0; i < hashsize / sizeof(u32); ++i) | |
827 | hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); | |
828 | ctx->flags |= SHA_FLAGS_RESTORE; | |
ebc82efa NR |
829 | } |
830 | ||
831 | static void atmel_sha_copy_ready_hash(struct ahash_request *req) | |
832 | { | |
833 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
834 | ||
835 | if (!req->result) | |
836 | return; | |
837 | ||
f07cebad CP |
838 | switch (ctx->flags & SHA_FLAGS_ALGO_MASK) { |
839 | default: | |
840 | case SHA_FLAGS_SHA1: | |
ebc82efa | 841 | memcpy(req->result, ctx->digest, SHA1_DIGEST_SIZE); |
f07cebad CP |
842 | break; |
843 | ||
844 | case SHA_FLAGS_SHA224: | |
d4905b38 | 845 | memcpy(req->result, ctx->digest, SHA224_DIGEST_SIZE); |
f07cebad CP |
846 | break; |
847 | ||
848 | case SHA_FLAGS_SHA256: | |
ebc82efa | 849 | memcpy(req->result, ctx->digest, SHA256_DIGEST_SIZE); |
f07cebad CP |
850 | break; |
851 | ||
852 | case SHA_FLAGS_SHA384: | |
d4905b38 | 853 | memcpy(req->result, ctx->digest, SHA384_DIGEST_SIZE); |
f07cebad CP |
854 | break; |
855 | ||
856 | case SHA_FLAGS_SHA512: | |
d4905b38 | 857 | memcpy(req->result, ctx->digest, SHA512_DIGEST_SIZE); |
f07cebad CP |
858 | break; |
859 | } | |
ebc82efa NR |
860 | } |
861 | ||
862 | static int atmel_sha_finish(struct ahash_request *req) | |
863 | { | |
864 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
865 | struct atmel_sha_dev *dd = ctx->dd; | |
ebc82efa | 866 | |
d4905b38 | 867 | if (ctx->digcnt[0] || ctx->digcnt[1]) |
ebc82efa NR |
868 | atmel_sha_copy_ready_hash(req); |
869 | ||
d4905b38 NR |
870 | dev_dbg(dd->dev, "digcnt: 0x%llx 0x%llx, bufcnt: %d\n", ctx->digcnt[1], |
871 | ctx->digcnt[0], ctx->bufcnt); | |
ebc82efa | 872 | |
871b88a8 | 873 | return 0; |
ebc82efa NR |
874 | } |
875 | ||
876 | static void atmel_sha_finish_req(struct ahash_request *req, int err) | |
877 | { | |
878 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
879 | struct atmel_sha_dev *dd = ctx->dd; | |
880 | ||
881 | if (!err) { | |
882 | atmel_sha_copy_hash(req); | |
883 | if (SHA_FLAGS_FINAL & dd->flags) | |
884 | err = atmel_sha_finish(req); | |
885 | } else { | |
886 | ctx->flags |= SHA_FLAGS_ERROR; | |
887 | } | |
888 | ||
889 | /* atomic operation is not needed here */ | |
a29af939 | 890 | (void)atmel_sha_complete(dd, err); |
ebc82efa NR |
891 | } |
892 | ||
893 | static int atmel_sha_hw_init(struct atmel_sha_dev *dd) | |
894 | { | |
9d83d299 LC |
895 | int err; |
896 | ||
c033042a | 897 | err = clk_enable(dd->iclk); |
9d83d299 LC |
898 | if (err) |
899 | return err; | |
ebc82efa | 900 | |
d4905b38 | 901 | if (!(SHA_FLAGS_INIT & dd->flags)) { |
ebc82efa | 902 | atmel_sha_write(dd, SHA_CR, SHA_CR_SWRST); |
ebc82efa NR |
903 | dd->flags |= SHA_FLAGS_INIT; |
904 | dd->err = 0; | |
905 | } | |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
d4905b38 NR |
910 | static inline unsigned int atmel_sha_get_version(struct atmel_sha_dev *dd) |
911 | { | |
912 | return atmel_sha_read(dd, SHA_HW_VERSION) & 0x00000fff; | |
913 | } | |
914 | ||
915 | static void atmel_sha_hw_version_init(struct atmel_sha_dev *dd) | |
916 | { | |
917 | atmel_sha_hw_init(dd); | |
918 | ||
919 | dd->hw_version = atmel_sha_get_version(dd); | |
920 | ||
921 | dev_info(dd->dev, | |
922 | "version: 0x%x\n", dd->hw_version); | |
923 | ||
c033042a | 924 | clk_disable(dd->iclk); |
d4905b38 NR |
925 | } |
926 | ||
ebc82efa NR |
927 | static int atmel_sha_handle_queue(struct atmel_sha_dev *dd, |
928 | struct ahash_request *req) | |
929 | { | |
930 | struct crypto_async_request *async_req, *backlog; | |
a29af939 | 931 | struct atmel_sha_ctx *ctx; |
ebc82efa | 932 | unsigned long flags; |
a29af939 | 933 | bool start_async; |
ebc82efa NR |
934 | int err = 0, ret = 0; |
935 | ||
936 | spin_lock_irqsave(&dd->lock, flags); | |
937 | if (req) | |
938 | ret = ahash_enqueue_request(&dd->queue, req); | |
939 | ||
940 | if (SHA_FLAGS_BUSY & dd->flags) { | |
941 | spin_unlock_irqrestore(&dd->lock, flags); | |
942 | return ret; | |
943 | } | |
944 | ||
945 | backlog = crypto_get_backlog(&dd->queue); | |
946 | async_req = crypto_dequeue_request(&dd->queue); | |
947 | if (async_req) | |
948 | dd->flags |= SHA_FLAGS_BUSY; | |
949 | ||
950 | spin_unlock_irqrestore(&dd->lock, flags); | |
951 | ||
952 | if (!async_req) | |
953 | return ret; | |
954 | ||
955 | if (backlog) | |
956 | backlog->complete(backlog, -EINPROGRESS); | |
957 | ||
a29af939 CP |
958 | ctx = crypto_tfm_ctx(async_req->tfm); |
959 | ||
960 | dd->req = ahash_request_cast(async_req); | |
961 | start_async = (dd->req != req); | |
962 | dd->is_async = start_async; | |
963 | ||
964 | /* WARNING: ctx->start() MAY change dd->is_async. */ | |
965 | err = ctx->start(dd); | |
966 | return (start_async) ? ret : err; | |
967 | } | |
968 | ||
b5ce82a7 CP |
969 | static int atmel_sha_done(struct atmel_sha_dev *dd); |
970 | ||
a29af939 CP |
971 | static int atmel_sha_start(struct atmel_sha_dev *dd) |
972 | { | |
973 | struct ahash_request *req = dd->req; | |
974 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
975 | int err; | |
ebc82efa NR |
976 | |
977 | dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", | |
978 | ctx->op, req->nbytes); | |
979 | ||
980 | err = atmel_sha_hw_init(dd); | |
981 | ||
982 | if (err) | |
983 | goto err1; | |
984 | ||
b5ce82a7 | 985 | dd->resume = atmel_sha_done; |
ebc82efa NR |
986 | if (ctx->op == SHA_OP_UPDATE) { |
987 | err = atmel_sha_update_req(dd); | |
d4905b38 | 988 | if (err != -EINPROGRESS && (ctx->flags & SHA_FLAGS_FINUP)) |
ebc82efa NR |
989 | /* no final() after finup() */ |
990 | err = atmel_sha_final_req(dd); | |
ebc82efa NR |
991 | } else if (ctx->op == SHA_OP_FINAL) { |
992 | err = atmel_sha_final_req(dd); | |
993 | } | |
994 | ||
995 | err1: | |
996 | if (err != -EINPROGRESS) | |
997 | /* done_task will not finish it, so do it here */ | |
998 | atmel_sha_finish_req(req, err); | |
999 | ||
1000 | dev_dbg(dd->dev, "exit, err: %d\n", err); | |
1001 | ||
a29af939 | 1002 | return err; |
ebc82efa NR |
1003 | } |
1004 | ||
1005 | static int atmel_sha_enqueue(struct ahash_request *req, unsigned int op) | |
1006 | { | |
1007 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
1008 | struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1009 | struct atmel_sha_dev *dd = tctx->dd; | |
1010 | ||
1011 | ctx->op = op; | |
1012 | ||
1013 | return atmel_sha_handle_queue(dd, req); | |
1014 | } | |
1015 | ||
1016 | static int atmel_sha_update(struct ahash_request *req) | |
1017 | { | |
1018 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
1019 | ||
1020 | if (!req->nbytes) | |
1021 | return 0; | |
1022 | ||
1023 | ctx->total = req->nbytes; | |
1024 | ctx->sg = req->src; | |
1025 | ctx->offset = 0; | |
1026 | ||
1027 | if (ctx->flags & SHA_FLAGS_FINUP) { | |
1028 | if (ctx->bufcnt + ctx->total < ATMEL_SHA_DMA_THRESHOLD) | |
1029 | /* faster to use CPU for short transfers */ | |
1030 | ctx->flags |= SHA_FLAGS_CPU; | |
1031 | } else if (ctx->bufcnt + ctx->total < ctx->buflen) { | |
1032 | atmel_sha_append_sg(ctx); | |
1033 | return 0; | |
1034 | } | |
1035 | return atmel_sha_enqueue(req, SHA_OP_UPDATE); | |
1036 | } | |
1037 | ||
1038 | static int atmel_sha_final(struct ahash_request *req) | |
1039 | { | |
1040 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
ebc82efa NR |
1041 | |
1042 | ctx->flags |= SHA_FLAGS_FINUP; | |
1043 | ||
1044 | if (ctx->flags & SHA_FLAGS_ERROR) | |
1045 | return 0; /* uncompleted hash is not needed */ | |
1046 | ||
ad84112a | 1047 | if (ctx->flags & SHA_FLAGS_PAD) |
ebc82efa NR |
1048 | /* copy ready hash (+ finalize hmac) */ |
1049 | return atmel_sha_finish(req); | |
ebc82efa | 1050 | |
ad84112a | 1051 | return atmel_sha_enqueue(req, SHA_OP_FINAL); |
ebc82efa NR |
1052 | } |
1053 | ||
1054 | static int atmel_sha_finup(struct ahash_request *req) | |
1055 | { | |
1056 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
1057 | int err1, err2; | |
1058 | ||
1059 | ctx->flags |= SHA_FLAGS_FINUP; | |
1060 | ||
1061 | err1 = atmel_sha_update(req); | |
1062 | if (err1 == -EINPROGRESS || err1 == -EBUSY) | |
1063 | return err1; | |
1064 | ||
1065 | /* | |
1066 | * final() has to be always called to cleanup resources | |
1067 | * even if udpate() failed, except EINPROGRESS | |
1068 | */ | |
1069 | err2 = atmel_sha_final(req); | |
1070 | ||
1071 | return err1 ?: err2; | |
1072 | } | |
1073 | ||
1074 | static int atmel_sha_digest(struct ahash_request *req) | |
1075 | { | |
1076 | return atmel_sha_init(req) ?: atmel_sha_finup(req); | |
1077 | } | |
1078 | ||
cc831d32 CP |
1079 | |
1080 | static int atmel_sha_export(struct ahash_request *req, void *out) | |
1081 | { | |
1082 | const struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
cc831d32 | 1083 | |
9c4274d9 | 1084 | memcpy(out, ctx, sizeof(*ctx)); |
cc831d32 CP |
1085 | return 0; |
1086 | } | |
1087 | ||
1088 | static int atmel_sha_import(struct ahash_request *req, const void *in) | |
1089 | { | |
1090 | struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); | |
cc831d32 | 1091 | |
9c4274d9 | 1092 | memcpy(ctx, in, sizeof(*ctx)); |
cc831d32 CP |
1093 | return 0; |
1094 | } | |
1095 | ||
be95f0fa | 1096 | static int atmel_sha_cra_init(struct crypto_tfm *tfm) |
ebc82efa | 1097 | { |
a29af939 CP |
1098 | struct atmel_sha_ctx *ctx = crypto_tfm_ctx(tfm); |
1099 | ||
ebc82efa | 1100 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), |
9c4274d9 | 1101 | sizeof(struct atmel_sha_reqctx)); |
a29af939 | 1102 | ctx->start = atmel_sha_start; |
ebc82efa NR |
1103 | |
1104 | return 0; | |
1105 | } | |
1106 | ||
d4905b38 | 1107 | static struct ahash_alg sha_1_256_algs[] = { |
ebc82efa NR |
1108 | { |
1109 | .init = atmel_sha_init, | |
1110 | .update = atmel_sha_update, | |
1111 | .final = atmel_sha_final, | |
1112 | .finup = atmel_sha_finup, | |
1113 | .digest = atmel_sha_digest, | |
cc831d32 CP |
1114 | .export = atmel_sha_export, |
1115 | .import = atmel_sha_import, | |
ebc82efa NR |
1116 | .halg = { |
1117 | .digestsize = SHA1_DIGEST_SIZE, | |
9c4274d9 | 1118 | .statesize = sizeof(struct atmel_sha_reqctx), |
ebc82efa NR |
1119 | .base = { |
1120 | .cra_name = "sha1", | |
1121 | .cra_driver_name = "atmel-sha1", | |
1122 | .cra_priority = 100, | |
be95f0fa | 1123 | .cra_flags = CRYPTO_ALG_ASYNC, |
ebc82efa NR |
1124 | .cra_blocksize = SHA1_BLOCK_SIZE, |
1125 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1126 | .cra_alignmask = 0, | |
1127 | .cra_module = THIS_MODULE, | |
1128 | .cra_init = atmel_sha_cra_init, | |
ebc82efa NR |
1129 | } |
1130 | } | |
1131 | }, | |
1132 | { | |
1133 | .init = atmel_sha_init, | |
1134 | .update = atmel_sha_update, | |
1135 | .final = atmel_sha_final, | |
1136 | .finup = atmel_sha_finup, | |
1137 | .digest = atmel_sha_digest, | |
cc831d32 CP |
1138 | .export = atmel_sha_export, |
1139 | .import = atmel_sha_import, | |
ebc82efa NR |
1140 | .halg = { |
1141 | .digestsize = SHA256_DIGEST_SIZE, | |
9c4274d9 | 1142 | .statesize = sizeof(struct atmel_sha_reqctx), |
ebc82efa NR |
1143 | .base = { |
1144 | .cra_name = "sha256", | |
1145 | .cra_driver_name = "atmel-sha256", | |
1146 | .cra_priority = 100, | |
be95f0fa | 1147 | .cra_flags = CRYPTO_ALG_ASYNC, |
ebc82efa NR |
1148 | .cra_blocksize = SHA256_BLOCK_SIZE, |
1149 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1150 | .cra_alignmask = 0, | |
1151 | .cra_module = THIS_MODULE, | |
1152 | .cra_init = atmel_sha_cra_init, | |
ebc82efa NR |
1153 | } |
1154 | } | |
1155 | }, | |
1156 | }; | |
1157 | ||
d4905b38 NR |
1158 | static struct ahash_alg sha_224_alg = { |
1159 | .init = atmel_sha_init, | |
1160 | .update = atmel_sha_update, | |
1161 | .final = atmel_sha_final, | |
1162 | .finup = atmel_sha_finup, | |
1163 | .digest = atmel_sha_digest, | |
cc831d32 CP |
1164 | .export = atmel_sha_export, |
1165 | .import = atmel_sha_import, | |
d4905b38 NR |
1166 | .halg = { |
1167 | .digestsize = SHA224_DIGEST_SIZE, | |
9c4274d9 | 1168 | .statesize = sizeof(struct atmel_sha_reqctx), |
d4905b38 NR |
1169 | .base = { |
1170 | .cra_name = "sha224", | |
1171 | .cra_driver_name = "atmel-sha224", | |
1172 | .cra_priority = 100, | |
be95f0fa | 1173 | .cra_flags = CRYPTO_ALG_ASYNC, |
d4905b38 NR |
1174 | .cra_blocksize = SHA224_BLOCK_SIZE, |
1175 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1176 | .cra_alignmask = 0, | |
1177 | .cra_module = THIS_MODULE, | |
1178 | .cra_init = atmel_sha_cra_init, | |
d4905b38 NR |
1179 | } |
1180 | } | |
1181 | }; | |
1182 | ||
1183 | static struct ahash_alg sha_384_512_algs[] = { | |
1184 | { | |
1185 | .init = atmel_sha_init, | |
1186 | .update = atmel_sha_update, | |
1187 | .final = atmel_sha_final, | |
1188 | .finup = atmel_sha_finup, | |
1189 | .digest = atmel_sha_digest, | |
cc831d32 CP |
1190 | .export = atmel_sha_export, |
1191 | .import = atmel_sha_import, | |
d4905b38 NR |
1192 | .halg = { |
1193 | .digestsize = SHA384_DIGEST_SIZE, | |
9c4274d9 | 1194 | .statesize = sizeof(struct atmel_sha_reqctx), |
d4905b38 NR |
1195 | .base = { |
1196 | .cra_name = "sha384", | |
1197 | .cra_driver_name = "atmel-sha384", | |
1198 | .cra_priority = 100, | |
be95f0fa | 1199 | .cra_flags = CRYPTO_ALG_ASYNC, |
d4905b38 NR |
1200 | .cra_blocksize = SHA384_BLOCK_SIZE, |
1201 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1202 | .cra_alignmask = 0x3, | |
1203 | .cra_module = THIS_MODULE, | |
1204 | .cra_init = atmel_sha_cra_init, | |
d4905b38 NR |
1205 | } |
1206 | } | |
1207 | }, | |
1208 | { | |
1209 | .init = atmel_sha_init, | |
1210 | .update = atmel_sha_update, | |
1211 | .final = atmel_sha_final, | |
1212 | .finup = atmel_sha_finup, | |
1213 | .digest = atmel_sha_digest, | |
cc831d32 CP |
1214 | .export = atmel_sha_export, |
1215 | .import = atmel_sha_import, | |
d4905b38 NR |
1216 | .halg = { |
1217 | .digestsize = SHA512_DIGEST_SIZE, | |
9c4274d9 | 1218 | .statesize = sizeof(struct atmel_sha_reqctx), |
d4905b38 NR |
1219 | .base = { |
1220 | .cra_name = "sha512", | |
1221 | .cra_driver_name = "atmel-sha512", | |
1222 | .cra_priority = 100, | |
be95f0fa | 1223 | .cra_flags = CRYPTO_ALG_ASYNC, |
d4905b38 NR |
1224 | .cra_blocksize = SHA512_BLOCK_SIZE, |
1225 | .cra_ctxsize = sizeof(struct atmel_sha_ctx), | |
1226 | .cra_alignmask = 0x3, | |
1227 | .cra_module = THIS_MODULE, | |
1228 | .cra_init = atmel_sha_cra_init, | |
d4905b38 NR |
1229 | } |
1230 | } | |
1231 | }, | |
1232 | }; | |
1233 | ||
f56809c3 CP |
1234 | static void atmel_sha_queue_task(unsigned long data) |
1235 | { | |
1236 | struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data; | |
1237 | ||
1238 | atmel_sha_handle_queue(dd, NULL); | |
1239 | } | |
1240 | ||
b5ce82a7 | 1241 | static int atmel_sha_done(struct atmel_sha_dev *dd) |
ebc82efa | 1242 | { |
ebc82efa NR |
1243 | int err = 0; |
1244 | ||
ebc82efa NR |
1245 | if (SHA_FLAGS_CPU & dd->flags) { |
1246 | if (SHA_FLAGS_OUTPUT_READY & dd->flags) { | |
1247 | dd->flags &= ~SHA_FLAGS_OUTPUT_READY; | |
1248 | goto finish; | |
1249 | } | |
1250 | } else if (SHA_FLAGS_DMA_READY & dd->flags) { | |
1251 | if (SHA_FLAGS_DMA_ACTIVE & dd->flags) { | |
1252 | dd->flags &= ~SHA_FLAGS_DMA_ACTIVE; | |
1253 | atmel_sha_update_dma_stop(dd); | |
1254 | if (dd->err) { | |
1255 | err = dd->err; | |
1256 | goto finish; | |
1257 | } | |
1258 | } | |
1259 | if (SHA_FLAGS_OUTPUT_READY & dd->flags) { | |
1260 | /* hash or semi-hash ready */ | |
1261 | dd->flags &= ~(SHA_FLAGS_DMA_READY | | |
1262 | SHA_FLAGS_OUTPUT_READY); | |
1263 | err = atmel_sha_update_dma_start(dd); | |
1264 | if (err != -EINPROGRESS) | |
1265 | goto finish; | |
1266 | } | |
1267 | } | |
b5ce82a7 | 1268 | return err; |
ebc82efa NR |
1269 | |
1270 | finish: | |
1271 | /* finish curent request */ | |
1272 | atmel_sha_finish_req(dd->req, err); | |
b5ce82a7 CP |
1273 | |
1274 | return err; | |
1275 | } | |
1276 | ||
1277 | static void atmel_sha_done_task(unsigned long data) | |
1278 | { | |
1279 | struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data; | |
1280 | ||
1281 | dd->is_async = true; | |
1282 | (void)dd->resume(dd); | |
ebc82efa NR |
1283 | } |
1284 | ||
1285 | static irqreturn_t atmel_sha_irq(int irq, void *dev_id) | |
1286 | { | |
1287 | struct atmel_sha_dev *sha_dd = dev_id; | |
1288 | u32 reg; | |
1289 | ||
1290 | reg = atmel_sha_read(sha_dd, SHA_ISR); | |
1291 | if (reg & atmel_sha_read(sha_dd, SHA_IMR)) { | |
1292 | atmel_sha_write(sha_dd, SHA_IDR, reg); | |
1293 | if (SHA_FLAGS_BUSY & sha_dd->flags) { | |
1294 | sha_dd->flags |= SHA_FLAGS_OUTPUT_READY; | |
1295 | if (!(SHA_FLAGS_CPU & sha_dd->flags)) | |
1296 | sha_dd->flags |= SHA_FLAGS_DMA_READY; | |
1297 | tasklet_schedule(&sha_dd->done_task); | |
1298 | } else { | |
1299 | dev_warn(sha_dd->dev, "SHA interrupt when no active requests.\n"); | |
1300 | } | |
1301 | return IRQ_HANDLED; | |
1302 | } | |
1303 | ||
1304 | return IRQ_NONE; | |
1305 | } | |
1306 | ||
1307 | static void atmel_sha_unregister_algs(struct atmel_sha_dev *dd) | |
1308 | { | |
1309 | int i; | |
1310 | ||
d4905b38 NR |
1311 | for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) |
1312 | crypto_unregister_ahash(&sha_1_256_algs[i]); | |
1313 | ||
1314 | if (dd->caps.has_sha224) | |
1315 | crypto_unregister_ahash(&sha_224_alg); | |
1316 | ||
1317 | if (dd->caps.has_sha_384_512) { | |
1318 | for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) | |
1319 | crypto_unregister_ahash(&sha_384_512_algs[i]); | |
1320 | } | |
ebc82efa NR |
1321 | } |
1322 | ||
1323 | static int atmel_sha_register_algs(struct atmel_sha_dev *dd) | |
1324 | { | |
1325 | int err, i, j; | |
1326 | ||
d4905b38 NR |
1327 | for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) { |
1328 | err = crypto_register_ahash(&sha_1_256_algs[i]); | |
ebc82efa | 1329 | if (err) |
d4905b38 NR |
1330 | goto err_sha_1_256_algs; |
1331 | } | |
1332 | ||
1333 | if (dd->caps.has_sha224) { | |
1334 | err = crypto_register_ahash(&sha_224_alg); | |
1335 | if (err) | |
1336 | goto err_sha_224_algs; | |
1337 | } | |
1338 | ||
1339 | if (dd->caps.has_sha_384_512) { | |
1340 | for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) { | |
1341 | err = crypto_register_ahash(&sha_384_512_algs[i]); | |
1342 | if (err) | |
1343 | goto err_sha_384_512_algs; | |
1344 | } | |
ebc82efa NR |
1345 | } |
1346 | ||
1347 | return 0; | |
1348 | ||
d4905b38 NR |
1349 | err_sha_384_512_algs: |
1350 | for (j = 0; j < i; j++) | |
1351 | crypto_unregister_ahash(&sha_384_512_algs[j]); | |
1352 | crypto_unregister_ahash(&sha_224_alg); | |
1353 | err_sha_224_algs: | |
1354 | i = ARRAY_SIZE(sha_1_256_algs); | |
1355 | err_sha_1_256_algs: | |
ebc82efa | 1356 | for (j = 0; j < i; j++) |
d4905b38 | 1357 | crypto_unregister_ahash(&sha_1_256_algs[j]); |
ebc82efa NR |
1358 | |
1359 | return err; | |
1360 | } | |
1361 | ||
d4905b38 NR |
1362 | static bool atmel_sha_filter(struct dma_chan *chan, void *slave) |
1363 | { | |
1364 | struct at_dma_slave *sl = slave; | |
1365 | ||
1366 | if (sl && sl->dma_dev == chan->device->dev) { | |
1367 | chan->private = sl; | |
1368 | return true; | |
1369 | } else { | |
1370 | return false; | |
1371 | } | |
1372 | } | |
1373 | ||
1374 | static int atmel_sha_dma_init(struct atmel_sha_dev *dd, | |
1375 | struct crypto_platform_data *pdata) | |
1376 | { | |
1377 | int err = -ENOMEM; | |
1378 | dma_cap_mask_t mask_in; | |
1379 | ||
abfe7ae4 NF |
1380 | /* Try to grab DMA channel */ |
1381 | dma_cap_zero(mask_in); | |
1382 | dma_cap_set(DMA_SLAVE, mask_in); | |
d4905b38 | 1383 | |
abfe7ae4 NF |
1384 | dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask_in, |
1385 | atmel_sha_filter, &pdata->dma_slave->rxdata, dd->dev, "tx"); | |
1386 | if (!dd->dma_lch_in.chan) { | |
1387 | dev_warn(dd->dev, "no DMA channel available\n"); | |
1388 | return err; | |
d4905b38 NR |
1389 | } |
1390 | ||
abfe7ae4 NF |
1391 | dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; |
1392 | dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + | |
1393 | SHA_REG_DIN(0); | |
1394 | dd->dma_lch_in.dma_conf.src_maxburst = 1; | |
1395 | dd->dma_lch_in.dma_conf.src_addr_width = | |
1396 | DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1397 | dd->dma_lch_in.dma_conf.dst_maxburst = 1; | |
1398 | dd->dma_lch_in.dma_conf.dst_addr_width = | |
1399 | DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1400 | dd->dma_lch_in.dma_conf.device_fc = false; | |
1401 | ||
1402 | return 0; | |
d4905b38 NR |
1403 | } |
1404 | ||
1405 | static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd) | |
1406 | { | |
1407 | dma_release_channel(dd->dma_lch_in.chan); | |
1408 | } | |
1409 | ||
1410 | static void atmel_sha_get_cap(struct atmel_sha_dev *dd) | |
1411 | { | |
1412 | ||
1413 | dd->caps.has_dma = 0; | |
1414 | dd->caps.has_dualbuff = 0; | |
1415 | dd->caps.has_sha224 = 0; | |
1416 | dd->caps.has_sha_384_512 = 0; | |
7cee3508 | 1417 | dd->caps.has_uihv = 0; |
d4905b38 NR |
1418 | |
1419 | /* keep only major version number */ | |
1420 | switch (dd->hw_version & 0xff0) { | |
507c5cc2 CP |
1421 | case 0x510: |
1422 | dd->caps.has_dma = 1; | |
1423 | dd->caps.has_dualbuff = 1; | |
1424 | dd->caps.has_sha224 = 1; | |
1425 | dd->caps.has_sha_384_512 = 1; | |
7cee3508 | 1426 | dd->caps.has_uihv = 1; |
507c5cc2 | 1427 | break; |
141824d0 LZ |
1428 | case 0x420: |
1429 | dd->caps.has_dma = 1; | |
1430 | dd->caps.has_dualbuff = 1; | |
1431 | dd->caps.has_sha224 = 1; | |
1432 | dd->caps.has_sha_384_512 = 1; | |
7cee3508 | 1433 | dd->caps.has_uihv = 1; |
141824d0 | 1434 | break; |
d4905b38 NR |
1435 | case 0x410: |
1436 | dd->caps.has_dma = 1; | |
1437 | dd->caps.has_dualbuff = 1; | |
1438 | dd->caps.has_sha224 = 1; | |
1439 | dd->caps.has_sha_384_512 = 1; | |
1440 | break; | |
1441 | case 0x400: | |
1442 | dd->caps.has_dma = 1; | |
1443 | dd->caps.has_dualbuff = 1; | |
1444 | dd->caps.has_sha224 = 1; | |
1445 | break; | |
1446 | case 0x320: | |
1447 | break; | |
1448 | default: | |
1449 | dev_warn(dd->dev, | |
1450 | "Unmanaged sha version, set minimum capabilities\n"); | |
1451 | break; | |
1452 | } | |
1453 | } | |
1454 | ||
abfe7ae4 NF |
1455 | #if defined(CONFIG_OF) |
1456 | static const struct of_device_id atmel_sha_dt_ids[] = { | |
1457 | { .compatible = "atmel,at91sam9g46-sha" }, | |
1458 | { /* sentinel */ } | |
1459 | }; | |
1460 | ||
1461 | MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids); | |
1462 | ||
1463 | static struct crypto_platform_data *atmel_sha_of_init(struct platform_device *pdev) | |
1464 | { | |
1465 | struct device_node *np = pdev->dev.of_node; | |
1466 | struct crypto_platform_data *pdata; | |
1467 | ||
1468 | if (!np) { | |
1469 | dev_err(&pdev->dev, "device node not found\n"); | |
1470 | return ERR_PTR(-EINVAL); | |
1471 | } | |
1472 | ||
1473 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1474 | if (!pdata) { | |
1475 | dev_err(&pdev->dev, "could not allocate memory for pdata\n"); | |
1476 | return ERR_PTR(-ENOMEM); | |
1477 | } | |
1478 | ||
1479 | pdata->dma_slave = devm_kzalloc(&pdev->dev, | |
1480 | sizeof(*(pdata->dma_slave)), | |
1481 | GFP_KERNEL); | |
1482 | if (!pdata->dma_slave) { | |
1483 | dev_err(&pdev->dev, "could not allocate memory for dma_slave\n"); | |
abfe7ae4 NF |
1484 | return ERR_PTR(-ENOMEM); |
1485 | } | |
1486 | ||
1487 | return pdata; | |
1488 | } | |
1489 | #else /* CONFIG_OF */ | |
1490 | static inline struct crypto_platform_data *atmel_sha_of_init(struct platform_device *dev) | |
1491 | { | |
1492 | return ERR_PTR(-EINVAL); | |
1493 | } | |
1494 | #endif | |
1495 | ||
49cfe4db | 1496 | static int atmel_sha_probe(struct platform_device *pdev) |
ebc82efa NR |
1497 | { |
1498 | struct atmel_sha_dev *sha_dd; | |
d4905b38 | 1499 | struct crypto_platform_data *pdata; |
ebc82efa NR |
1500 | struct device *dev = &pdev->dev; |
1501 | struct resource *sha_res; | |
ebc82efa NR |
1502 | int err; |
1503 | ||
b0e8b341 | 1504 | sha_dd = devm_kzalloc(&pdev->dev, sizeof(*sha_dd), GFP_KERNEL); |
ebc82efa NR |
1505 | if (sha_dd == NULL) { |
1506 | dev_err(dev, "unable to alloc data struct.\n"); | |
1507 | err = -ENOMEM; | |
1508 | goto sha_dd_err; | |
1509 | } | |
1510 | ||
1511 | sha_dd->dev = dev; | |
1512 | ||
1513 | platform_set_drvdata(pdev, sha_dd); | |
1514 | ||
1515 | INIT_LIST_HEAD(&sha_dd->list); | |
62728e82 | 1516 | spin_lock_init(&sha_dd->lock); |
ebc82efa NR |
1517 | |
1518 | tasklet_init(&sha_dd->done_task, atmel_sha_done_task, | |
1519 | (unsigned long)sha_dd); | |
f56809c3 CP |
1520 | tasklet_init(&sha_dd->queue_task, atmel_sha_queue_task, |
1521 | (unsigned long)sha_dd); | |
ebc82efa NR |
1522 | |
1523 | crypto_init_queue(&sha_dd->queue, ATMEL_SHA_QUEUE_LENGTH); | |
1524 | ||
1525 | sha_dd->irq = -1; | |
1526 | ||
1527 | /* Get the base address */ | |
1528 | sha_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1529 | if (!sha_res) { | |
1530 | dev_err(dev, "no MEM resource info\n"); | |
1531 | err = -ENODEV; | |
1532 | goto res_err; | |
1533 | } | |
1534 | sha_dd->phys_base = sha_res->start; | |
ebc82efa NR |
1535 | |
1536 | /* Get the IRQ */ | |
1537 | sha_dd->irq = platform_get_irq(pdev, 0); | |
1538 | if (sha_dd->irq < 0) { | |
1539 | dev_err(dev, "no IRQ resource info\n"); | |
1540 | err = sha_dd->irq; | |
1541 | goto res_err; | |
1542 | } | |
1543 | ||
b0e8b341 LC |
1544 | err = devm_request_irq(&pdev->dev, sha_dd->irq, atmel_sha_irq, |
1545 | IRQF_SHARED, "atmel-sha", sha_dd); | |
ebc82efa NR |
1546 | if (err) { |
1547 | dev_err(dev, "unable to request sha irq.\n"); | |
1548 | goto res_err; | |
1549 | } | |
1550 | ||
1551 | /* Initializing the clock */ | |
b0e8b341 | 1552 | sha_dd->iclk = devm_clk_get(&pdev->dev, "sha_clk"); |
ebc82efa | 1553 | if (IS_ERR(sha_dd->iclk)) { |
be208356 | 1554 | dev_err(dev, "clock initialization failed.\n"); |
ebc82efa | 1555 | err = PTR_ERR(sha_dd->iclk); |
b0e8b341 | 1556 | goto res_err; |
ebc82efa NR |
1557 | } |
1558 | ||
b0e8b341 | 1559 | sha_dd->io_base = devm_ioremap_resource(&pdev->dev, sha_res); |
9b52d55f | 1560 | if (IS_ERR(sha_dd->io_base)) { |
ebc82efa | 1561 | dev_err(dev, "can't ioremap\n"); |
9b52d55f | 1562 | err = PTR_ERR(sha_dd->io_base); |
b0e8b341 | 1563 | goto res_err; |
ebc82efa NR |
1564 | } |
1565 | ||
c033042a CP |
1566 | err = clk_prepare(sha_dd->iclk); |
1567 | if (err) | |
1568 | goto res_err; | |
1569 | ||
d4905b38 NR |
1570 | atmel_sha_hw_version_init(sha_dd); |
1571 | ||
1572 | atmel_sha_get_cap(sha_dd); | |
1573 | ||
1574 | if (sha_dd->caps.has_dma) { | |
1575 | pdata = pdev->dev.platform_data; | |
1576 | if (!pdata) { | |
abfe7ae4 NF |
1577 | pdata = atmel_sha_of_init(pdev); |
1578 | if (IS_ERR(pdata)) { | |
1579 | dev_err(&pdev->dev, "platform data not available\n"); | |
1580 | err = PTR_ERR(pdata); | |
c033042a | 1581 | goto iclk_unprepare; |
abfe7ae4 NF |
1582 | } |
1583 | } | |
1584 | if (!pdata->dma_slave) { | |
d4905b38 | 1585 | err = -ENXIO; |
c033042a | 1586 | goto iclk_unprepare; |
d4905b38 NR |
1587 | } |
1588 | err = atmel_sha_dma_init(sha_dd, pdata); | |
1589 | if (err) | |
1590 | goto err_sha_dma; | |
abfe7ae4 NF |
1591 | |
1592 | dev_info(dev, "using %s for DMA transfers\n", | |
1593 | dma_chan_name(sha_dd->dma_lch_in.chan)); | |
d4905b38 NR |
1594 | } |
1595 | ||
ebc82efa NR |
1596 | spin_lock(&atmel_sha.lock); |
1597 | list_add_tail(&sha_dd->list, &atmel_sha.dev_list); | |
1598 | spin_unlock(&atmel_sha.lock); | |
1599 | ||
1600 | err = atmel_sha_register_algs(sha_dd); | |
1601 | if (err) | |
1602 | goto err_algs; | |
1603 | ||
1ca5b7d9 NF |
1604 | dev_info(dev, "Atmel SHA1/SHA256%s%s\n", |
1605 | sha_dd->caps.has_sha224 ? "/SHA224" : "", | |
1606 | sha_dd->caps.has_sha_384_512 ? "/SHA384/SHA512" : ""); | |
ebc82efa NR |
1607 | |
1608 | return 0; | |
1609 | ||
1610 | err_algs: | |
1611 | spin_lock(&atmel_sha.lock); | |
1612 | list_del(&sha_dd->list); | |
1613 | spin_unlock(&atmel_sha.lock); | |
d4905b38 NR |
1614 | if (sha_dd->caps.has_dma) |
1615 | atmel_sha_dma_cleanup(sha_dd); | |
1616 | err_sha_dma: | |
c033042a CP |
1617 | iclk_unprepare: |
1618 | clk_unprepare(sha_dd->iclk); | |
ebc82efa | 1619 | res_err: |
f56809c3 | 1620 | tasklet_kill(&sha_dd->queue_task); |
ebc82efa | 1621 | tasklet_kill(&sha_dd->done_task); |
ebc82efa NR |
1622 | sha_dd_err: |
1623 | dev_err(dev, "initialization failed.\n"); | |
1624 | ||
1625 | return err; | |
1626 | } | |
1627 | ||
49cfe4db | 1628 | static int atmel_sha_remove(struct platform_device *pdev) |
ebc82efa NR |
1629 | { |
1630 | static struct atmel_sha_dev *sha_dd; | |
1631 | ||
1632 | sha_dd = platform_get_drvdata(pdev); | |
1633 | if (!sha_dd) | |
1634 | return -ENODEV; | |
1635 | spin_lock(&atmel_sha.lock); | |
1636 | list_del(&sha_dd->list); | |
1637 | spin_unlock(&atmel_sha.lock); | |
1638 | ||
1639 | atmel_sha_unregister_algs(sha_dd); | |
1640 | ||
f56809c3 | 1641 | tasklet_kill(&sha_dd->queue_task); |
ebc82efa NR |
1642 | tasklet_kill(&sha_dd->done_task); |
1643 | ||
d4905b38 NR |
1644 | if (sha_dd->caps.has_dma) |
1645 | atmel_sha_dma_cleanup(sha_dd); | |
1646 | ||
c033042a CP |
1647 | clk_unprepare(sha_dd->iclk); |
1648 | ||
ebc82efa NR |
1649 | return 0; |
1650 | } | |
1651 | ||
1652 | static struct platform_driver atmel_sha_driver = { | |
1653 | .probe = atmel_sha_probe, | |
49cfe4db | 1654 | .remove = atmel_sha_remove, |
ebc82efa NR |
1655 | .driver = { |
1656 | .name = "atmel_sha", | |
abfe7ae4 | 1657 | .of_match_table = of_match_ptr(atmel_sha_dt_ids), |
ebc82efa NR |
1658 | }, |
1659 | }; | |
1660 | ||
1661 | module_platform_driver(atmel_sha_driver); | |
1662 | ||
d4905b38 | 1663 | MODULE_DESCRIPTION("Atmel SHA (1/256/224/384/512) hw acceleration support."); |
ebc82efa NR |
1664 | MODULE_LICENSE("GPL v2"); |
1665 | MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique"); |