[mirror_ubuntu-bionic-kernel.git] / drivers / crypto / bfin_crc.h

/*
 * bfin_crc.h - interface to Blackfin CRC controllers
 *
 * Copyright 2012 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef __BFIN_CRC_H__
#define __BFIN_CRC_H__

/* Function driver which use hardware crc must initialize the structure */
struct crc_info {
	/* Input data address */
	unsigned char *in_addr;
	/* Output data address */
	unsigned char *out_addr;
	/* Input or output bytes */
	unsigned long datasize;
	union {
	/* CRC to compare with that of input buffer */
	unsigned long crc_compare;
	/* Value to compare with input data */
	unsigned long val_verify;
	/* Value to fill */
	unsigned long val_fill;
	};
	/* Value to program the 32b CRC Polynomial */
	unsigned long crc_poly;
	union {
	/* CRC calculated from the input data */
	unsigned long crc_result;
	/* First failed position to verify input data */
	unsigned long pos_verify;
	};
	/* CRC mirror flags */
	unsigned int bitmirr:1;
	unsigned int bytmirr:1;
	unsigned int w16swp:1;
	unsigned int fdsel:1;
	unsigned int rsltmirr:1;
	unsigned int polymirr:1;
	unsigned int cmpmirr:1;
};

/* Userspace interface */
#define CRC_IOC_MAGIC		'C'
#define CRC_IOC_CALC_CRC	_IOWR('C', 0x01, unsigned int)
#define CRC_IOC_MEMCPY_CRC	_IOWR('C', 0x02, unsigned int)
#define CRC_IOC_VERIFY_VAL	_IOWR('C', 0x03, unsigned int)
#define CRC_IOC_FILL_VAL	_IOWR('C', 0x04, unsigned int)


#ifdef __KERNEL__

#include <linux/types.h>
#include <linux/spinlock.h>

struct crc_register {
	u32 control;
	u32 datacnt;
	u32 datacntrld;
	u32 __pad_1[2];
	u32 compare;
	u32 fillval;
	u32 datafifo;
	u32 intren;
	u32 intrenset;
	u32 intrenclr;
	u32 poly;
	u32 __pad_2[4];
	u32 status;
	u32 datacntcap;
	u32 __pad_3;
	u32 result;
	u32 curresult;
	u32 __pad_4[3];
	u32 revid;
};

/* CRC_STATUS Masks */
#define CMPERR			0x00000002	/* Compare error */
#define DCNTEXP			0x00000010	/* datacnt register expired */
#define IBR			0x00010000	/* Input buffer ready */
#define OBR			0x00020000	/* Output buffer ready */
#define IRR			0x00040000	/* Immediate result readt */
#define LUTDONE			0x00080000	/* Look-up table generation done */
#define FSTAT			0x00700000	/* FIFO status */
#define MAX_FIFO		4		/* Max fifo size */

/* CRC_CONTROL Masks */
#define BLKEN			0x00000001	/* Block enable */
#define OPMODE			0x000000F0	/* Operation mode */
#define OPMODE_OFFSET		4		/* Operation mode mask offset*/
#define MODE_DMACPY_CRC		1		/* MTM CRC compute and compare */
#define MODE_DATA_FILL		2		/* MTM data fill */
#define MODE_CALC_CRC		3		/* MSM CRC compute and compare */
#define MODE_DATA_VERIFY	4		/* MSM data verify */
#define AUTOCLRZ		0x00000100	/* Auto clear to zero */
#define AUTOCLRF		0x00000200	/* Auto clear to one */
#define OBRSTALL		0x00001000	/* Stall on output buffer ready */
#define IRRSTALL		0x00002000	/* Stall on immediate result ready */
#define BITMIRR			0x00010000	/* Mirror bits within each byte of 32-bit input data */
#define BITMIRR_OFFSET		16		/* Mirror bits offset */
#define BYTMIRR			0x00020000	/* Mirror bytes of 32-bit input data */
#define BYTMIRR_OFFSET		17		/* Mirror bytes offset */
#define W16SWP			0x00040000	/* Mirror uppper and lower 16-bit word of 32-bit input data */
#define W16SWP_OFFSET		18		/* Mirror 16-bit word offset */
#define FDSEL			0x00080000	/* FIFO is written after input data is mirrored */
#define FDSEL_OFFSET		19		/* Mirror FIFO offset */
#define RSLTMIRR		0x00100000	/* CRC result registers are mirrored. */
#define RSLTMIRR_OFFSET		20		/* Mirror CRC result offset. */
#define POLYMIRR		0x00200000	/* CRC poly register is mirrored. */
#define POLYMIRR_OFFSET		21		/* Mirror CRC poly offset. */
#define CMPMIRR			0x00400000	/* CRC compare register is mirrored. */
#define CMPMIRR_OFFSET		22		/* Mirror CRC compare offset. */

/* CRC_INTREN Masks */
#define CMPERRI 		0x02		/* CRC_ERROR_INTR */
#define DCNTEXPI 		0x10		/* CRC_STATUS_INTR */

#endif

#endif
Commit	Line	Data
7967ba01 SZ	1	/*
	2	* bfin_crc.h - interface to Blackfin CRC controllers
	3	*
	4	* Copyright 2012 Analog Devices Inc.
	5	*
	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	#ifndef __BFIN_CRC_H__
	10	#define __BFIN_CRC_H__
	11
	12	/* Function driver which use hardware crc must initialize the structure */
	13	struct crc_info {
	14	/* Input data address */
	15	unsigned char *in_addr;
	16	/* Output data address */
	17	unsigned char *out_addr;
	18	/* Input or output bytes */
	19	unsigned long datasize;
	20	union {
	21	/* CRC to compare with that of input buffer */
	22	unsigned long crc_compare;
	23	/* Value to compare with input data */
	24	unsigned long val_verify;
	25	/* Value to fill */
	26	unsigned long val_fill;
	27	};
	28	/* Value to program the 32b CRC Polynomial */
	29	unsigned long crc_poly;
	30	union {
	31	/* CRC calculated from the input data */
	32	unsigned long crc_result;
	33	/* First failed position to verify input data */
	34	unsigned long pos_verify;
	35	};
	36	/* CRC mirror flags */
	37	unsigned int bitmirr:1;
	38	unsigned int bytmirr:1;
	39	unsigned int w16swp:1;
	40	unsigned int fdsel:1;
	41	unsigned int rsltmirr:1;
	42	unsigned int polymirr:1;
	43	unsigned int cmpmirr:1;
	44	};
	45
	46	/* Userspace interface */
	47	#define CRC_IOC_MAGIC 'C'
	48	#define CRC_IOC_CALC_CRC _IOWR('C', 0x01, unsigned int)
	49	#define CRC_IOC_MEMCPY_CRC _IOWR('C', 0x02, unsigned int)
	50	#define CRC_IOC_VERIFY_VAL _IOWR('C', 0x03, unsigned int)
	51	#define CRC_IOC_FILL_VAL _IOWR('C', 0x04, unsigned int)
	52
	53
	54	#ifdef __KERNEL__
	55
	56	#include <linux/types.h>
	57	#include <linux/spinlock.h>
7967ba01 SZ	58
	59	struct crc_register {
	60	u32 control;
	61	u32 datacnt;
	62	u32 datacntrld;
	63	u32 __pad_1[2];
	64	u32 compare;
	65	u32 fillval;
	66	u32 datafifo;
	67	u32 intren;
	68	u32 intrenset;
	69	u32 intrenclr;
	70	u32 poly;
	71	u32 __pad_2[4];
	72	u32 status;
	73	u32 datacntcap;
	74	u32 __pad_3;
	75	u32 result;
	76	u32 curresult;
	77	u32 __pad_4[3];
	78	u32 revid;
	79	};
	80
7967ba01 SZ	81	/* CRC_STATUS Masks */
	82	#define CMPERR 0x00000002 /* Compare error */
	83	#define DCNTEXP 0x00000010 /* datacnt register expired */
	84	#define IBR 0x00010000 /* Input buffer ready */
	85	#define OBR 0x00020000 /* Output buffer ready */
	86	#define IRR 0x00040000 /* Immediate result readt */
	87	#define LUTDONE 0x00080000 /* Look-up table generation done */
	88	#define FSTAT 0x00700000 /* FIFO status */
	89	#define MAX_FIFO 4 /* Max fifo size */
	90
	91	/* CRC_CONTROL Masks */
	92	#define BLKEN 0x00000001 /* Block enable */
	93	#define OPMODE 0x000000F0 /* Operation mode */
	94	#define OPMODE_OFFSET 4 /* Operation mode mask offset*/
	95	#define MODE_DMACPY_CRC 1 /* MTM CRC compute and compare */
	96	#define MODE_DATA_FILL 2 /* MTM data fill */
	97	#define MODE_CALC_CRC 3 /* MSM CRC compute and compare */
	98	#define MODE_DATA_VERIFY 4 /* MSM data verify */
	99	#define AUTOCLRZ 0x00000100 /* Auto clear to zero */
	100	#define AUTOCLRF 0x00000200 /* Auto clear to one */
	101	#define OBRSTALL 0x00001000 /* Stall on output buffer ready */
	102	#define IRRSTALL 0x00002000 /* Stall on immediate result ready */
	103	#define BITMIRR 0x00010000 /* Mirror bits within each byte of 32-bit input data */
	104	#define BITMIRR_OFFSET 16 /* Mirror bits offset */
	105	#define BYTMIRR 0x00020000 /* Mirror bytes of 32-bit input data */
	106	#define BYTMIRR_OFFSET 17 /* Mirror bytes offset */
	107	#define W16SWP 0x00040000 /* Mirror uppper and lower 16-bit word of 32-bit input data */
	108	#define W16SWP_OFFSET 18 /* Mirror 16-bit word offset */
	109	#define FDSEL 0x00080000 /* FIFO is written after input data is mirrored */
	110	#define FDSEL_OFFSET 19 /* Mirror FIFO offset */
	111	#define RSLTMIRR 0x00100000 /* CRC result registers are mirrored. */
	112	#define RSLTMIRR_OFFSET 20 /* Mirror CRC result offset. */
	113	#define POLYMIRR 0x00200000 /* CRC poly register is mirrored. */
	114	#define POLYMIRR_OFFSET 21 /* Mirror CRC poly offset. */
	115	#define CMPMIRR 0x00400000 /* CRC compare register is mirrored. */
	116	#define CMPMIRR_OFFSET 22 /* Mirror CRC compare offset. */
	117
	118	/* CRC_INTREN Masks */
	119	#define CMPERRI 0x02 /* CRC_ERROR_INTR */
	120	#define DCNTEXPI 0x10 /* CRC_STATUS_INTR */
	121
	122	#endif
	123
	124	#endif