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Commit | Line | Data |
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fb4562b2 | 1 | /* * CAAM control-plane driver backend |
8e8ec596 KP |
2 | * Controller-level driver, kernel property detection, initialization |
3 | * | |
281922a1 | 4 | * Copyright 2008-2012 Freescale Semiconductor, Inc. |
8e8ec596 KP |
5 | */ |
6 | ||
4776d381 | 7 | #include <linux/device.h> |
5af50730 RH |
8 | #include <linux/of_address.h> |
9 | #include <linux/of_irq.h> | |
10 | ||
8e8ec596 KP |
11 | #include "compat.h" |
12 | #include "regs.h" | |
13 | #include "intern.h" | |
14 | #include "jr.h" | |
281922a1 KP |
15 | #include "desc_constr.h" |
16 | #include "error.h" | |
1ac6b731 | 17 | #include "ctrl.h" |
8e8ec596 | 18 | |
261ea058 HG |
19 | bool caam_little_end; |
20 | EXPORT_SYMBOL(caam_little_end); | |
21 | ||
24821c46 | 22 | /* |
6c3af955 | 23 | * i.MX targets tend to have clock control subsystems that can |
24821c46 VM |
24 | * enable/disable clocking to our device. |
25 | */ | |
6c3af955 | 26 | #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX |
24821c46 VM |
27 | static inline struct clk *caam_drv_identify_clk(struct device *dev, |
28 | char *clk_name) | |
29 | { | |
30 | return devm_clk_get(dev, clk_name); | |
31 | } | |
32 | #else | |
33 | static inline struct clk *caam_drv_identify_clk(struct device *dev, | |
34 | char *clk_name) | |
35 | { | |
36 | return NULL; | |
37 | } | |
38 | #endif | |
39 | ||
281922a1 KP |
40 | /* |
41 | * Descriptor to instantiate RNG State Handle 0 in normal mode and | |
42 | * load the JDKEK, TDKEK and TDSK registers | |
43 | */ | |
1005bccd | 44 | static void build_instantiation_desc(u32 *desc, int handle, int do_sk) |
281922a1 | 45 | { |
1005bccd | 46 | u32 *jump_cmd, op_flags; |
281922a1 KP |
47 | |
48 | init_job_desc(desc, 0); | |
49 | ||
1005bccd AP |
50 | op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | |
51 | (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; | |
52 | ||
281922a1 | 53 | /* INIT RNG in non-test mode */ |
1005bccd | 54 | append_operation(desc, op_flags); |
281922a1 | 55 | |
1005bccd AP |
56 | if (!handle && do_sk) { |
57 | /* | |
58 | * For SH0, Secure Keys must be generated as well | |
59 | */ | |
281922a1 | 60 | |
1005bccd AP |
61 | /* wait for done */ |
62 | jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); | |
63 | set_jump_tgt_here(desc, jump_cmd); | |
281922a1 | 64 | |
1005bccd AP |
65 | /* |
66 | * load 1 to clear written reg: | |
67 | * resets the done interrrupt and returns the RNG to idle. | |
68 | */ | |
69 | append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); | |
70 | ||
71 | /* Initialize State Handle */ | |
72 | append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | | |
73 | OP_ALG_AAI_RNG4_SK); | |
74 | } | |
281922a1 | 75 | |
d5e4e999 | 76 | append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); |
281922a1 | 77 | } |
281922a1 | 78 | |
b1f996e0 | 79 | /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */ |
1005bccd | 80 | static void build_deinstantiation_desc(u32 *desc, int handle) |
b1f996e0 AP |
81 | { |
82 | init_job_desc(desc, 0); | |
281922a1 | 83 | |
b1f996e0 | 84 | /* Uninstantiate State Handle 0 */ |
281922a1 | 85 | append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | |
1005bccd | 86 | (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL); |
b1f996e0 AP |
87 | |
88 | append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); | |
281922a1 KP |
89 | } |
90 | ||
04cddbfe AP |
91 | /* |
92 | * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of | |
93 | * the software (no JR/QI used). | |
94 | * @ctrldev - pointer to device | |
1005bccd AP |
95 | * @status - descriptor status, after being run |
96 | * | |
04cddbfe AP |
97 | * Return: - 0 if no error occurred |
98 | * - -ENODEV if the DECO couldn't be acquired | |
99 | * - -EAGAIN if an error occurred while executing the descriptor | |
100 | */ | |
1005bccd AP |
101 | static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, |
102 | u32 *status) | |
281922a1 | 103 | { |
997ad290 | 104 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); |
fb4562b2 NNL |
105 | struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; |
106 | struct caam_deco __iomem *deco = ctrlpriv->deco; | |
997ad290 | 107 | unsigned int timeout = 100000; |
04cddbfe | 108 | u32 deco_dbg_reg, flags; |
b1f996e0 | 109 | int i; |
997ad290 | 110 | |
17157c90 | 111 | |
8f1da7b9 | 112 | if (ctrlpriv->virt_en == 1) { |
261ea058 | 113 | clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); |
17157c90 | 114 | |
fb4562b2 | 115 | while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && |
8f1da7b9 HG |
116 | --timeout) |
117 | cpu_relax(); | |
118 | ||
119 | timeout = 100000; | |
120 | } | |
17157c90 | 121 | |
261ea058 | 122 | clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE); |
997ad290 | 123 | |
fb4562b2 | 124 | while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && |
997ad290 RG |
125 | --timeout) |
126 | cpu_relax(); | |
127 | ||
128 | if (!timeout) { | |
129 | dev_err(ctrldev, "failed to acquire DECO 0\n"); | |
261ea058 | 130 | clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); |
04cddbfe | 131 | return -ENODEV; |
281922a1 KP |
132 | } |
133 | ||
997ad290 | 134 | for (i = 0; i < desc_len(desc); i++) |
261ea058 | 135 | wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i))); |
281922a1 | 136 | |
04cddbfe AP |
137 | flags = DECO_JQCR_WHL; |
138 | /* | |
139 | * If the descriptor length is longer than 4 words, then the | |
140 | * FOUR bit in JRCTRL register must be set. | |
141 | */ | |
142 | if (desc_len(desc) >= 4) | |
143 | flags |= DECO_JQCR_FOUR; | |
144 | ||
145 | /* Instruct the DECO to execute it */ | |
261ea058 | 146 | clrsetbits_32(&deco->jr_ctl_hi, 0, flags); |
997ad290 RG |
147 | |
148 | timeout = 10000000; | |
84cf4827 | 149 | do { |
fb4562b2 | 150 | deco_dbg_reg = rd_reg32(&deco->desc_dbg); |
84cf4827 AP |
151 | /* |
152 | * If an error occured in the descriptor, then | |
153 | * the DECO status field will be set to 0x0D | |
154 | */ | |
155 | if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) == | |
156 | DESC_DBG_DECO_STAT_HOST_ERR) | |
157 | break; | |
997ad290 | 158 | cpu_relax(); |
84cf4827 | 159 | } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); |
281922a1 | 160 | |
fb4562b2 | 161 | *status = rd_reg32(&deco->op_status_hi) & |
1005bccd | 162 | DECO_OP_STATUS_HI_ERR_MASK; |
997ad290 | 163 | |
17157c90 | 164 | if (ctrlpriv->virt_en == 1) |
261ea058 | 165 | clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0); |
17157c90 | 166 | |
04cddbfe | 167 | /* Mark the DECO as free */ |
261ea058 | 168 | clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); |
04cddbfe AP |
169 | |
170 | if (!timeout) | |
171 | return -EAGAIN; | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | /* | |
177 | * instantiate_rng - builds and executes a descriptor on DECO0, | |
178 | * which initializes the RNG block. | |
179 | * @ctrldev - pointer to device | |
1005bccd AP |
180 | * @state_handle_mask - bitmask containing the instantiation status |
181 | * for the RNG4 state handles which exist in | |
182 | * the RNG4 block: 1 if it's been instantiated | |
183 | * by an external entry, 0 otherwise. | |
184 | * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK; | |
185 | * Caution: this can be done only once; if the keys need to be | |
186 | * regenerated, a POR is required | |
187 | * | |
04cddbfe AP |
188 | * Return: - 0 if no error occurred |
189 | * - -ENOMEM if there isn't enough memory to allocate the descriptor | |
190 | * - -ENODEV if DECO0 couldn't be acquired | |
191 | * - -EAGAIN if an error occurred when executing the descriptor | |
192 | * f.i. there was a RNG hardware error due to not "good enough" | |
193 | * entropy being aquired. | |
194 | */ | |
1005bccd AP |
195 | static int instantiate_rng(struct device *ctrldev, int state_handle_mask, |
196 | int gen_sk) | |
04cddbfe | 197 | { |
1005bccd | 198 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); |
fb4562b2 | 199 | struct caam_ctrl __iomem *ctrl; |
62743a41 | 200 | u32 *desc, status = 0, rdsta_val; |
1005bccd AP |
201 | int ret = 0, sh_idx; |
202 | ||
fb4562b2 | 203 | ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; |
04cddbfe AP |
204 | desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL); |
205 | if (!desc) | |
206 | return -ENOMEM; | |
04cddbfe | 207 | |
1005bccd AP |
208 | for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { |
209 | /* | |
210 | * If the corresponding bit is set, this state handle | |
211 | * was initialized by somebody else, so it's left alone. | |
212 | */ | |
213 | if ((1 << sh_idx) & state_handle_mask) | |
214 | continue; | |
215 | ||
216 | /* Create the descriptor for instantiating RNG State Handle */ | |
217 | build_instantiation_desc(desc, sh_idx, gen_sk); | |
218 | ||
219 | /* Try to run it through DECO0 */ | |
220 | ret = run_descriptor_deco0(ctrldev, desc, &status); | |
221 | ||
222 | /* | |
223 | * If ret is not 0, or descriptor status is not 0, then | |
224 | * something went wrong. No need to try the next state | |
225 | * handle (if available), bail out here. | |
226 | * Also, if for some reason, the State Handle didn't get | |
227 | * instantiated although the descriptor has finished | |
228 | * without any error (HW optimizations for later | |
229 | * CAAM eras), then try again. | |
230 | */ | |
467707b2 | 231 | rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; |
62743a41 HG |
232 | if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) || |
233 | !(rdsta_val & (1 << sh_idx))) | |
1005bccd AP |
234 | ret = -EAGAIN; |
235 | if (ret) | |
236 | break; | |
1005bccd AP |
237 | dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx); |
238 | /* Clear the contents before recreating the descriptor */ | |
239 | memset(desc, 0x00, CAAM_CMD_SZ * 7); | |
240 | } | |
04cddbfe | 241 | |
997ad290 | 242 | kfree(desc); |
04cddbfe | 243 | |
281922a1 KP |
244 | return ret; |
245 | } | |
246 | ||
247 | /* | |
b1f996e0 AP |
248 | * deinstantiate_rng - builds and executes a descriptor on DECO0, |
249 | * which deinitializes the RNG block. | |
250 | * @ctrldev - pointer to device | |
1005bccd AP |
251 | * @state_handle_mask - bitmask containing the instantiation status |
252 | * for the RNG4 state handles which exist in | |
253 | * the RNG4 block: 1 if it's been instantiated | |
b1f996e0 AP |
254 | * |
255 | * Return: - 0 if no error occurred | |
256 | * - -ENOMEM if there isn't enough memory to allocate the descriptor | |
257 | * - -ENODEV if DECO0 couldn't be acquired | |
258 | * - -EAGAIN if an error occurred when executing the descriptor | |
281922a1 | 259 | */ |
1005bccd | 260 | static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) |
b1f996e0 | 261 | { |
1005bccd AP |
262 | u32 *desc, status; |
263 | int sh_idx, ret = 0; | |
b1f996e0 AP |
264 | |
265 | desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL); | |
266 | if (!desc) | |
267 | return -ENOMEM; | |
268 | ||
1005bccd AP |
269 | for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { |
270 | /* | |
271 | * If the corresponding bit is set, then it means the state | |
272 | * handle was initialized by us, and thus it needs to be | |
273 | * deintialized as well | |
274 | */ | |
275 | if ((1 << sh_idx) & state_handle_mask) { | |
276 | /* | |
277 | * Create the descriptor for deinstantating this state | |
278 | * handle | |
279 | */ | |
280 | build_deinstantiation_desc(desc, sh_idx); | |
281 | ||
282 | /* Try to run it through DECO0 */ | |
283 | ret = run_descriptor_deco0(ctrldev, desc, &status); | |
284 | ||
285 | if (ret || status) { | |
286 | dev_err(ctrldev, | |
287 | "Failed to deinstantiate RNG4 SH%d\n", | |
288 | sh_idx); | |
289 | break; | |
290 | } | |
291 | dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx); | |
292 | } | |
293 | } | |
b1f996e0 AP |
294 | |
295 | kfree(desc); | |
296 | ||
297 | return ret; | |
298 | } | |
299 | ||
04cddbfe AP |
300 | static int caam_remove(struct platform_device *pdev) |
301 | { | |
302 | struct device *ctrldev; | |
303 | struct caam_drv_private *ctrlpriv; | |
fb4562b2 | 304 | struct caam_ctrl __iomem *ctrl; |
e558017b | 305 | int ring; |
04cddbfe AP |
306 | |
307 | ctrldev = &pdev->dev; | |
308 | ctrlpriv = dev_get_drvdata(ctrldev); | |
fb4562b2 | 309 | ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; |
04cddbfe | 310 | |
313ea293 | 311 | /* Remove platform devices for JobRs */ |
04cddbfe | 312 | for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) { |
313ea293 RG |
313 | if (ctrlpriv->jrpdev[ring]) |
314 | of_device_unregister(ctrlpriv->jrpdev[ring]); | |
04cddbfe AP |
315 | } |
316 | ||
1005bccd AP |
317 | /* De-initialize RNG state handles initialized by this driver. */ |
318 | if (ctrlpriv->rng4_sh_init) | |
319 | deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); | |
b1f996e0 | 320 | |
04cddbfe AP |
321 | /* Shut down debug views */ |
322 | #ifdef CONFIG_DEBUG_FS | |
323 | debugfs_remove_recursive(ctrlpriv->dfs_root); | |
324 | #endif | |
325 | ||
326 | /* Unmap controller region */ | |
f4ec6aa5 | 327 | iounmap(ctrl); |
04cddbfe | 328 | |
24821c46 VM |
329 | /* shut clocks off before finalizing shutdown */ |
330 | clk_disable_unprepare(ctrlpriv->caam_ipg); | |
331 | clk_disable_unprepare(ctrlpriv->caam_mem); | |
332 | clk_disable_unprepare(ctrlpriv->caam_aclk); | |
333 | clk_disable_unprepare(ctrlpriv->caam_emi_slow); | |
334 | ||
e558017b | 335 | return 0; |
281922a1 KP |
336 | } |
337 | ||
338 | /* | |
84cf4827 AP |
339 | * kick_trng - sets the various parameters for enabling the initialization |
340 | * of the RNG4 block in CAAM | |
341 | * @pdev - pointer to the platform device | |
342 | * @ent_delay - Defines the length (in system clocks) of each entropy sample. | |
281922a1 | 343 | */ |
84cf4827 | 344 | static void kick_trng(struct platform_device *pdev, int ent_delay) |
281922a1 KP |
345 | { |
346 | struct device *ctrldev = &pdev->dev; | |
347 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); | |
fb4562b2 | 348 | struct caam_ctrl __iomem *ctrl; |
281922a1 KP |
349 | struct rng4tst __iomem *r4tst; |
350 | u32 val; | |
351 | ||
fb4562b2 NNL |
352 | ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; |
353 | r4tst = &ctrl->r4tst[0]; | |
281922a1 KP |
354 | |
355 | /* put RNG4 into program mode */ | |
261ea058 | 356 | clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM); |
84cf4827 AP |
357 | |
358 | /* | |
359 | * Performance-wise, it does not make sense to | |
360 | * set the delay to a value that is lower | |
361 | * than the last one that worked (i.e. the state handles | |
362 | * were instantiated properly. Thus, instead of wasting | |
363 | * time trying to set the values controlling the sample | |
364 | * frequency, the function simply returns. | |
365 | */ | |
366 | val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) | |
367 | >> RTSDCTL_ENT_DLY_SHIFT; | |
368 | if (ent_delay <= val) { | |
369 | /* put RNG4 into run mode */ | |
261ea058 | 370 | clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, 0); |
84cf4827 AP |
371 | return; |
372 | } | |
373 | ||
281922a1 | 374 | val = rd_reg32(&r4tst->rtsdctl); |
84cf4827 AP |
375 | val = (val & ~RTSDCTL_ENT_DLY_MASK) | |
376 | (ent_delay << RTSDCTL_ENT_DLY_SHIFT); | |
281922a1 | 377 | wr_reg32(&r4tst->rtsdctl, val); |
84cf4827 AP |
378 | /* min. freq. count, equal to 1/4 of the entropy sample length */ |
379 | wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); | |
b061f3fe AP |
380 | /* disable maximum frequency count */ |
381 | wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); | |
e5ffbfc1 AP |
382 | /* read the control register */ |
383 | val = rd_reg32(&r4tst->rtmctl); | |
384 | /* | |
385 | * select raw sampling in both entropy shifter | |
386 | * and statistical checker | |
387 | */ | |
261ea058 | 388 | clrsetbits_32(&val, 0, RTMCTL_SAMP_MODE_RAW_ES_SC); |
281922a1 | 389 | /* put RNG4 into run mode */ |
261ea058 | 390 | clrsetbits_32(&val, RTMCTL_PRGM, 0); |
e5ffbfc1 AP |
391 | /* write back the control register */ |
392 | wr_reg32(&r4tst->rtmctl, val); | |
281922a1 KP |
393 | } |
394 | ||
82c2f960 AP |
395 | /** |
396 | * caam_get_era() - Return the ERA of the SEC on SoC, based | |
883619a9 | 397 | * on "sec-era" propery in the DTS. This property is updated by u-boot. |
82c2f960 | 398 | **/ |
883619a9 | 399 | int caam_get_era(void) |
82c2f960 | 400 | { |
883619a9 | 401 | struct device_node *caam_node; |
e27513eb AP |
402 | int ret; |
403 | u32 prop; | |
404 | ||
405 | caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); | |
406 | ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); | |
407 | of_node_put(caam_node); | |
82c2f960 | 408 | |
287980e4 | 409 | return ret ? -ENOTSUPP : prop; |
82c2f960 AP |
410 | } |
411 | EXPORT_SYMBOL(caam_get_era); | |
412 | ||
261ea058 HG |
413 | #ifdef CONFIG_DEBUG_FS |
414 | static int caam_debugfs_u64_get(void *data, u64 *val) | |
415 | { | |
416 | *val = caam64_to_cpu(*(u64 *)data); | |
417 | return 0; | |
418 | } | |
419 | ||
420 | static int caam_debugfs_u32_get(void *data, u64 *val) | |
421 | { | |
422 | *val = caam32_to_cpu(*(u32 *)data); | |
423 | return 0; | |
424 | } | |
425 | ||
426 | DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro, caam_debugfs_u32_get, NULL, "%llu\n"); | |
427 | DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro, caam_debugfs_u64_get, NULL, "%llu\n"); | |
428 | #endif | |
429 | ||
8e8ec596 | 430 | /* Probe routine for CAAM top (controller) level */ |
2930d497 | 431 | static int caam_probe(struct platform_device *pdev) |
8e8ec596 | 432 | { |
1005bccd | 433 | int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; |
82c2f960 | 434 | u64 caam_id; |
8e8ec596 KP |
435 | struct device *dev; |
436 | struct device_node *nprop, *np; | |
437 | struct caam_ctrl __iomem *ctrl; | |
8e8ec596 | 438 | struct caam_drv_private *ctrlpriv; |
24821c46 | 439 | struct clk *clk; |
23457bc9 KP |
440 | #ifdef CONFIG_DEBUG_FS |
441 | struct caam_perfmon *perfmon; | |
442 | #endif | |
17157c90 | 443 | u32 scfgr, comp_params; |
eb1139cd | 444 | u32 cha_vid_ls; |
fb4562b2 NNL |
445 | int pg_size; |
446 | int BLOCK_OFFSET = 0; | |
8e8ec596 | 447 | |
9c4f9733 | 448 | ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); |
8e8ec596 KP |
449 | if (!ctrlpriv) |
450 | return -ENOMEM; | |
451 | ||
452 | dev = &pdev->dev; | |
453 | dev_set_drvdata(dev, ctrlpriv); | |
454 | ctrlpriv->pdev = pdev; | |
455 | nprop = pdev->dev.of_node; | |
456 | ||
24821c46 VM |
457 | /* Enable clocking */ |
458 | clk = caam_drv_identify_clk(&pdev->dev, "ipg"); | |
459 | if (IS_ERR(clk)) { | |
460 | ret = PTR_ERR(clk); | |
461 | dev_err(&pdev->dev, | |
462 | "can't identify CAAM ipg clk: %d\n", ret); | |
a3c09550 | 463 | return ret; |
24821c46 VM |
464 | } |
465 | ctrlpriv->caam_ipg = clk; | |
466 | ||
467 | clk = caam_drv_identify_clk(&pdev->dev, "mem"); | |
468 | if (IS_ERR(clk)) { | |
469 | ret = PTR_ERR(clk); | |
470 | dev_err(&pdev->dev, | |
471 | "can't identify CAAM mem clk: %d\n", ret); | |
a3c09550 | 472 | return ret; |
24821c46 VM |
473 | } |
474 | ctrlpriv->caam_mem = clk; | |
475 | ||
476 | clk = caam_drv_identify_clk(&pdev->dev, "aclk"); | |
477 | if (IS_ERR(clk)) { | |
478 | ret = PTR_ERR(clk); | |
479 | dev_err(&pdev->dev, | |
480 | "can't identify CAAM aclk clk: %d\n", ret); | |
a3c09550 | 481 | return ret; |
24821c46 VM |
482 | } |
483 | ctrlpriv->caam_aclk = clk; | |
484 | ||
485 | clk = caam_drv_identify_clk(&pdev->dev, "emi_slow"); | |
486 | if (IS_ERR(clk)) { | |
487 | ret = PTR_ERR(clk); | |
488 | dev_err(&pdev->dev, | |
489 | "can't identify CAAM emi_slow clk: %d\n", ret); | |
a3c09550 | 490 | return ret; |
24821c46 VM |
491 | } |
492 | ctrlpriv->caam_emi_slow = clk; | |
493 | ||
494 | ret = clk_prepare_enable(ctrlpriv->caam_ipg); | |
495 | if (ret < 0) { | |
496 | dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret); | |
31f44d15 | 497 | return ret; |
24821c46 VM |
498 | } |
499 | ||
500 | ret = clk_prepare_enable(ctrlpriv->caam_mem); | |
501 | if (ret < 0) { | |
502 | dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", | |
503 | ret); | |
31f44d15 | 504 | goto disable_caam_ipg; |
24821c46 VM |
505 | } |
506 | ||
507 | ret = clk_prepare_enable(ctrlpriv->caam_aclk); | |
508 | if (ret < 0) { | |
509 | dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret); | |
31f44d15 | 510 | goto disable_caam_mem; |
24821c46 VM |
511 | } |
512 | ||
513 | ret = clk_prepare_enable(ctrlpriv->caam_emi_slow); | |
514 | if (ret < 0) { | |
515 | dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n", | |
516 | ret); | |
31f44d15 | 517 | goto disable_caam_aclk; |
24821c46 VM |
518 | } |
519 | ||
8e8ec596 KP |
520 | /* Get configuration properties from device tree */ |
521 | /* First, get register page */ | |
522 | ctrl = of_iomap(nprop, 0); | |
523 | if (ctrl == NULL) { | |
524 | dev_err(dev, "caam: of_iomap() failed\n"); | |
31f44d15 FE |
525 | ret = -ENOMEM; |
526 | goto disable_caam_emi_slow; | |
8e8ec596 | 527 | } |
261ea058 HG |
528 | |
529 | caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) & | |
530 | (CSTA_PLEND | CSTA_ALT_PLEND)); | |
531 | ||
fb4562b2 NNL |
532 | /* Finding the page size for using the CTPR_MS register */ |
533 | comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); | |
534 | pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; | |
8e8ec596 | 535 | |
fb4562b2 NNL |
536 | /* Allocating the BLOCK_OFFSET based on the supported page size on |
537 | * the platform | |
538 | */ | |
539 | if (pg_size == 0) | |
540 | BLOCK_OFFSET = PG_SIZE_4K; | |
541 | else | |
542 | BLOCK_OFFSET = PG_SIZE_64K; | |
543 | ||
544 | ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl; | |
545 | ctrlpriv->assure = (struct caam_assurance __force *) | |
546 | ((uint8_t *)ctrl + | |
547 | BLOCK_OFFSET * ASSURE_BLOCK_NUMBER | |
548 | ); | |
549 | ctrlpriv->deco = (struct caam_deco __force *) | |
550 | ((uint8_t *)ctrl + | |
551 | BLOCK_OFFSET * DECO_BLOCK_NUMBER | |
552 | ); | |
8e8ec596 KP |
553 | |
554 | /* Get the IRQ of the controller (for security violations only) */ | |
f7578496 | 555 | ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); |
8e8ec596 KP |
556 | |
557 | /* | |
558 | * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, | |
e13af18a | 559 | * long pointers in master configuration register |
8e8ec596 | 560 | */ |
509da8fd | 561 | clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH | |
624144a7 | 562 | MCFGR_AWCACHE_BUFF | MCFGR_WDENABLE | MCFGR_LARGE_BURST | |
e7a7104e | 563 | (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); |
8e8ec596 | 564 | |
17157c90 RG |
565 | /* |
566 | * Read the Compile Time paramters and SCFGR to determine | |
567 | * if Virtualization is enabled for this platform | |
568 | */ | |
fb4562b2 | 569 | scfgr = rd_reg32(&ctrl->scfgr); |
17157c90 RG |
570 | |
571 | ctrlpriv->virt_en = 0; | |
572 | if (comp_params & CTPR_MS_VIRT_EN_INCL) { | |
573 | /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or | |
574 | * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1 | |
575 | */ | |
576 | if ((comp_params & CTPR_MS_VIRT_EN_POR) || | |
577 | (!(comp_params & CTPR_MS_VIRT_EN_POR) && | |
578 | (scfgr & SCFGR_VIRT_EN))) | |
579 | ctrlpriv->virt_en = 1; | |
580 | } else { | |
581 | /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ | |
582 | if (comp_params & CTPR_MS_VIRT_EN_POR) | |
583 | ctrlpriv->virt_en = 1; | |
584 | } | |
585 | ||
586 | if (ctrlpriv->virt_en == 1) | |
261ea058 HG |
587 | clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | |
588 | JRSTART_JR1_START | JRSTART_JR2_START | | |
589 | JRSTART_JR3_START); | |
17157c90 | 590 | |
8e8ec596 | 591 | if (sizeof(dma_addr_t) == sizeof(u64)) |
e13af18a | 592 | if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) |
a2ac287e | 593 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); |
e13af18a | 594 | else |
a2ac287e | 595 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); |
e13af18a | 596 | else |
a2ac287e | 597 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
8e8ec596 | 598 | |
8e8ec596 KP |
599 | /* |
600 | * Detect and enable JobRs | |
601 | * First, find out how many ring spec'ed, allocate references | |
602 | * for all, then go probe each one. | |
603 | */ | |
604 | rspec = 0; | |
0a63b09d NL |
605 | for_each_available_child_of_node(nprop, np) |
606 | if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || | |
607 | of_device_is_compatible(np, "fsl,sec4.0-job-ring")) | |
a0ea0f6d | 608 | rspec++; |
a0ea0f6d | 609 | |
9c4f9733 FE |
610 | ctrlpriv->jrpdev = devm_kcalloc(&pdev->dev, rspec, |
611 | sizeof(*ctrlpriv->jrpdev), GFP_KERNEL); | |
313ea293 | 612 | if (ctrlpriv->jrpdev == NULL) { |
31f44d15 FE |
613 | ret = -ENOMEM; |
614 | goto iounmap_ctrl; | |
8e8ec596 KP |
615 | } |
616 | ||
617 | ring = 0; | |
618 | ctrlpriv->total_jobrs = 0; | |
0a63b09d NL |
619 | for_each_available_child_of_node(nprop, np) |
620 | if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || | |
621 | of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { | |
313ea293 RG |
622 | ctrlpriv->jrpdev[ring] = |
623 | of_platform_device_create(np, NULL, dev); | |
624 | if (!ctrlpriv->jrpdev[ring]) { | |
625 | pr_warn("JR%d Platform device creation error\n", | |
626 | ring); | |
627 | continue; | |
628 | } | |
fb4562b2 NNL |
629 | ctrlpriv->jr[ring] = (struct caam_job_ring __force *) |
630 | ((uint8_t *)ctrl + | |
631 | (ring + JR_BLOCK_NUMBER) * | |
632 | BLOCK_OFFSET | |
633 | ); | |
a0ea0f6d SL |
634 | ctrlpriv->total_jobrs++; |
635 | ring++; | |
fb4562b2 | 636 | } |
8e8ec596 KP |
637 | |
638 | /* Check to see if QI present. If so, enable */ | |
eb1139cd | 639 | ctrlpriv->qi_present = |
fb4562b2 | 640 | !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) & |
eb1139cd | 641 | CTPR_MS_QI_MASK); |
8e8ec596 | 642 | if (ctrlpriv->qi_present) { |
fb4562b2 NNL |
643 | ctrlpriv->qi = (struct caam_queue_if __force *) |
644 | ((uint8_t *)ctrl + | |
645 | BLOCK_OFFSET * QI_BLOCK_NUMBER | |
646 | ); | |
8e8ec596 | 647 | /* This is all that's required to physically enable QI */ |
fb4562b2 | 648 | wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN); |
8e8ec596 KP |
649 | } |
650 | ||
651 | /* If no QI and no rings specified, quit and go home */ | |
652 | if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { | |
653 | dev_err(dev, "no queues configured, terminating\n"); | |
31f44d15 FE |
654 | ret = -ENOMEM; |
655 | goto caam_remove; | |
8e8ec596 KP |
656 | } |
657 | ||
fb4562b2 | 658 | cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls); |
986dfbcf | 659 | |
281922a1 | 660 | /* |
986dfbcf | 661 | * If SEC has RNG version >= 4 and RNG state handle has not been |
84cf4827 | 662 | * already instantiated, do RNG instantiation |
281922a1 | 663 | */ |
eb1139cd | 664 | if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { |
1005bccd | 665 | ctrlpriv->rng4_sh_init = |
fb4562b2 | 666 | rd_reg32(&ctrl->r4tst[0].rdsta); |
1005bccd AP |
667 | /* |
668 | * If the secure keys (TDKEK, JDKEK, TDSK), were already | |
669 | * generated, signal this to the function that is instantiating | |
670 | * the state handles. An error would occur if RNG4 attempts | |
671 | * to regenerate these keys before the next POR. | |
672 | */ | |
673 | gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; | |
674 | ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; | |
84cf4827 | 675 | do { |
1005bccd | 676 | int inst_handles = |
fb4562b2 | 677 | rd_reg32(&ctrl->r4tst[0].rdsta) & |
1005bccd AP |
678 | RDSTA_IFMASK; |
679 | /* | |
680 | * If either SH were instantiated by somebody else | |
681 | * (e.g. u-boot) then it is assumed that the entropy | |
682 | * parameters are properly set and thus the function | |
683 | * setting these (kick_trng(...)) is skipped. | |
684 | * Also, if a handle was instantiated, do not change | |
685 | * the TRNG parameters. | |
686 | */ | |
687 | if (!(ctrlpriv->rng4_sh_init || inst_handles)) { | |
eeaa1724 AP |
688 | dev_info(dev, |
689 | "Entropy delay = %u\n", | |
690 | ent_delay); | |
1005bccd AP |
691 | kick_trng(pdev, ent_delay); |
692 | ent_delay += 400; | |
693 | } | |
694 | /* | |
695 | * if instantiate_rng(...) fails, the loop will rerun | |
696 | * and the kick_trng(...) function will modfiy the | |
697 | * upper and lower limits of the entropy sampling | |
698 | * interval, leading to a sucessful initialization of | |
699 | * the RNG. | |
700 | */ | |
701 | ret = instantiate_rng(dev, inst_handles, | |
702 | gen_sk); | |
eeaa1724 AP |
703 | if (ret == -EAGAIN) |
704 | /* | |
705 | * if here, the loop will rerun, | |
706 | * so don't hog the CPU | |
707 | */ | |
708 | cpu_relax(); | |
04cddbfe | 709 | } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); |
281922a1 | 710 | if (ret) { |
84cf4827 | 711 | dev_err(dev, "failed to instantiate RNG"); |
31f44d15 | 712 | goto caam_remove; |
281922a1 | 713 | } |
1005bccd AP |
714 | /* |
715 | * Set handles init'ed by this module as the complement of the | |
716 | * already initialized ones | |
717 | */ | |
718 | ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; | |
575c1bd5 VG |
719 | |
720 | /* Enable RDB bit so that RNG works faster */ | |
261ea058 | 721 | clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); |
281922a1 KP |
722 | } |
723 | ||
8e8ec596 KP |
724 | /* NOTE: RTIC detection ought to go here, around Si time */ |
725 | ||
fb4562b2 NNL |
726 | caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | |
727 | (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); | |
82c2f960 | 728 | |
8e8ec596 | 729 | /* Report "alive" for developer to see */ |
82c2f960 | 730 | dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, |
883619a9 | 731 | caam_get_era()); |
8e8ec596 KP |
732 | dev_info(dev, "job rings = %d, qi = %d\n", |
733 | ctrlpriv->total_jobrs, ctrlpriv->qi_present); | |
734 | ||
735 | #ifdef CONFIG_DEBUG_FS | |
736 | /* | |
737 | * FIXME: needs better naming distinction, as some amalgamation of | |
738 | * "caam" and nprop->full_name. The OF name isn't distinctive, | |
739 | * but does separate instances | |
740 | */ | |
741 | perfmon = (struct caam_perfmon __force *)&ctrl->perfmon; | |
742 | ||
178f827a | 743 | ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL); |
8e8ec596 KP |
744 | ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root); |
745 | ||
746 | /* Controller-level - performance monitor counters */ | |
261ea058 | 747 | |
8e8ec596 | 748 | ctrlpriv->ctl_rq_dequeued = |
261ea058 HG |
749 | debugfs_create_file("rq_dequeued", |
750 | S_IRUSR | S_IRGRP | S_IROTH, | |
751 | ctrlpriv->ctl, &perfmon->req_dequeued, | |
752 | &caam_fops_u64_ro); | |
8e8ec596 | 753 | ctrlpriv->ctl_ob_enc_req = |
261ea058 HG |
754 | debugfs_create_file("ob_rq_encrypted", |
755 | S_IRUSR | S_IRGRP | S_IROTH, | |
756 | ctrlpriv->ctl, &perfmon->ob_enc_req, | |
757 | &caam_fops_u64_ro); | |
8e8ec596 | 758 | ctrlpriv->ctl_ib_dec_req = |
261ea058 HG |
759 | debugfs_create_file("ib_rq_decrypted", |
760 | S_IRUSR | S_IRGRP | S_IROTH, | |
761 | ctrlpriv->ctl, &perfmon->ib_dec_req, | |
762 | &caam_fops_u64_ro); | |
8e8ec596 | 763 | ctrlpriv->ctl_ob_enc_bytes = |
261ea058 HG |
764 | debugfs_create_file("ob_bytes_encrypted", |
765 | S_IRUSR | S_IRGRP | S_IROTH, | |
766 | ctrlpriv->ctl, &perfmon->ob_enc_bytes, | |
767 | &caam_fops_u64_ro); | |
8e8ec596 | 768 | ctrlpriv->ctl_ob_prot_bytes = |
261ea058 HG |
769 | debugfs_create_file("ob_bytes_protected", |
770 | S_IRUSR | S_IRGRP | S_IROTH, | |
771 | ctrlpriv->ctl, &perfmon->ob_prot_bytes, | |
772 | &caam_fops_u64_ro); | |
8e8ec596 | 773 | ctrlpriv->ctl_ib_dec_bytes = |
261ea058 HG |
774 | debugfs_create_file("ib_bytes_decrypted", |
775 | S_IRUSR | S_IRGRP | S_IROTH, | |
776 | ctrlpriv->ctl, &perfmon->ib_dec_bytes, | |
777 | &caam_fops_u64_ro); | |
8e8ec596 | 778 | ctrlpriv->ctl_ib_valid_bytes = |
261ea058 HG |
779 | debugfs_create_file("ib_bytes_validated", |
780 | S_IRUSR | S_IRGRP | S_IROTH, | |
781 | ctrlpriv->ctl, &perfmon->ib_valid_bytes, | |
782 | &caam_fops_u64_ro); | |
8e8ec596 KP |
783 | |
784 | /* Controller level - global status values */ | |
785 | ctrlpriv->ctl_faultaddr = | |
261ea058 HG |
786 | debugfs_create_file("fault_addr", |
787 | S_IRUSR | S_IRGRP | S_IROTH, | |
788 | ctrlpriv->ctl, &perfmon->faultaddr, | |
789 | &caam_fops_u32_ro); | |
8e8ec596 | 790 | ctrlpriv->ctl_faultdetail = |
261ea058 HG |
791 | debugfs_create_file("fault_detail", |
792 | S_IRUSR | S_IRGRP | S_IROTH, | |
793 | ctrlpriv->ctl, &perfmon->faultdetail, | |
794 | &caam_fops_u32_ro); | |
8e8ec596 | 795 | ctrlpriv->ctl_faultstatus = |
261ea058 HG |
796 | debugfs_create_file("fault_status", |
797 | S_IRUSR | S_IRGRP | S_IROTH, | |
798 | ctrlpriv->ctl, &perfmon->status, | |
799 | &caam_fops_u32_ro); | |
8e8ec596 KP |
800 | |
801 | /* Internal covering keys (useful in non-secure mode only) */ | |
802 | ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0]; | |
803 | ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); | |
804 | ctrlpriv->ctl_kek = debugfs_create_blob("kek", | |
eda65cc6 | 805 | S_IRUSR | |
8e8ec596 KP |
806 | S_IRGRP | S_IROTH, |
807 | ctrlpriv->ctl, | |
808 | &ctrlpriv->ctl_kek_wrap); | |
809 | ||
810 | ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0]; | |
811 | ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32); | |
812 | ctrlpriv->ctl_tkek = debugfs_create_blob("tkek", | |
eda65cc6 | 813 | S_IRUSR | |
8e8ec596 KP |
814 | S_IRGRP | S_IROTH, |
815 | ctrlpriv->ctl, | |
816 | &ctrlpriv->ctl_tkek_wrap); | |
817 | ||
818 | ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0]; | |
819 | ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32); | |
820 | ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk", | |
eda65cc6 | 821 | S_IRUSR | |
8e8ec596 KP |
822 | S_IRGRP | S_IROTH, |
823 | ctrlpriv->ctl, | |
824 | &ctrlpriv->ctl_tdsk_wrap); | |
825 | #endif | |
826 | return 0; | |
31f44d15 FE |
827 | |
828 | caam_remove: | |
829 | caam_remove(pdev); | |
bdc67da7 RK |
830 | return ret; |
831 | ||
31f44d15 FE |
832 | iounmap_ctrl: |
833 | iounmap(ctrl); | |
834 | disable_caam_emi_slow: | |
835 | clk_disable_unprepare(ctrlpriv->caam_emi_slow); | |
836 | disable_caam_aclk: | |
837 | clk_disable_unprepare(ctrlpriv->caam_aclk); | |
838 | disable_caam_mem: | |
839 | clk_disable_unprepare(ctrlpriv->caam_mem); | |
840 | disable_caam_ipg: | |
841 | clk_disable_unprepare(ctrlpriv->caam_ipg); | |
842 | return ret; | |
8e8ec596 KP |
843 | } |
844 | ||
845 | static struct of_device_id caam_match[] = { | |
846 | { | |
54e198d4 | 847 | .compatible = "fsl,sec-v4.0", |
8e8ec596 | 848 | }, |
a0ea0f6d SL |
849 | { |
850 | .compatible = "fsl,sec4.0", | |
851 | }, | |
8e8ec596 KP |
852 | {}, |
853 | }; | |
854 | MODULE_DEVICE_TABLE(of, caam_match); | |
855 | ||
2930d497 | 856 | static struct platform_driver caam_driver = { |
8e8ec596 KP |
857 | .driver = { |
858 | .name = "caam", | |
8e8ec596 KP |
859 | .of_match_table = caam_match, |
860 | }, | |
861 | .probe = caam_probe, | |
49cfe4db | 862 | .remove = caam_remove, |
8e8ec596 KP |
863 | }; |
864 | ||
741e8c2d | 865 | module_platform_driver(caam_driver); |
8e8ec596 KP |
866 | |
867 | MODULE_LICENSE("GPL"); | |
868 | MODULE_DESCRIPTION("FSL CAAM request backend"); | |
869 | MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); |