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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
8e8ec596 KP |
2 | /* |
3 | * CAAM hardware register-level view | |
4 | * | |
5 | * Copyright 2008-2011 Freescale Semiconductor, Inc. | |
d239b10d | 6 | * Copyright 2018 NXP |
8e8ec596 KP |
7 | */ |
8 | ||
9 | #ifndef REGS_H | |
10 | #define REGS_H | |
11 | ||
12 | #include <linux/types.h> | |
261ea058 | 13 | #include <linux/bitops.h> |
8e8ec596 KP |
14 | #include <linux/io.h> |
15 | ||
16 | /* | |
17 | * Architecture-specific register access methods | |
18 | * | |
19 | * CAAM's bus-addressable registers are 64 bits internally. | |
20 | * They have been wired to be safely accessible on 32-bit | |
21 | * architectures, however. Registers were organized such | |
22 | * that (a) they can be contained in 32 bits, (b) if not, then they | |
23 | * can be treated as two 32-bit entities, or finally (c) if they | |
24 | * must be treated as a single 64-bit value, then this can safely | |
25 | * be done with two 32-bit cycles. | |
26 | * | |
27 | * For 32-bit operations on 64-bit values, CAAM follows the same | |
28 | * 64-bit register access conventions as it's predecessors, in that | |
29 | * writes are "triggered" by a write to the register at the numerically | |
30 | * higher address, thus, a full 64-bit write cycle requires a write | |
31 | * to the lower address, followed by a write to the higher address, | |
32 | * which will latch/execute the write cycle. | |
33 | * | |
34 | * For example, let's assume a SW reset of CAAM through the master | |
35 | * configuration register. | |
36 | * - SWRST is in bit 31 of MCFG. | |
37 | * - MCFG begins at base+0x0000. | |
38 | * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower) | |
39 | * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher) | |
40 | * | |
41 | * (and on Power, the convention is 0-31, 32-63, I know...) | |
42 | * | |
43 | * Assuming a 64-bit write to this MCFG to perform a software reset | |
44 | * would then require a write of 0 to base+0x0000, followed by a | |
45 | * write of 0x80000000 to base+0x0004, which would "execute" the | |
46 | * reset. | |
47 | * | |
48 | * Of course, since MCFG 63-32 is all zero, we could cheat and simply | |
49 | * write 0x8000000 to base+0x0004, and the reset would work fine. | |
50 | * However, since CAAM does contain some write-and-read-intended | |
51 | * 64-bit registers, this code defines 64-bit access methods for | |
52 | * the sake of internal consistency and simplicity, and so that a | |
53 | * clean transition to 64-bit is possible when it becomes necessary. | |
54 | * | |
55 | * There are limitations to this that the developer must recognize. | |
56 | * 32-bit architectures cannot enforce an atomic-64 operation, | |
57 | * Therefore: | |
58 | * | |
59 | * - On writes, since the HW is assumed to latch the cycle on the | |
60 | * write of the higher-numeric-address word, then ordered | |
61 | * writes work OK. | |
62 | * | |
63 | * - For reads, where a register contains a relevant value of more | |
64 | * that 32 bits, the hardware employs logic to latch the other | |
65 | * "half" of the data until read, ensuring an accurate value. | |
66 | * This is of particular relevance when dealing with CAAM's | |
67 | * performance counters. | |
68 | * | |
69 | */ | |
70 | ||
261ea058 | 71 | extern bool caam_little_end; |
c056d910 | 72 | extern bool caam_imx; |
509da8fd | 73 | |
aae733a3 HG |
74 | #define caam_to_cpu(len) \ |
75 | static inline u##len caam##len ## _to_cpu(u##len val) \ | |
76 | { \ | |
77 | if (caam_little_end) \ | |
78 | return le##len ## _to_cpu((__force __le##len)val); \ | |
79 | else \ | |
80 | return be##len ## _to_cpu((__force __be##len)val); \ | |
261ea058 | 81 | } |
509da8fd | 82 | |
aae733a3 HG |
83 | #define cpu_to_caam(len) \ |
84 | static inline u##len cpu_to_caam##len(u##len val) \ | |
85 | { \ | |
86 | if (caam_little_end) \ | |
87 | return (__force u##len)cpu_to_le##len(val); \ | |
88 | else \ | |
89 | return (__force u##len)cpu_to_be##len(val); \ | |
261ea058 | 90 | } |
509da8fd | 91 | |
261ea058 HG |
92 | caam_to_cpu(16) |
93 | caam_to_cpu(32) | |
94 | caam_to_cpu(64) | |
95 | cpu_to_caam(16) | |
96 | cpu_to_caam(32) | |
97 | cpu_to_caam(64) | |
509da8fd | 98 | |
261ea058 HG |
99 | static inline void wr_reg32(void __iomem *reg, u32 data) |
100 | { | |
101 | if (caam_little_end) | |
102 | iowrite32(data, reg); | |
103 | else | |
104 | iowrite32be(data, reg); | |
105 | } | |
509da8fd | 106 | |
261ea058 HG |
107 | static inline u32 rd_reg32(void __iomem *reg) |
108 | { | |
109 | if (caam_little_end) | |
110 | return ioread32(reg); | |
509da8fd | 111 | |
261ea058 HG |
112 | return ioread32be(reg); |
113 | } | |
114 | ||
115 | static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set) | |
116 | { | |
117 | if (caam_little_end) | |
118 | iowrite32((ioread32(reg) & ~clear) | set, reg); | |
119 | else | |
120 | iowrite32be((ioread32be(reg) & ~clear) | set, reg); | |
121 | } | |
8e8ec596 | 122 | |
f657f82c ST |
123 | /* |
124 | * The only users of these wr/rd_reg64 functions is the Job Ring (JR). | |
6c3af955 HG |
125 | * The DMA address registers in the JR are handled differently depending on |
126 | * platform: | |
127 | * | |
128 | * 1. All BE CAAM platforms and i.MX platforms (LE CAAM): | |
f657f82c ST |
129 | * |
130 | * base + 0x0000 : most-significant 32 bits | |
131 | * base + 0x0004 : least-significant 32 bits | |
132 | * | |
133 | * The 32-bit version of this core therefore has to write to base + 0x0004 | |
6c3af955 HG |
134 | * to set the 32-bit wide DMA address. |
135 | * | |
136 | * 2. All other LE CAAM platforms (LS1021A etc.) | |
137 | * base + 0x0000 : least-significant 32 bits | |
138 | * base + 0x0004 : most-significant 32 bits | |
f657f82c | 139 | */ |
261ea058 HG |
140 | #ifdef CONFIG_64BIT |
141 | static inline void wr_reg64(void __iomem *reg, u64 data) | |
142 | { | |
143 | if (caam_little_end) | |
144 | iowrite64(data, reg); | |
145 | else | |
146 | iowrite64be(data, reg); | |
147 | } | |
f657f82c | 148 | |
261ea058 | 149 | static inline u64 rd_reg64(void __iomem *reg) |
ef94b1d8 | 150 | { |
261ea058 HG |
151 | if (caam_little_end) |
152 | return ioread64(reg); | |
153 | else | |
154 | return ioread64be(reg); | |
ef94b1d8 RG |
155 | } |
156 | ||
261ea058 HG |
157 | #else /* CONFIG_64BIT */ |
158 | static inline void wr_reg64(void __iomem *reg, u64 data) | |
ef94b1d8 | 159 | { |
c056d910 | 160 | if (!caam_imx && caam_little_end) { |
261ea058 HG |
161 | wr_reg32((u32 __iomem *)(reg) + 1, data >> 32); |
162 | wr_reg32((u32 __iomem *)(reg), data); | |
c056d910 | 163 | } else { |
261ea058 HG |
164 | wr_reg32((u32 __iomem *)(reg), data >> 32); |
165 | wr_reg32((u32 __iomem *)(reg) + 1, data); | |
166 | } | |
ef94b1d8 | 167 | } |
261ea058 HG |
168 | |
169 | static inline u64 rd_reg64(void __iomem *reg) | |
170 | { | |
c056d910 | 171 | if (!caam_imx && caam_little_end) |
261ea058 HG |
172 | return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 | |
173 | (u64)rd_reg32((u32 __iomem *)(reg))); | |
c056d910 HG |
174 | |
175 | return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 | | |
176 | (u64)rd_reg32((u32 __iomem *)(reg) + 1)); | |
261ea058 HG |
177 | } |
178 | #endif /* CONFIG_64BIT */ | |
179 | ||
c056d910 HG |
180 | static inline u64 cpu_to_caam_dma64(dma_addr_t value) |
181 | { | |
182 | if (caam_imx) | |
183 | return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | | |
184 | (u64)cpu_to_caam32(upper_32_bits(value))); | |
185 | ||
186 | return cpu_to_caam64(value); | |
187 | } | |
188 | ||
189 | static inline u64 caam_dma64_to_cpu(u64 value) | |
190 | { | |
191 | if (caam_imx) | |
192 | return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) | | |
193 | (u64)caam32_to_cpu(upper_32_bits(value))); | |
194 | ||
195 | return caam64_to_cpu(value); | |
196 | } | |
197 | ||
261ea058 | 198 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
c056d910 HG |
199 | #define cpu_to_caam_dma(value) cpu_to_caam_dma64(value) |
200 | #define caam_dma_to_cpu(value) caam_dma64_to_cpu(value) | |
261ea058 HG |
201 | #else |
202 | #define cpu_to_caam_dma(value) cpu_to_caam32(value) | |
203 | #define caam_dma_to_cpu(value) caam32_to_cpu(value) | |
c056d910 | 204 | #endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */ |
f97581cf | 205 | |
8e8ec596 KP |
206 | /* |
207 | * jr_outentry | |
208 | * Represents each entry in a JobR output ring | |
209 | */ | |
210 | struct jr_outentry { | |
211 | dma_addr_t desc;/* Pointer to completed descriptor */ | |
212 | u32 jrstatus; /* Status for completed descriptor */ | |
213 | } __packed; | |
214 | ||
d239b10d HG |
215 | /* Version registers (Era 10+) e80-eff */ |
216 | struct version_regs { | |
217 | u32 crca; /* CRCA_VERSION */ | |
218 | u32 afha; /* AFHA_VERSION */ | |
219 | u32 kfha; /* KFHA_VERSION */ | |
220 | u32 pkha; /* PKHA_VERSION */ | |
221 | u32 aesa; /* AESA_VERSION */ | |
222 | u32 mdha; /* MDHA_VERSION */ | |
223 | u32 desa; /* DESA_VERSION */ | |
224 | u32 snw8a; /* SNW8A_VERSION */ | |
225 | u32 snw9a; /* SNW9A_VERSION */ | |
226 | u32 zuce; /* ZUCE_VERSION */ | |
227 | u32 zuca; /* ZUCA_VERSION */ | |
228 | u32 ccha; /* CCHA_VERSION */ | |
229 | u32 ptha; /* PTHA_VERSION */ | |
230 | u32 rng; /* RNG_VERSION */ | |
231 | u32 trng; /* TRNG_VERSION */ | |
232 | u32 aaha; /* AAHA_VERSION */ | |
233 | u32 rsvd[10]; | |
234 | u32 sr; /* SR_VERSION */ | |
235 | u32 dma; /* DMA_VERSION */ | |
236 | u32 ai; /* AI_VERSION */ | |
237 | u32 qi; /* QI_VERSION */ | |
238 | u32 jr; /* JR_VERSION */ | |
239 | u32 deco; /* DECO_VERSION */ | |
240 | }; | |
241 | ||
242 | /* Version registers bitfields */ | |
243 | ||
244 | /* Number of CHAs instantiated */ | |
245 | #define CHA_VER_NUM_MASK 0xffull | |
246 | /* CHA Miscellaneous Information */ | |
247 | #define CHA_VER_MISC_SHIFT 8 | |
248 | #define CHA_VER_MISC_MASK (0xffull << CHA_VER_MISC_SHIFT) | |
249 | /* CHA Revision Number */ | |
250 | #define CHA_VER_REV_SHIFT 16 | |
251 | #define CHA_VER_REV_MASK (0xffull << CHA_VER_REV_SHIFT) | |
252 | /* CHA Version ID */ | |
253 | #define CHA_VER_VID_SHIFT 24 | |
254 | #define CHA_VER_VID_MASK (0xffull << CHA_VER_VID_SHIFT) | |
255 | ||
df80bfd3 HG |
256 | /* CHA Miscellaneous Information - AESA_MISC specific */ |
257 | #define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT) | |
258 | ||
8e8ec596 KP |
259 | /* |
260 | * caam_perfmon - Performance Monitor/Secure Memory Status/ | |
261 | * CAAM Global Status/Component Version IDs | |
262 | * | |
263 | * Spans f00-fff wherever instantiated | |
264 | */ | |
265 | ||
266 | /* Number of DECOs */ | |
eb1139cd RG |
267 | #define CHA_NUM_MS_DECONUM_SHIFT 24 |
268 | #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT) | |
8e8ec596 | 269 | |
bf83490e | 270 | /* |
d239b10d | 271 | * CHA version IDs / instantiation bitfields (< Era 10) |
bf83490e VM |
272 | * Defined for use with the cha_id fields in perfmon, but the same shift/mask |
273 | * selectors can be used to pull out the number of instantiated blocks within | |
274 | * cha_num fields in perfmon because the locations are the same. | |
275 | */ | |
eb1139cd | 276 | #define CHA_ID_LS_AES_SHIFT 0 |
bf83490e | 277 | #define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) |
986dfbcf | 278 | |
eb1139cd | 279 | #define CHA_ID_LS_DES_SHIFT 4 |
bf83490e | 280 | #define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) |
986dfbcf | 281 | |
eb1139cd RG |
282 | #define CHA_ID_LS_ARC4_SHIFT 8 |
283 | #define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) | |
986dfbcf | 284 | |
eb1139cd RG |
285 | #define CHA_ID_LS_MD_SHIFT 12 |
286 | #define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) | |
986dfbcf | 287 | |
eb1139cd RG |
288 | #define CHA_ID_LS_RNG_SHIFT 16 |
289 | #define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) | |
986dfbcf | 290 | |
eb1139cd RG |
291 | #define CHA_ID_LS_SNW8_SHIFT 20 |
292 | #define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) | |
986dfbcf | 293 | |
eb1139cd RG |
294 | #define CHA_ID_LS_KAS_SHIFT 24 |
295 | #define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) | |
986dfbcf | 296 | |
eb1139cd RG |
297 | #define CHA_ID_LS_PK_SHIFT 28 |
298 | #define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) | |
986dfbcf | 299 | |
eb1139cd RG |
300 | #define CHA_ID_MS_CRC_SHIFT 0 |
301 | #define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) | |
986dfbcf | 302 | |
eb1139cd RG |
303 | #define CHA_ID_MS_SNW9_SHIFT 4 |
304 | #define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) | |
986dfbcf | 305 | |
eb1139cd RG |
306 | #define CHA_ID_MS_DECO_SHIFT 24 |
307 | #define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT) | |
986dfbcf | 308 | |
eb1139cd RG |
309 | #define CHA_ID_MS_JR_SHIFT 28 |
310 | #define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT) | |
986dfbcf | 311 | |
d239b10d HG |
312 | /* Specific CHA version IDs */ |
313 | #define CHA_VER_VID_AES_LP 0x3ull | |
314 | #define CHA_VER_VID_AES_HP 0x4ull | |
315 | #define CHA_VER_VID_MD_LP256 0x0ull | |
316 | #define CHA_VER_VID_MD_LP512 0x1ull | |
317 | #define CHA_VER_VID_MD_HP 0x2ull | |
318 | ||
82c2f960 AP |
319 | struct sec_vid { |
320 | u16 ip_id; | |
321 | u8 maj_rev; | |
322 | u8 min_rev; | |
323 | }; | |
324 | ||
8e8ec596 KP |
325 | struct caam_perfmon { |
326 | /* Performance Monitor Registers f00-f9f */ | |
327 | u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ | |
328 | u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */ | |
329 | u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */ | |
330 | u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */ | |
331 | u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */ | |
332 | u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */ | |
333 | u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */ | |
334 | u64 rsvd[13]; | |
335 | ||
336 | /* CAAM Hardware Instantiation Parameters fa0-fbf */ | |
eb1139cd RG |
337 | u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/ |
338 | u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/ | |
339 | #define CTPR_MS_QI_SHIFT 25 | |
340 | #define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT) | |
297b9ceb | 341 | #define CTPR_MS_DPAA2 BIT(13) |
17157c90 RG |
342 | #define CTPR_MS_VIRT_EN_INCL 0x00000001 |
343 | #define CTPR_MS_VIRT_EN_POR 0x00000002 | |
fb4562b2 NNL |
344 | #define CTPR_MS_PG_SZ_MASK 0x10 |
345 | #define CTPR_MS_PG_SZ_SHIFT 4 | |
eb1139cd RG |
346 | u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ |
347 | u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ | |
8e8ec596 KP |
348 | u64 rsvd1[2]; |
349 | ||
350 | /* CAAM Global Status fc0-fdf */ | |
351 | u64 faultaddr; /* FAR - Fault Address */ | |
352 | u32 faultliodn; /* FALR - Fault Address LIODN */ | |
353 | u32 faultdetail; /* FADR - Fault Addr Detail */ | |
354 | u32 rsvd2; | |
261ea058 HG |
355 | #define CSTA_PLEND BIT(10) |
356 | #define CSTA_ALT_PLEND BIT(18) | |
8e8ec596 KP |
357 | u32 status; /* CSTA - CAAM Status */ |
358 | u64 rsvd3; | |
359 | ||
360 | /* Component Instantiation Parameters fe0-fff */ | |
361 | u32 rtic_id; /* RVID - RTIC Version ID */ | |
654f2b93 FE |
362 | #define CCBVID_ERA_MASK 0xff000000 |
363 | #define CCBVID_ERA_SHIFT 24 | |
8e8ec596 | 364 | u32 ccb_id; /* CCBVID - CCB Version ID */ |
eb1139cd RG |
365 | u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/ |
366 | u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/ | |
367 | u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */ | |
368 | u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/ | |
654f2b93 FE |
369 | #define SECVID_MS_IPID_MASK 0xffff0000 |
370 | #define SECVID_MS_IPID_SHIFT 16 | |
371 | #define SECVID_MS_MAJ_REV_MASK 0x0000ff00 | |
372 | #define SECVID_MS_MAJ_REV_SHIFT 8 | |
eb1139cd RG |
373 | u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */ |
374 | u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ | |
8e8ec596 KP |
375 | }; |
376 | ||
377 | /* LIODN programming for DMA configuration */ | |
378 | #define MSTRID_LOCK_LIODN 0x80000000 | |
379 | #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ | |
380 | ||
381 | #define MSTRID_LIODN_MASK 0x0fff | |
382 | struct masterid { | |
383 | u32 liodn_ms; /* lock and make-trusted control bits */ | |
384 | u32 liodn_ls; /* LIODN for non-sequence and seq access */ | |
385 | }; | |
386 | ||
387 | /* Partition ID for DMA configuration */ | |
388 | struct partid { | |
389 | u32 rsvd1; | |
390 | u32 pidr; /* partition ID, DECO */ | |
391 | }; | |
392 | ||
281922a1 | 393 | /* RNGB test mode (replicated twice in some configurations) */ |
8e8ec596 KP |
394 | /* Padded out to 0x100 */ |
395 | struct rngtst { | |
396 | u32 mode; /* RTSTMODEx - Test mode */ | |
397 | u32 rsvd1[3]; | |
398 | u32 reset; /* RTSTRESETx - Test reset control */ | |
399 | u32 rsvd2[3]; | |
400 | u32 status; /* RTSTSSTATUSx - Test status */ | |
401 | u32 rsvd3; | |
402 | u32 errstat; /* RTSTERRSTATx - Test error status */ | |
403 | u32 rsvd4; | |
404 | u32 errctl; /* RTSTERRCTLx - Test error control */ | |
405 | u32 rsvd5; | |
406 | u32 entropy; /* RTSTENTROPYx - Test entropy */ | |
407 | u32 rsvd6[15]; | |
408 | u32 verifctl; /* RTSTVERIFCTLx - Test verification control */ | |
409 | u32 rsvd7; | |
410 | u32 verifstat; /* RTSTVERIFSTATx - Test verification status */ | |
411 | u32 rsvd8; | |
412 | u32 verifdata; /* RTSTVERIFDx - Test verification data */ | |
413 | u32 rsvd9; | |
414 | u32 xkey; /* RTSTXKEYx - Test XKEY */ | |
415 | u32 rsvd10; | |
416 | u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */ | |
417 | u32 rsvd11; | |
418 | u32 oscct; /* RTSTOSCCTx - Test oscillator counter */ | |
419 | u32 rsvd12; | |
420 | u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */ | |
421 | u32 rsvd13[2]; | |
422 | u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */ | |
423 | u32 rsvd14[15]; | |
424 | }; | |
425 | ||
281922a1 KP |
426 | /* RNG4 TRNG test registers */ |
427 | struct rng4tst { | |
1005bccd | 428 | #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ |
e5ffbfc1 AP |
429 | #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in |
430 | both entropy shifter and | |
431 | statistical checker */ | |
432 | #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both | |
433 | entropy shifter and | |
434 | statistical checker */ | |
435 | #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in | |
436 | entropy shifter, raw data | |
437 | in statistical checker */ | |
438 | #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ | |
281922a1 KP |
439 | u32 rtmctl; /* misc. control register */ |
440 | u32 rtscmisc; /* statistical check misc. register */ | |
441 | u32 rtpkrrng; /* poker range register */ | |
442 | union { | |
443 | u32 rtpkrmax; /* PRGM=1: poker max. limit register */ | |
444 | u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ | |
445 | }; | |
446 | #define RTSDCTL_ENT_DLY_SHIFT 16 | |
447 | #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) | |
eeaa1724 | 448 | #define RTSDCTL_ENT_DLY_MIN 3200 |
84cf4827 | 449 | #define RTSDCTL_ENT_DLY_MAX 12800 |
281922a1 KP |
450 | u32 rtsdctl; /* seed control register */ |
451 | union { | |
452 | u32 rtsblim; /* PRGM=1: sparse bit limit register */ | |
453 | u32 rttotsam; /* PRGM=0: total samples register */ | |
454 | }; | |
455 | u32 rtfrqmin; /* frequency count min. limit register */ | |
b061f3fe | 456 | #define RTFRQMAX_DISABLE (1 << 20) |
281922a1 KP |
457 | union { |
458 | u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ | |
459 | u32 rtfrqcnt; /* PRGM=0: freq. count register */ | |
460 | }; | |
986dfbcf | 461 | u32 rsvd1[40]; |
1005bccd AP |
462 | #define RDSTA_SKVT 0x80000000 |
463 | #define RDSTA_SKVN 0x40000000 | |
986dfbcf | 464 | #define RDSTA_IF0 0x00000001 |
1005bccd AP |
465 | #define RDSTA_IF1 0x00000002 |
466 | #define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0) | |
986dfbcf RG |
467 | u32 rdsta; |
468 | u32 rsvd2[15]; | |
281922a1 KP |
469 | }; |
470 | ||
8e8ec596 KP |
471 | /* |
472 | * caam_ctrl - basic core configuration | |
473 | * starts base + 0x0000 padded out to 0x1000 | |
474 | */ | |
475 | ||
476 | #define KEK_KEY_SIZE 8 | |
477 | #define TKEK_KEY_SIZE 8 | |
478 | #define TDSK_KEY_SIZE 8 | |
479 | ||
480 | #define DECO_RESET 1 /* Use with DECO reset/availability regs */ | |
481 | #define DECO_RESET_0 (DECO_RESET << 0) | |
482 | #define DECO_RESET_1 (DECO_RESET << 1) | |
483 | #define DECO_RESET_2 (DECO_RESET << 2) | |
484 | #define DECO_RESET_3 (DECO_RESET << 3) | |
485 | #define DECO_RESET_4 (DECO_RESET << 4) | |
486 | ||
487 | struct caam_ctrl { | |
488 | /* Basic Configuration Section 000-01f */ | |
489 | /* Read/Writable */ | |
490 | u32 rsvd1; | |
491 | u32 mcr; /* MCFG Master Config Register */ | |
575c1bd5 VG |
492 | u32 rsvd2; |
493 | u32 scfgr; /* SCFGR, Security Config Register */ | |
8e8ec596 KP |
494 | |
495 | /* Bus Access Configuration Section 010-11f */ | |
496 | /* Read/Writable */ | |
497 | struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */ | |
17157c90 RG |
498 | u32 rsvd3[11]; |
499 | u32 jrstart; /* JRSTART - Job Ring Start Register */ | |
8e8ec596 | 500 | struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */ |
17157c90 RG |
501 | u32 rsvd4[5]; |
502 | u32 deco_rsr; /* DECORSR - Deco Request Source */ | |
503 | u32 rsvd11; | |
8e8ec596 KP |
504 | u32 deco_rq; /* DECORR - DECO Request */ |
505 | struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ | |
506 | u32 rsvd5[22]; | |
507 | ||
508 | /* DECO Availability/Reset Section 120-3ff */ | |
509 | u32 deco_avail; /* DAR - DECO availability */ | |
510 | u32 deco_reset; /* DRR - DECO reset */ | |
511 | u32 rsvd6[182]; | |
512 | ||
513 | /* Key Encryption/Decryption Configuration 400-5ff */ | |
514 | /* Read/Writable only while in Non-secure mode */ | |
515 | u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */ | |
516 | u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */ | |
517 | u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */ | |
518 | u32 rsvd7[32]; | |
519 | u64 sknonce; /* SKNR - Secure Key Nonce */ | |
520 | u32 rsvd8[70]; | |
521 | ||
522 | /* RNG Test/Verification/Debug Access 600-7ff */ | |
523 | /* (Useful in Test/Debug modes only...) */ | |
281922a1 KP |
524 | union { |
525 | struct rngtst rtst[2]; | |
526 | struct rng4tst r4tst[2]; | |
527 | }; | |
8e8ec596 | 528 | |
d239b10d | 529 | u32 rsvd9[416]; |
8e8ec596 | 530 | |
d239b10d HG |
531 | /* Version registers - introduced with era 10 e80-eff */ |
532 | struct version_regs vreg; | |
8e8ec596 KP |
533 | /* Performance Monitor f00-fff */ |
534 | struct caam_perfmon perfmon; | |
535 | }; | |
536 | ||
537 | /* | |
538 | * Controller master config register defs | |
539 | */ | |
540 | #define MCFGR_SWRESET 0x80000000 /* software reset */ | |
541 | #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */ | |
542 | #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ | |
543 | #define MCFGR_DMA_RESET 0x10000000 | |
544 | #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ | |
575c1bd5 | 545 | #define SCFGR_RDBENABLE 0x00000400 |
17157c90 | 546 | #define SCFGR_VIRT_EN 0x00008000 |
997ad290 | 547 | #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */ |
17157c90 RG |
548 | #define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */ |
549 | #define DECORSR_VALID 0x80000000 | |
997ad290 | 550 | #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/ |
8e8ec596 KP |
551 | |
552 | /* AXI read cache control */ | |
553 | #define MCFGR_ARCACHE_SHIFT 12 | |
554 | #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) | |
f1096749 HG |
555 | #define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT) |
556 | #define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT) | |
557 | #define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT) | |
8e8ec596 KP |
558 | |
559 | /* AXI write cache control */ | |
560 | #define MCFGR_AWCACHE_SHIFT 8 | |
561 | #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) | |
f1096749 HG |
562 | #define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT) |
563 | #define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT) | |
564 | #define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT) | |
8e8ec596 KP |
565 | |
566 | /* AXI pipeline depth */ | |
567 | #define MCFGR_AXIPIPE_SHIFT 4 | |
568 | #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) | |
569 | ||
570 | #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ | |
624144a7 HG |
571 | #define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */ |
572 | #define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */ | |
8e8ec596 | 573 | |
17157c90 RG |
574 | /* JRSTART register offsets */ |
575 | #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ | |
576 | #define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */ | |
577 | #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ | |
578 | #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ | |
579 | ||
8e8ec596 KP |
580 | /* |
581 | * caam_job_ring - direct job ring setup | |
582 | * 1-4 possible per instantiation, base + 1000/2000/3000/4000 | |
583 | * Padded out to 0x1000 | |
584 | */ | |
585 | struct caam_job_ring { | |
586 | /* Input ring */ | |
587 | u64 inpring_base; /* IRBAx - Input desc ring baseaddr */ | |
588 | u32 rsvd1; | |
589 | u32 inpring_size; /* IRSx - Input ring size */ | |
590 | u32 rsvd2; | |
591 | u32 inpring_avail; /* IRSAx - Input ring room remaining */ | |
592 | u32 rsvd3; | |
593 | u32 inpring_jobadd; /* IRJAx - Input ring jobs added */ | |
594 | ||
595 | /* Output Ring */ | |
596 | u64 outring_base; /* ORBAx - Output status ring base addr */ | |
597 | u32 rsvd4; | |
598 | u32 outring_size; /* ORSx - Output ring size */ | |
599 | u32 rsvd5; | |
600 | u32 outring_rmvd; /* ORJRx - Output ring jobs removed */ | |
601 | u32 rsvd6; | |
602 | u32 outring_used; /* ORSFx - Output ring slots full */ | |
603 | ||
604 | /* Status/Configuration */ | |
605 | u32 rsvd7; | |
606 | u32 jroutstatus; /* JRSTAx - JobR output status */ | |
607 | u32 rsvd8; | |
608 | u32 jrintstatus; /* JRINTx - JobR interrupt status */ | |
609 | u32 rconfig_hi; /* JRxCFG - Ring configuration */ | |
610 | u32 rconfig_lo; | |
611 | ||
612 | /* Indices. CAAM maintains as "heads" of each queue */ | |
613 | u32 rsvd9; | |
614 | u32 inp_rdidx; /* IRRIx - Input ring read index */ | |
615 | u32 rsvd10; | |
616 | u32 out_wtidx; /* ORWIx - Output ring write index */ | |
617 | ||
618 | /* Command/control */ | |
619 | u32 rsvd11; | |
620 | u32 jrcommand; /* JRCRx - JobR command */ | |
621 | ||
d239b10d | 622 | u32 rsvd12[900]; |
8e8ec596 | 623 | |
d239b10d HG |
624 | /* Version registers - introduced with era 10 e80-eff */ |
625 | struct version_regs vreg; | |
8e8ec596 KP |
626 | /* Performance Monitor f00-fff */ |
627 | struct caam_perfmon perfmon; | |
628 | }; | |
629 | ||
630 | #define JR_RINGSIZE_MASK 0x03ff | |
631 | /* | |
632 | * jrstatus - Job Ring Output Status | |
633 | * All values in lo word | |
634 | * Also note, same values written out as status through QI | |
635 | * in the command/status field of a frame descriptor | |
636 | */ | |
637 | #define JRSTA_SSRC_SHIFT 28 | |
638 | #define JRSTA_SSRC_MASK 0xf0000000 | |
639 | ||
640 | #define JRSTA_SSRC_NONE 0x00000000 | |
641 | #define JRSTA_SSRC_CCB_ERROR 0x20000000 | |
642 | #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000 | |
643 | #define JRSTA_SSRC_DECO 0x40000000 | |
644 | #define JRSTA_SSRC_JRERROR 0x60000000 | |
645 | #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000 | |
646 | ||
647 | #define JRSTA_DECOERR_JUMP 0x08000000 | |
648 | #define JRSTA_DECOERR_INDEX_SHIFT 8 | |
649 | #define JRSTA_DECOERR_INDEX_MASK 0xff00 | |
650 | #define JRSTA_DECOERR_ERROR_MASK 0x00ff | |
651 | ||
652 | #define JRSTA_DECOERR_NONE 0x00 | |
653 | #define JRSTA_DECOERR_LINKLEN 0x01 | |
654 | #define JRSTA_DECOERR_LINKPTR 0x02 | |
655 | #define JRSTA_DECOERR_JRCTRL 0x03 | |
656 | #define JRSTA_DECOERR_DESCCMD 0x04 | |
657 | #define JRSTA_DECOERR_ORDER 0x05 | |
658 | #define JRSTA_DECOERR_KEYCMD 0x06 | |
659 | #define JRSTA_DECOERR_LOADCMD 0x07 | |
660 | #define JRSTA_DECOERR_STORECMD 0x08 | |
661 | #define JRSTA_DECOERR_OPCMD 0x09 | |
662 | #define JRSTA_DECOERR_FIFOLDCMD 0x0a | |
663 | #define JRSTA_DECOERR_FIFOSTCMD 0x0b | |
664 | #define JRSTA_DECOERR_MOVECMD 0x0c | |
665 | #define JRSTA_DECOERR_JUMPCMD 0x0d | |
666 | #define JRSTA_DECOERR_MATHCMD 0x0e | |
667 | #define JRSTA_DECOERR_SHASHCMD 0x0f | |
668 | #define JRSTA_DECOERR_SEQCMD 0x10 | |
669 | #define JRSTA_DECOERR_DECOINTERNAL 0x11 | |
670 | #define JRSTA_DECOERR_SHDESCHDR 0x12 | |
671 | #define JRSTA_DECOERR_HDRLEN 0x13 | |
672 | #define JRSTA_DECOERR_BURSTER 0x14 | |
673 | #define JRSTA_DECOERR_DESCSIGNATURE 0x15 | |
674 | #define JRSTA_DECOERR_DMA 0x16 | |
675 | #define JRSTA_DECOERR_BURSTFIFO 0x17 | |
676 | #define JRSTA_DECOERR_JRRESET 0x1a | |
677 | #define JRSTA_DECOERR_JOBFAIL 0x1b | |
678 | #define JRSTA_DECOERR_DNRERR 0x80 | |
679 | #define JRSTA_DECOERR_UNDEFPCL 0x81 | |
680 | #define JRSTA_DECOERR_PDBERR 0x82 | |
681 | #define JRSTA_DECOERR_ANRPLY_LATE 0x83 | |
682 | #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84 | |
683 | #define JRSTA_DECOERR_SEQOVF 0x85 | |
684 | #define JRSTA_DECOERR_INVSIGN 0x86 | |
685 | #define JRSTA_DECOERR_DSASIGN 0x87 | |
686 | ||
94cebd9d HG |
687 | #define JRSTA_QIERR_ERROR_MASK 0x00ff |
688 | ||
8e8ec596 KP |
689 | #define JRSTA_CCBERR_JUMP 0x08000000 |
690 | #define JRSTA_CCBERR_INDEX_MASK 0xff00 | |
691 | #define JRSTA_CCBERR_INDEX_SHIFT 8 | |
692 | #define JRSTA_CCBERR_CHAID_MASK 0x00f0 | |
693 | #define JRSTA_CCBERR_CHAID_SHIFT 4 | |
694 | #define JRSTA_CCBERR_ERRID_MASK 0x000f | |
695 | ||
696 | #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT) | |
697 | #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT) | |
698 | #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT) | |
699 | #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT) | |
700 | #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT) | |
701 | #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT) | |
702 | #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT) | |
703 | #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT) | |
704 | #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT) | |
705 | ||
706 | #define JRSTA_CCBERR_ERRID_NONE 0x00 | |
707 | #define JRSTA_CCBERR_ERRID_MODE 0x01 | |
708 | #define JRSTA_CCBERR_ERRID_DATASIZ 0x02 | |
709 | #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03 | |
710 | #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04 | |
711 | #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05 | |
712 | #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06 | |
713 | #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07 | |
714 | #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08 | |
715 | #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09 | |
716 | #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a | |
717 | #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b | |
718 | #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c | |
719 | #define JRSTA_CCBERR_ERRID_INVCHA 0x0f | |
720 | ||
721 | #define JRINT_ERR_INDEX_MASK 0x3fff0000 | |
722 | #define JRINT_ERR_INDEX_SHIFT 16 | |
723 | #define JRINT_ERR_TYPE_MASK 0xf00 | |
724 | #define JRINT_ERR_TYPE_SHIFT 8 | |
725 | #define JRINT_ERR_HALT_MASK 0xc | |
726 | #define JRINT_ERR_HALT_SHIFT 2 | |
727 | #define JRINT_ERR_HALT_INPROGRESS 0x4 | |
728 | #define JRINT_ERR_HALT_COMPLETE 0x8 | |
729 | #define JRINT_JR_ERROR 0x02 | |
730 | #define JRINT_JR_INT 0x01 | |
731 | ||
732 | #define JRINT_ERR_TYPE_WRITE 1 | |
733 | #define JRINT_ERR_TYPE_BAD_INPADDR 3 | |
734 | #define JRINT_ERR_TYPE_BAD_OUTADDR 4 | |
735 | #define JRINT_ERR_TYPE_INV_INPWRT 5 | |
736 | #define JRINT_ERR_TYPE_INV_OUTWRT 6 | |
737 | #define JRINT_ERR_TYPE_RESET 7 | |
738 | #define JRINT_ERR_TYPE_REMOVE_OFL 8 | |
739 | #define JRINT_ERR_TYPE_ADD_OFL 9 | |
740 | ||
741 | #define JRCFG_SOE 0x04 | |
742 | #define JRCFG_ICEN 0x02 | |
743 | #define JRCFG_IMSK 0x01 | |
744 | #define JRCFG_ICDCT_SHIFT 8 | |
745 | #define JRCFG_ICTT_SHIFT 16 | |
746 | ||
747 | #define JRCR_RESET 0x01 | |
748 | ||
749 | /* | |
750 | * caam_assurance - Assurance Controller View | |
751 | * base + 0x6000 padded out to 0x1000 | |
752 | */ | |
753 | ||
754 | struct rtic_element { | |
755 | u64 address; | |
756 | u32 rsvd; | |
757 | u32 length; | |
758 | }; | |
759 | ||
760 | struct rtic_block { | |
761 | struct rtic_element element[2]; | |
762 | }; | |
763 | ||
764 | struct rtic_memhash { | |
765 | u32 memhash_be[32]; | |
766 | u32 memhash_le[32]; | |
767 | }; | |
768 | ||
769 | struct caam_assurance { | |
770 | /* Status/Command/Watchdog */ | |
771 | u32 rsvd1; | |
772 | u32 status; /* RSTA - Status */ | |
773 | u32 rsvd2; | |
774 | u32 cmd; /* RCMD - Command */ | |
775 | u32 rsvd3; | |
776 | u32 ctrl; /* RCTL - Control */ | |
777 | u32 rsvd4; | |
778 | u32 throttle; /* RTHR - Throttle */ | |
779 | u32 rsvd5[2]; | |
780 | u64 watchdog; /* RWDOG - Watchdog Timer */ | |
781 | u32 rsvd6; | |
782 | u32 rend; /* REND - Endian corrections */ | |
783 | u32 rsvd7[50]; | |
784 | ||
785 | /* Block access/configuration @ 100/110/120/130 */ | |
786 | struct rtic_block memblk[4]; /* Memory Blocks A-D */ | |
787 | u32 rsvd8[32]; | |
788 | ||
789 | /* Block hashes @ 200/300/400/500 */ | |
790 | struct rtic_memhash hash[4]; /* Block hash values A-D */ | |
791 | u32 rsvd_3[640]; | |
792 | }; | |
793 | ||
794 | /* | |
795 | * caam_queue_if - QI configuration and control | |
796 | * starts base + 0x7000, padded out to 0x1000 long | |
797 | */ | |
798 | ||
799 | struct caam_queue_if { | |
800 | u32 qi_control_hi; /* QICTL - QI Control */ | |
801 | u32 qi_control_lo; | |
802 | u32 rsvd1; | |
803 | u32 qi_status; /* QISTA - QI Status */ | |
804 | u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */ | |
805 | u32 qi_deq_cfg_lo; | |
806 | u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */ | |
807 | u32 qi_enq_cfg_lo; | |
808 | u32 rsvd2[1016]; | |
809 | }; | |
810 | ||
811 | /* QI control bits - low word */ | |
812 | #define QICTL_DQEN 0x01 /* Enable frame pop */ | |
813 | #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */ | |
814 | #define QICTL_SOE 0x04 /* Stop on error */ | |
815 | ||
816 | /* QI control bits - high word */ | |
817 | #define QICTL_MBSI 0x01 | |
818 | #define QICTL_MHWSI 0x02 | |
819 | #define QICTL_MWSI 0x04 | |
820 | #define QICTL_MDWSI 0x08 | |
821 | #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */ | |
822 | #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */ | |
823 | #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */ | |
824 | #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */ | |
825 | #define QICTL_MBSO 0x0100 | |
826 | #define QICTL_MHWSO 0x0200 | |
827 | #define QICTL_MWSO 0x0400 | |
828 | #define QICTL_MDWSO 0x0800 | |
829 | #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */ | |
830 | #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */ | |
831 | #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */ | |
832 | #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */ | |
833 | #define QICTL_DMBS 0x010000 | |
834 | #define QICTL_EPO 0x020000 | |
835 | ||
836 | /* QI status bits */ | |
837 | #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */ | |
838 | #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */ | |
839 | #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */ | |
840 | #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */ | |
841 | #define QISTA_BTSERR 0x10 /* Buffer Undersize */ | |
842 | #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */ | |
843 | #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */ | |
844 | ||
845 | /* deco_sg_table - DECO view of scatter/gather table */ | |
846 | struct deco_sg_table { | |
847 | u64 addr; /* Segment Address */ | |
848 | u32 elen; /* E, F bits + 30-bit length */ | |
849 | u32 bpid_offset; /* Buffer Pool ID + 16-bit length */ | |
850 | }; | |
851 | ||
852 | /* | |
853 | * caam_deco - descriptor controller - CHA cluster block | |
854 | * | |
855 | * Only accessible when direct DECO access is turned on | |
856 | * (done in DECORR, via MID programmed in DECOxMID | |
857 | * | |
858 | * 5 typical, base + 0x8000/9000/a000/b000 | |
859 | * Padded out to 0x1000 long | |
860 | */ | |
861 | struct caam_deco { | |
862 | u32 rsvd1; | |
863 | u32 cls1_mode; /* CxC1MR - Class 1 Mode */ | |
864 | u32 rsvd2; | |
865 | u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */ | |
866 | u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */ | |
867 | u32 cls1_datasize_lo; | |
868 | u32 rsvd3; | |
869 | u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */ | |
870 | u32 rsvd4[5]; | |
871 | u32 cha_ctrl; /* CCTLR - CHA control */ | |
872 | u32 rsvd5; | |
873 | u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */ | |
874 | u32 rsvd6; | |
875 | u32 clr_written; /* CxCWR - Clear-Written */ | |
876 | u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */ | |
877 | u32 ccb_status_lo; | |
878 | u32 rsvd7[3]; | |
879 | u32 aad_size; /* CxAADSZR - Current AAD Size */ | |
880 | u32 rsvd8; | |
881 | u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */ | |
882 | u32 rsvd9[7]; | |
883 | u32 pkha_a_size; /* PKASZRx - Size of PKHA A */ | |
884 | u32 rsvd10; | |
885 | u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */ | |
886 | u32 rsvd11; | |
887 | u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */ | |
888 | u32 rsvd12; | |
889 | u32 pkha_e_size; /* PKESZRx - Size of PKHA E */ | |
890 | u32 rsvd13[24]; | |
891 | u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */ | |
892 | u32 rsvd14[48]; | |
893 | u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */ | |
894 | u32 rsvd15[121]; | |
895 | u32 cls2_mode; /* CxC2MR - Class 2 Mode */ | |
896 | u32 rsvd16; | |
897 | u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */ | |
898 | u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */ | |
899 | u32 cls2_datasize_lo; | |
900 | u32 rsvd17; | |
901 | u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */ | |
902 | u32 rsvd18[56]; | |
903 | u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */ | |
904 | u32 rsvd19[46]; | |
905 | u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */ | |
906 | u32 rsvd20[84]; | |
907 | u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */ | |
908 | u32 inp_infofifo_lo; | |
909 | u32 rsvd21[2]; | |
910 | u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */ | |
911 | u32 rsvd22[2]; | |
912 | u64 out_datafifo; /* CxOFIFO - Output Data FIFO */ | |
913 | u32 rsvd23[2]; | |
914 | u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ | |
915 | u32 jr_ctl_lo; | |
916 | u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ | |
1005bccd | 917 | #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF |
8e8ec596 KP |
918 | u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ |
919 | u32 op_status_lo; | |
920 | u32 rsvd24[2]; | |
921 | u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */ | |
922 | u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */ | |
923 | u32 rsvd26[6]; | |
924 | u64 math[4]; /* DxMTH - Math register */ | |
925 | u32 rsvd27[8]; | |
926 | struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */ | |
927 | u32 rsvd28[16]; | |
928 | struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */ | |
929 | u32 rsvd29[48]; | |
930 | u32 descbuf[64]; /* DxDESB - Descriptor buffer */ | |
997ad290 | 931 | u32 rscvd30[193]; |
84cf4827 AP |
932 | #define DESC_DBG_DECO_STAT_VALID 0x80000000 |
933 | #define DESC_DBG_DECO_STAT_MASK 0x00F00000 | |
d239b10d | 934 | #define DESC_DBG_DECO_STAT_SHIFT 20 |
997ad290 | 935 | u32 desc_dbg; /* DxDDR - DECO Debug Register */ |
d239b10d HG |
936 | u32 rsvd31[13]; |
937 | #define DESC_DER_DECO_STAT_MASK 0x000F0000 | |
938 | #define DESC_DER_DECO_STAT_SHIFT 16 | |
939 | u32 dbg_exec; /* DxDER - DECO Debug Exec Register */ | |
940 | u32 rsvd32[112]; | |
8e8ec596 KP |
941 | }; |
942 | ||
d239b10d HG |
943 | #define DECO_STAT_HOST_ERR 0xD |
944 | ||
997ad290 RG |
945 | #define DECO_JQCR_WHL 0x20000000 |
946 | #define DECO_JQCR_FOUR 0x10000000 | |
947 | ||
fb4562b2 NNL |
948 | #define JR_BLOCK_NUMBER 1 |
949 | #define ASSURE_BLOCK_NUMBER 6 | |
950 | #define QI_BLOCK_NUMBER 7 | |
951 | #define DECO_BLOCK_NUMBER 8 | |
952 | #define PG_SIZE_4K 0x1000 | |
953 | #define PG_SIZE_64K 0x10000 | |
8e8ec596 | 954 | #endif /* REGS_H */ |