[mirror_ubuntu-focal-kernel.git] / drivers / crypto / ccree / cc_driver.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */

/* \file cc_driver.h
 * ARM CryptoCell Linux Crypto Driver
 */

#ifndef __CC_DRIVER_H__
#define __CC_DRIVER_H__

#ifdef COMP_IN_WQ
#include <linux/workqueue.h>
#else
#include <linux/interrupt.h>
#endif
#include <linux/dma-mapping.h>
#include <crypto/algapi.h>
#include <crypto/internal/skcipher.h>
#include <crypto/aes.h>
#include <crypto/sha.h>
#include <crypto/aead.h>
#include <crypto/authenc.h>
#include <crypto/hash.h>
#include <crypto/skcipher.h>
#include <linux/version.h>
#include <linux/clk.h>
#include <linux/platform_device.h>

/* Registers definitions from shared/hw/ree_include */
#include "cc_host_regs.h"
#define CC_DEV_SHA_MAX 512
#include "cc_crypto_ctx.h"
#include "cc_hw_queue_defs.h"
#include "cc_sram_mgr.h"

extern bool cc_dump_desc;
extern bool cc_dump_bytes;

#define DRV_MODULE_VERSION "5.0"

enum cc_hw_rev {
	CC_HW_REV_630 = 630,
	CC_HW_REV_710 = 710,
	CC_HW_REV_712 = 712,
	CC_HW_REV_713 = 713
};

enum cc_std_body {
	CC_STD_NIST = 0x1,
	CC_STD_OSCCA = 0x2,
	CC_STD_ALL = 0x3
};

#define CC_COHERENT_CACHE_PARAMS 0xEEE

/* Maximum DMA mask supported by IP */
#define DMA_BIT_MASK_LEN 48

#define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \
			  (1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
			  (1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \
			  (1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT))

#define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)

#define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)

#define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \
				    CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
				    CC_AXIM_MON_COMP_VALUE_BIT_SHIFT)

/* Register name mangling macro */
#define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET

/* TEE FIPS status interrupt */
#define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT)

#define CC_CRA_PRIO 400

#define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */

#define MAX_REQUEST_QUEUE_SIZE 4096
#define MAX_MLLI_BUFF_SIZE 2080
#define MAX_ICV_NENTS_SUPPORTED 2

/* Definitions for HW descriptors DIN/DOUT fields */
#define NS_BIT 1
#define AXI_ID 0
/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
 * field in the HW descriptor. The DMA engine +8 that value.
 */

#define CC_MAX_IVGEN_DMA_ADDRESSES	3
struct cc_crypto_req {
	void (*user_cb)(struct device *dev, void *req, int err);
	void *user_arg;
	dma_addr_t ivgen_dma_addr[CC_MAX_IVGEN_DMA_ADDRESSES];
	/* For the first 'ivgen_dma_addr_len' addresses of this array,
	 * generated IV would be placed in it by send_request().
	 * Same generated IV for all addresses!
	 */
	/* Amount of 'ivgen_dma_addr' elements to be filled. */
	unsigned int ivgen_dma_addr_len;
	/* The generated IV size required, 8/16 B allowed. */
	unsigned int ivgen_size;
	struct completion seq_compl; /* request completion */
};

/**
 * struct cc_drvdata - driver private data context
 * @cc_base:	virt address of the CC registers
 * @irq:	device IRQ number
 * @irq_mask:	Interrupt mask shadow (1 for masked interrupts)
 * @fw_ver:	SeP loaded firmware version
 */
struct cc_drvdata {
	void __iomem *cc_base;
	int irq;
	u32 irq_mask;
	u32 fw_ver;
	struct completion hw_queue_avail; /* wait for HW queue availability */
	struct platform_device *plat_dev;
	cc_sram_addr_t mlli_sram_addr;
	void *buff_mgr_handle;
	void *cipher_handle;
	void *hash_handle;
	void *aead_handle;
	void *request_mgr_handle;
	void *fips_handle;
	void *ivgen_handle;
	void *sram_mgr_handle;
	void *debugfs;
	struct clk *clk;
	bool coherent;
	char *hw_rev_name;
	enum cc_hw_rev hw_rev;
	u32 axim_mon_offset;
	u32 sig_offset;
	u32 ver_offset;
	int std_bodies;
};

struct cc_crypto_alg {
	struct list_head entry;
	int cipher_mode;
	int flow_mode; /* Note: currently, refers to the cipher mode only. */
	int auth_mode;
	unsigned int data_unit;
	struct cc_drvdata *drvdata;
	struct skcipher_alg skcipher_alg;
	struct aead_alg aead_alg;
};

struct cc_alg_template {
	char name[CRYPTO_MAX_ALG_NAME];
	char driver_name[CRYPTO_MAX_ALG_NAME];
	unsigned int blocksize;
	union {
		struct skcipher_alg skcipher;
		struct aead_alg aead;
	} template_u;
	int cipher_mode;
	int flow_mode; /* Note: currently, refers to the cipher mode only. */
	int auth_mode;
	u32 min_hw_rev;
	enum cc_std_body std_body;
	unsigned int data_unit;
	struct cc_drvdata *drvdata;
};

struct async_gen_req_ctx {
	dma_addr_t iv_dma_addr;
	enum drv_crypto_direction op_type;
};

static inline struct device *drvdata_to_dev(struct cc_drvdata *drvdata)
{
	return &drvdata->plat_dev->dev;
}

void __dump_byte_array(const char *name, const u8 *buf, size_t len);
static inline void dump_byte_array(const char *name, const u8 *the_array,
				   size_t size)
{
	if (cc_dump_bytes)
		__dump_byte_array(name, the_array, size);
}

int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe);
void fini_cc_regs(struct cc_drvdata *drvdata);
int cc_clk_on(struct cc_drvdata *drvdata);
void cc_clk_off(struct cc_drvdata *drvdata);
unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata);

static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val)
{
	iowrite32(val, (drvdata->cc_base + reg));
}

static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg)
{
	return ioread32(drvdata->cc_base + reg);
}

static inline gfp_t cc_gfp_flags(struct crypto_async_request *req)
{
	return (req->flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
			GFP_KERNEL : GFP_ATOMIC;
}

static inline void set_queue_last_ind(struct cc_drvdata *drvdata,
				      struct cc_hw_desc *pdesc)
{
	if (drvdata->hw_rev >= CC_HW_REV_712)
		set_queue_last_ind_bit(pdesc);
}

#endif /*__CC_DRIVER_H__*/
Commit	Line	Data
4c3f9727 GBY	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
	3
	4	/* \file cc_driver.h
	5	* ARM CryptoCell Linux Crypto Driver
	6	*/
	7
	8	#ifndef __CC_DRIVER_H__
	9	#define __CC_DRIVER_H__
	10
	11	#ifdef COMP_IN_WQ
	12	#include <linux/workqueue.h>
	13	#else
	14	#include <linux/interrupt.h>
	15	#endif
	16	#include <linux/dma-mapping.h>
	17	#include <crypto/algapi.h>
63ee04c8	18	#include <crypto/internal/skcipher.h>
4c3f9727 GBY	19	#include <crypto/aes.h>
	20	#include <crypto/sha.h>
	21	#include <crypto/aead.h>
	22	#include <crypto/authenc.h>
	23	#include <crypto/hash.h>
	24	#include <crypto/skcipher.h>
	25	#include <linux/version.h>
	26	#include <linux/clk.h>
	27	#include <linux/platform_device.h>
	28
	29	/* Registers definitions from shared/hw/ree_include */
	30	#include "cc_host_regs.h"
	31	#define CC_DEV_SHA_MAX 512
	32	#include "cc_crypto_ctx.h"
	33	#include "cc_hw_queue_defs.h"
	34	#include "cc_sram_mgr.h"
	35
	36	extern bool cc_dump_desc;
	37	extern bool cc_dump_bytes;
	38
e40fdb50	39	#define DRV_MODULE_VERSION "5.0"
27b3b22d GBY	40
	41	enum cc_hw_rev {
	42	CC_HW_REV_630 = 630,
	43	CC_HW_REV_710 = 710,
e40fdb50 GBY	44	CC_HW_REV_712 = 712,
e40fdb50 GBY	45	CC_HW_REV_713 = 713
27b3b22d	46	};
4c3f9727	47
1c876a90 GBY	48	enum cc_std_body {
	49	CC_STD_NIST = 0x1,
	50	CC_STD_OSCCA = 0x2,
	51	CC_STD_ALL = 0x3
	52	};
	53
4c3f9727 GBY	54	#define CC_COHERENT_CACHE_PARAMS 0xEEE
	55
	56	/* Maximum DMA mask supported by IP */
	57	#define DMA_BIT_MASK_LEN 48
	58
4c3f9727 GBY	59	#define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) \| \
	60	(1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) \| \
	61	(1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) \| \
	62	(1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT))
	63
	64	#define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
	65
	66	#define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
	67
	68	#define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \
	69	CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
	70	CC_AXIM_MON_COMP_VALUE_BIT_SHIFT)
	71
	72	/* Register name mangling macro */
	73	#define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET
	74
	75	/* TEE FIPS status interrupt */
	76	#define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT)
	77
	78	#define CC_CRA_PRIO 400
	79
	80	#define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */
	81
	82	#define MAX_REQUEST_QUEUE_SIZE 4096
	83	#define MAX_MLLI_BUFF_SIZE 2080
	84	#define MAX_ICV_NENTS_SUPPORTED 2
	85
	86	/* Definitions for HW descriptors DIN/DOUT fields */
	87	#define NS_BIT 1
	88	#define AXI_ID 0
	89	/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
	90	* field in the HW descriptor. The DMA engine +8 that value.
	91	*/
	92
	93	#define CC_MAX_IVGEN_DMA_ADDRESSES 3
	94	struct cc_crypto_req {
	95	void (user_cb)(struct device dev, void *req, int err);
	96	void *user_arg;
	97	dma_addr_t ivgen_dma_addr[CC_MAX_IVGEN_DMA_ADDRESSES];
	98	/* For the first 'ivgen_dma_addr_len' addresses of this array,
	99	* generated IV would be placed in it by send_request().
	100	* Same generated IV for all addresses!
	101	*/
	102	/* Amount of 'ivgen_dma_addr' elements to be filled. */
	103	unsigned int ivgen_dma_addr_len;
	104	/* The generated IV size required, 8/16 B allowed. */
	105	unsigned int ivgen_size;
	106	struct completion seq_compl; /* request completion */
	107	};
	108
	109	/**
	110	* struct cc_drvdata - driver private data context
	111	* @cc_base: virt address of the CC registers
	112	* @irq: device IRQ number
	113	* @irq_mask: Interrupt mask shadow (1 for masked interrupts)
	114	* @fw_ver: SeP loaded firmware version
	115	*/
	116	struct cc_drvdata {
	117	void __iomem *cc_base;
	118	int irq;
	119	u32 irq_mask;
	120	u32 fw_ver;
	121	struct completion hw_queue_avail; /* wait for HW queue availability */
	122	struct platform_device *plat_dev;
123	cc_sram_addr_t mlli_sram_addr;
124	void *buff_mgr_handle;
63ee04c8	125	void *cipher_handle;
63893811	126	void *hash_handle;
ff27e85a	127	void *aead_handle;
4c3f9727	128	void *request_mgr_handle;
ab8ec965	129	void *fips_handle;
4c3f9727 GBY	130	void *ivgen_handle;
	131	void *sram_mgr_handle;
	132	void *debugfs;
	133	struct clk *clk;
	134	bool coherent;
27b3b22d GBY	135	char *hw_rev_name;
27b3b22d GBY	136	enum cc_hw_rev hw_rev;
27b3b22d	137	u32 axim_mon_offset;
281a58c8 GBY	138	u32 sig_offset;
281a58c8 GBY	139	u32 ver_offset;
1c876a90	140	int std_bodies;
4c3f9727 GBY	141	};
	142
	143	struct cc_crypto_alg {
	144	struct list_head entry;
	145	int cipher_mode;
	146	int flow_mode; /* Note: currently, refers to the cipher mode only. */
	147	int auth_mode;
63ee04c8	148	unsigned int data_unit;
4c3f9727	149	struct cc_drvdata *drvdata;
63ee04c8	150	struct skcipher_alg skcipher_alg;
ff27e85a	151	struct aead_alg aead_alg;
4c3f9727 GBY	152	};
	153
	154	struct cc_alg_template {
	155	char name[CRYPTO_MAX_ALG_NAME];
	156	char driver_name[CRYPTO_MAX_ALG_NAME];
	157	unsigned int blocksize;
4c3f9727 GBY	158	union {
	159	struct skcipher_alg skcipher;
	160	struct aead_alg aead;
	161	} template_u;
	162	int cipher_mode;
	163	int flow_mode; /* Note: currently, refers to the cipher mode only. */
	164	int auth_mode;
27b3b22d	165	u32 min_hw_rev;
1c876a90	166	enum cc_std_body std_body;
63ee04c8	167	unsigned int data_unit;
4c3f9727 GBY	168	struct cc_drvdata *drvdata;
	169	};
	170
	171	struct async_gen_req_ctx {
	172	dma_addr_t iv_dma_addr;
	173	enum drv_crypto_direction op_type;
	174	};
	175
	176	static inline struct device drvdata_to_dev(struct cc_drvdata drvdata)
	177	{
	178	return &drvdata->plat_dev->dev;
	179	}
	180
	181	void __dump_byte_array(const char name, const u8 buf, size_t len);
	182	static inline void dump_byte_array(const char name, const u8 the_array,
	183	size_t size)
	184	{
	185	if (cc_dump_bytes)
	186	__dump_byte_array(name, the_array, size);
	187	}
	188
	189	int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe);
	190	void fini_cc_regs(struct cc_drvdata *drvdata);
	191	int cc_clk_on(struct cc_drvdata *drvdata);
	192	void cc_clk_off(struct cc_drvdata *drvdata);
f1e52fd0	193	unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata);
4c3f9727 GBY	194
	195	static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val)
	196	{
	197	iowrite32(val, (drvdata->cc_base + reg));
	198	}
	199
	200	static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg)
	201	{
	202	return ioread32(drvdata->cc_base + reg);
	203	}
	204
	205	static inline gfp_t cc_gfp_flags(struct crypto_async_request *req)
	206	{
	207	return (req->flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
	208	GFP_KERNEL : GFP_ATOMIC;
	209	}
	210
27b3b22d GBY	211	static inline void set_queue_last_ind(struct cc_drvdata *drvdata,
	212	struct cc_hw_desc *pdesc)
	213	{
	214	if (drvdata->hw_rev >= CC_HW_REV_712)
	215	set_queue_last_ind_bit(pdesc);
	216	}
	217
4c3f9727	218	#endif /__CC_DRIVER_H__/