]>
Commit | Line | Data |
---|---|---|
f7d0561e EP |
1 | /* |
2 | * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru> | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
37a8023c | 22 | #include <linux/moduleparam.h> |
f7d0561e EP |
23 | #include <linux/mod_devicetable.h> |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/mm.h> | |
102d49d3 AM |
29 | #include <linux/dma-mapping.h> |
30 | #include <linux/scatterlist.h> | |
f7d0561e EP |
31 | #include <linux/highmem.h> |
32 | #include <linux/crypto.h> | |
fcd06755 PM |
33 | #include <linux/hw_random.h> |
34 | #include <linux/ktime.h> | |
f7d0561e EP |
35 | |
36 | #include <crypto/algapi.h> | |
c3041f9c | 37 | #include <crypto/des.h> |
f7d0561e EP |
38 | |
39 | #include <asm/kmap_types.h> | |
40 | ||
41 | #undef dprintk | |
42 | ||
43 | #define HIFN_TEST | |
44 | //#define HIFN_DEBUG | |
45 | ||
46 | #ifdef HIFN_DEBUG | |
47 | #define dprintk(f, a...) printk(f, ##a) | |
48 | #else | |
49 | #define dprintk(f, a...) do {} while (0) | |
50 | #endif | |
51 | ||
37a8023c PM |
52 | static char hifn_pll_ref[sizeof("extNNN")] = "ext"; |
53 | module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444); | |
54 | MODULE_PARM_DESC(hifn_pll_ref, | |
55 | "PLL reference clock (pci[freq] or ext[freq], default ext)"); | |
56 | ||
f7d0561e EP |
57 | static atomic_t hifn_dev_number; |
58 | ||
59 | #define ACRYPTO_OP_DECRYPT 0 | |
60 | #define ACRYPTO_OP_ENCRYPT 1 | |
61 | #define ACRYPTO_OP_HMAC 2 | |
62 | #define ACRYPTO_OP_RNG 3 | |
63 | ||
64 | #define ACRYPTO_MODE_ECB 0 | |
65 | #define ACRYPTO_MODE_CBC 1 | |
66 | #define ACRYPTO_MODE_CFB 2 | |
67 | #define ACRYPTO_MODE_OFB 3 | |
68 | ||
69 | #define ACRYPTO_TYPE_AES_128 0 | |
70 | #define ACRYPTO_TYPE_AES_192 1 | |
71 | #define ACRYPTO_TYPE_AES_256 2 | |
72 | #define ACRYPTO_TYPE_3DES 3 | |
73 | #define ACRYPTO_TYPE_DES 4 | |
74 | ||
75 | #define PCI_VENDOR_ID_HIFN 0x13A3 | |
76 | #define PCI_DEVICE_ID_HIFN_7955 0x0020 | |
77 | #define PCI_DEVICE_ID_HIFN_7956 0x001d | |
78 | ||
79 | /* I/O region sizes */ | |
80 | ||
81 | #define HIFN_BAR0_SIZE 0x1000 | |
82 | #define HIFN_BAR1_SIZE 0x2000 | |
83 | #define HIFN_BAR2_SIZE 0x8000 | |
84 | ||
85 | /* DMA registres */ | |
86 | ||
87 | #define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */ | |
88 | #define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */ | |
89 | #define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */ | |
90 | #define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */ | |
91 | #define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */ | |
92 | #define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */ | |
93 | #define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */ | |
94 | #define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */ | |
95 | #define HIFN_CHIP_ID 0x98 /* Chip ID */ | |
96 | ||
97 | /* | |
98 | * Processing Unit Registers (offset from BASEREG0) | |
99 | */ | |
100 | #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ | |
101 | #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ | |
102 | #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ | |
103 | #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ | |
104 | #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ | |
105 | #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ | |
106 | #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ | |
107 | #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ | |
108 | #define HIFN_0_SPACESIZE 0x20 /* Register space size */ | |
109 | ||
110 | /* Processing Unit Control Register (HIFN_0_PUCTRL) */ | |
111 | #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ | |
112 | #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ | |
113 | #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ | |
114 | #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ | |
115 | #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ | |
116 | ||
117 | /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ | |
118 | #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ | |
119 | #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ | |
120 | #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ | |
121 | #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ | |
122 | #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ | |
123 | #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ | |
124 | #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ | |
125 | #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ | |
126 | #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ | |
127 | #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ | |
128 | ||
129 | /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ | |
130 | #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ | |
131 | #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ | |
132 | #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ | |
133 | #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ | |
134 | #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ | |
135 | #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ | |
136 | #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ | |
137 | #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ | |
138 | #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ | |
139 | #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ | |
140 | #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ | |
141 | #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ | |
142 | #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ | |
143 | #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ | |
144 | #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ | |
145 | #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ | |
146 | #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ | |
147 | #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ | |
148 | #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ | |
149 | #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ | |
150 | #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ | |
151 | #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ | |
152 | #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ | |
153 | ||
154 | /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ | |
155 | #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ | |
156 | #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ | |
157 | #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ | |
158 | #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ | |
159 | #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ | |
160 | #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ | |
161 | #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ | |
162 | #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ | |
163 | #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ | |
164 | #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ | |
165 | ||
166 | /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ | |
167 | #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ | |
168 | #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ | |
169 | #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ | |
170 | #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ | |
171 | #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ | |
172 | #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ | |
173 | #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ | |
174 | #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ | |
175 | #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ | |
176 | #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ | |
177 | #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ | |
178 | #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ | |
179 | #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ | |
180 | #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ | |
181 | #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ | |
182 | #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ | |
183 | #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ | |
184 | ||
185 | /* FIFO Status Register (HIFN_0_FIFOSTAT) */ | |
186 | #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ | |
187 | #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ | |
188 | ||
189 | /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ | |
190 | #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */ | |
191 | ||
192 | /* | |
193 | * DMA Interface Registers (offset from BASEREG1) | |
194 | */ | |
195 | #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ | |
196 | #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ | |
197 | #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ | |
198 | #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ | |
199 | #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ | |
200 | #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ | |
201 | #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ | |
202 | #define HIFN_1_PLL 0x4c /* 795x: PLL config */ | |
203 | #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ | |
204 | #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ | |
205 | #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ | |
206 | #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ | |
207 | #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ | |
208 | #define HIFN_1_REVID 0x98 /* Revision ID */ | |
209 | #define HIFN_1_UNLOCK_SECRET1 0xf4 | |
210 | #define HIFN_1_UNLOCK_SECRET2 0xfc | |
211 | #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ | |
212 | #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ | |
213 | #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */ | |
214 | #define HIFN_1_PUB_OP 0x308 /* Public Operand */ | |
215 | #define HIFN_1_PUB_STATUS 0x30c /* Public Status */ | |
216 | #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ | |
217 | #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ | |
218 | #define HIFN_1_RNG_DATA 0x318 /* RNG data */ | |
219 | #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ | |
220 | #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ | |
221 | ||
222 | /* DMA Status and Control Register (HIFN_1_DMA_CSR) */ | |
223 | #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ | |
224 | #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ | |
225 | #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ | |
226 | #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ | |
227 | #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ | |
228 | #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ | |
229 | #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ | |
230 | #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ | |
231 | #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ | |
232 | #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ | |
233 | #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ | |
234 | #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ | |
235 | #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ | |
236 | #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ | |
237 | #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ | |
238 | #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ | |
239 | #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ | |
240 | #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ | |
241 | #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ | |
242 | #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ | |
243 | #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ | |
244 | #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ | |
245 | #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ | |
246 | #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ | |
247 | #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ | |
248 | #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ | |
249 | #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ | |
250 | #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ | |
251 | #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ | |
252 | #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ | |
253 | #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ | |
254 | #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ | |
255 | #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ | |
256 | #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ | |
257 | #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ | |
258 | #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ | |
259 | #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ | |
260 | #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ | |
261 | ||
262 | /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ | |
263 | #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ | |
264 | #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ | |
265 | #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ | |
266 | #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ | |
267 | #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ | |
268 | #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ | |
269 | #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ | |
270 | #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ | |
271 | #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ | |
272 | #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ | |
273 | #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ | |
274 | #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ | |
275 | #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ | |
276 | #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ | |
277 | #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ | |
278 | #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ | |
279 | #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ | |
280 | #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ | |
281 | #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ | |
282 | #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ | |
283 | #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ | |
284 | #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ | |
285 | ||
286 | /* DMA Configuration Register (HIFN_1_DMA_CNFG) */ | |
287 | #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ | |
288 | #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ | |
289 | #define HIFN_DMACNFG_UNLOCK 0x00000800 | |
290 | #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ | |
291 | #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ | |
292 | #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ | |
293 | #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ | |
294 | #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ | |
295 | ||
37a8023c PM |
296 | /* PLL configuration register */ |
297 | #define HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */ | |
298 | #define HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */ | |
299 | #define HIFN_PLL_BP 0x00000002 /* Reference clock bypass */ | |
300 | #define HIFN_PLL_PK_CLK_HBI 0x00000000 /* PK engine HBI clock */ | |
301 | #define HIFN_PLL_PK_CLK_PLL 0x00000008 /* PK engine PLL clock */ | |
302 | #define HIFN_PLL_PE_CLK_HBI 0x00000000 /* PE engine HBI clock */ | |
303 | #define HIFN_PLL_PE_CLK_PLL 0x00000010 /* PE engine PLL clock */ | |
304 | #define HIFN_PLL_RESERVED_1 0x00000400 /* Reserved bit, must be 1 */ | |
305 | #define HIFN_PLL_ND_SHIFT 11 /* Clock multiplier shift */ | |
306 | #define HIFN_PLL_ND_MULT_2 0x00000000 /* PLL clock multiplier 2 */ | |
307 | #define HIFN_PLL_ND_MULT_4 0x00000800 /* PLL clock multiplier 4 */ | |
308 | #define HIFN_PLL_ND_MULT_6 0x00001000 /* PLL clock multiplier 6 */ | |
309 | #define HIFN_PLL_ND_MULT_8 0x00001800 /* PLL clock multiplier 8 */ | |
310 | #define HIFN_PLL_ND_MULT_10 0x00002000 /* PLL clock multiplier 10 */ | |
311 | #define HIFN_PLL_ND_MULT_12 0x00002800 /* PLL clock multiplier 12 */ | |
312 | #define HIFN_PLL_IS_1_8 0x00000000 /* charge pump (mult. 1-8) */ | |
313 | #define HIFN_PLL_IS_9_12 0x00010000 /* charge pump (mult. 9-12) */ | |
314 | ||
315 | #define HIFN_PLL_FCK_MAX 266 /* Maximum PLL frequency */ | |
f7d0561e EP |
316 | |
317 | /* Public key reset register (HIFN_1_PUB_RESET) */ | |
318 | #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ | |
319 | ||
320 | /* Public base address register (HIFN_1_PUB_BASE) */ | |
321 | #define HIFN_PUBBASE_ADDR 0x00003fff /* base address */ | |
322 | ||
323 | /* Public operand length register (HIFN_1_PUB_OPLEN) */ | |
324 | #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */ | |
325 | #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */ | |
326 | #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */ | |
327 | #define HIFN_PUBOPLEN_EXP_S 7 /* exponent lenght shift */ | |
328 | #define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */ | |
329 | #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */ | |
330 | ||
331 | /* Public operation register (HIFN_1_PUB_OP) */ | |
332 | #define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */ | |
333 | #define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */ | |
334 | #define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */ | |
335 | #define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */ | |
336 | #define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */ | |
337 | #define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */ | |
338 | #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ | |
339 | #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ | |
340 | #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ | |
341 | #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ | |
342 | #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ | |
343 | #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ | |
344 | #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ | |
345 | #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ | |
346 | #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ | |
347 | #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ | |
348 | #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ | |
349 | #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ | |
350 | #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */ | |
351 | #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */ | |
352 | ||
353 | /* Public status register (HIFN_1_PUB_STATUS) */ | |
354 | #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ | |
355 | #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ | |
356 | ||
357 | /* Public interrupt enable register (HIFN_1_PUB_IEN) */ | |
358 | #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ | |
359 | ||
360 | /* Random number generator config register (HIFN_1_RNG_CONFIG) */ | |
361 | #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ | |
362 | ||
363 | #define HIFN_NAMESIZE 32 | |
364 | #define HIFN_MAX_RESULT_ORDER 5 | |
365 | ||
366 | #define HIFN_D_CMD_RSIZE 24*4 | |
367 | #define HIFN_D_SRC_RSIZE 80*4 | |
368 | #define HIFN_D_DST_RSIZE 80*4 | |
369 | #define HIFN_D_RES_RSIZE 24*4 | |
370 | ||
d069033b PM |
371 | #define HIFN_D_DST_DALIGN 4 |
372 | ||
6cd3d674 | 373 | #define HIFN_QUEUE_LENGTH HIFN_D_CMD_RSIZE-1 |
f7d0561e EP |
374 | |
375 | #define AES_MIN_KEY_SIZE 16 | |
376 | #define AES_MAX_KEY_SIZE 32 | |
377 | ||
378 | #define HIFN_DES_KEY_LENGTH 8 | |
379 | #define HIFN_3DES_KEY_LENGTH 24 | |
380 | #define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE | |
381 | #define HIFN_IV_LENGTH 8 | |
382 | #define HIFN_AES_IV_LENGTH 16 | |
383 | #define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH | |
384 | ||
385 | #define HIFN_MAC_KEY_LENGTH 64 | |
386 | #define HIFN_MD5_LENGTH 16 | |
387 | #define HIFN_SHA1_LENGTH 20 | |
388 | #define HIFN_MAC_TRUNC_LENGTH 12 | |
389 | ||
390 | #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) | |
391 | #define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4) | |
392 | #define HIFN_USED_RESULT 12 | |
393 | ||
394 | struct hifn_desc | |
395 | { | |
e68970cd AV |
396 | volatile __le32 l; |
397 | volatile __le32 p; | |
f7d0561e EP |
398 | }; |
399 | ||
400 | struct hifn_dma { | |
401 | struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; | |
402 | struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; | |
403 | struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; | |
404 | struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; | |
405 | ||
406 | u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; | |
407 | u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; | |
408 | ||
409 | u64 test_src, test_dst; | |
410 | ||
411 | /* | |
412 | * Our current positions for insertion and removal from the descriptor | |
413 | * rings. | |
414 | */ | |
415 | volatile int cmdi, srci, dsti, resi; | |
416 | volatile int cmdu, srcu, dstu, resu; | |
417 | int cmdk, srck, dstk, resk; | |
418 | }; | |
419 | ||
420 | #define HIFN_FLAG_CMD_BUSY (1<<0) | |
421 | #define HIFN_FLAG_SRC_BUSY (1<<1) | |
422 | #define HIFN_FLAG_DST_BUSY (1<<2) | |
423 | #define HIFN_FLAG_RES_BUSY (1<<3) | |
424 | #define HIFN_FLAG_OLD_KEY (1<<4) | |
425 | ||
426 | #define HIFN_DEFAULT_ACTIVE_NUM 5 | |
427 | ||
428 | struct hifn_device | |
429 | { | |
430 | char name[HIFN_NAMESIZE]; | |
431 | ||
432 | int irq; | |
433 | ||
434 | struct pci_dev *pdev; | |
435 | void __iomem *bar[3]; | |
436 | ||
437 | unsigned long result_mem; | |
438 | dma_addr_t dst; | |
439 | ||
440 | void *desc_virt; | |
441 | dma_addr_t desc_dma; | |
442 | ||
443 | u32 dmareg; | |
444 | ||
445 | void *sa[HIFN_D_RES_RSIZE]; | |
446 | ||
447 | spinlock_t lock; | |
448 | ||
449 | void *priv; | |
450 | ||
451 | u32 flags; | |
452 | int active, started; | |
453 | struct delayed_work work; | |
454 | unsigned long reset; | |
455 | unsigned long success; | |
456 | unsigned long prev_success; | |
457 | ||
458 | u8 snum; | |
459 | ||
a1e6ef2f EP |
460 | struct tasklet_struct tasklet; |
461 | ||
f7d0561e EP |
462 | struct crypto_queue queue; |
463 | struct list_head alg_list; | |
fcd06755 PM |
464 | |
465 | unsigned int pk_clk_freq; | |
466 | ||
f881d829 | 467 | #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG |
fcd06755 PM |
468 | unsigned int rng_wait_time; |
469 | ktime_t rngtime; | |
470 | struct hwrng rng; | |
471 | #endif | |
f7d0561e EP |
472 | }; |
473 | ||
474 | #define HIFN_D_LENGTH 0x0000ffff | |
475 | #define HIFN_D_NOINVALID 0x01000000 | |
476 | #define HIFN_D_MASKDONEIRQ 0x02000000 | |
477 | #define HIFN_D_DESTOVER 0x04000000 | |
478 | #define HIFN_D_OVER 0x08000000 | |
479 | #define HIFN_D_LAST 0x20000000 | |
480 | #define HIFN_D_JUMP 0x40000000 | |
481 | #define HIFN_D_VALID 0x80000000 | |
482 | ||
483 | struct hifn_base_command | |
484 | { | |
e68970cd AV |
485 | volatile __le16 masks; |
486 | volatile __le16 session_num; | |
487 | volatile __le16 total_source_count; | |
488 | volatile __le16 total_dest_count; | |
f7d0561e EP |
489 | }; |
490 | ||
491 | #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */ | |
492 | #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */ | |
493 | #define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */ | |
494 | #define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */ | |
495 | #define HIFN_BASE_CMD_DECODE 0x2000 | |
496 | #define HIFN_BASE_CMD_SRCLEN_M 0xc000 | |
497 | #define HIFN_BASE_CMD_SRCLEN_S 14 | |
498 | #define HIFN_BASE_CMD_DSTLEN_M 0x3000 | |
499 | #define HIFN_BASE_CMD_DSTLEN_S 12 | |
500 | #define HIFN_BASE_CMD_LENMASK_HI 0x30000 | |
501 | #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff | |
502 | ||
503 | /* | |
504 | * Structure to help build up the command data structure. | |
505 | */ | |
506 | struct hifn_crypt_command | |
507 | { | |
e68970cd AV |
508 | volatile __le16 masks; |
509 | volatile __le16 header_skip; | |
510 | volatile __le16 source_count; | |
511 | volatile __le16 reserved; | |
f7d0561e EP |
512 | }; |
513 | ||
514 | #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ | |
515 | #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ | |
516 | #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ | |
517 | #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ | |
518 | #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ | |
519 | #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ | |
520 | #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ | |
521 | #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ | |
522 | #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ | |
523 | #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ | |
524 | #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ | |
525 | #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ | |
526 | #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ | |
527 | #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ | |
528 | #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ | |
529 | #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ | |
530 | #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ | |
531 | #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 | |
532 | #define HIFN_CRYPT_CMD_SRCLEN_S 14 | |
533 | ||
534 | /* | |
535 | * Structure to help build up the command data structure. | |
536 | */ | |
537 | struct hifn_mac_command | |
538 | { | |
3c42cbc2 PM |
539 | volatile __le16 masks; |
540 | volatile __le16 header_skip; | |
541 | volatile __le16 source_count; | |
542 | volatile __le16 reserved; | |
f7d0561e EP |
543 | }; |
544 | ||
545 | #define HIFN_MAC_CMD_ALG_MASK 0x0001 | |
546 | #define HIFN_MAC_CMD_ALG_SHA1 0x0000 | |
547 | #define HIFN_MAC_CMD_ALG_MD5 0x0001 | |
548 | #define HIFN_MAC_CMD_MODE_MASK 0x000c | |
549 | #define HIFN_MAC_CMD_MODE_HMAC 0x0000 | |
550 | #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 | |
551 | #define HIFN_MAC_CMD_MODE_HASH 0x0008 | |
552 | #define HIFN_MAC_CMD_MODE_FULL 0x0004 | |
553 | #define HIFN_MAC_CMD_TRUNC 0x0010 | |
554 | #define HIFN_MAC_CMD_RESULT 0x0020 | |
555 | #define HIFN_MAC_CMD_APPEND 0x0040 | |
556 | #define HIFN_MAC_CMD_SRCLEN_M 0xc000 | |
557 | #define HIFN_MAC_CMD_SRCLEN_S 14 | |
558 | ||
559 | /* | |
560 | * MAC POS IPsec initiates authentication after encryption on encodes | |
561 | * and before decryption on decodes. | |
562 | */ | |
563 | #define HIFN_MAC_CMD_POS_IPSEC 0x0200 | |
564 | #define HIFN_MAC_CMD_NEW_KEY 0x0800 | |
565 | ||
566 | struct hifn_comp_command | |
567 | { | |
3c42cbc2 PM |
568 | volatile __le16 masks; |
569 | volatile __le16 header_skip; | |
570 | volatile __le16 source_count; | |
571 | volatile __le16 reserved; | |
f7d0561e EP |
572 | }; |
573 | ||
574 | #define HIFN_COMP_CMD_SRCLEN_M 0xc000 | |
575 | #define HIFN_COMP_CMD_SRCLEN_S 14 | |
576 | #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */ | |
577 | #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */ | |
578 | #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */ | |
579 | #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */ | |
580 | #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */ | |
581 | #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */ | |
582 | #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */ | |
583 | #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */ | |
584 | ||
585 | struct hifn_base_result | |
586 | { | |
3c42cbc2 PM |
587 | volatile __le16 flags; |
588 | volatile __le16 session; | |
589 | volatile __le16 src_cnt; /* 15:0 of source count */ | |
590 | volatile __le16 dst_cnt; /* 15:0 of dest count */ | |
f7d0561e EP |
591 | }; |
592 | ||
593 | #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */ | |
594 | #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */ | |
595 | #define HIFN_BASE_RES_SRCLEN_S 14 | |
596 | #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */ | |
597 | #define HIFN_BASE_RES_DSTLEN_S 12 | |
598 | ||
599 | struct hifn_comp_result | |
600 | { | |
3c42cbc2 PM |
601 | volatile __le16 flags; |
602 | volatile __le16 crc; | |
f7d0561e EP |
603 | }; |
604 | ||
605 | #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */ | |
606 | #define HIFN_COMP_RES_LCB_S 8 | |
607 | #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */ | |
608 | #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */ | |
609 | #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */ | |
610 | ||
611 | struct hifn_mac_result | |
612 | { | |
3c42cbc2 PM |
613 | volatile __le16 flags; |
614 | volatile __le16 reserved; | |
f7d0561e EP |
615 | /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */ |
616 | }; | |
617 | ||
618 | #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */ | |
619 | #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */ | |
620 | ||
621 | struct hifn_crypt_result | |
622 | { | |
3c42cbc2 PM |
623 | volatile __le16 flags; |
624 | volatile __le16 reserved; | |
f7d0561e EP |
625 | }; |
626 | ||
627 | #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */ | |
628 | ||
629 | #ifndef HIFN_POLL_FREQUENCY | |
630 | #define HIFN_POLL_FREQUENCY 0x1 | |
631 | #endif | |
632 | ||
633 | #ifndef HIFN_POLL_SCALAR | |
634 | #define HIFN_POLL_SCALAR 0x0 | |
635 | #endif | |
636 | ||
637 | #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ | |
638 | #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ | |
639 | ||
640 | struct hifn_crypto_alg | |
641 | { | |
642 | struct list_head entry; | |
643 | struct crypto_alg alg; | |
644 | struct hifn_device *dev; | |
645 | }; | |
646 | ||
647 | #define ASYNC_SCATTERLIST_CACHE 16 | |
648 | ||
649 | #define ASYNC_FLAGS_MISALIGNED (1<<0) | |
650 | ||
651 | struct ablkcipher_walk | |
652 | { | |
653 | struct scatterlist cache[ASYNC_SCATTERLIST_CACHE]; | |
654 | u32 flags; | |
655 | int num; | |
656 | }; | |
657 | ||
658 | struct hifn_context | |
659 | { | |
660 | u8 key[HIFN_MAX_CRYPT_KEY_LENGTH], *iv; | |
661 | struct hifn_device *dev; | |
662 | unsigned int keysize, ivsize; | |
663 | u8 op, type, mode, unused; | |
664 | struct ablkcipher_walk walk; | |
f7d0561e EP |
665 | }; |
666 | ||
b966b546 | 667 | #define crypto_alg_to_hifn(a) container_of(a, struct hifn_crypto_alg, alg) |
f7d0561e EP |
668 | |
669 | static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg) | |
670 | { | |
671 | u32 ret; | |
672 | ||
e68970cd | 673 | ret = readl(dev->bar[0] + reg); |
f7d0561e EP |
674 | |
675 | return ret; | |
676 | } | |
677 | ||
678 | static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg) | |
679 | { | |
680 | u32 ret; | |
681 | ||
e68970cd | 682 | ret = readl(dev->bar[1] + reg); |
f7d0561e EP |
683 | |
684 | return ret; | |
685 | } | |
686 | ||
687 | static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val) | |
688 | { | |
3c42cbc2 | 689 | writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg); |
f7d0561e EP |
690 | } |
691 | ||
692 | static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val) | |
693 | { | |
3c42cbc2 | 694 | writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg); |
f7d0561e EP |
695 | } |
696 | ||
697 | static void hifn_wait_puc(struct hifn_device *dev) | |
698 | { | |
699 | int i; | |
700 | u32 ret; | |
701 | ||
702 | for (i=10000; i > 0; --i) { | |
703 | ret = hifn_read_0(dev, HIFN_0_PUCTRL); | |
704 | if (!(ret & HIFN_PUCTRL_RESET)) | |
705 | break; | |
706 | ||
707 | udelay(1); | |
708 | } | |
709 | ||
710 | if (!i) | |
711 | dprintk("%s: Failed to reset PUC unit.\n", dev->name); | |
712 | } | |
713 | ||
714 | static void hifn_reset_puc(struct hifn_device *dev) | |
715 | { | |
716 | hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); | |
717 | hifn_wait_puc(dev); | |
718 | } | |
719 | ||
720 | static void hifn_stop_device(struct hifn_device *dev) | |
721 | { | |
722 | hifn_write_1(dev, HIFN_1_DMA_CSR, | |
723 | HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | | |
724 | HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS); | |
725 | hifn_write_0(dev, HIFN_0_PUIER, 0); | |
726 | hifn_write_1(dev, HIFN_1_DMA_IER, 0); | |
727 | } | |
728 | ||
729 | static void hifn_reset_dma(struct hifn_device *dev, int full) | |
730 | { | |
731 | hifn_stop_device(dev); | |
732 | ||
733 | /* | |
734 | * Setting poll frequency and others to 0. | |
735 | */ | |
736 | hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | | |
737 | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); | |
738 | mdelay(1); | |
739 | ||
740 | /* | |
741 | * Reset DMA. | |
742 | */ | |
743 | if (full) { | |
744 | hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); | |
745 | mdelay(1); | |
746 | } else { | |
747 | hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE | | |
748 | HIFN_DMACNFG_MSTRESET); | |
749 | hifn_reset_puc(dev); | |
750 | } | |
751 | ||
752 | hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | | |
753 | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); | |
754 | ||
755 | hifn_reset_puc(dev); | |
756 | } | |
757 | ||
758 | static u32 hifn_next_signature(u_int32_t a, u_int cnt) | |
759 | { | |
760 | int i; | |
761 | u32 v; | |
762 | ||
763 | for (i = 0; i < cnt; i++) { | |
764 | ||
765 | /* get the parity */ | |
766 | v = a & 0x80080125; | |
767 | v ^= v >> 16; | |
768 | v ^= v >> 8; | |
769 | v ^= v >> 4; | |
770 | v ^= v >> 2; | |
771 | v ^= v >> 1; | |
772 | ||
773 | a = (v & 1) ^ (a << 1); | |
774 | } | |
775 | ||
776 | return a; | |
777 | } | |
778 | ||
779 | static struct pci2id { | |
780 | u_short pci_vendor; | |
781 | u_short pci_prod; | |
782 | char card_id[13]; | |
783 | } pci2id[] = { | |
784 | { | |
785 | PCI_VENDOR_ID_HIFN, | |
786 | PCI_DEVICE_ID_HIFN_7955, | |
787 | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
788 | 0x00, 0x00, 0x00, 0x00, 0x00 } | |
789 | }, | |
790 | { | |
791 | PCI_VENDOR_ID_HIFN, | |
792 | PCI_DEVICE_ID_HIFN_7956, | |
793 | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
794 | 0x00, 0x00, 0x00, 0x00, 0x00 } | |
795 | } | |
796 | }; | |
797 | ||
f881d829 | 798 | #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG |
fcd06755 PM |
799 | static int hifn_rng_data_present(struct hwrng *rng, int wait) |
800 | { | |
801 | struct hifn_device *dev = (struct hifn_device *)rng->priv; | |
802 | s64 nsec; | |
803 | ||
804 | nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime)); | |
805 | nsec -= dev->rng_wait_time; | |
806 | if (nsec <= 0) | |
807 | return 1; | |
808 | if (!wait) | |
809 | return 0; | |
810 | ndelay(nsec); | |
811 | return 1; | |
812 | } | |
813 | ||
814 | static int hifn_rng_data_read(struct hwrng *rng, u32 *data) | |
815 | { | |
816 | struct hifn_device *dev = (struct hifn_device *)rng->priv; | |
817 | ||
818 | *data = hifn_read_1(dev, HIFN_1_RNG_DATA); | |
819 | dev->rngtime = ktime_get(); | |
820 | return 4; | |
821 | } | |
822 | ||
823 | static int hifn_register_rng(struct hifn_device *dev) | |
824 | { | |
825 | /* | |
826 | * We must wait at least 256 Pk_clk cycles between two reads of the rng. | |
827 | */ | |
828 | dev->rng_wait_time = DIV_ROUND_UP(NSEC_PER_SEC, dev->pk_clk_freq) * | |
829 | 256; | |
830 | ||
831 | dev->rng.name = dev->name; | |
832 | dev->rng.data_present = hifn_rng_data_present, | |
833 | dev->rng.data_read = hifn_rng_data_read, | |
834 | dev->rng.priv = (unsigned long)dev; | |
835 | ||
836 | return hwrng_register(&dev->rng); | |
837 | } | |
838 | ||
839 | static void hifn_unregister_rng(struct hifn_device *dev) | |
840 | { | |
841 | hwrng_unregister(&dev->rng); | |
842 | } | |
843 | #else | |
844 | #define hifn_register_rng(dev) 0 | |
845 | #define hifn_unregister_rng(dev) | |
846 | #endif | |
847 | ||
f7d0561e EP |
848 | static int hifn_init_pubrng(struct hifn_device *dev) |
849 | { | |
850 | int i; | |
851 | ||
852 | hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) | | |
853 | HIFN_PUBRST_RESET); | |
854 | ||
855 | for (i=100; i > 0; --i) { | |
856 | mdelay(1); | |
857 | ||
858 | if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0) | |
859 | break; | |
860 | } | |
861 | ||
862 | if (!i) | |
863 | dprintk("Chip %s: Failed to initialise public key engine.\n", | |
864 | dev->name); | |
865 | else { | |
866 | hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); | |
867 | dev->dmareg |= HIFN_DMAIER_PUBDONE; | |
868 | hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); | |
869 | ||
870 | dprintk("Chip %s: Public key engine has been sucessfully " | |
871 | "initialised.\n", dev->name); | |
872 | } | |
873 | ||
874 | /* | |
875 | * Enable RNG engine. | |
876 | */ | |
877 | ||
878 | hifn_write_1(dev, HIFN_1_RNG_CONFIG, | |
879 | hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA); | |
880 | dprintk("Chip %s: RNG engine has been successfully initialised.\n", | |
881 | dev->name); | |
882 | ||
f881d829 | 883 | #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG |
fcd06755 PM |
884 | /* First value must be discarded */ |
885 | hifn_read_1(dev, HIFN_1_RNG_DATA); | |
886 | dev->rngtime = ktime_get(); | |
887 | #endif | |
f7d0561e EP |
888 | return 0; |
889 | } | |
890 | ||
891 | static int hifn_enable_crypto(struct hifn_device *dev) | |
892 | { | |
893 | u32 dmacfg, addr; | |
894 | char *offtbl = NULL; | |
895 | int i; | |
896 | ||
0936a944 | 897 | for (i = 0; i < ARRAY_SIZE(pci2id); i++) { |
f7d0561e EP |
898 | if (pci2id[i].pci_vendor == dev->pdev->vendor && |
899 | pci2id[i].pci_prod == dev->pdev->device) { | |
900 | offtbl = pci2id[i].card_id; | |
901 | break; | |
902 | } | |
903 | } | |
904 | ||
905 | if (offtbl == NULL) { | |
906 | dprintk("Chip %s: Unknown card!\n", dev->name); | |
907 | return -ENODEV; | |
908 | } | |
909 | ||
910 | dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG); | |
911 | ||
912 | hifn_write_1(dev, HIFN_1_DMA_CNFG, | |
913 | HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET | | |
914 | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); | |
915 | mdelay(1); | |
916 | addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1); | |
917 | mdelay(1); | |
918 | hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0); | |
919 | mdelay(1); | |
920 | ||
921 | for (i=0; i<12; ++i) { | |
922 | addr = hifn_next_signature(addr, offtbl[i] + 0x101); | |
923 | hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr); | |
924 | ||
925 | mdelay(1); | |
926 | } | |
927 | hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg); | |
928 | ||
929 | dprintk("Chip %s: %s.\n", dev->name, pci_name(dev->pdev)); | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
934 | static void hifn_init_dma(struct hifn_device *dev) | |
935 | { | |
936 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
937 | u32 dptr = dev->desc_dma; | |
938 | int i; | |
939 | ||
940 | for (i=0; i<HIFN_D_CMD_RSIZE; ++i) | |
941 | dma->cmdr[i].p = __cpu_to_le32(dptr + | |
942 | offsetof(struct hifn_dma, command_bufs[i][0])); | |
943 | for (i=0; i<HIFN_D_RES_RSIZE; ++i) | |
944 | dma->resr[i].p = __cpu_to_le32(dptr + | |
945 | offsetof(struct hifn_dma, result_bufs[i][0])); | |
946 | ||
947 | /* | |
948 | * Setup LAST descriptors. | |
949 | */ | |
950 | dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr + | |
951 | offsetof(struct hifn_dma, cmdr[0])); | |
952 | dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr + | |
953 | offsetof(struct hifn_dma, srcr[0])); | |
954 | dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr + | |
955 | offsetof(struct hifn_dma, dstr[0])); | |
956 | dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr + | |
957 | offsetof(struct hifn_dma, resr[0])); | |
958 | ||
959 | dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; | |
960 | dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; | |
961 | dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; | |
962 | } | |
963 | ||
37a8023c PM |
964 | /* |
965 | * Initialize the PLL. We need to know the frequency of the reference clock | |
966 | * to calculate the optimal multiplier. For PCI we assume 66MHz, since that | |
967 | * allows us to operate without the risk of overclocking the chip. If it | |
968 | * actually uses 33MHz, the chip will operate at half the speed, this can be | |
969 | * overriden by specifying the frequency as module parameter (pci33). | |
970 | * | |
971 | * Unfortunately the PCI clock is not very suitable since the HIFN needs a | |
972 | * stable clock and the PCI clock frequency may vary, so the default is the | |
973 | * external clock. There is no way to find out its frequency, we default to | |
974 | * 66MHz since according to Mike Ham of HiFn, almost every board in existence | |
975 | * has an external crystal populated at 66MHz. | |
976 | */ | |
977 | static void hifn_init_pll(struct hifn_device *dev) | |
978 | { | |
979 | unsigned int freq, m; | |
980 | u32 pllcfg; | |
981 | ||
982 | pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1; | |
983 | ||
984 | if (strncmp(hifn_pll_ref, "ext", 3) == 0) | |
985 | pllcfg |= HIFN_PLL_REF_CLK_PLL; | |
986 | else | |
987 | pllcfg |= HIFN_PLL_REF_CLK_HBI; | |
988 | ||
989 | if (hifn_pll_ref[3] != '\0') | |
990 | freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10); | |
991 | else { | |
992 | freq = 66; | |
993 | printk(KERN_INFO "hifn795x: assuming %uMHz clock speed, " | |
994 | "override with hifn_pll_ref=%.3s<frequency>\n", | |
995 | freq, hifn_pll_ref); | |
996 | } | |
997 | ||
998 | m = HIFN_PLL_FCK_MAX / freq; | |
999 | ||
1000 | pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT; | |
1001 | if (m <= 8) | |
1002 | pllcfg |= HIFN_PLL_IS_1_8; | |
1003 | else | |
1004 | pllcfg |= HIFN_PLL_IS_9_12; | |
1005 | ||
1006 | /* Select clock source and enable clock bypass */ | |
1007 | hifn_write_1(dev, HIFN_1_PLL, pllcfg | | |
1008 | HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP); | |
1009 | ||
1010 | /* Let the chip lock to the input clock */ | |
1011 | mdelay(10); | |
1012 | ||
1013 | /* Disable clock bypass */ | |
1014 | hifn_write_1(dev, HIFN_1_PLL, pllcfg | | |
1015 | HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI); | |
1016 | ||
1017 | /* Switch the engines to the PLL */ | |
1018 | hifn_write_1(dev, HIFN_1_PLL, pllcfg | | |
1019 | HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL); | |
fcd06755 PM |
1020 | |
1021 | /* | |
1022 | * The Fpk_clk runs at half the total speed. Its frequency is needed to | |
1023 | * calculate the minimum time between two reads of the rng. Since 33MHz | |
1024 | * is actually 33.333... we overestimate the frequency here, resulting | |
1025 | * in slightly larger intervals. | |
1026 | */ | |
1027 | dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2; | |
37a8023c PM |
1028 | } |
1029 | ||
f7d0561e EP |
1030 | static void hifn_init_registers(struct hifn_device *dev) |
1031 | { | |
1032 | u32 dptr = dev->desc_dma; | |
1033 | ||
1034 | /* Initialization magic... */ | |
1035 | hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); | |
1036 | hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); | |
1037 | hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); | |
1038 | ||
1039 | /* write all 4 ring address registers */ | |
3c42cbc2 PM |
1040 | hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr + |
1041 | offsetof(struct hifn_dma, cmdr[0])); | |
1042 | hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr + | |
1043 | offsetof(struct hifn_dma, srcr[0])); | |
1044 | hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr + | |
1045 | offsetof(struct hifn_dma, dstr[0])); | |
1046 | hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr + | |
1047 | offsetof(struct hifn_dma, resr[0])); | |
f7d0561e EP |
1048 | |
1049 | mdelay(2); | |
1050 | #if 0 | |
1051 | hifn_write_1(dev, HIFN_1_DMA_CSR, | |
1052 | HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | | |
1053 | HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | | |
1054 | HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | | |
1055 | HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | | |
1056 | HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | | |
1057 | HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | | |
1058 | HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | | |
1059 | HIFN_DMACSR_S_WAIT | | |
1060 | HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | | |
1061 | HIFN_DMACSR_C_WAIT | | |
1062 | HIFN_DMACSR_ENGINE | | |
1063 | HIFN_DMACSR_PUBDONE); | |
1064 | #else | |
1065 | hifn_write_1(dev, HIFN_1_DMA_CSR, | |
1066 | HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | | |
1067 | HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA | | |
1068 | HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | | |
1069 | HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | | |
1070 | HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | | |
1071 | HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | | |
1072 | HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | | |
1073 | HIFN_DMACSR_S_WAIT | | |
1074 | HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | | |
1075 | HIFN_DMACSR_C_WAIT | | |
1076 | HIFN_DMACSR_ENGINE | | |
1077 | HIFN_DMACSR_PUBDONE); | |
1078 | #endif | |
1079 | hifn_read_1(dev, HIFN_1_DMA_CSR); | |
1080 | ||
1081 | dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | | |
1082 | HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | | |
1083 | HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | | |
1084 | HIFN_DMAIER_ENGINE; | |
1085 | dev->dmareg &= ~HIFN_DMAIER_C_WAIT; | |
1086 | ||
1087 | hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); | |
1088 | hifn_read_1(dev, HIFN_1_DMA_IER); | |
1089 | #if 0 | |
1090 | hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG | | |
1091 | HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | | |
1092 | HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | | |
1093 | HIFN_PUCNFG_DRAM); | |
1094 | #else | |
1095 | hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342); | |
1096 | #endif | |
37a8023c | 1097 | hifn_init_pll(dev); |
f7d0561e EP |
1098 | |
1099 | hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); | |
1100 | hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | | |
1101 | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | | |
1102 | ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | | |
1103 | ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); | |
1104 | } | |
1105 | ||
1106 | static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf, | |
1107 | unsigned dlen, unsigned slen, u16 mask, u8 snum) | |
1108 | { | |
1109 | struct hifn_base_command *base_cmd; | |
1110 | u8 *buf_pos = buf; | |
1111 | ||
1112 | base_cmd = (struct hifn_base_command *)buf_pos; | |
1113 | base_cmd->masks = __cpu_to_le16(mask); | |
1114 | base_cmd->total_source_count = | |
1115 | __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO); | |
1116 | base_cmd->total_dest_count = | |
1117 | __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO); | |
1118 | ||
1119 | dlen >>= 16; | |
1120 | slen >>= 16; | |
1121 | base_cmd->session_num = __cpu_to_le16(snum | | |
1122 | ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | | |
1123 | ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); | |
1124 | ||
1125 | return sizeof(struct hifn_base_command); | |
1126 | } | |
1127 | ||
1128 | static int hifn_setup_crypto_command(struct hifn_device *dev, | |
1129 | u8 *buf, unsigned dlen, unsigned slen, | |
1130 | u8 *key, int keylen, u8 *iv, int ivsize, u16 mode) | |
1131 | { | |
1132 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1133 | struct hifn_crypt_command *cry_cmd; | |
1134 | u8 *buf_pos = buf; | |
1135 | u16 cmd_len; | |
1136 | ||
1137 | cry_cmd = (struct hifn_crypt_command *)buf_pos; | |
1138 | ||
1139 | cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff); | |
1140 | dlen >>= 16; | |
1141 | cry_cmd->masks = __cpu_to_le16(mode | | |
1142 | ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & | |
1143 | HIFN_CRYPT_CMD_SRCLEN_M)); | |
1144 | cry_cmd->header_skip = 0; | |
1145 | cry_cmd->reserved = 0; | |
1146 | ||
1147 | buf_pos += sizeof(struct hifn_crypt_command); | |
1148 | ||
1149 | dma->cmdu++; | |
1150 | if (dma->cmdu > 1) { | |
1151 | dev->dmareg |= HIFN_DMAIER_C_WAIT; | |
1152 | hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); | |
1153 | } | |
1154 | ||
1155 | if (keylen) { | |
1156 | memcpy(buf_pos, key, keylen); | |
1157 | buf_pos += keylen; | |
1158 | } | |
1159 | if (ivsize) { | |
1160 | memcpy(buf_pos, iv, ivsize); | |
1161 | buf_pos += ivsize; | |
1162 | } | |
1163 | ||
1164 | cmd_len = buf_pos - buf; | |
1165 | ||
1166 | return cmd_len; | |
1167 | } | |
1168 | ||
85e7e60b PM |
1169 | static int hifn_setup_cmd_desc(struct hifn_device *dev, |
1170 | struct hifn_context *ctx, void *priv, unsigned int nbytes) | |
f7d0561e EP |
1171 | { |
1172 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1173 | int cmd_len, sa_idx; | |
1174 | u8 *buf, *buf_pos; | |
1175 | u16 mask; | |
1176 | ||
85e7e60b | 1177 | sa_idx = dma->cmdi; |
f7d0561e EP |
1178 | buf_pos = buf = dma->command_bufs[dma->cmdi]; |
1179 | ||
1180 | mask = 0; | |
1181 | switch (ctx->op) { | |
1182 | case ACRYPTO_OP_DECRYPT: | |
1183 | mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE; | |
1184 | break; | |
1185 | case ACRYPTO_OP_ENCRYPT: | |
1186 | mask = HIFN_BASE_CMD_CRYPT; | |
1187 | break; | |
1188 | case ACRYPTO_OP_HMAC: | |
1189 | mask = HIFN_BASE_CMD_MAC; | |
1190 | break; | |
1191 | default: | |
1192 | goto err_out; | |
1193 | } | |
1194 | ||
1195 | buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes, | |
1196 | nbytes, mask, dev->snum); | |
1197 | ||
1198 | if (ctx->op == ACRYPTO_OP_ENCRYPT || ctx->op == ACRYPTO_OP_DECRYPT) { | |
1199 | u16 md = 0; | |
1200 | ||
1201 | if (ctx->keysize) | |
1202 | md |= HIFN_CRYPT_CMD_NEW_KEY; | |
1203 | if (ctx->iv && ctx->mode != ACRYPTO_MODE_ECB) | |
1204 | md |= HIFN_CRYPT_CMD_NEW_IV; | |
1205 | ||
1206 | switch (ctx->mode) { | |
1207 | case ACRYPTO_MODE_ECB: | |
1208 | md |= HIFN_CRYPT_CMD_MODE_ECB; | |
1209 | break; | |
1210 | case ACRYPTO_MODE_CBC: | |
1211 | md |= HIFN_CRYPT_CMD_MODE_CBC; | |
1212 | break; | |
1213 | case ACRYPTO_MODE_CFB: | |
1214 | md |= HIFN_CRYPT_CMD_MODE_CFB; | |
1215 | break; | |
1216 | case ACRYPTO_MODE_OFB: | |
1217 | md |= HIFN_CRYPT_CMD_MODE_OFB; | |
1218 | break; | |
1219 | default: | |
1220 | goto err_out; | |
1221 | } | |
1222 | ||
1223 | switch (ctx->type) { | |
1224 | case ACRYPTO_TYPE_AES_128: | |
1225 | if (ctx->keysize != 16) | |
1226 | goto err_out; | |
1227 | md |= HIFN_CRYPT_CMD_KSZ_128 | | |
1228 | HIFN_CRYPT_CMD_ALG_AES; | |
1229 | break; | |
1230 | case ACRYPTO_TYPE_AES_192: | |
1231 | if (ctx->keysize != 24) | |
1232 | goto err_out; | |
1233 | md |= HIFN_CRYPT_CMD_KSZ_192 | | |
1234 | HIFN_CRYPT_CMD_ALG_AES; | |
1235 | break; | |
1236 | case ACRYPTO_TYPE_AES_256: | |
1237 | if (ctx->keysize != 32) | |
1238 | goto err_out; | |
1239 | md |= HIFN_CRYPT_CMD_KSZ_256 | | |
1240 | HIFN_CRYPT_CMD_ALG_AES; | |
1241 | break; | |
1242 | case ACRYPTO_TYPE_3DES: | |
1243 | if (ctx->keysize != 24) | |
1244 | goto err_out; | |
1245 | md |= HIFN_CRYPT_CMD_ALG_3DES; | |
1246 | break; | |
1247 | case ACRYPTO_TYPE_DES: | |
1248 | if (ctx->keysize != 8) | |
1249 | goto err_out; | |
1250 | md |= HIFN_CRYPT_CMD_ALG_DES; | |
1251 | break; | |
1252 | default: | |
1253 | goto err_out; | |
1254 | } | |
1255 | ||
1256 | buf_pos += hifn_setup_crypto_command(dev, buf_pos, | |
1257 | nbytes, nbytes, ctx->key, ctx->keysize, | |
1258 | ctx->iv, ctx->ivsize, md); | |
1259 | } | |
1260 | ||
1261 | dev->sa[sa_idx] = priv; | |
1262 | ||
1263 | cmd_len = buf_pos - buf; | |
1264 | dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID | | |
1265 | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); | |
1266 | ||
1267 | if (++dma->cmdi == HIFN_D_CMD_RSIZE) { | |
1268 | dma->cmdr[dma->cmdi].l = __cpu_to_le32(HIFN_MAX_COMMAND | | |
1269 | HIFN_D_VALID | HIFN_D_LAST | | |
1270 | HIFN_D_MASKDONEIRQ | HIFN_D_JUMP); | |
1271 | dma->cmdi = 0; | |
1272 | } else | |
1273 | dma->cmdr[dma->cmdi-1].l |= __cpu_to_le32(HIFN_D_VALID); | |
1274 | ||
1275 | if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) { | |
1276 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); | |
1277 | dev->flags |= HIFN_FLAG_CMD_BUSY; | |
1278 | } | |
f7d0561e EP |
1279 | return 0; |
1280 | ||
1281 | err_out: | |
1282 | return -EINVAL; | |
1283 | } | |
1284 | ||
85e7e60b | 1285 | static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page, |
75741a03 | 1286 | unsigned int offset, unsigned int size, int last) |
85e7e60b PM |
1287 | { |
1288 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1289 | int idx; | |
1290 | dma_addr_t addr; | |
1291 | ||
1292 | addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE); | |
1293 | ||
1294 | idx = dma->srci; | |
1295 | ||
1296 | dma->srcr[idx].p = __cpu_to_le32(addr); | |
1297 | dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | | |
75741a03 | 1298 | HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0)); |
85e7e60b PM |
1299 | |
1300 | if (++idx == HIFN_D_SRC_RSIZE) { | |
1301 | dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID | | |
75741a03 PM |
1302 | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | |
1303 | (last ? HIFN_D_LAST : 0)); | |
85e7e60b PM |
1304 | idx = 0; |
1305 | } | |
1306 | ||
1307 | dma->srci = idx; | |
1308 | dma->srcu++; | |
1309 | ||
1310 | if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) { | |
1311 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); | |
1312 | dev->flags |= HIFN_FLAG_SRC_BUSY; | |
1313 | } | |
1314 | ||
1315 | return size; | |
1316 | } | |
1317 | ||
1318 | static void hifn_setup_res_desc(struct hifn_device *dev) | |
1319 | { | |
1320 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1321 | ||
1322 | dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT | | |
1323 | HIFN_D_VALID | HIFN_D_LAST); | |
1324 | /* | |
1325 | * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID | | |
692af5da | 1326 | * HIFN_D_LAST); |
85e7e60b PM |
1327 | */ |
1328 | ||
1329 | if (++dma->resi == HIFN_D_RES_RSIZE) { | |
1330 | dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID | | |
1331 | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST); | |
1332 | dma->resi = 0; | |
1333 | } | |
1334 | ||
1335 | dma->resu++; | |
1336 | ||
1337 | if (!(dev->flags & HIFN_FLAG_RES_BUSY)) { | |
1338 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); | |
1339 | dev->flags |= HIFN_FLAG_RES_BUSY; | |
1340 | } | |
1341 | } | |
1342 | ||
1343 | static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page, | |
75741a03 | 1344 | unsigned offset, unsigned size, int last) |
85e7e60b PM |
1345 | { |
1346 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1347 | int idx; | |
1348 | dma_addr_t addr; | |
1349 | ||
1350 | addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE); | |
1351 | ||
1352 | idx = dma->dsti; | |
1353 | dma->dstr[idx].p = __cpu_to_le32(addr); | |
1354 | dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | | |
75741a03 | 1355 | HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0)); |
85e7e60b PM |
1356 | |
1357 | if (++idx == HIFN_D_DST_RSIZE) { | |
1358 | dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID | | |
1359 | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | | |
75741a03 | 1360 | (last ? HIFN_D_LAST : 0)); |
85e7e60b PM |
1361 | idx = 0; |
1362 | } | |
1363 | dma->dsti = idx; | |
1364 | dma->dstu++; | |
1365 | ||
1366 | if (!(dev->flags & HIFN_FLAG_DST_BUSY)) { | |
1367 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); | |
1368 | dev->flags |= HIFN_FLAG_DST_BUSY; | |
1369 | } | |
1370 | } | |
1371 | ||
75741a03 PM |
1372 | static int hifn_setup_dma(struct hifn_device *dev, struct hifn_context *ctx, |
1373 | struct scatterlist *src, struct scatterlist *dst, | |
1374 | unsigned int nbytes, void *priv) | |
85e7e60b | 1375 | { |
75741a03 PM |
1376 | struct scatterlist *t; |
1377 | struct page *spage, *dpage; | |
1378 | unsigned int soff, doff; | |
1379 | unsigned int n, len; | |
1380 | ||
34161586 PM |
1381 | n = nbytes; |
1382 | while (n) { | |
1383 | spage = sg_page(src); | |
1384 | soff = src->offset; | |
1385 | len = min(src->length, n); | |
1386 | ||
1387 | dprintk("%s: spage: %p, soffset: %u, nbytes: %u, " | |
1388 | "priv: %p, ctx: %p.\n", | |
1389 | dev->name, spage, soff, nbytes, priv, ctx); | |
1390 | hifn_setup_src_desc(dev, spage, soff, len, n - len == 0); | |
1391 | ||
1392 | src++; | |
1393 | n -= len; | |
1394 | } | |
1395 | ||
75741a03 PM |
1396 | t = &ctx->walk.cache[0]; |
1397 | n = nbytes; | |
1398 | while (n) { | |
1399 | if (t->length) { | |
34161586 PM |
1400 | dpage = sg_page(t); |
1401 | doff = 0; | |
75741a03 PM |
1402 | len = t->length; |
1403 | } else { | |
75741a03 PM |
1404 | dpage = sg_page(dst); |
1405 | doff = dst->offset; | |
75741a03 PM |
1406 | len = dst->length; |
1407 | } | |
1408 | len = min(len, n); | |
1409 | ||
34161586 PM |
1410 | dprintk("%s: dpage: %p, doffset: %u, nbytes: %u, " |
1411 | "priv: %p, ctx: %p.\n", | |
1412 | dev->name, dpage, doff, nbytes, priv, ctx); | |
75741a03 PM |
1413 | hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0); |
1414 | ||
75741a03 PM |
1415 | dst++; |
1416 | t++; | |
1417 | n -= len; | |
1418 | } | |
1419 | ||
85e7e60b | 1420 | hifn_setup_cmd_desc(dev, ctx, priv, nbytes); |
85e7e60b PM |
1421 | hifn_setup_res_desc(dev); |
1422 | return 0; | |
1423 | } | |
1424 | ||
f7d0561e EP |
1425 | static int ablkcipher_walk_init(struct ablkcipher_walk *w, |
1426 | int num, gfp_t gfp_flags) | |
1427 | { | |
1428 | int i; | |
1429 | ||
1430 | num = min(ASYNC_SCATTERLIST_CACHE, num); | |
1431 | sg_init_table(w->cache, num); | |
1432 | ||
1433 | w->num = 0; | |
1434 | for (i=0; i<num; ++i) { | |
1435 | struct page *page = alloc_page(gfp_flags); | |
1436 | struct scatterlist *s; | |
1437 | ||
1438 | if (!page) | |
1439 | break; | |
1440 | ||
1441 | s = &w->cache[i]; | |
1442 | ||
1443 | sg_set_page(s, page, PAGE_SIZE, 0); | |
1444 | w->num++; | |
1445 | } | |
1446 | ||
1447 | return i; | |
1448 | } | |
1449 | ||
1450 | static void ablkcipher_walk_exit(struct ablkcipher_walk *w) | |
1451 | { | |
1452 | int i; | |
1453 | ||
1454 | for (i=0; i<w->num; ++i) { | |
1455 | struct scatterlist *s = &w->cache[i]; | |
1456 | ||
1457 | __free_page(sg_page(s)); | |
1458 | ||
1459 | s->length = 0; | |
1460 | } | |
1461 | ||
1462 | w->num = 0; | |
1463 | } | |
1464 | ||
34161586 | 1465 | static int ablkcipher_add(unsigned int *drestp, struct scatterlist *dst, |
f7d0561e EP |
1466 | unsigned int size, unsigned int *nbytesp) |
1467 | { | |
1468 | unsigned int copy, drest = *drestp, nbytes = *nbytesp; | |
1469 | int idx = 0; | |
f7d0561e EP |
1470 | |
1471 | if (drest < size || size > nbytes) | |
1472 | return -EINVAL; | |
1473 | ||
1474 | while (size) { | |
34161586 | 1475 | copy = min(drest, min(size, dst->length)); |
f7d0561e EP |
1476 | |
1477 | size -= copy; | |
1478 | drest -= copy; | |
1479 | nbytes -= copy; | |
f7d0561e EP |
1480 | |
1481 | dprintk("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n", | |
1482 | __func__, copy, size, drest, nbytes); | |
1483 | ||
34161586 | 1484 | dst++; |
f7d0561e EP |
1485 | idx++; |
1486 | } | |
1487 | ||
1488 | *nbytesp = nbytes; | |
1489 | *drestp = drest; | |
1490 | ||
1491 | return idx; | |
1492 | } | |
1493 | ||
1494 | static int ablkcipher_walk(struct ablkcipher_request *req, | |
1495 | struct ablkcipher_walk *w) | |
1496 | { | |
34161586 | 1497 | struct scatterlist *dst, *t; |
f7d0561e EP |
1498 | unsigned int nbytes = req->nbytes, offset, copy, diff; |
1499 | int idx, tidx, err; | |
1500 | ||
1501 | tidx = idx = 0; | |
1502 | offset = 0; | |
1503 | while (nbytes) { | |
1504 | if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED)) | |
1505 | return -EINVAL; | |
1506 | ||
f7d0561e EP |
1507 | dst = &req->dst[idx]; |
1508 | ||
34161586 PM |
1509 | dprintk("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n", |
1510 | __func__, dst->length, dst->offset, offset, nbytes); | |
f7d0561e | 1511 | |
d069033b PM |
1512 | if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) || |
1513 | !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) || | |
1514 | offset) { | |
34161586 | 1515 | unsigned slen = min(dst->length - offset, nbytes); |
f7d0561e EP |
1516 | unsigned dlen = PAGE_SIZE; |
1517 | ||
1518 | t = &w->cache[idx]; | |
1519 | ||
34161586 | 1520 | err = ablkcipher_add(&dlen, dst, slen, &nbytes); |
f7d0561e | 1521 | if (err < 0) |
34161586 | 1522 | return err; |
f7d0561e EP |
1523 | |
1524 | idx += err; | |
1525 | ||
d069033b PM |
1526 | copy = slen & ~(HIFN_D_DST_DALIGN - 1); |
1527 | diff = slen & (HIFN_D_DST_DALIGN - 1); | |
f7d0561e EP |
1528 | |
1529 | if (dlen < nbytes) { | |
1530 | /* | |
1531 | * Destination page does not have enough space | |
1532 | * to put there additional blocksized chunk, | |
1533 | * so we mark that page as containing only | |
1534 | * blocksize aligned chunks: | |
d069033b | 1535 | * t->length = (slen & ~(HIFN_D_DST_DALIGN - 1)); |
f7d0561e EP |
1536 | * and increase number of bytes to be processed |
1537 | * in next chunk: | |
1538 | * nbytes += diff; | |
1539 | */ | |
1540 | nbytes += diff; | |
1541 | ||
1542 | /* | |
1543 | * Temporary of course... | |
1544 | * Kick author if you will catch this one. | |
1545 | */ | |
1546 | printk(KERN_ERR "%s: dlen: %u, nbytes: %u," | |
1547 | "slen: %u, offset: %u.\n", | |
1548 | __func__, dlen, nbytes, slen, offset); | |
1549 | printk(KERN_ERR "%s: please contact author to fix this " | |
1550 | "issue, generally you should not catch " | |
1551 | "this path under any condition but who " | |
1552 | "knows how did you use crypto code.\n" | |
1553 | "Thank you.\n", __func__); | |
1554 | BUG(); | |
1555 | } else { | |
1556 | copy += diff + nbytes; | |
1557 | ||
34161586 | 1558 | dst = &req->dst[idx]; |
f7d0561e | 1559 | |
34161586 | 1560 | err = ablkcipher_add(&dlen, dst, nbytes, &nbytes); |
f7d0561e | 1561 | if (err < 0) |
34161586 | 1562 | return err; |
f7d0561e EP |
1563 | |
1564 | idx += err; | |
1565 | } | |
1566 | ||
1567 | t->length = copy; | |
1568 | t->offset = offset; | |
f7d0561e | 1569 | } else { |
34161586 | 1570 | nbytes -= min(dst->length, nbytes); |
f7d0561e EP |
1571 | idx++; |
1572 | } | |
1573 | ||
1574 | tidx++; | |
1575 | } | |
1576 | ||
1577 | return tidx; | |
f7d0561e EP |
1578 | } |
1579 | ||
1580 | static int hifn_setup_session(struct ablkcipher_request *req) | |
1581 | { | |
1582 | struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); | |
1583 | struct hifn_device *dev = ctx->dev; | |
75741a03 PM |
1584 | unsigned long dlen, flags; |
1585 | unsigned int nbytes = req->nbytes, idx = 0; | |
f7d0561e | 1586 | int err = -EINVAL, sg_num; |
75741a03 | 1587 | struct scatterlist *dst; |
f7d0561e EP |
1588 | |
1589 | if (ctx->iv && !ctx->ivsize && ctx->mode != ACRYPTO_MODE_ECB) | |
1590 | goto err_out_exit; | |
1591 | ||
1592 | ctx->walk.flags = 0; | |
1593 | ||
1594 | while (nbytes) { | |
f7d0561e | 1595 | dst = &req->dst[idx]; |
136f702f | 1596 | dlen = min(dst->length, nbytes); |
f7d0561e | 1597 | |
d069033b | 1598 | if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) || |
136f702f | 1599 | !IS_ALIGNED(dlen, HIFN_D_DST_DALIGN)) |
f7d0561e | 1600 | ctx->walk.flags |= ASYNC_FLAGS_MISALIGNED; |
f7d0561e | 1601 | |
136f702f | 1602 | nbytes -= dlen; |
f7d0561e EP |
1603 | idx++; |
1604 | } | |
1605 | ||
1606 | if (ctx->walk.flags & ASYNC_FLAGS_MISALIGNED) { | |
1607 | err = ablkcipher_walk_init(&ctx->walk, idx, GFP_ATOMIC); | |
1608 | if (err < 0) | |
1609 | return err; | |
1610 | } | |
1611 | ||
f7d0561e | 1612 | sg_num = ablkcipher_walk(req, &ctx->walk); |
94eaa1bd PM |
1613 | if (sg_num < 0) { |
1614 | err = sg_num; | |
1615 | goto err_out_exit; | |
1616 | } | |
f7d0561e EP |
1617 | |
1618 | spin_lock_irqsave(&dev->lock, flags); | |
1619 | if (dev->started + sg_num > HIFN_QUEUE_LENGTH) { | |
1620 | err = -EAGAIN; | |
1621 | goto err_out; | |
1622 | } | |
1623 | ||
1624 | dev->snum++; | |
75741a03 | 1625 | dev->started++; |
f7d0561e | 1626 | |
75741a03 PM |
1627 | err = hifn_setup_dma(dev, ctx, req->src, req->dst, req->nbytes, req); |
1628 | if (err) | |
1629 | goto err_out; | |
f7d0561e EP |
1630 | |
1631 | dev->active = HIFN_DEFAULT_ACTIVE_NUM; | |
1632 | spin_unlock_irqrestore(&dev->lock, flags); | |
1633 | ||
1634 | return 0; | |
1635 | ||
1636 | err_out: | |
1637 | spin_unlock_irqrestore(&dev->lock, flags); | |
1638 | err_out_exit: | |
7808f073 | 1639 | if (err) |
f7d0561e EP |
1640 | dprintk("%s: iv: %p [%d], key: %p [%d], mode: %u, op: %u, " |
1641 | "type: %u, err: %d.\n", | |
1642 | dev->name, ctx->iv, ctx->ivsize, | |
1643 | ctx->key, ctx->keysize, | |
1644 | ctx->mode, ctx->op, ctx->type, err); | |
1645 | ||
1646 | return err; | |
1647 | } | |
1648 | ||
1649 | static int hifn_test(struct hifn_device *dev, int encdec, u8 snum) | |
1650 | { | |
1651 | int n, err; | |
1652 | u8 src[16]; | |
1653 | struct hifn_context ctx; | |
1654 | u8 fips_aes_ecb_from_zero[16] = { | |
1655 | 0x66, 0xE9, 0x4B, 0xD4, | |
1656 | 0xEF, 0x8A, 0x2C, 0x3B, | |
1657 | 0x88, 0x4C, 0xFA, 0x59, | |
1658 | 0xCA, 0x34, 0x2B, 0x2E}; | |
75741a03 | 1659 | struct scatterlist sg; |
f7d0561e EP |
1660 | |
1661 | memset(src, 0, sizeof(src)); | |
1662 | memset(ctx.key, 0, sizeof(ctx.key)); | |
1663 | ||
1664 | ctx.dev = dev; | |
1665 | ctx.keysize = 16; | |
1666 | ctx.ivsize = 0; | |
1667 | ctx.iv = NULL; | |
1668 | ctx.op = (encdec)?ACRYPTO_OP_ENCRYPT:ACRYPTO_OP_DECRYPT; | |
1669 | ctx.mode = ACRYPTO_MODE_ECB; | |
1670 | ctx.type = ACRYPTO_TYPE_AES_128; | |
75741a03 PM |
1671 | ctx.walk.cache[0].length = 0; |
1672 | ||
1673 | sg_init_one(&sg, &src, sizeof(src)); | |
f7d0561e | 1674 | |
75741a03 | 1675 | err = hifn_setup_dma(dev, &ctx, &sg, &sg, sizeof(src), NULL); |
f7d0561e EP |
1676 | if (err) |
1677 | goto err_out; | |
1678 | ||
1679 | msleep(200); | |
1680 | ||
1681 | dprintk("%s: decoded: ", dev->name); | |
1682 | for (n=0; n<sizeof(src); ++n) | |
1683 | dprintk("%02x ", src[n]); | |
1684 | dprintk("\n"); | |
1685 | dprintk("%s: FIPS : ", dev->name); | |
1686 | for (n=0; n<sizeof(fips_aes_ecb_from_zero); ++n) | |
1687 | dprintk("%02x ", fips_aes_ecb_from_zero[n]); | |
1688 | dprintk("\n"); | |
1689 | ||
1690 | if (!memcmp(src, fips_aes_ecb_from_zero, sizeof(fips_aes_ecb_from_zero))) { | |
1691 | printk(KERN_INFO "%s: AES 128 ECB test has been successfully " | |
1692 | "passed.\n", dev->name); | |
1693 | return 0; | |
1694 | } | |
1695 | ||
1696 | err_out: | |
1697 | printk(KERN_INFO "%s: AES 128 ECB test has been failed.\n", dev->name); | |
1698 | return -1; | |
1699 | } | |
1700 | ||
1701 | static int hifn_start_device(struct hifn_device *dev) | |
1702 | { | |
1703 | int err; | |
1704 | ||
1705 | hifn_reset_dma(dev, 1); | |
1706 | ||
1707 | err = hifn_enable_crypto(dev); | |
1708 | if (err) | |
1709 | return err; | |
1710 | ||
1711 | hifn_reset_puc(dev); | |
1712 | ||
1713 | hifn_init_dma(dev); | |
1714 | ||
1715 | hifn_init_registers(dev); | |
1716 | ||
1717 | hifn_init_pubrng(dev); | |
1718 | ||
1719 | return 0; | |
1720 | } | |
1721 | ||
1722 | static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset, | |
1723 | struct scatterlist *dst, unsigned int size, unsigned int *nbytesp) | |
1724 | { | |
1725 | unsigned int srest = *srestp, nbytes = *nbytesp, copy; | |
1726 | void *daddr; | |
1727 | int idx = 0; | |
1728 | ||
1729 | if (srest < size || size > nbytes) | |
1730 | return -EINVAL; | |
1731 | ||
1732 | while (size) { | |
136f702f | 1733 | copy = min(srest, min(dst->length, size)); |
f7d0561e EP |
1734 | |
1735 | daddr = kmap_atomic(sg_page(dst), KM_IRQ0); | |
1736 | memcpy(daddr + dst->offset + offset, saddr, copy); | |
1737 | kunmap_atomic(daddr, KM_IRQ0); | |
1738 | ||
1739 | nbytes -= copy; | |
1740 | size -= copy; | |
1741 | srest -= copy; | |
1742 | saddr += copy; | |
1743 | offset = 0; | |
1744 | ||
1745 | dprintk("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n", | |
1746 | __func__, copy, size, srest, nbytes); | |
1747 | ||
1748 | dst++; | |
1749 | idx++; | |
1750 | } | |
1751 | ||
1752 | *nbytesp = nbytes; | |
1753 | *srestp = srest; | |
1754 | ||
1755 | return idx; | |
1756 | } | |
1757 | ||
1758 | static void hifn_process_ready(struct ablkcipher_request *req, int error) | |
1759 | { | |
1760 | struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); | |
1761 | struct hifn_device *dev; | |
1762 | ||
1763 | dprintk("%s: req: %p, ctx: %p.\n", __func__, req, ctx); | |
1764 | ||
1765 | dev = ctx->dev; | |
75741a03 | 1766 | dprintk("%s: req: %p, started: %d.\n", __func__, req, dev->started); |
f7d0561e EP |
1767 | |
1768 | if (--dev->started < 0) | |
1769 | BUG(); | |
1770 | ||
75741a03 | 1771 | if (ctx->walk.flags & ASYNC_FLAGS_MISALIGNED) { |
f7d0561e EP |
1772 | unsigned int nbytes = req->nbytes; |
1773 | int idx = 0, err; | |
1774 | struct scatterlist *dst, *t; | |
1775 | void *saddr; | |
1776 | ||
75741a03 PM |
1777 | while (nbytes) { |
1778 | t = &ctx->walk.cache[idx]; | |
1779 | dst = &req->dst[idx]; | |
f7d0561e | 1780 | |
75741a03 PM |
1781 | dprintk("\n%s: sg_page(t): %p, t->length: %u, " |
1782 | "sg_page(dst): %p, dst->length: %u, " | |
1783 | "nbytes: %u.\n", | |
1784 | __func__, sg_page(t), t->length, | |
1785 | sg_page(dst), dst->length, nbytes); | |
f7d0561e | 1786 | |
75741a03 PM |
1787 | if (!t->length) { |
1788 | nbytes -= min(dst->length, nbytes); | |
1789 | idx++; | |
1790 | continue; | |
1791 | } | |
f7d0561e | 1792 | |
75741a03 | 1793 | saddr = kmap_atomic(sg_page(t), KM_IRQ1); |
f7d0561e | 1794 | |
75741a03 PM |
1795 | err = ablkcipher_get(saddr, &t->length, t->offset, |
1796 | dst, nbytes, &nbytes); | |
1797 | if (err < 0) { | |
f7d0561e | 1798 | kunmap_atomic(saddr, KM_IRQ1); |
75741a03 | 1799 | break; |
f7d0561e EP |
1800 | } |
1801 | ||
75741a03 PM |
1802 | idx += err; |
1803 | kunmap_atomic(saddr, KM_IRQ1); | |
f7d0561e EP |
1804 | } |
1805 | ||
75741a03 | 1806 | ablkcipher_walk_exit(&ctx->walk); |
f7d0561e | 1807 | } |
75741a03 PM |
1808 | |
1809 | req->base.complete(&req->base, error); | |
f7d0561e EP |
1810 | } |
1811 | ||
1812 | static void hifn_check_for_completion(struct hifn_device *dev, int error) | |
1813 | { | |
1814 | int i; | |
1815 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1816 | ||
1817 | for (i=0; i<HIFN_D_RES_RSIZE; ++i) { | |
1818 | struct hifn_desc *d = &dma->resr[i]; | |
1819 | ||
1820 | if (!(d->l & __cpu_to_le32(HIFN_D_VALID)) && dev->sa[i]) { | |
1821 | dev->success++; | |
1822 | dev->reset = 0; | |
1823 | hifn_process_ready(dev->sa[i], error); | |
1824 | dev->sa[i] = NULL; | |
1825 | } | |
1826 | ||
1827 | if (d->l & __cpu_to_le32(HIFN_D_DESTOVER | HIFN_D_OVER)) | |
1828 | if (printk_ratelimit()) | |
1829 | printk("%s: overflow detected [d: %u, o: %u] " | |
1830 | "at %d resr: l: %08x, p: %08x.\n", | |
1831 | dev->name, | |
1832 | !!(d->l & __cpu_to_le32(HIFN_D_DESTOVER)), | |
1833 | !!(d->l & __cpu_to_le32(HIFN_D_OVER)), | |
1834 | i, d->l, d->p); | |
1835 | } | |
1836 | } | |
1837 | ||
1838 | static void hifn_clear_rings(struct hifn_device *dev) | |
1839 | { | |
1840 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1841 | int i, u; | |
1842 | ||
1843 | dprintk("%s: ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, " | |
1844 | "k: %d.%d.%d.%d.\n", | |
1845 | dev->name, | |
1846 | dma->cmdi, dma->srci, dma->dsti, dma->resi, | |
1847 | dma->cmdu, dma->srcu, dma->dstu, dma->resu, | |
1848 | dma->cmdk, dma->srck, dma->dstk, dma->resk); | |
1849 | ||
1850 | i = dma->resk; u = dma->resu; | |
1851 | while (u != 0) { | |
1852 | if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID)) | |
1853 | break; | |
1854 | ||
1855 | if (i != HIFN_D_RES_RSIZE) | |
1856 | u--; | |
1857 | ||
1858 | if (++i == (HIFN_D_RES_RSIZE + 1)) | |
1859 | i = 0; | |
1860 | } | |
1861 | dma->resk = i; dma->resu = u; | |
1862 | ||
1863 | i = dma->srck; u = dma->srcu; | |
1864 | while (u != 0) { | |
1865 | if (i == HIFN_D_SRC_RSIZE) | |
1866 | i = 0; | |
1867 | if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID)) | |
1868 | break; | |
1869 | i++, u--; | |
1870 | } | |
1871 | dma->srck = i; dma->srcu = u; | |
1872 | ||
1873 | i = dma->cmdk; u = dma->cmdu; | |
1874 | while (u != 0) { | |
1875 | if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID)) | |
1876 | break; | |
1877 | if (i != HIFN_D_CMD_RSIZE) | |
1878 | u--; | |
1879 | if (++i == (HIFN_D_CMD_RSIZE + 1)) | |
1880 | i = 0; | |
1881 | } | |
1882 | dma->cmdk = i; dma->cmdu = u; | |
1883 | ||
1884 | i = dma->dstk; u = dma->dstu; | |
1885 | while (u != 0) { | |
1886 | if (i == HIFN_D_DST_RSIZE) | |
1887 | i = 0; | |
1888 | if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID)) | |
1889 | break; | |
1890 | i++, u--; | |
1891 | } | |
1892 | dma->dstk = i; dma->dstu = u; | |
1893 | ||
1894 | dprintk("%s: ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, " | |
1895 | "k: %d.%d.%d.%d.\n", | |
1896 | dev->name, | |
1897 | dma->cmdi, dma->srci, dma->dsti, dma->resi, | |
1898 | dma->cmdu, dma->srcu, dma->dstu, dma->resu, | |
1899 | dma->cmdk, dma->srck, dma->dstk, dma->resk); | |
1900 | } | |
1901 | ||
1902 | static void hifn_work(struct work_struct *work) | |
1903 | { | |
1904 | struct delayed_work *dw = container_of(work, struct delayed_work, work); | |
1905 | struct hifn_device *dev = container_of(dw, struct hifn_device, work); | |
1906 | unsigned long flags; | |
1907 | int reset = 0; | |
1908 | u32 r = 0; | |
1909 | ||
1910 | spin_lock_irqsave(&dev->lock, flags); | |
1911 | if (dev->active == 0) { | |
1912 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1913 | ||
1914 | if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) { | |
1915 | dev->flags &= ~HIFN_FLAG_CMD_BUSY; | |
1916 | r |= HIFN_DMACSR_C_CTRL_DIS; | |
1917 | } | |
1918 | if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) { | |
1919 | dev->flags &= ~HIFN_FLAG_SRC_BUSY; | |
1920 | r |= HIFN_DMACSR_S_CTRL_DIS; | |
1921 | } | |
1922 | if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) { | |
1923 | dev->flags &= ~HIFN_FLAG_DST_BUSY; | |
1924 | r |= HIFN_DMACSR_D_CTRL_DIS; | |
1925 | } | |
1926 | if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) { | |
1927 | dev->flags &= ~HIFN_FLAG_RES_BUSY; | |
1928 | r |= HIFN_DMACSR_R_CTRL_DIS; | |
1929 | } | |
1930 | if (r) | |
1931 | hifn_write_1(dev, HIFN_1_DMA_CSR, r); | |
1932 | } else | |
1933 | dev->active--; | |
1934 | ||
1935 | if (dev->prev_success == dev->success && dev->started) | |
1936 | reset = 1; | |
1937 | dev->prev_success = dev->success; | |
1938 | spin_unlock_irqrestore(&dev->lock, flags); | |
1939 | ||
1940 | if (reset) { | |
1941 | dprintk("%s: r: %08x, active: %d, started: %d, " | |
1942 | "success: %lu: reset: %d.\n", | |
1943 | dev->name, r, dev->active, dev->started, | |
1944 | dev->success, reset); | |
1945 | ||
1946 | if (++dev->reset >= 5) { | |
1947 | dprintk("%s: really hard reset.\n", dev->name); | |
1948 | hifn_reset_dma(dev, 1); | |
1949 | hifn_stop_device(dev); | |
1950 | hifn_start_device(dev); | |
1951 | dev->reset = 0; | |
1952 | } | |
1953 | ||
1954 | spin_lock_irqsave(&dev->lock, flags); | |
1955 | hifn_check_for_completion(dev, -EBUSY); | |
1956 | hifn_clear_rings(dev); | |
1957 | dev->started = 0; | |
1958 | spin_unlock_irqrestore(&dev->lock, flags); | |
1959 | } | |
1960 | ||
1961 | schedule_delayed_work(&dev->work, HZ); | |
1962 | } | |
1963 | ||
1964 | static irqreturn_t hifn_interrupt(int irq, void *data) | |
1965 | { | |
1966 | struct hifn_device *dev = (struct hifn_device *)data; | |
1967 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1968 | u32 dmacsr, restart; | |
1969 | ||
1970 | dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR); | |
1971 | ||
1972 | dprintk("%s: 1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], " | |
1973 | "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n", | |
1974 | dev->name, dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi, | |
1975 | dma->cmdu, dma->srcu, dma->dstu, dma->resu, | |
1976 | dma->cmdi, dma->srci, dma->dsti, dma->resi); | |
1977 | ||
1978 | if ((dmacsr & dev->dmareg) == 0) | |
1979 | return IRQ_NONE; | |
1980 | ||
1981 | hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg); | |
1982 | ||
1983 | if (dmacsr & HIFN_DMACSR_ENGINE) | |
1984 | hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR)); | |
1985 | if (dmacsr & HIFN_DMACSR_PUBDONE) | |
1986 | hifn_write_1(dev, HIFN_1_PUB_STATUS, | |
1987 | hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); | |
1988 | ||
1989 | restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER); | |
1990 | if (restart) { | |
1991 | u32 puisr = hifn_read_0(dev, HIFN_0_PUISR); | |
1992 | ||
1993 | if (printk_ratelimit()) | |
1994 | printk("%s: overflow: r: %d, d: %d, puisr: %08x, d: %u.\n", | |
1995 | dev->name, !!(dmacsr & HIFN_DMACSR_R_OVER), | |
1996 | !!(dmacsr & HIFN_DMACSR_D_OVER), | |
1997 | puisr, !!(puisr & HIFN_PUISR_DSTOVER)); | |
1998 | if (!!(puisr & HIFN_PUISR_DSTOVER)) | |
1999 | hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); | |
2000 | hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER | | |
2001 | HIFN_DMACSR_D_OVER)); | |
2002 | } | |
2003 | ||
2004 | restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | | |
2005 | HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); | |
2006 | if (restart) { | |
2007 | if (printk_ratelimit()) | |
2008 | printk("%s: abort: c: %d, s: %d, d: %d, r: %d.\n", | |
2009 | dev->name, !!(dmacsr & HIFN_DMACSR_C_ABORT), | |
2010 | !!(dmacsr & HIFN_DMACSR_S_ABORT), | |
2011 | !!(dmacsr & HIFN_DMACSR_D_ABORT), | |
2012 | !!(dmacsr & HIFN_DMACSR_R_ABORT)); | |
2013 | hifn_reset_dma(dev, 1); | |
2014 | hifn_init_dma(dev); | |
2015 | hifn_init_registers(dev); | |
2016 | } | |
2017 | ||
2018 | if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { | |
2019 | dprintk("%s: wait on command.\n", dev->name); | |
2020 | dev->dmareg &= ~(HIFN_DMAIER_C_WAIT); | |
2021 | hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); | |
2022 | } | |
2023 | ||
a1e6ef2f | 2024 | tasklet_schedule(&dev->tasklet); |
f7d0561e EP |
2025 | hifn_clear_rings(dev); |
2026 | ||
2027 | return IRQ_HANDLED; | |
2028 | } | |
2029 | ||
2030 | static void hifn_flush(struct hifn_device *dev) | |
2031 | { | |
2032 | unsigned long flags; | |
2033 | struct crypto_async_request *async_req; | |
2034 | struct hifn_context *ctx; | |
2035 | struct ablkcipher_request *req; | |
2036 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
2037 | int i; | |
2038 | ||
2039 | spin_lock_irqsave(&dev->lock, flags); | |
2040 | for (i=0; i<HIFN_D_RES_RSIZE; ++i) { | |
2041 | struct hifn_desc *d = &dma->resr[i]; | |
2042 | ||
2043 | if (dev->sa[i]) { | |
2044 | hifn_process_ready(dev->sa[i], | |
2045 | (d->l & __cpu_to_le32(HIFN_D_VALID))?-ENODEV:0); | |
2046 | } | |
2047 | } | |
2048 | ||
2049 | while ((async_req = crypto_dequeue_request(&dev->queue))) { | |
2050 | ctx = crypto_tfm_ctx(async_req->tfm); | |
2051 | req = container_of(async_req, struct ablkcipher_request, base); | |
2052 | ||
2053 | hifn_process_ready(req, -ENODEV); | |
2054 | } | |
2055 | spin_unlock_irqrestore(&dev->lock, flags); | |
2056 | } | |
2057 | ||
2058 | static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key, | |
2059 | unsigned int len) | |
2060 | { | |
2061 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
2062 | struct hifn_context *ctx = crypto_tfm_ctx(tfm); | |
2063 | struct hifn_device *dev = ctx->dev; | |
2064 | ||
2065 | if (len > HIFN_MAX_CRYPT_KEY_LENGTH) { | |
2066 | crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
2067 | return -1; | |
2068 | } | |
2069 | ||
c3041f9c EP |
2070 | if (len == HIFN_DES_KEY_LENGTH) { |
2071 | u32 tmp[DES_EXPKEY_WORDS]; | |
2072 | int ret = des_ekey(tmp, key); | |
2073 | ||
2074 | if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) { | |
2075 | tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY; | |
2076 | return -EINVAL; | |
2077 | } | |
2078 | } | |
2079 | ||
f7d0561e EP |
2080 | dev->flags &= ~HIFN_FLAG_OLD_KEY; |
2081 | ||
2082 | memcpy(ctx->key, key, len); | |
2083 | ctx->keysize = len; | |
2084 | ||
2085 | return 0; | |
2086 | } | |
2087 | ||
2088 | static int hifn_handle_req(struct ablkcipher_request *req) | |
2089 | { | |
2090 | struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); | |
2091 | struct hifn_device *dev = ctx->dev; | |
2092 | int err = -EAGAIN; | |
2093 | ||
2094 | if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH) | |
2095 | err = hifn_setup_session(req); | |
2096 | ||
2097 | if (err == -EAGAIN) { | |
2098 | unsigned long flags; | |
2099 | ||
2100 | spin_lock_irqsave(&dev->lock, flags); | |
2101 | err = ablkcipher_enqueue_request(&dev->queue, req); | |
2102 | spin_unlock_irqrestore(&dev->lock, flags); | |
2103 | } | |
2104 | ||
2105 | return err; | |
2106 | } | |
2107 | ||
2108 | static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op, | |
2109 | u8 type, u8 mode) | |
2110 | { | |
2111 | struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); | |
2112 | unsigned ivsize; | |
2113 | ||
2114 | ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req)); | |
2115 | ||
2116 | if (req->info && mode != ACRYPTO_MODE_ECB) { | |
2117 | if (type == ACRYPTO_TYPE_AES_128) | |
2118 | ivsize = HIFN_AES_IV_LENGTH; | |
2119 | else if (type == ACRYPTO_TYPE_DES) | |
2120 | ivsize = HIFN_DES_KEY_LENGTH; | |
2121 | else if (type == ACRYPTO_TYPE_3DES) | |
2122 | ivsize = HIFN_3DES_KEY_LENGTH; | |
2123 | } | |
2124 | ||
2125 | if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) { | |
2126 | if (ctx->keysize == 24) | |
2127 | type = ACRYPTO_TYPE_AES_192; | |
2128 | else if (ctx->keysize == 32) | |
2129 | type = ACRYPTO_TYPE_AES_256; | |
2130 | } | |
2131 | ||
2132 | ctx->op = op; | |
2133 | ctx->mode = mode; | |
2134 | ctx->type = type; | |
2135 | ctx->iv = req->info; | |
2136 | ctx->ivsize = ivsize; | |
2137 | ||
2138 | /* | |
2139 | * HEAVY TODO: needs to kick Herbert XU to write documentation. | |
2140 | * HEAVY TODO: needs to kick Herbert XU to write documentation. | |
2141 | * HEAVY TODO: needs to kick Herbert XU to write documentation. | |
2142 | */ | |
2143 | ||
2144 | return hifn_handle_req(req); | |
2145 | } | |
2146 | ||
2147 | static int hifn_process_queue(struct hifn_device *dev) | |
2148 | { | |
2149 | struct crypto_async_request *async_req; | |
2150 | struct hifn_context *ctx; | |
2151 | struct ablkcipher_request *req; | |
2152 | unsigned long flags; | |
2153 | int err = 0; | |
2154 | ||
2155 | while (dev->started < HIFN_QUEUE_LENGTH) { | |
2156 | spin_lock_irqsave(&dev->lock, flags); | |
2157 | async_req = crypto_dequeue_request(&dev->queue); | |
2158 | spin_unlock_irqrestore(&dev->lock, flags); | |
2159 | ||
2160 | if (!async_req) | |
2161 | break; | |
2162 | ||
2163 | ctx = crypto_tfm_ctx(async_req->tfm); | |
2164 | req = container_of(async_req, struct ablkcipher_request, base); | |
2165 | ||
2166 | err = hifn_handle_req(req); | |
2167 | if (err) | |
2168 | break; | |
2169 | } | |
2170 | ||
2171 | return err; | |
2172 | } | |
2173 | ||
2174 | static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op, | |
2175 | u8 type, u8 mode) | |
2176 | { | |
2177 | int err; | |
2178 | struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); | |
2179 | struct hifn_device *dev = ctx->dev; | |
2180 | ||
2181 | err = hifn_setup_crypto_req(req, op, type, mode); | |
2182 | if (err) | |
2183 | return err; | |
2184 | ||
2185 | if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen) | |
9e70a408 | 2186 | hifn_process_queue(dev); |
f7d0561e | 2187 | |
9e70a408 | 2188 | return -EINPROGRESS; |
f7d0561e EP |
2189 | } |
2190 | ||
2191 | /* | |
2192 | * AES ecryption functions. | |
2193 | */ | |
2194 | static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req) | |
2195 | { | |
2196 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2197 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB); | |
2198 | } | |
2199 | static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req) | |
2200 | { | |
2201 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2202 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC); | |
2203 | } | |
2204 | static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req) | |
2205 | { | |
2206 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2207 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB); | |
2208 | } | |
2209 | static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req) | |
2210 | { | |
2211 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2212 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB); | |
2213 | } | |
2214 | ||
2215 | /* | |
2216 | * AES decryption functions. | |
2217 | */ | |
2218 | static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req) | |
2219 | { | |
2220 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2221 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB); | |
2222 | } | |
2223 | static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req) | |
2224 | { | |
2225 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2226 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC); | |
2227 | } | |
2228 | static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req) | |
2229 | { | |
2230 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2231 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB); | |
2232 | } | |
2233 | static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req) | |
2234 | { | |
2235 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2236 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB); | |
2237 | } | |
2238 | ||
2239 | /* | |
2240 | * DES ecryption functions. | |
2241 | */ | |
2242 | static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req) | |
2243 | { | |
2244 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2245 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB); | |
2246 | } | |
2247 | static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req) | |
2248 | { | |
2249 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2250 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC); | |
2251 | } | |
2252 | static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req) | |
2253 | { | |
2254 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2255 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB); | |
2256 | } | |
2257 | static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req) | |
2258 | { | |
2259 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2260 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB); | |
2261 | } | |
2262 | ||
2263 | /* | |
2264 | * DES decryption functions. | |
2265 | */ | |
2266 | static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req) | |
2267 | { | |
2268 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2269 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB); | |
2270 | } | |
2271 | static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req) | |
2272 | { | |
2273 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2274 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC); | |
2275 | } | |
2276 | static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req) | |
2277 | { | |
2278 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2279 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB); | |
2280 | } | |
2281 | static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req) | |
2282 | { | |
2283 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2284 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB); | |
2285 | } | |
2286 | ||
2287 | /* | |
2288 | * 3DES ecryption functions. | |
2289 | */ | |
2290 | static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req) | |
2291 | { | |
2292 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2293 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB); | |
2294 | } | |
2295 | static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req) | |
2296 | { | |
2297 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2298 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC); | |
2299 | } | |
2300 | static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req) | |
2301 | { | |
2302 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2303 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB); | |
2304 | } | |
2305 | static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req) | |
2306 | { | |
2307 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2308 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB); | |
2309 | } | |
2310 | ||
2311 | /* | |
2312 | * 3DES decryption functions. | |
2313 | */ | |
2314 | static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req) | |
2315 | { | |
2316 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2317 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB); | |
2318 | } | |
2319 | static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req) | |
2320 | { | |
2321 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2322 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC); | |
2323 | } | |
2324 | static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req) | |
2325 | { | |
2326 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2327 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB); | |
2328 | } | |
2329 | static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req) | |
2330 | { | |
2331 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2332 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB); | |
2333 | } | |
2334 | ||
2335 | struct hifn_alg_template | |
2336 | { | |
2337 | char name[CRYPTO_MAX_ALG_NAME]; | |
2338 | char drv_name[CRYPTO_MAX_ALG_NAME]; | |
2339 | unsigned int bsize; | |
2340 | struct ablkcipher_alg ablkcipher; | |
2341 | }; | |
2342 | ||
2343 | static struct hifn_alg_template hifn_alg_templates[] = { | |
2344 | /* | |
2345 | * 3DES ECB, CBC, CFB and OFB modes. | |
2346 | */ | |
2347 | { | |
281d6bd4 | 2348 | .name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8, |
f7d0561e EP |
2349 | .ablkcipher = { |
2350 | .min_keysize = HIFN_3DES_KEY_LENGTH, | |
2351 | .max_keysize = HIFN_3DES_KEY_LENGTH, | |
2352 | .setkey = hifn_setkey, | |
2353 | .encrypt = hifn_encrypt_3des_cfb, | |
2354 | .decrypt = hifn_decrypt_3des_cfb, | |
2355 | }, | |
2356 | }, | |
2357 | { | |
281d6bd4 | 2358 | .name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8, |
f7d0561e EP |
2359 | .ablkcipher = { |
2360 | .min_keysize = HIFN_3DES_KEY_LENGTH, | |
2361 | .max_keysize = HIFN_3DES_KEY_LENGTH, | |
2362 | .setkey = hifn_setkey, | |
2363 | .encrypt = hifn_encrypt_3des_ofb, | |
2364 | .decrypt = hifn_decrypt_3des_ofb, | |
2365 | }, | |
2366 | }, | |
2367 | { | |
281d6bd4 | 2368 | .name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8, |
f7d0561e | 2369 | .ablkcipher = { |
4b804b53 | 2370 | .ivsize = HIFN_IV_LENGTH, |
f7d0561e EP |
2371 | .min_keysize = HIFN_3DES_KEY_LENGTH, |
2372 | .max_keysize = HIFN_3DES_KEY_LENGTH, | |
2373 | .setkey = hifn_setkey, | |
2374 | .encrypt = hifn_encrypt_3des_cbc, | |
2375 | .decrypt = hifn_decrypt_3des_cbc, | |
2376 | }, | |
2377 | }, | |
2378 | { | |
281d6bd4 | 2379 | .name = "ecb(des3_ede)", .drv_name = "ecb-3des", .bsize = 8, |
f7d0561e EP |
2380 | .ablkcipher = { |
2381 | .min_keysize = HIFN_3DES_KEY_LENGTH, | |
2382 | .max_keysize = HIFN_3DES_KEY_LENGTH, | |
2383 | .setkey = hifn_setkey, | |
2384 | .encrypt = hifn_encrypt_3des_ecb, | |
2385 | .decrypt = hifn_decrypt_3des_ecb, | |
2386 | }, | |
2387 | }, | |
2388 | ||
2389 | /* | |
2390 | * DES ECB, CBC, CFB and OFB modes. | |
2391 | */ | |
2392 | { | |
281d6bd4 | 2393 | .name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8, |
f7d0561e EP |
2394 | .ablkcipher = { |
2395 | .min_keysize = HIFN_DES_KEY_LENGTH, | |
2396 | .max_keysize = HIFN_DES_KEY_LENGTH, | |
2397 | .setkey = hifn_setkey, | |
2398 | .encrypt = hifn_encrypt_des_cfb, | |
2399 | .decrypt = hifn_decrypt_des_cfb, | |
2400 | }, | |
2401 | }, | |
2402 | { | |
281d6bd4 | 2403 | .name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8, |
f7d0561e EP |
2404 | .ablkcipher = { |
2405 | .min_keysize = HIFN_DES_KEY_LENGTH, | |
2406 | .max_keysize = HIFN_DES_KEY_LENGTH, | |
2407 | .setkey = hifn_setkey, | |
2408 | .encrypt = hifn_encrypt_des_ofb, | |
2409 | .decrypt = hifn_decrypt_des_ofb, | |
2410 | }, | |
2411 | }, | |
2412 | { | |
281d6bd4 | 2413 | .name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8, |
f7d0561e | 2414 | .ablkcipher = { |
4b804b53 | 2415 | .ivsize = HIFN_IV_LENGTH, |
f7d0561e EP |
2416 | .min_keysize = HIFN_DES_KEY_LENGTH, |
2417 | .max_keysize = HIFN_DES_KEY_LENGTH, | |
2418 | .setkey = hifn_setkey, | |
2419 | .encrypt = hifn_encrypt_des_cbc, | |
2420 | .decrypt = hifn_decrypt_des_cbc, | |
2421 | }, | |
2422 | }, | |
2423 | { | |
281d6bd4 | 2424 | .name = "ecb(des)", .drv_name = "ecb-des", .bsize = 8, |
f7d0561e EP |
2425 | .ablkcipher = { |
2426 | .min_keysize = HIFN_DES_KEY_LENGTH, | |
2427 | .max_keysize = HIFN_DES_KEY_LENGTH, | |
2428 | .setkey = hifn_setkey, | |
2429 | .encrypt = hifn_encrypt_des_ecb, | |
2430 | .decrypt = hifn_decrypt_des_ecb, | |
2431 | }, | |
2432 | }, | |
2433 | ||
2434 | /* | |
2435 | * AES ECB, CBC, CFB and OFB modes. | |
2436 | */ | |
2437 | { | |
281d6bd4 | 2438 | .name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16, |
f7d0561e EP |
2439 | .ablkcipher = { |
2440 | .min_keysize = AES_MIN_KEY_SIZE, | |
2441 | .max_keysize = AES_MAX_KEY_SIZE, | |
2442 | .setkey = hifn_setkey, | |
2443 | .encrypt = hifn_encrypt_aes_ecb, | |
2444 | .decrypt = hifn_decrypt_aes_ecb, | |
2445 | }, | |
2446 | }, | |
2447 | { | |
281d6bd4 | 2448 | .name = "cbc(aes)", .drv_name = "cbc-aes", .bsize = 16, |
f7d0561e | 2449 | .ablkcipher = { |
4b804b53 | 2450 | .ivsize = HIFN_AES_IV_LENGTH, |
f7d0561e EP |
2451 | .min_keysize = AES_MIN_KEY_SIZE, |
2452 | .max_keysize = AES_MAX_KEY_SIZE, | |
2453 | .setkey = hifn_setkey, | |
2454 | .encrypt = hifn_encrypt_aes_cbc, | |
2455 | .decrypt = hifn_decrypt_aes_cbc, | |
2456 | }, | |
2457 | }, | |
2458 | { | |
281d6bd4 | 2459 | .name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16, |
f7d0561e EP |
2460 | .ablkcipher = { |
2461 | .min_keysize = AES_MIN_KEY_SIZE, | |
2462 | .max_keysize = AES_MAX_KEY_SIZE, | |
2463 | .setkey = hifn_setkey, | |
2464 | .encrypt = hifn_encrypt_aes_cfb, | |
2465 | .decrypt = hifn_decrypt_aes_cfb, | |
2466 | }, | |
2467 | }, | |
2468 | { | |
281d6bd4 | 2469 | .name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16, |
f7d0561e EP |
2470 | .ablkcipher = { |
2471 | .min_keysize = AES_MIN_KEY_SIZE, | |
2472 | .max_keysize = AES_MAX_KEY_SIZE, | |
2473 | .setkey = hifn_setkey, | |
2474 | .encrypt = hifn_encrypt_aes_ofb, | |
2475 | .decrypt = hifn_decrypt_aes_ofb, | |
2476 | }, | |
2477 | }, | |
2478 | }; | |
2479 | ||
2480 | static int hifn_cra_init(struct crypto_tfm *tfm) | |
2481 | { | |
2482 | struct crypto_alg *alg = tfm->__crt_alg; | |
2483 | struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg); | |
2484 | struct hifn_context *ctx = crypto_tfm_ctx(tfm); | |
2485 | ||
2486 | ctx->dev = ha->dev; | |
2487 | ||
2488 | return 0; | |
2489 | } | |
2490 | ||
2491 | static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t) | |
2492 | { | |
2493 | struct hifn_crypto_alg *alg; | |
2494 | int err; | |
2495 | ||
2496 | alg = kzalloc(sizeof(struct hifn_crypto_alg), GFP_KERNEL); | |
2497 | if (!alg) | |
2498 | return -ENOMEM; | |
2499 | ||
2500 | snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name); | |
281d6bd4 PM |
2501 | snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s", |
2502 | t->drv_name, dev->name); | |
f7d0561e EP |
2503 | |
2504 | alg->alg.cra_priority = 300; | |
332f8840 | 2505 | alg->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC; |
f7d0561e EP |
2506 | alg->alg.cra_blocksize = t->bsize; |
2507 | alg->alg.cra_ctxsize = sizeof(struct hifn_context); | |
d069033b | 2508 | alg->alg.cra_alignmask = 0; |
f7d0561e EP |
2509 | alg->alg.cra_type = &crypto_ablkcipher_type; |
2510 | alg->alg.cra_module = THIS_MODULE; | |
2511 | alg->alg.cra_u.ablkcipher = t->ablkcipher; | |
2512 | alg->alg.cra_init = hifn_cra_init; | |
2513 | ||
2514 | alg->dev = dev; | |
2515 | ||
2516 | list_add_tail(&alg->entry, &dev->alg_list); | |
2517 | ||
2518 | err = crypto_register_alg(&alg->alg); | |
2519 | if (err) { | |
2520 | list_del(&alg->entry); | |
2521 | kfree(alg); | |
2522 | } | |
2523 | ||
2524 | return err; | |
2525 | } | |
2526 | ||
2527 | static void hifn_unregister_alg(struct hifn_device *dev) | |
2528 | { | |
2529 | struct hifn_crypto_alg *a, *n; | |
2530 | ||
2531 | list_for_each_entry_safe(a, n, &dev->alg_list, entry) { | |
2532 | list_del(&a->entry); | |
2533 | crypto_unregister_alg(&a->alg); | |
2534 | kfree(a); | |
2535 | } | |
2536 | } | |
2537 | ||
2538 | static int hifn_register_alg(struct hifn_device *dev) | |
2539 | { | |
2540 | int i, err; | |
2541 | ||
2542 | for (i=0; i<ARRAY_SIZE(hifn_alg_templates); ++i) { | |
2543 | err = hifn_alg_alloc(dev, &hifn_alg_templates[i]); | |
2544 | if (err) | |
2545 | goto err_out_exit; | |
2546 | } | |
2547 | ||
2548 | return 0; | |
2549 | ||
2550 | err_out_exit: | |
2551 | hifn_unregister_alg(dev); | |
2552 | return err; | |
2553 | } | |
2554 | ||
a1e6ef2f EP |
2555 | static void hifn_tasklet_callback(unsigned long data) |
2556 | { | |
2557 | struct hifn_device *dev = (struct hifn_device *)data; | |
2558 | ||
2559 | /* | |
2560 | * This is ok to call this without lock being held, | |
2561 | * althogh it modifies some parameters used in parallel, | |
2562 | * (like dev->success), but they are used in process | |
2563 | * context or update is atomic (like setting dev->sa[i] to NULL). | |
2564 | */ | |
2565 | hifn_check_for_completion(dev, 0); | |
2566 | } | |
2567 | ||
f7d0561e EP |
2568 | static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
2569 | { | |
2570 | int err, i; | |
2571 | struct hifn_device *dev; | |
2572 | char name[8]; | |
2573 | ||
2574 | err = pci_enable_device(pdev); | |
2575 | if (err) | |
2576 | return err; | |
2577 | pci_set_master(pdev); | |
2578 | ||
2579 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2580 | if (err) | |
2581 | goto err_out_disable_pci_device; | |
2582 | ||
2583 | snprintf(name, sizeof(name), "hifn%d", | |
2584 | atomic_inc_return(&hifn_dev_number)-1); | |
2585 | ||
2586 | err = pci_request_regions(pdev, name); | |
2587 | if (err) | |
2588 | goto err_out_disable_pci_device; | |
2589 | ||
2590 | if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE || | |
2591 | pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE || | |
2592 | pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) { | |
2593 | dprintk("%s: Broken hardware - I/O regions are too small.\n", | |
2594 | pci_name(pdev)); | |
2595 | err = -ENODEV; | |
2596 | goto err_out_free_regions; | |
2597 | } | |
2598 | ||
2599 | dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg), | |
2600 | GFP_KERNEL); | |
2601 | if (!dev) { | |
2602 | err = -ENOMEM; | |
2603 | goto err_out_free_regions; | |
2604 | } | |
2605 | ||
2606 | INIT_LIST_HEAD(&dev->alg_list); | |
2607 | ||
2608 | snprintf(dev->name, sizeof(dev->name), "%s", name); | |
2609 | spin_lock_init(&dev->lock); | |
2610 | ||
2611 | for (i=0; i<3; ++i) { | |
2612 | unsigned long addr, size; | |
2613 | ||
2614 | addr = pci_resource_start(pdev, i); | |
2615 | size = pci_resource_len(pdev, i); | |
2616 | ||
2617 | dev->bar[i] = ioremap_nocache(addr, size); | |
2618 | if (!dev->bar[i]) | |
2619 | goto err_out_unmap_bars; | |
2620 | } | |
2621 | ||
2622 | dev->result_mem = __get_free_pages(GFP_KERNEL, HIFN_MAX_RESULT_ORDER); | |
2623 | if (!dev->result_mem) { | |
2624 | dprintk("Failed to allocate %d pages for result_mem.\n", | |
2625 | HIFN_MAX_RESULT_ORDER); | |
2626 | goto err_out_unmap_bars; | |
2627 | } | |
2628 | memset((void *)dev->result_mem, 0, PAGE_SIZE*(1<<HIFN_MAX_RESULT_ORDER)); | |
2629 | ||
2630 | dev->dst = pci_map_single(pdev, (void *)dev->result_mem, | |
2631 | PAGE_SIZE << HIFN_MAX_RESULT_ORDER, PCI_DMA_FROMDEVICE); | |
2632 | ||
2633 | dev->desc_virt = pci_alloc_consistent(pdev, sizeof(struct hifn_dma), | |
2634 | &dev->desc_dma); | |
2635 | if (!dev->desc_virt) { | |
2636 | dprintk("Failed to allocate descriptor rings.\n"); | |
2637 | goto err_out_free_result_pages; | |
2638 | } | |
2639 | memset(dev->desc_virt, 0, sizeof(struct hifn_dma)); | |
2640 | ||
2641 | dev->pdev = pdev; | |
2642 | dev->irq = pdev->irq; | |
2643 | ||
2644 | for (i=0; i<HIFN_D_RES_RSIZE; ++i) | |
2645 | dev->sa[i] = NULL; | |
2646 | ||
2647 | pci_set_drvdata(pdev, dev); | |
2648 | ||
a1e6ef2f EP |
2649 | tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev); |
2650 | ||
f7d0561e EP |
2651 | crypto_init_queue(&dev->queue, 1); |
2652 | ||
2653 | err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev); | |
2654 | if (err) { | |
2655 | dprintk("Failed to request IRQ%d: err: %d.\n", dev->irq, err); | |
2656 | dev->irq = 0; | |
2657 | goto err_out_free_desc; | |
2658 | } | |
2659 | ||
2660 | err = hifn_start_device(dev); | |
2661 | if (err) | |
2662 | goto err_out_free_irq; | |
2663 | ||
2664 | err = hifn_test(dev, 1, 0); | |
2665 | if (err) | |
2666 | goto err_out_stop_device; | |
2667 | ||
fcd06755 | 2668 | err = hifn_register_rng(dev); |
f7d0561e EP |
2669 | if (err) |
2670 | goto err_out_stop_device; | |
2671 | ||
fcd06755 PM |
2672 | err = hifn_register_alg(dev); |
2673 | if (err) | |
2674 | goto err_out_unregister_rng; | |
2675 | ||
f7d0561e EP |
2676 | INIT_DELAYED_WORK(&dev->work, hifn_work); |
2677 | schedule_delayed_work(&dev->work, HZ); | |
2678 | ||
2679 | dprintk("HIFN crypto accelerator card at %s has been " | |
2680 | "successfully registered as %s.\n", | |
2681 | pci_name(pdev), dev->name); | |
2682 | ||
2683 | return 0; | |
2684 | ||
fcd06755 PM |
2685 | err_out_unregister_rng: |
2686 | hifn_unregister_rng(dev); | |
f7d0561e EP |
2687 | err_out_stop_device: |
2688 | hifn_reset_dma(dev, 1); | |
2689 | hifn_stop_device(dev); | |
2690 | err_out_free_irq: | |
2691 | free_irq(dev->irq, dev->name); | |
a1e6ef2f | 2692 | tasklet_kill(&dev->tasklet); |
f7d0561e EP |
2693 | err_out_free_desc: |
2694 | pci_free_consistent(pdev, sizeof(struct hifn_dma), | |
2695 | dev->desc_virt, dev->desc_dma); | |
2696 | ||
2697 | err_out_free_result_pages: | |
2698 | pci_unmap_single(pdev, dev->dst, PAGE_SIZE << HIFN_MAX_RESULT_ORDER, | |
2699 | PCI_DMA_FROMDEVICE); | |
2700 | free_pages(dev->result_mem, HIFN_MAX_RESULT_ORDER); | |
2701 | ||
2702 | err_out_unmap_bars: | |
2703 | for (i=0; i<3; ++i) | |
2704 | if (dev->bar[i]) | |
2705 | iounmap(dev->bar[i]); | |
2706 | ||
2707 | err_out_free_regions: | |
2708 | pci_release_regions(pdev); | |
2709 | ||
2710 | err_out_disable_pci_device: | |
2711 | pci_disable_device(pdev); | |
2712 | ||
2713 | return err; | |
2714 | } | |
2715 | ||
2716 | static void hifn_remove(struct pci_dev *pdev) | |
2717 | { | |
2718 | int i; | |
2719 | struct hifn_device *dev; | |
2720 | ||
2721 | dev = pci_get_drvdata(pdev); | |
2722 | ||
2723 | if (dev) { | |
2724 | cancel_delayed_work(&dev->work); | |
2725 | flush_scheduled_work(); | |
2726 | ||
fcd06755 | 2727 | hifn_unregister_rng(dev); |
f7d0561e EP |
2728 | hifn_unregister_alg(dev); |
2729 | hifn_reset_dma(dev, 1); | |
2730 | hifn_stop_device(dev); | |
2731 | ||
2732 | free_irq(dev->irq, dev->name); | |
a1e6ef2f | 2733 | tasklet_kill(&dev->tasklet); |
f7d0561e EP |
2734 | |
2735 | hifn_flush(dev); | |
2736 | ||
2737 | pci_free_consistent(pdev, sizeof(struct hifn_dma), | |
2738 | dev->desc_virt, dev->desc_dma); | |
2739 | pci_unmap_single(pdev, dev->dst, | |
2740 | PAGE_SIZE << HIFN_MAX_RESULT_ORDER, | |
2741 | PCI_DMA_FROMDEVICE); | |
2742 | free_pages(dev->result_mem, HIFN_MAX_RESULT_ORDER); | |
2743 | for (i=0; i<3; ++i) | |
2744 | if (dev->bar[i]) | |
2745 | iounmap(dev->bar[i]); | |
2746 | ||
2747 | kfree(dev); | |
2748 | } | |
2749 | ||
2750 | pci_release_regions(pdev); | |
2751 | pci_disable_device(pdev); | |
2752 | } | |
2753 | ||
2754 | static struct pci_device_id hifn_pci_tbl[] = { | |
2755 | { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) }, | |
2756 | { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) }, | |
2757 | { 0 } | |
2758 | }; | |
2759 | MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); | |
2760 | ||
2761 | static struct pci_driver hifn_pci_driver = { | |
2762 | .name = "hifn795x", | |
2763 | .id_table = hifn_pci_tbl, | |
2764 | .probe = hifn_probe, | |
2765 | .remove = __devexit_p(hifn_remove), | |
2766 | }; | |
2767 | ||
2768 | static int __devinit hifn_init(void) | |
2769 | { | |
37a8023c | 2770 | unsigned int freq; |
f7d0561e EP |
2771 | int err; |
2772 | ||
a44b56cc EP |
2773 | if (sizeof(dma_addr_t) > 4) { |
2774 | printk(KERN_INFO "HIFN supports only 32-bit addresses.\n"); | |
2775 | return -EINVAL; | |
2776 | } | |
2777 | ||
37a8023c PM |
2778 | if (strncmp(hifn_pll_ref, "ext", 3) && |
2779 | strncmp(hifn_pll_ref, "pci", 3)) { | |
2780 | printk(KERN_ERR "hifn795x: invalid hifn_pll_ref clock, " | |
2781 | "must be pci or ext"); | |
2782 | return -EINVAL; | |
2783 | } | |
2784 | ||
2785 | /* | |
2786 | * For the 7955/7956 the reference clock frequency must be in the | |
2787 | * range of 20MHz-100MHz. For the 7954 the upper bound is 66.67MHz, | |
2788 | * but this chip is currently not supported. | |
2789 | */ | |
2790 | if (hifn_pll_ref[3] != '\0') { | |
2791 | freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10); | |
2792 | if (freq < 20 || freq > 100) { | |
2793 | printk(KERN_ERR "hifn795x: invalid hifn_pll_ref " | |
2794 | "frequency, must be in the range " | |
2795 | "of 20-100"); | |
2796 | return -EINVAL; | |
2797 | } | |
2798 | } | |
2799 | ||
f7d0561e EP |
2800 | err = pci_register_driver(&hifn_pci_driver); |
2801 | if (err < 0) { | |
2802 | dprintk("Failed to register PCI driver for %s device.\n", | |
2803 | hifn_pci_driver.name); | |
2804 | return -ENODEV; | |
2805 | } | |
2806 | ||
2807 | printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip " | |
2808 | "has been successfully registered.\n"); | |
2809 | ||
2810 | return 0; | |
2811 | } | |
2812 | ||
2813 | static void __devexit hifn_fini(void) | |
2814 | { | |
2815 | pci_unregister_driver(&hifn_pci_driver); | |
2816 | ||
2817 | printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip " | |
2818 | "has been successfully unregistered.\n"); | |
2819 | } | |
2820 | ||
2821 | module_init(hifn_init); | |
2822 | module_exit(hifn_fini); | |
2823 | ||
2824 | MODULE_LICENSE("GPL"); | |
2825 | MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>"); | |
2826 | MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip."); |