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301422e3 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1b44c5a6 AT |
2 | /* |
3 | * Copyright (C) 2017 Marvell | |
4 | * | |
5 | * Antoine Tenart <antoine.tenart@free-electrons.com> | |
1b44c5a6 AT |
6 | */ |
7 | ||
8 | #ifndef __SAFEXCEL_H__ | |
9 | #define __SAFEXCEL_H__ | |
10 | ||
f6beaea3 | 11 | #include <crypto/aead.h> |
1b44c5a6 AT |
12 | #include <crypto/algapi.h> |
13 | #include <crypto/internal/hash.h> | |
f6beaea3 | 14 | #include <crypto/sha.h> |
1b44c5a6 AT |
15 | #include <crypto/skcipher.h> |
16 | ||
118db42d PL |
17 | #define EIP197_HIA_VERSION_BE 0xca35 |
18 | #define EIP197_HIA_VERSION_LE 0x35ca | |
19 | #define EIP97_VERSION_LE 0x9e61 | |
20 | #define EIP197_VERSION_LE 0x3ac5 | |
21 | #define EIP96_VERSION_LE 0x9f60 | |
22 | #define EIP197_REG_LO16(reg) (reg & 0xffff) | |
23 | #define EIP197_REG_HI16(reg) ((reg >> 16) & 0xffff) | |
24 | #define EIP197_VERSION_MASK(reg) ((reg >> 16) & 0xfff) | |
25 | #define EIP197_VERSION_SWAP(reg) (((reg & 0xf0) << 4) | \ | |
26 | ((reg >> 4) & 0xf0) | \ | |
27 | ((reg >> 12) & 0xf)) | |
1b44c5a6 AT |
28 | |
29 | /* Static configuration */ | |
fc8c72b2 | 30 | #define EIP197_DEFAULT_RING_SIZE 400 |
4eb76faf | 31 | #define EIP197_MAX_TOKENS 18 |
1b44c5a6 | 32 | #define EIP197_MAX_RINGS 4 |
35c0e6c3 | 33 | #define EIP197_FETCH_DEPTH 2 |
fc8c72b2 | 34 | #define EIP197_MAX_BATCH_SZ 64 |
1b44c5a6 AT |
35 | |
36 | #define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \ | |
37 | GFP_KERNEL : GFP_ATOMIC) | |
38 | ||
61824806 AT |
39 | /* Custom on-stack requests (for invalidation) */ |
40 | #define EIP197_SKCIPHER_REQ_SIZE sizeof(struct skcipher_request) + \ | |
41 | sizeof(struct safexcel_cipher_req) | |
42 | #define EIP197_AHASH_REQ_SIZE sizeof(struct ahash_request) + \ | |
43 | sizeof(struct safexcel_ahash_req) | |
f6beaea3 AT |
44 | #define EIP197_AEAD_REQ_SIZE sizeof(struct aead_request) + \ |
45 | sizeof(struct safexcel_cipher_req) | |
61824806 AT |
46 | #define EIP197_REQUEST_ON_STACK(name, type, size) \ |
47 | char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \ | |
48 | struct type##_request *name = (void *)__##name##_desc | |
49 | ||
625f269a PL |
50 | /* Xilinx dev board base offsets */ |
51 | #define EIP197_XLX_GPIO_BASE 0x200000 | |
52 | #define EIP197_XLX_IRQ_BLOCK_ID_ADDR 0x2000 | |
53 | #define EIP197_XLX_IRQ_BLOCK_ID_VALUE 0x1fc2 | |
54 | #define EIP197_XLX_USER_INT_ENB_MSK 0x2004 | |
55 | #define EIP197_XLX_USER_INT_ENB_SET 0x2008 | |
56 | #define EIP197_XLX_USER_INT_ENB_CLEAR 0x200c | |
57 | #define EIP197_XLX_USER_INT_BLOCK 0x2040 | |
58 | #define EIP197_XLX_USER_INT_PEND 0x2048 | |
59 | #define EIP197_XLX_USER_VECT_LUT0_ADDR 0x2080 | |
60 | #define EIP197_XLX_USER_VECT_LUT0_IDENT 0x03020100 | |
61 | #define EIP197_XLX_USER_VECT_LUT1_ADDR 0x2084 | |
62 | #define EIP197_XLX_USER_VECT_LUT1_IDENT 0x07060504 | |
63 | #define EIP197_XLX_USER_VECT_LUT2_ADDR 0x2088 | |
64 | #define EIP197_XLX_USER_VECT_LUT2_IDENT 0x0b0a0908 | |
65 | #define EIP197_XLX_USER_VECT_LUT3_ADDR 0x208c | |
66 | #define EIP197_XLX_USER_VECT_LUT3_IDENT 0x0f0e0d0c | |
67 | ||
68 | /* Helper defines for probe function */ | |
69 | #define EIP197_IRQ_NUMBER(i, is_pci) (i + is_pci) | |
70 | ||
871df319 AT |
71 | /* Register base offsets */ |
72 | #define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic) | |
73 | #define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g) | |
74 | #define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r) | |
75 | #define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr) | |
76 | #define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe) | |
77 | #define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr) | |
78 | #define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse) | |
79 | #define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr) | |
80 | #define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg) | |
81 | #define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe) | |
118db42d | 82 | #define EIP197_GLOBAL(priv) ((priv)->base + (priv)->offsets.global) |
871df319 AT |
83 | |
84 | /* EIP197 base offsets */ | |
85 | #define EIP197_HIA_AIC_BASE 0x90000 | |
86 | #define EIP197_HIA_AIC_G_BASE 0x90000 | |
87 | #define EIP197_HIA_AIC_R_BASE 0x90800 | |
88 | #define EIP197_HIA_AIC_xDR_BASE 0x80000 | |
89 | #define EIP197_HIA_DFE_BASE 0x8c000 | |
90 | #define EIP197_HIA_DFE_THR_BASE 0x8c040 | |
91 | #define EIP197_HIA_DSE_BASE 0x8d000 | |
92 | #define EIP197_HIA_DSE_THR_BASE 0x8d040 | |
93 | #define EIP197_HIA_GEN_CFG_BASE 0xf0000 | |
94 | #define EIP197_PE_BASE 0xa0000 | |
118db42d | 95 | #define EIP197_GLOBAL_BASE 0xf0000 |
871df319 AT |
96 | |
97 | /* EIP97 base offsets */ | |
98 | #define EIP97_HIA_AIC_BASE 0x0 | |
99 | #define EIP97_HIA_AIC_G_BASE 0x0 | |
100 | #define EIP97_HIA_AIC_R_BASE 0x0 | |
101 | #define EIP97_HIA_AIC_xDR_BASE 0x0 | |
102 | #define EIP97_HIA_DFE_BASE 0xf000 | |
103 | #define EIP97_HIA_DFE_THR_BASE 0xf200 | |
104 | #define EIP97_HIA_DSE_BASE 0xf400 | |
105 | #define EIP97_HIA_DSE_THR_BASE 0xf600 | |
106 | #define EIP97_HIA_GEN_CFG_BASE 0x10000 | |
107 | #define EIP97_PE_BASE 0x10000 | |
118db42d | 108 | #define EIP97_GLOBAL_BASE 0x10000 |
871df319 | 109 | |
1b44c5a6 | 110 | /* CDR/RDR register offsets */ |
871df319 AT |
111 | #define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000) |
112 | #define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r)) | |
113 | #define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800) | |
114 | #define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000 | |
115 | #define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004 | |
116 | #define EIP197_HIA_xDR_RING_SIZE 0x0018 | |
117 | #define EIP197_HIA_xDR_DESC_SIZE 0x001c | |
118 | #define EIP197_HIA_xDR_CFG 0x0020 | |
119 | #define EIP197_HIA_xDR_DMA_CFG 0x0024 | |
120 | #define EIP197_HIA_xDR_THRESH 0x0028 | |
121 | #define EIP197_HIA_xDR_PREP_COUNT 0x002c | |
122 | #define EIP197_HIA_xDR_PROC_COUNT 0x0030 | |
123 | #define EIP197_HIA_xDR_PREP_PNTR 0x0034 | |
124 | #define EIP197_HIA_xDR_PROC_PNTR 0x0038 | |
125 | #define EIP197_HIA_xDR_STAT 0x003c | |
1b44c5a6 AT |
126 | |
127 | /* register offsets */ | |
367571e4 OH |
128 | #define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n))) |
129 | #define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n))) | |
130 | #define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n))) | |
131 | #define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n))) | |
132 | #define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n))) | |
133 | #define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n))) | |
134 | #define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n))) | |
871df319 | 135 | #define EIP197_HIA_RA_PE_STAT 0x0014 |
1b44c5a6 | 136 | #define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000) |
871df319 AT |
137 | #define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r)) |
138 | #define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r)) | |
139 | #define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r)) | |
140 | #define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r)) | |
141 | #define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808 | |
142 | #define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810 | |
143 | #define EIP197_HIA_AIC_G_ACK 0xf810 | |
144 | #define EIP197_HIA_MST_CTRL 0xfff4 | |
145 | #define EIP197_HIA_OPTIONS 0xfff8 | |
146 | #define EIP197_HIA_VERSION 0xfffc | |
367571e4 OH |
147 | #define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n))) |
148 | #define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n))) | |
149 | #define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n))) | |
150 | #define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n))) | |
f6cc45c8 | 151 | #define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n))) |
367571e4 OH |
152 | #define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n))) |
153 | #define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n))) | |
f6cc45c8 | 154 | #define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n))) |
367571e4 | 155 | #define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n))) |
97a1440d | 156 | #define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n))) |
367571e4 OH |
157 | #define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n))) |
158 | #define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n))) | |
159 | #define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n))) | |
4bdf712c | 160 | #define EIP197_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n))) |
062b64ca | 161 | #define EIP197_PE_EIP96_OPTIONS(n) (0x13f8 + (0x2000 * (n))) |
118db42d | 162 | #define EIP197_PE_EIP96_VERSION(n) (0x13fc + (0x2000 * (n))) |
367571e4 OH |
163 | #define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n))) |
164 | #define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n))) | |
871df319 | 165 | #define EIP197_MST_CTRL 0xfff4 |
118db42d | 166 | #define EIP197_VERSION 0xfffc |
871df319 AT |
167 | |
168 | /* EIP197-specific registers, no indirection */ | |
1b44c5a6 AT |
169 | #define EIP197_CLASSIFICATION_RAMS 0xe0000 |
170 | #define EIP197_TRC_CTRL 0xf0800 | |
171 | #define EIP197_TRC_LASTRES 0xf0804 | |
172 | #define EIP197_TRC_REGINDEX 0xf0808 | |
173 | #define EIP197_TRC_PARAMS 0xf0820 | |
174 | #define EIP197_TRC_FREECHAIN 0xf0824 | |
175 | #define EIP197_TRC_PARAMS2 0xf0828 | |
176 | #define EIP197_TRC_ECCCTRL 0xf0830 | |
177 | #define EIP197_TRC_ECCSTAT 0xf0834 | |
178 | #define EIP197_TRC_ECCADMINSTAT 0xf0838 | |
179 | #define EIP197_TRC_ECCDATASTAT 0xf083c | |
180 | #define EIP197_TRC_ECCDATA 0xf0840 | |
465527bc PL |
181 | #define EIP197_FLUE_CACHEBASE_LO(n) (0xf6000 + (32 * (n))) |
182 | #define EIP197_FLUE_CACHEBASE_HI(n) (0xf6004 + (32 * (n))) | |
183 | #define EIP197_FLUE_CONFIG(n) (0xf6010 + (32 * (n))) | |
184 | #define EIP197_FLUE_OFFSETS 0xf6808 | |
185 | #define EIP197_FLUE_ARC4_OFFSET 0xf680c | |
186 | #define EIP197_FLUE_IFC_LUT(n) (0xf6820 + (4 * (n))) | |
1b44c5a6 | 187 | #define EIP197_CS_RAM_CTRL 0xf7ff0 |
1b44c5a6 AT |
188 | |
189 | /* EIP197_HIA_xDR_DESC_SIZE */ | |
190 | #define EIP197_xDR_DESC_MODE_64BIT BIT(31) | |
191 | ||
192 | /* EIP197_HIA_xDR_DMA_CFG */ | |
193 | #define EIP197_HIA_xDR_WR_RES_BUF BIT(22) | |
d9107087 | 194 | #define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23) |
1b44c5a6 | 195 | #define EIP197_HIA_xDR_WR_OWN_BUF BIT(24) |
aefa794e | 196 | #define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25) |
1b44c5a6 AT |
197 | #define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29) |
198 | ||
199 | /* EIP197_HIA_CDR_THRESH */ | |
200 | #define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n) | |
201 | #define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22) | |
202 | #define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23) | |
203 | #define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ | |
204 | ||
205 | /* EIP197_HIA_RDR_THRESH */ | |
206 | #define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n) | |
207 | #define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23) | |
208 | #define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ | |
209 | ||
210 | /* EIP197_HIA_xDR_PREP_COUNT */ | |
211 | #define EIP197_xDR_PREP_CLR_COUNT BIT(31) | |
212 | ||
213 | /* EIP197_HIA_xDR_PROC_COUNT */ | |
7f77f5a4 AT |
214 | #define EIP197_xDR_PROC_xD_PKT_OFFSET 24 |
215 | #define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0) | |
1b44c5a6 AT |
216 | #define EIP197_xDR_PROC_xD_COUNT(n) ((n) << 2) |
217 | #define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24) | |
218 | #define EIP197_xDR_PROC_CLR_COUNT BIT(31) | |
219 | ||
220 | /* EIP197_HIA_xDR_STAT */ | |
221 | #define EIP197_xDR_DMA_ERR BIT(0) | |
222 | #define EIP197_xDR_PREP_CMD_THRES BIT(1) | |
223 | #define EIP197_xDR_ERR BIT(2) | |
224 | #define EIP197_xDR_THRESH BIT(4) | |
225 | #define EIP197_xDR_TIMEOUT BIT(5) | |
226 | ||
227 | #define EIP197_HIA_RA_PE_CTRL_RESET BIT(31) | |
228 | #define EIP197_HIA_RA_PE_CTRL_EN BIT(30) | |
229 | ||
367571e4 OH |
230 | /* EIP197_HIA_OPTIONS */ |
231 | #define EIP197_N_PES_OFFSET 4 | |
232 | #define EIP197_N_PES_MASK GENMASK(4, 0) | |
233 | #define EIP97_N_PES_MASK GENMASK(2, 0) | |
35c0e6c3 PL |
234 | #define EIP197_HWDATAW_OFFSET 25 |
235 | #define EIP197_HWDATAW_MASK GENMASK(3, 0) | |
236 | #define EIP97_HWDATAW_MASK GENMASK(2, 0) | |
237 | #define EIP197_CFSIZE_OFFSET 9 | |
238 | #define EIP197_CFSIZE_ADJUST 4 | |
239 | #define EIP97_CFSIZE_OFFSET 8 | |
240 | #define EIP197_CFSIZE_MASK GENMASK(3, 0) | |
241 | #define EIP97_CFSIZE_MASK GENMASK(4, 0) | |
b2d92ac1 PL |
242 | #define EIP197_RFSIZE_OFFSET 12 |
243 | #define EIP197_RFSIZE_ADJUST 4 | |
244 | #define EIP97_RFSIZE_OFFSET 12 | |
245 | #define EIP197_RFSIZE_MASK GENMASK(3, 0) | |
246 | #define EIP97_RFSIZE_MASK GENMASK(4, 0) | |
367571e4 | 247 | |
1b44c5a6 AT |
248 | /* EIP197_HIA_AIC_R_ENABLE_CTRL */ |
249 | #define EIP197_CDR_IRQ(n) BIT((n) * 2) | |
250 | #define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1) | |
251 | ||
252 | /* EIP197_HIA_DFE/DSE_CFG */ | |
253 | #define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0) | |
254 | #define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4) | |
255 | #define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8) | |
c2c55404 | 256 | #define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14) |
1b44c5a6 AT |
257 | #define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16) |
258 | #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20) | |
259 | #define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24) | |
260 | #define EIP197_HIA_DFE_CFG_DIS_DEBUG (BIT(31) | BIT(29)) | |
c87925bf | 261 | #define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29) |
1b44c5a6 AT |
262 | #define EIP197_HIA_DSE_CFG_DIS_DEBUG BIT(31) |
263 | ||
264 | /* EIP197_HIA_DFE/DSE_THR_CTRL */ | |
265 | #define EIP197_DxE_THR_CTRL_EN BIT(30) | |
266 | #define EIP197_DxE_THR_CTRL_RESET_PE BIT(31) | |
267 | ||
f6cc45c8 PL |
268 | /* EIP197_PE_ICE_PUE/FPP_CTRL */ |
269 | #define EIP197_PE_ICE_UENG_START_OFFSET(n) ((n) << 16) | |
270 | #define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK 0x7ff0 | |
271 | #define EIP197_PE_ICE_UENG_DEBUG_RESET BIT(3) | |
272 | ||
1b44c5a6 AT |
273 | /* EIP197_HIA_AIC_G_ENABLED_STAT */ |
274 | #define EIP197_G_IRQ_DFE(n) BIT((n) << 1) | |
275 | #define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1) | |
276 | #define EIP197_G_IRQ_RING BIT(16) | |
277 | #define EIP197_G_IRQ_PE(n) BIT((n) + 20) | |
278 | ||
279 | /* EIP197_HIA_MST_CTRL */ | |
280 | #define RD_CACHE_3BITS 0x5 | |
281 | #define WR_CACHE_3BITS 0x3 | |
282 | #define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0)) | |
283 | #define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0)) | |
284 | #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) | |
285 | #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) | |
63b94278 | 286 | #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) |
1b44c5a6 AT |
287 | #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) |
288 | #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) | |
118db42d | 289 | #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) |
1b44c5a6 AT |
290 | |
291 | /* EIP197_PE_IN_DBUF/TBUF_THRES */ | |
292 | #define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8) | |
293 | #define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12) | |
294 | ||
295 | /* EIP197_PE_OUT_DBUF_THRES */ | |
296 | #define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0) | |
297 | #define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4) | |
298 | ||
299 | /* EIP197_PE_ICE_SCRATCH_CTRL */ | |
300 | #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2) | |
301 | #define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3) | |
302 | #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24) | |
303 | #define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25) | |
304 | ||
305 | /* EIP197_PE_ICE_SCRATCH_RAM */ | |
306 | #define EIP197_NUM_OF_SCRATCH_BLOCKS 32 | |
307 | ||
308 | /* EIP197_PE_ICE_PUE/FPP_CTRL */ | |
309 | #define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0) | |
310 | #define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14) | |
311 | #define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15) | |
312 | ||
313 | /* EIP197_PE_ICE_RAM_CTRL */ | |
314 | #define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0) | |
315 | #define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1) | |
316 | ||
97a1440d AT |
317 | /* EIP197_PE_EIP96_TOKEN_CTRL */ |
318 | #define EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES BIT(16) | |
f9d131d9 PL |
319 | #define EIP197_PE_EIP96_TOKEN_CTRL_NO_TOKEN_WAIT BIT(17) |
320 | #define EIP197_PE_EIP96_TOKEN_CTRL_ENABLE_TIMEOUT BIT(22) | |
97a1440d | 321 | |
1b44c5a6 | 322 | /* EIP197_PE_EIP96_FUNCTION_EN */ |
54f9e8fa | 323 | #define EIP197_FUNCTION_ALL 0xffffffff |
1b44c5a6 AT |
324 | |
325 | /* EIP197_PE_EIP96_CONTEXT_CTRL */ | |
326 | #define EIP197_CONTEXT_SIZE(n) (n) | |
327 | #define EIP197_ADDRESS_MODE BIT(8) | |
328 | #define EIP197_CONTROL_MODE BIT(9) | |
329 | ||
465527bc PL |
330 | /* EIP197_FLUE_CONFIG */ |
331 | #define EIP197_FLUE_CONFIG_MAGIC 0xc7000004 | |
332 | ||
1b44c5a6 AT |
333 | /* Context Control */ |
334 | struct safexcel_context_record { | |
335 | u32 control0; | |
336 | u32 control1; | |
337 | ||
0de54fb1 | 338 | __le32 data[40]; |
1b44c5a6 AT |
339 | } __packed; |
340 | ||
341 | /* control0 */ | |
342 | #define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0 | |
343 | #define CONTEXT_CONTROL_TYPE_NULL_IN 0x1 | |
344 | #define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2 | |
345 | #define CONTEXT_CONTROL_TYPE_HASH_IN 0x3 | |
346 | #define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4 | |
347 | #define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5 | |
348 | #define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6 | |
349 | #define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7 | |
8a21f067 AT |
350 | #define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe |
351 | #define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf | |
1b44c5a6 AT |
352 | #define CONTEXT_CONTROL_RESTART_HASH BIT(4) |
353 | #define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5) | |
354 | #define CONTEXT_CONTROL_SIZE(n) ((n) << 8) | |
355 | #define CONTEXT_CONTROL_KEY_EN BIT(16) | |
a7dea8c0 | 356 | #define CONTEXT_CONTROL_CRYPTO_ALG_DES (0x0 << 17) |
62469879 | 357 | #define CONTEXT_CONTROL_CRYPTO_ALG_3DES (0x2 << 17) |
1b44c5a6 AT |
358 | #define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17) |
359 | #define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17) | |
360 | #define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17) | |
4a593fb3 | 361 | #define CONTEXT_CONTROL_CRYPTO_ALG_CHACHA20 (0x8 << 17) |
fcca797d | 362 | #define CONTEXT_CONTROL_CRYPTO_ALG_SM4 (0xd << 17) |
aaf5a383 | 363 | #define CONTEXT_CONTROL_DIGEST_INITIAL (0x0 << 21) |
1b44c5a6 | 364 | #define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21) |
3e450886 | 365 | #define CONTEXT_CONTROL_DIGEST_XCM (0x2 << 21) |
1b44c5a6 | 366 | #define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21) |
293f89cf | 367 | #define CONTEXT_CONTROL_CRYPTO_ALG_MD5 (0x0 << 23) |
a7cf8658 | 368 | #define CONTEXT_CONTROL_CRYPTO_ALG_CRC32 (0x0 << 23) |
1b44c5a6 AT |
369 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23) |
370 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23) | |
371 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23) | |
b460edb6 AT |
372 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA384 (0x6 << 23) |
373 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA512 (0x5 << 23) | |
3e450886 | 374 | #define CONTEXT_CONTROL_CRYPTO_ALG_GHASH (0x4 << 23) |
4eb76faf PL |
375 | #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC128 (0x1 << 23) |
376 | #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC192 (0x2 << 23) | |
377 | #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC256 (0x3 << 23) | |
0f2bc131 | 378 | #define CONTEXT_CONTROL_CRYPTO_ALG_SM3 (0x7 << 23) |
aaf5a383 PL |
379 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_256 (0xb << 23) |
380 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_224 (0xc << 23) | |
381 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_512 (0xd << 23) | |
382 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_384 (0xe << 23) | |
a6061921 | 383 | #define CONTEXT_CONTROL_CRYPTO_ALG_POLY1305 (0xf << 23) |
1b44c5a6 AT |
384 | #define CONTEXT_CONTROL_INV_FR (0x5 << 24) |
385 | #define CONTEXT_CONTROL_INV_TR (0x6 << 24) | |
386 | ||
387 | /* control1 */ | |
388 | #define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0) | |
389 | #define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0) | |
4a593fb3 | 390 | #define CONTEXT_CONTROL_CHACHA20_MODE_256_32 (2 << 0) |
50485dfb | 391 | #define CONTEXT_CONTROL_CRYPTO_MODE_OFB (4 << 0) |
48e97afa | 392 | #define CONTEXT_CONTROL_CRYPTO_MODE_CFB (5 << 0) |
54f9e8fa | 393 | #define CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD (6 << 0) |
c7da38a7 | 394 | #define CONTEXT_CONTROL_CRYPTO_MODE_XTS (7 << 0) |
3e450886 | 395 | #define CONTEXT_CONTROL_CRYPTO_MODE_XCM ((6 << 0) | BIT(17)) |
a6061921 | 396 | #define CONTEXT_CONTROL_CHACHA20_MODE_CALC_OTK (12 << 0) |
1b44c5a6 AT |
397 | #define CONTEXT_CONTROL_IV0 BIT(5) |
398 | #define CONTEXT_CONTROL_IV1 BIT(6) | |
399 | #define CONTEXT_CONTROL_IV2 BIT(7) | |
400 | #define CONTEXT_CONTROL_IV3 BIT(8) | |
401 | #define CONTEXT_CONTROL_DIGEST_CNT BIT(9) | |
402 | #define CONTEXT_CONTROL_COUNTER_MODE BIT(10) | |
57660b11 | 403 | #define CONTEXT_CONTROL_CRYPTO_STORE BIT(12) |
1b44c5a6 AT |
404 | #define CONTEXT_CONTROL_HASH_STORE BIT(19) |
405 | ||
4eb76faf PL |
406 | #define EIP197_XCM_MODE_GCM 1 |
407 | #define EIP197_XCM_MODE_CCM 2 | |
408 | ||
a6061921 PL |
409 | #define EIP197_AEAD_TYPE_IPSEC_ESP 2 |
410 | #define EIP197_AEAD_IPSEC_IV_SIZE 8 | |
411 | #define EIP197_AEAD_IPSEC_NONCE_SIZE 4 | |
412 | ||
25bc9551 AT |
413 | /* The hash counter given to the engine in the context has a granularity of |
414 | * 64 bits. | |
415 | */ | |
416 | #define EIP197_COUNTER_BLOCK_SIZE 64 | |
417 | ||
1b44c5a6 AT |
418 | /* EIP197_CS_RAM_CTRL */ |
419 | #define EIP197_TRC_ENABLE_0 BIT(4) | |
420 | #define EIP197_TRC_ENABLE_1 BIT(5) | |
421 | #define EIP197_TRC_ENABLE_2 BIT(6) | |
422 | #define EIP197_TRC_ENABLE_MASK GENMASK(6, 4) | |
465527bc PL |
423 | #define EIP197_CS_BANKSEL_MASK GENMASK(14, 12) |
424 | #define EIP197_CS_BANKSEL_OFS 12 | |
1b44c5a6 AT |
425 | |
426 | /* EIP197_TRC_PARAMS */ | |
427 | #define EIP197_TRC_PARAMS_SW_RESET BIT(0) | |
428 | #define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2) | |
429 | #define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4) | |
430 | #define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10) | |
431 | #define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18) | |
432 | ||
433 | /* EIP197_TRC_FREECHAIN */ | |
434 | #define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p) | |
435 | #define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16) | |
436 | ||
437 | /* EIP197_TRC_PARAMS2 */ | |
438 | #define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p) | |
439 | #define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18) | |
440 | ||
441 | /* Cache helpers */ | |
465527bc | 442 | #define EIP197_CS_TRC_REC_WC 64 |
1b44c5a6 AT |
443 | #define EIP197_CS_RC_SIZE (4 * sizeof(u32)) |
444 | #define EIP197_CS_RC_NEXT(x) (x) | |
445 | #define EIP197_CS_RC_PREV(x) ((x) << 10) | |
446 | #define EIP197_RC_NULL 0x3ff | |
1b44c5a6 AT |
447 | |
448 | /* Result data */ | |
449 | struct result_data_desc { | |
450 | u32 packet_length:17; | |
451 | u32 error_code:15; | |
452 | ||
453 | u8 bypass_length:4; | |
454 | u8 e15:1; | |
455 | u16 rsvd0; | |
456 | u8 hash_bytes:1; | |
457 | u8 hash_length:6; | |
458 | u8 generic_bytes:1; | |
459 | u8 checksum:1; | |
460 | u8 next_header:1; | |
461 | u8 length:1; | |
462 | ||
463 | u16 application_id; | |
464 | u16 rsvd1; | |
465 | ||
466 | u32 rsvd2; | |
467 | } __packed; | |
468 | ||
469 | ||
470 | /* Basic Result Descriptor format */ | |
471 | struct safexcel_result_desc { | |
472 | u32 particle_size:17; | |
473 | u8 rsvd0:3; | |
474 | u8 descriptor_overflow:1; | |
475 | u8 buffer_overflow:1; | |
476 | u8 last_seg:1; | |
477 | u8 first_seg:1; | |
478 | u16 result_size:8; | |
479 | ||
480 | u32 rsvd1; | |
481 | ||
482 | u32 data_lo; | |
483 | u32 data_hi; | |
484 | ||
485 | struct result_data_desc result_data; | |
486 | } __packed; | |
487 | ||
b2d92ac1 PL |
488 | /* |
489 | * The EIP(1)97 only needs to fetch the descriptor part of | |
490 | * the result descriptor, not the result token part! | |
491 | */ | |
492 | #define EIP197_RD64_FETCH_SIZE ((sizeof(struct safexcel_result_desc) -\ | |
493 | sizeof(struct result_data_desc)) /\ | |
494 | sizeof(u32)) | |
495 | ||
1b44c5a6 AT |
496 | struct safexcel_token { |
497 | u32 packet_length:17; | |
498 | u8 stat:2; | |
499 | u16 instructions:9; | |
500 | u8 opcode:4; | |
501 | } __packed; | |
502 | ||
f6beaea3 AT |
503 | #define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16) |
504 | ||
57660b11 AT |
505 | #define EIP197_TOKEN_CTX_OFFSET(x) (x) |
506 | #define EIP197_TOKEN_DIRECTION_EXTERNAL BIT(11) | |
507 | #define EIP197_TOKEN_EXEC_IF_SUCCESSFUL (0x1 << 12) | |
508 | ||
1b44c5a6 AT |
509 | #define EIP197_TOKEN_STAT_LAST_HASH BIT(0) |
510 | #define EIP197_TOKEN_STAT_LAST_PACKET BIT(1) | |
511 | #define EIP197_TOKEN_OPCODE_DIRECTION 0x0 | |
512 | #define EIP197_TOKEN_OPCODE_INSERT 0x2 | |
513 | #define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT | |
f6beaea3 | 514 | #define EIP197_TOKEN_OPCODE_RETRIEVE 0x4 |
3e450886 | 515 | #define EIP197_TOKEN_OPCODE_INSERT_REMRES 0xa |
f6beaea3 | 516 | #define EIP197_TOKEN_OPCODE_VERIFY 0xd |
57660b11 | 517 | #define EIP197_TOKEN_OPCODE_CTX_ACCESS 0xe |
1b44c5a6 AT |
518 | #define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0) |
519 | ||
520 | static inline void eip197_noop_token(struct safexcel_token *token) | |
521 | { | |
522 | token->opcode = EIP197_TOKEN_OPCODE_NOOP; | |
523 | token->packet_length = BIT(2); | |
524 | } | |
525 | ||
526 | /* Instructions */ | |
527 | #define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c | |
57660b11 | 528 | #define EIP197_TOKEN_INS_ORIGIN_IV0 0x14 |
4eb76faf | 529 | #define EIP197_TOKEN_INS_ORIGIN_TOKEN 0x1b |
57660b11 | 530 | #define EIP197_TOKEN_INS_ORIGIN_LEN(x) ((x) << 5) |
1b44c5a6 AT |
531 | #define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5) |
532 | #define EIP197_TOKEN_INS_TYPE_HASH BIT(6) | |
a74d850f | 533 | #define EIP197_TOKEN_INS_TYPE_CRYPTO BIT(7) |
1b44c5a6 AT |
534 | #define EIP197_TOKEN_INS_LAST BIT(8) |
535 | ||
536 | /* Processing Engine Control Data */ | |
537 | struct safexcel_control_data_desc { | |
538 | u32 packet_length:17; | |
539 | u16 options:13; | |
540 | u8 type:2; | |
541 | ||
542 | u16 application_id; | |
543 | u16 rsvd; | |
544 | ||
545 | u8 refresh:2; | |
546 | u32 context_lo:30; | |
547 | u32 context_hi; | |
548 | ||
549 | u32 control0; | |
550 | u32 control1; | |
551 | ||
552 | u32 token[EIP197_MAX_TOKENS]; | |
553 | } __packed; | |
554 | ||
555 | #define EIP197_OPTION_MAGIC_VALUE BIT(0) | |
556 | #define EIP197_OPTION_64BIT_CTX BIT(1) | |
97a1440d | 557 | #define EIP197_OPTION_RC_AUTO (0x2 << 3) |
1b44c5a6 | 558 | #define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8) |
a7dea8c0 | 559 | #define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10) |
1b44c5a6 AT |
560 | #define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9) |
561 | ||
562 | #define EIP197_TYPE_EXTENDED 0x3 | |
563 | ||
564 | /* Basic Command Descriptor format */ | |
565 | struct safexcel_command_desc { | |
566 | u32 particle_size:17; | |
567 | u8 rsvd0:5; | |
568 | u8 last_seg:1; | |
569 | u8 first_seg:1; | |
570 | u16 additional_cdata_size:8; | |
571 | ||
572 | u32 rsvd1; | |
573 | ||
574 | u32 data_lo; | |
575 | u32 data_hi; | |
576 | ||
577 | struct safexcel_control_data_desc control_data; | |
578 | } __packed; | |
579 | ||
580 | /* | |
581 | * Internal structures & functions | |
582 | */ | |
583 | ||
f6cc45c8 PL |
584 | #define EIP197_FW_TERMINAL_NOPS 2 |
585 | #define EIP197_FW_START_POLLCNT 16 | |
586 | #define EIP197_FW_PUE_READY 0x14 | |
587 | #define EIP197_FW_FPP_READY 0x18 | |
588 | ||
1b44c5a6 AT |
589 | enum eip197_fw { |
590 | FW_IFPP = 0, | |
591 | FW_IPUE, | |
592 | FW_NB | |
593 | }; | |
594 | ||
18e0e95b | 595 | struct safexcel_desc_ring { |
1b44c5a6 AT |
596 | void *base; |
597 | void *base_end; | |
598 | dma_addr_t base_dma; | |
599 | ||
600 | /* write and read pointers */ | |
601 | void *write; | |
602 | void *read; | |
603 | ||
9744fec9 | 604 | /* descriptor element offset */ |
1b44c5a6 AT |
605 | unsigned offset; |
606 | }; | |
607 | ||
608 | enum safexcel_alg_type { | |
609 | SAFEXCEL_ALG_TYPE_SKCIPHER, | |
f6beaea3 | 610 | SAFEXCEL_ALG_TYPE_AEAD, |
1b44c5a6 AT |
611 | SAFEXCEL_ALG_TYPE_AHASH, |
612 | }; | |
613 | ||
1b44c5a6 | 614 | struct safexcel_config { |
367571e4 | 615 | u32 pes; |
1b44c5a6 AT |
616 | u32 rings; |
617 | ||
618 | u32 cd_size; | |
619 | u32 cd_offset; | |
620 | ||
621 | u32 rd_size; | |
622 | u32 rd_offset; | |
623 | }; | |
624 | ||
625 | struct safexcel_work_data { | |
626 | struct work_struct work; | |
627 | struct safexcel_crypto_priv *priv; | |
628 | int ring; | |
629 | }; | |
630 | ||
18e0e95b OH |
631 | struct safexcel_ring { |
632 | spinlock_t lock; | |
18e0e95b | 633 | |
18e0e95b OH |
634 | struct workqueue_struct *workqueue; |
635 | struct safexcel_work_data work_data; | |
636 | ||
637 | /* command/result rings */ | |
638 | struct safexcel_desc_ring cdr; | |
639 | struct safexcel_desc_ring rdr; | |
640 | ||
9744fec9 OH |
641 | /* result ring crypto API request */ |
642 | struct crypto_async_request **rdr_req; | |
643 | ||
18e0e95b OH |
644 | /* queue */ |
645 | struct crypto_queue queue; | |
646 | spinlock_t queue_lock; | |
647 | ||
648 | /* Number of requests in the engine. */ | |
649 | int requests; | |
650 | ||
651 | /* The ring is currently handling at least one request */ | |
652 | bool busy; | |
653 | ||
654 | /* Store for current requests when bailing out of the dequeueing | |
655 | * function when no enough resources are available. | |
656 | */ | |
657 | struct crypto_async_request *req; | |
658 | struct crypto_async_request *backlog; | |
659 | }; | |
660 | ||
625f269a | 661 | /* EIP integration context flags */ |
871df319 | 662 | enum safexcel_eip_version { |
625f269a PL |
663 | /* Platform (EIP integration context) specifier */ |
664 | EIP97IES_MRVL, | |
665 | EIP197B_MRVL, | |
666 | EIP197D_MRVL, | |
667 | EIP197_DEVBRD | |
871df319 AT |
668 | }; |
669 | ||
aa88f331 PL |
670 | /* Priority we use for advertising our algorithms */ |
671 | #define SAFEXCEL_CRA_PRIORITY 300 | |
672 | ||
0f2bc131 PL |
673 | /* SM3 digest result for zero length message */ |
674 | #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \ | |
675 | "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \ | |
676 | "\x22\xBE\xC8\xC7\x28\xFE\xFB\x74" \ | |
677 | "\x7E\xD0\x35\xEB\x50\x82\xAA\x2B" | |
678 | ||
062b64ca PL |
679 | /* EIP algorithm presence flags */ |
680 | enum safexcel_eip_algorithms { | |
681 | SAFEXCEL_ALG_BC0 = BIT(5), | |
682 | SAFEXCEL_ALG_SM4 = BIT(6), | |
683 | SAFEXCEL_ALG_SM3 = BIT(7), | |
684 | SAFEXCEL_ALG_CHACHA20 = BIT(8), | |
685 | SAFEXCEL_ALG_POLY1305 = BIT(9), | |
686 | SAFEXCEL_SEQMASK_256 = BIT(10), | |
687 | SAFEXCEL_SEQMASK_384 = BIT(11), | |
688 | SAFEXCEL_ALG_AES = BIT(12), | |
689 | SAFEXCEL_ALG_AES_XFB = BIT(13), | |
690 | SAFEXCEL_ALG_DES = BIT(15), | |
691 | SAFEXCEL_ALG_DES_XFB = BIT(16), | |
692 | SAFEXCEL_ALG_ARC4 = BIT(18), | |
693 | SAFEXCEL_ALG_AES_XTS = BIT(20), | |
694 | SAFEXCEL_ALG_WIRELESS = BIT(21), | |
695 | SAFEXCEL_ALG_MD5 = BIT(22), | |
696 | SAFEXCEL_ALG_SHA1 = BIT(23), | |
697 | SAFEXCEL_ALG_SHA2_256 = BIT(25), | |
698 | SAFEXCEL_ALG_SHA2_512 = BIT(26), | |
699 | SAFEXCEL_ALG_XCBC_MAC = BIT(27), | |
700 | SAFEXCEL_ALG_CBC_MAC_ALL = BIT(29), | |
701 | SAFEXCEL_ALG_GHASH = BIT(30), | |
702 | SAFEXCEL_ALG_SHA3 = BIT(31), | |
703 | }; | |
704 | ||
871df319 AT |
705 | struct safexcel_register_offsets { |
706 | u32 hia_aic; | |
707 | u32 hia_aic_g; | |
708 | u32 hia_aic_r; | |
709 | u32 hia_aic_xdr; | |
710 | u32 hia_dfe; | |
711 | u32 hia_dfe_thr; | |
712 | u32 hia_dse; | |
713 | u32 hia_dse_thr; | |
714 | u32 hia_gen_cfg; | |
715 | u32 pe; | |
118db42d | 716 | u32 global; |
871df319 AT |
717 | }; |
718 | ||
53c83e91 | 719 | enum safexcel_flags { |
118db42d PL |
720 | EIP197_TRC_CACHE = BIT(0), |
721 | SAFEXCEL_HW_EIP197 = BIT(1), | |
53c83e91 AT |
722 | }; |
723 | ||
062b64ca PL |
724 | struct safexcel_hwconfig { |
725 | enum safexcel_eip_algorithms algo_flags; | |
118db42d PL |
726 | int hwver; |
727 | int hiaver; | |
728 | int pever; | |
35c0e6c3 PL |
729 | int hwdataw; |
730 | int hwcfsize; | |
b2d92ac1 | 731 | int hwrfsize; |
062b64ca PL |
732 | }; |
733 | ||
1b44c5a6 AT |
734 | struct safexcel_crypto_priv { |
735 | void __iomem *base; | |
736 | struct device *dev; | |
737 | struct clk *clk; | |
1d17cbfb | 738 | struct clk *reg_clk; |
1b44c5a6 AT |
739 | struct safexcel_config config; |
740 | ||
871df319 AT |
741 | enum safexcel_eip_version version; |
742 | struct safexcel_register_offsets offsets; | |
062b64ca | 743 | struct safexcel_hwconfig hwconfig; |
53c83e91 | 744 | u32 flags; |
871df319 | 745 | |
1b44c5a6 AT |
746 | /* context DMA pool */ |
747 | struct dma_pool *context_pool; | |
748 | ||
749 | atomic_t ring_used; | |
750 | ||
18e0e95b | 751 | struct safexcel_ring *ring; |
1b44c5a6 AT |
752 | }; |
753 | ||
754 | struct safexcel_context { | |
755 | int (*send)(struct crypto_async_request *req, int ring, | |
9744fec9 | 756 | int *commands, int *results); |
1b44c5a6 AT |
757 | int (*handle_result)(struct safexcel_crypto_priv *priv, int ring, |
758 | struct crypto_async_request *req, bool *complete, | |
759 | int *ret); | |
760 | struct safexcel_context_record *ctxr; | |
761 | dma_addr_t ctxr_dma; | |
762 | ||
763 | int ring; | |
764 | bool needs_inv; | |
765 | bool exit_inv; | |
1b44c5a6 AT |
766 | }; |
767 | ||
41abed7d PL |
768 | #define HASH_CACHE_SIZE SHA512_BLOCK_SIZE |
769 | ||
f6beaea3 | 770 | struct safexcel_ahash_export_state { |
31fb084c PL |
771 | u64 len; |
772 | u64 processed; | |
f6beaea3 AT |
773 | |
774 | u32 digest; | |
775 | ||
b460edb6 | 776 | u32 state[SHA512_DIGEST_SIZE / sizeof(u32)]; |
41abed7d | 777 | u8 cache[HASH_CACHE_SIZE]; |
f6beaea3 AT |
778 | }; |
779 | ||
1b44c5a6 AT |
780 | /* |
781 | * Template structure to describe the algorithms in order to register them. | |
782 | * It also has the purpose to contain our private structure and is actually | |
783 | * the only way I know in this framework to avoid having global pointers... | |
784 | */ | |
785 | struct safexcel_alg_template { | |
786 | struct safexcel_crypto_priv *priv; | |
787 | enum safexcel_alg_type type; | |
062b64ca | 788 | enum safexcel_eip_algorithms algo_mask; |
1b44c5a6 AT |
789 | union { |
790 | struct skcipher_alg skcipher; | |
f6beaea3 | 791 | struct aead_alg aead; |
1b44c5a6 AT |
792 | struct ahash_alg ahash; |
793 | } alg; | |
794 | }; | |
795 | ||
796 | struct safexcel_inv_result { | |
797 | struct completion completion; | |
798 | int error; | |
799 | }; | |
800 | ||
86671abb | 801 | void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring); |
bdfd1909 AT |
802 | int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv, |
803 | struct safexcel_result_desc *rdesc); | |
1b44c5a6 | 804 | void safexcel_complete(struct safexcel_crypto_priv *priv, int ring); |
1b44c5a6 | 805 | int safexcel_invalidate_cache(struct crypto_async_request *async, |
1b44c5a6 | 806 | struct safexcel_crypto_priv *priv, |
9744fec9 | 807 | dma_addr_t ctxr_dma, int ring); |
1b44c5a6 | 808 | int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv, |
18e0e95b OH |
809 | struct safexcel_desc_ring *cdr, |
810 | struct safexcel_desc_ring *rdr); | |
1b44c5a6 AT |
811 | int safexcel_select_ring(struct safexcel_crypto_priv *priv); |
812 | void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv, | |
18e0e95b | 813 | struct safexcel_desc_ring *ring); |
9744fec9 | 814 | void *safexcel_ring_first_rptr(struct safexcel_crypto_priv *priv, int ring); |
1b44c5a6 | 815 | void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv, |
18e0e95b | 816 | struct safexcel_desc_ring *ring); |
1b44c5a6 AT |
817 | struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv, |
818 | int ring_id, | |
819 | bool first, bool last, | |
820 | dma_addr_t data, u32 len, | |
821 | u32 full_data_len, | |
822 | dma_addr_t context); | |
823 | struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv, | |
824 | int ring_id, | |
825 | bool first, bool last, | |
826 | dma_addr_t data, u32 len); | |
9744fec9 OH |
827 | int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv, |
828 | int ring); | |
829 | int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv, | |
830 | int ring, | |
831 | struct safexcel_result_desc *rdesc); | |
832 | void safexcel_rdr_req_set(struct safexcel_crypto_priv *priv, | |
833 | int ring, | |
834 | struct safexcel_result_desc *rdesc, | |
835 | struct crypto_async_request *req); | |
836 | inline struct crypto_async_request * | |
837 | safexcel_rdr_req_get(struct safexcel_crypto_priv *priv, int ring); | |
1b44c5a6 | 838 | void safexcel_inv_complete(struct crypto_async_request *req, int error); |
f6beaea3 AT |
839 | int safexcel_hmac_setkey(const char *alg, const u8 *key, unsigned int keylen, |
840 | void *istate, void *ostate); | |
1b44c5a6 AT |
841 | |
842 | /* available algorithms */ | |
a7dea8c0 OH |
843 | extern struct safexcel_alg_template safexcel_alg_ecb_des; |
844 | extern struct safexcel_alg_template safexcel_alg_cbc_des; | |
62469879 OH |
845 | extern struct safexcel_alg_template safexcel_alg_ecb_des3_ede; |
846 | extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede; | |
1b44c5a6 AT |
847 | extern struct safexcel_alg_template safexcel_alg_ecb_aes; |
848 | extern struct safexcel_alg_template safexcel_alg_cbc_aes; | |
48e97afa | 849 | extern struct safexcel_alg_template safexcel_alg_cfb_aes; |
50485dfb | 850 | extern struct safexcel_alg_template safexcel_alg_ofb_aes; |
54f9e8fa | 851 | extern struct safexcel_alg_template safexcel_alg_ctr_aes; |
293f89cf | 852 | extern struct safexcel_alg_template safexcel_alg_md5; |
1b44c5a6 AT |
853 | extern struct safexcel_alg_template safexcel_alg_sha1; |
854 | extern struct safexcel_alg_template safexcel_alg_sha224; | |
855 | extern struct safexcel_alg_template safexcel_alg_sha256; | |
9e46eafd | 856 | extern struct safexcel_alg_template safexcel_alg_sha384; |
b460edb6 | 857 | extern struct safexcel_alg_template safexcel_alg_sha512; |
b471e4b9 | 858 | extern struct safexcel_alg_template safexcel_alg_hmac_md5; |
1b44c5a6 | 859 | extern struct safexcel_alg_template safexcel_alg_hmac_sha1; |
3ad618d8 | 860 | extern struct safexcel_alg_template safexcel_alg_hmac_sha224; |
73f36ea7 | 861 | extern struct safexcel_alg_template safexcel_alg_hmac_sha256; |
1f5d5d98 | 862 | extern struct safexcel_alg_template safexcel_alg_hmac_sha384; |
0de54fb1 | 863 | extern struct safexcel_alg_template safexcel_alg_hmac_sha512; |
01ba061d | 864 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_aes; |
678b2878 | 865 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_aes; |
f6beaea3 | 866 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes; |
ea23cb53 | 867 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_aes; |
87eee125 | 868 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_aes; |
77cdd4ef | 869 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des3_ede; |
0e17e362 PL |
870 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_aes; |
871 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_ctr_aes; | |
872 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_ctr_aes; | |
873 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_ctr_aes; | |
874 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_ctr_aes; | |
c7da38a7 | 875 | extern struct safexcel_alg_template safexcel_alg_xts_aes; |
3e450886 | 876 | extern struct safexcel_alg_template safexcel_alg_gcm; |
4eb76faf | 877 | extern struct safexcel_alg_template safexcel_alg_ccm; |
a7cf8658 | 878 | extern struct safexcel_alg_template safexcel_alg_crc32; |
b98687bb | 879 | extern struct safexcel_alg_template safexcel_alg_cbcmac; |
38f21b4b | 880 | extern struct safexcel_alg_template safexcel_alg_xcbcmac; |
7a627db9 | 881 | extern struct safexcel_alg_template safexcel_alg_cmac; |
4a593fb3 | 882 | extern struct safexcel_alg_template safexcel_alg_chacha20; |
a6061921 PL |
883 | extern struct safexcel_alg_template safexcel_alg_chachapoly; |
884 | extern struct safexcel_alg_template safexcel_alg_chachapoly_esp; | |
0f2bc131 | 885 | extern struct safexcel_alg_template safexcel_alg_sm3; |
aa3a43e6 | 886 | extern struct safexcel_alg_template safexcel_alg_hmac_sm3; |
fcca797d | 887 | extern struct safexcel_alg_template safexcel_alg_ecb_sm4; |
6f2d1428 | 888 | extern struct safexcel_alg_template safexcel_alg_cbc_sm4; |
03a6cfb9 | 889 | extern struct safexcel_alg_template safexcel_alg_ofb_sm4; |
7468ab22 | 890 | extern struct safexcel_alg_template safexcel_alg_cfb_sm4; |
f77e5dc0 | 891 | extern struct safexcel_alg_template safexcel_alg_ctr_sm4; |
1769f704 PL |
892 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_sm4; |
893 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_cbc_sm4; | |
894 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_sm4; | |
895 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_ctr_sm4; | |
aaf5a383 PL |
896 | extern struct safexcel_alg_template safexcel_alg_sha3_224; |
897 | extern struct safexcel_alg_template safexcel_alg_sha3_256; | |
898 | extern struct safexcel_alg_template safexcel_alg_sha3_384; | |
899 | extern struct safexcel_alg_template safexcel_alg_sha3_512; | |
1b44c5a6 AT |
900 | |
901 | #endif |