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25763b3c | 1 | // SPDX-License-Identifier: GPL-2.0-only |
81bef015 CH |
2 | /* |
3 | * Intel IXP4xx NPE-C crypto driver | |
4 | * | |
5 | * Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com> | |
81bef015 CH |
6 | */ |
7 | ||
8 | #include <linux/platform_device.h> | |
9 | #include <linux/dma-mapping.h> | |
10 | #include <linux/dmapool.h> | |
11 | #include <linux/crypto.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/rtnetlink.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/spinlock.h> | |
5a0e3ad6 | 16 | #include <linux/gfp.h> |
75258723 | 17 | #include <linux/module.h> |
81bef015 CH |
18 | |
19 | #include <crypto/ctr.h> | |
3ca20b65 | 20 | #include <crypto/internal/des.h> |
81bef015 | 21 | #include <crypto/aes.h> |
bb9634df | 22 | #include <crypto/hmac.h> |
a24d22b2 | 23 | #include <crypto/sha1.h> |
81bef015 | 24 | #include <crypto/algapi.h> |
5290b428 | 25 | #include <crypto/internal/aead.h> |
4aaf3840 | 26 | #include <crypto/internal/skcipher.h> |
81bef015 CH |
27 | #include <crypto/authenc.h> |
28 | #include <crypto/scatterwalk.h> | |
29 | ||
4af20dc5 LW |
30 | #include <linux/soc/ixp4xx/npe.h> |
31 | #include <linux/soc/ixp4xx/qmgr.h> | |
81bef015 CH |
32 | |
33 | #define MAX_KEYLEN 32 | |
34 | ||
35 | /* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */ | |
36 | #define NPE_CTX_LEN 80 | |
37 | #define AES_BLOCK128 16 | |
38 | ||
39 | #define NPE_OP_HASH_VERIFY 0x01 | |
40 | #define NPE_OP_CCM_ENABLE 0x04 | |
41 | #define NPE_OP_CRYPT_ENABLE 0x08 | |
42 | #define NPE_OP_HASH_ENABLE 0x10 | |
43 | #define NPE_OP_NOT_IN_PLACE 0x20 | |
44 | #define NPE_OP_HMAC_DISABLE 0x40 | |
45 | #define NPE_OP_CRYPT_ENCRYPT 0x80 | |
46 | ||
47 | #define NPE_OP_CCM_GEN_MIC 0xcc | |
48 | #define NPE_OP_HASH_GEN_ICV 0x50 | |
49 | #define NPE_OP_ENC_GEN_KEY 0xc9 | |
50 | ||
51 | #define MOD_ECB 0x0000 | |
52 | #define MOD_CTR 0x1000 | |
53 | #define MOD_CBC_ENC 0x2000 | |
54 | #define MOD_CBC_DEC 0x3000 | |
55 | #define MOD_CCM_ENC 0x4000 | |
56 | #define MOD_CCM_DEC 0x5000 | |
57 | ||
58 | #define KEYLEN_128 4 | |
59 | #define KEYLEN_192 6 | |
60 | #define KEYLEN_256 8 | |
61 | ||
62 | #define CIPH_DECR 0x0000 | |
63 | #define CIPH_ENCR 0x0400 | |
64 | ||
65 | #define MOD_DES 0x0000 | |
66 | #define MOD_TDEA2 0x0100 | |
67 | #define MOD_3DES 0x0200 | |
68 | #define MOD_AES 0x0800 | |
69 | #define MOD_AES128 (0x0800 | KEYLEN_128) | |
70 | #define MOD_AES192 (0x0900 | KEYLEN_192) | |
71 | #define MOD_AES256 (0x0a00 | KEYLEN_256) | |
72 | ||
73 | #define MAX_IVLEN 16 | |
74 | #define NPE_ID 2 /* NPE C */ | |
75 | #define NPE_QLEN 16 | |
76 | /* Space for registering when the first | |
77 | * NPE_QLEN crypt_ctl are busy */ | |
78 | #define NPE_QLEN_TOTAL 64 | |
79 | ||
80 | #define SEND_QID 29 | |
81 | #define RECV_QID 30 | |
82 | ||
83 | #define CTL_FLAG_UNUSED 0x0000 | |
84 | #define CTL_FLAG_USED 0x1000 | |
85 | #define CTL_FLAG_PERFORM_ABLK 0x0001 | |
86 | #define CTL_FLAG_GEN_ICV 0x0002 | |
87 | #define CTL_FLAG_GEN_REVAES 0x0004 | |
88 | #define CTL_FLAG_PERFORM_AEAD 0x0008 | |
89 | #define CTL_FLAG_MASK 0x000f | |
90 | ||
81bef015 CH |
91 | #define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE |
92 | ||
93 | #define MD5_DIGEST_SIZE 16 | |
94 | ||
95 | struct buffer_desc { | |
96 | u32 phys_next; | |
ce057297 | 97 | #ifdef __ARMEB__ |
81bef015 CH |
98 | u16 buf_len; |
99 | u16 pkt_len; | |
ce057297 KH |
100 | #else |
101 | u16 pkt_len; | |
102 | u16 buf_len; | |
103 | #endif | |
ff455ad9 | 104 | dma_addr_t phys_addr; |
81bef015 CH |
105 | u32 __reserved[4]; |
106 | struct buffer_desc *next; | |
0d44dc59 | 107 | enum dma_data_direction dir; |
81bef015 CH |
108 | }; |
109 | ||
110 | struct crypt_ctl { | |
ce057297 | 111 | #ifdef __ARMEB__ |
81bef015 CH |
112 | u8 mode; /* NPE_OP_* operation mode */ |
113 | u8 init_len; | |
114 | u16 reserved; | |
ce057297 KH |
115 | #else |
116 | u16 reserved; | |
117 | u8 init_len; | |
118 | u8 mode; /* NPE_OP_* operation mode */ | |
119 | #endif | |
81bef015 | 120 | u8 iv[MAX_IVLEN]; /* IV for CBC mode or CTR IV for CTR mode */ |
ff455ad9 HX |
121 | dma_addr_t icv_rev_aes; /* icv or rev aes */ |
122 | dma_addr_t src_buf; | |
123 | dma_addr_t dst_buf; | |
ce057297 | 124 | #ifdef __ARMEB__ |
81bef015 CH |
125 | u16 auth_offs; /* Authentication start offset */ |
126 | u16 auth_len; /* Authentication data length */ | |
127 | u16 crypt_offs; /* Cryption start offset */ | |
128 | u16 crypt_len; /* Cryption data length */ | |
ce057297 KH |
129 | #else |
130 | u16 auth_len; /* Authentication data length */ | |
131 | u16 auth_offs; /* Authentication start offset */ | |
132 | u16 crypt_len; /* Cryption data length */ | |
133 | u16 crypt_offs; /* Cryption start offset */ | |
134 | #endif | |
81bef015 CH |
135 | u32 aadAddr; /* Additional Auth Data Addr for CCM mode */ |
136 | u32 crypto_ctx; /* NPE Crypto Param structure address */ | |
137 | ||
138 | /* Used by Host: 4*4 bytes*/ | |
3557084e | 139 | unsigned int ctl_flags; |
81bef015 | 140 | union { |
4aaf3840 | 141 | struct skcipher_request *ablk_req; |
81bef015 CH |
142 | struct aead_request *aead_req; |
143 | struct crypto_tfm *tfm; | |
144 | } data; | |
145 | struct buffer_desc *regist_buf; | |
146 | u8 *regist_ptr; | |
147 | }; | |
148 | ||
149 | struct ablk_ctx { | |
150 | struct buffer_desc *src; | |
151 | struct buffer_desc *dst; | |
e8acf011 CL |
152 | u8 iv[MAX_IVLEN]; |
153 | bool encrypt; | |
dfb098d6 | 154 | struct skcipher_request fallback_req; // keep at the end |
81bef015 CH |
155 | }; |
156 | ||
157 | struct aead_ctx { | |
d7295a8d HX |
158 | struct buffer_desc *src; |
159 | struct buffer_desc *dst; | |
81bef015 CH |
160 | struct scatterlist ivlist; |
161 | /* used when the hmac is not on one sg entry */ | |
162 | u8 *hmac_virt; | |
163 | int encrypt; | |
164 | }; | |
165 | ||
166 | struct ix_hash_algo { | |
167 | u32 cfgword; | |
168 | unsigned char *icv; | |
169 | }; | |
170 | ||
171 | struct ix_sa_dir { | |
172 | unsigned char *npe_ctx; | |
173 | dma_addr_t npe_ctx_phys; | |
174 | int npe_ctx_idx; | |
175 | u8 npe_mode; | |
176 | }; | |
177 | ||
178 | struct ixp_ctx { | |
179 | struct ix_sa_dir encrypt; | |
180 | struct ix_sa_dir decrypt; | |
181 | int authkey_len; | |
182 | u8 authkey[MAX_KEYLEN]; | |
183 | int enckey_len; | |
184 | u8 enckey[MAX_KEYLEN]; | |
185 | u8 salt[MAX_IVLEN]; | |
186 | u8 nonce[CTR_RFC3686_NONCE_SIZE]; | |
3557084e | 187 | unsigned int salted; |
81bef015 CH |
188 | atomic_t configuring; |
189 | struct completion completion; | |
dfb098d6 | 190 | struct crypto_skcipher *fallback_tfm; |
81bef015 CH |
191 | }; |
192 | ||
193 | struct ixp_alg { | |
4aaf3840 | 194 | struct skcipher_alg crypto; |
81bef015 CH |
195 | const struct ix_hash_algo *hash; |
196 | u32 cfg_enc; | |
197 | u32 cfg_dec; | |
198 | ||
199 | int registered; | |
200 | }; | |
201 | ||
d7295a8d HX |
202 | struct ixp_aead_alg { |
203 | struct aead_alg crypto; | |
204 | const struct ix_hash_algo *hash; | |
205 | u32 cfg_enc; | |
206 | u32 cfg_dec; | |
207 | ||
208 | int registered; | |
209 | }; | |
210 | ||
81bef015 CH |
211 | static const struct ix_hash_algo hash_alg_md5 = { |
212 | .cfgword = 0xAA010004, | |
213 | .icv = "\x01\x23\x45\x67\x89\xAB\xCD\xEF" | |
214 | "\xFE\xDC\xBA\x98\x76\x54\x32\x10", | |
215 | }; | |
216 | static const struct ix_hash_algo hash_alg_sha1 = { | |
217 | .cfgword = 0x00000005, | |
218 | .icv = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA" | |
219 | "\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0", | |
220 | }; | |
221 | ||
222 | static struct npe *npe_c; | |
223 | static struct dma_pool *buffer_pool = NULL; | |
224 | static struct dma_pool *ctx_pool = NULL; | |
225 | ||
226 | static struct crypt_ctl *crypt_virt = NULL; | |
227 | static dma_addr_t crypt_phys; | |
228 | ||
229 | static int support_aes = 1; | |
230 | ||
81bef015 | 231 | #define DRIVER_NAME "ixp4xx_crypto" |
81bef015 | 232 | |
d8cbc3f7 | 233 | static struct platform_device *pdev; |
81bef015 CH |
234 | |
235 | static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt) | |
236 | { | |
237 | return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl); | |
238 | } | |
239 | ||
240 | static inline struct crypt_ctl *crypt_phys2virt(dma_addr_t phys) | |
241 | { | |
242 | return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl); | |
243 | } | |
244 | ||
245 | static inline u32 cipher_cfg_enc(struct crypto_tfm *tfm) | |
246 | { | |
4aaf3840 | 247 | return container_of(tfm->__crt_alg, struct ixp_alg,crypto.base)->cfg_enc; |
81bef015 CH |
248 | } |
249 | ||
250 | static inline u32 cipher_cfg_dec(struct crypto_tfm *tfm) | |
251 | { | |
4aaf3840 | 252 | return container_of(tfm->__crt_alg, struct ixp_alg,crypto.base)->cfg_dec; |
81bef015 CH |
253 | } |
254 | ||
255 | static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm) | |
256 | { | |
4aaf3840 | 257 | return container_of(tfm->__crt_alg, struct ixp_alg, crypto.base)->hash; |
81bef015 CH |
258 | } |
259 | ||
260 | static int setup_crypt_desc(void) | |
261 | { | |
27c1789c | 262 | struct device *dev = &pdev->dev; |
81bef015 | 263 | BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64); |
750afb08 LC |
264 | crypt_virt = dma_alloc_coherent(dev, |
265 | NPE_QLEN * sizeof(struct crypt_ctl), | |
266 | &crypt_phys, GFP_ATOMIC); | |
81bef015 CH |
267 | if (!crypt_virt) |
268 | return -ENOMEM; | |
81bef015 CH |
269 | return 0; |
270 | } | |
271 | ||
7dad7d00 | 272 | static DEFINE_SPINLOCK(desc_lock); |
81bef015 CH |
273 | static struct crypt_ctl *get_crypt_desc(void) |
274 | { | |
275 | int i; | |
276 | static int idx = 0; | |
277 | unsigned long flags; | |
278 | ||
279 | spin_lock_irqsave(&desc_lock, flags); | |
280 | ||
281 | if (unlikely(!crypt_virt)) | |
282 | setup_crypt_desc(); | |
283 | if (unlikely(!crypt_virt)) { | |
284 | spin_unlock_irqrestore(&desc_lock, flags); | |
285 | return NULL; | |
286 | } | |
287 | i = idx; | |
288 | if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) { | |
289 | if (++idx >= NPE_QLEN) | |
290 | idx = 0; | |
291 | crypt_virt[i].ctl_flags = CTL_FLAG_USED; | |
292 | spin_unlock_irqrestore(&desc_lock, flags); | |
293 | return crypt_virt +i; | |
294 | } else { | |
295 | spin_unlock_irqrestore(&desc_lock, flags); | |
296 | return NULL; | |
297 | } | |
298 | } | |
299 | ||
7dad7d00 | 300 | static DEFINE_SPINLOCK(emerg_lock); |
81bef015 CH |
301 | static struct crypt_ctl *get_crypt_desc_emerg(void) |
302 | { | |
303 | int i; | |
304 | static int idx = NPE_QLEN; | |
305 | struct crypt_ctl *desc; | |
306 | unsigned long flags; | |
307 | ||
308 | desc = get_crypt_desc(); | |
309 | if (desc) | |
310 | return desc; | |
311 | if (unlikely(!crypt_virt)) | |
312 | return NULL; | |
313 | ||
314 | spin_lock_irqsave(&emerg_lock, flags); | |
315 | i = idx; | |
316 | if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) { | |
317 | if (++idx >= NPE_QLEN_TOTAL) | |
318 | idx = NPE_QLEN; | |
319 | crypt_virt[i].ctl_flags = CTL_FLAG_USED; | |
320 | spin_unlock_irqrestore(&emerg_lock, flags); | |
321 | return crypt_virt +i; | |
322 | } else { | |
323 | spin_unlock_irqrestore(&emerg_lock, flags); | |
324 | return NULL; | |
325 | } | |
326 | } | |
327 | ||
ff455ad9 HX |
328 | static void free_buf_chain(struct device *dev, struct buffer_desc *buf, |
329 | dma_addr_t phys) | |
81bef015 CH |
330 | { |
331 | while (buf) { | |
332 | struct buffer_desc *buf1; | |
333 | u32 phys1; | |
334 | ||
335 | buf1 = buf->next; | |
336 | phys1 = buf->phys_next; | |
9395c58f | 337 | dma_unmap_single(dev, buf->phys_addr, buf->buf_len, buf->dir); |
81bef015 CH |
338 | dma_pool_free(buffer_pool, buf, phys); |
339 | buf = buf1; | |
340 | phys = phys1; | |
341 | } | |
342 | } | |
343 | ||
344 | static struct tasklet_struct crypto_done_tasklet; | |
345 | ||
346 | static void finish_scattered_hmac(struct crypt_ctl *crypt) | |
347 | { | |
348 | struct aead_request *req = crypt->data.aead_req; | |
349 | struct aead_ctx *req_ctx = aead_request_ctx(req); | |
350 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | |
351 | int authsize = crypto_aead_authsize(tfm); | |
d7295a8d | 352 | int decryptlen = req->assoclen + req->cryptlen - authsize; |
81bef015 CH |
353 | |
354 | if (req_ctx->encrypt) { | |
355 | scatterwalk_map_and_copy(req_ctx->hmac_virt, | |
d7295a8d | 356 | req->dst, decryptlen, authsize, 1); |
81bef015 CH |
357 | } |
358 | dma_pool_free(buffer_pool, req_ctx->hmac_virt, crypt->icv_rev_aes); | |
359 | } | |
360 | ||
361 | static void one_packet(dma_addr_t phys) | |
362 | { | |
27c1789c | 363 | struct device *dev = &pdev->dev; |
81bef015 CH |
364 | struct crypt_ctl *crypt; |
365 | struct ixp_ctx *ctx; | |
366 | int failed; | |
81bef015 CH |
367 | |
368 | failed = phys & 0x1 ? -EBADMSG : 0; | |
369 | phys &= ~0x3; | |
370 | crypt = crypt_phys2virt(phys); | |
371 | ||
372 | switch (crypt->ctl_flags & CTL_FLAG_MASK) { | |
373 | case CTL_FLAG_PERFORM_AEAD: { | |
374 | struct aead_request *req = crypt->data.aead_req; | |
375 | struct aead_ctx *req_ctx = aead_request_ctx(req); | |
81bef015 | 376 | |
d7295a8d HX |
377 | free_buf_chain(dev, req_ctx->src, crypt->src_buf); |
378 | free_buf_chain(dev, req_ctx->dst, crypt->dst_buf); | |
81bef015 CH |
379 | if (req_ctx->hmac_virt) { |
380 | finish_scattered_hmac(crypt); | |
381 | } | |
382 | req->base.complete(&req->base, failed); | |
383 | break; | |
384 | } | |
385 | case CTL_FLAG_PERFORM_ABLK: { | |
4aaf3840 AB |
386 | struct skcipher_request *req = crypt->data.ablk_req; |
387 | struct ablk_ctx *req_ctx = skcipher_request_ctx(req); | |
e8acf011 CL |
388 | struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); |
389 | unsigned int ivsize = crypto_skcipher_ivsize(tfm); | |
390 | unsigned int offset; | |
391 | ||
392 | if (ivsize > 0) { | |
393 | offset = req->cryptlen - ivsize; | |
394 | if (req_ctx->encrypt) { | |
395 | scatterwalk_map_and_copy(req->iv, req->dst, | |
396 | offset, ivsize, 0); | |
397 | } else { | |
398 | memcpy(req->iv, req_ctx->iv, ivsize); | |
399 | memzero_explicit(req_ctx->iv, ivsize); | |
400 | } | |
401 | } | |
0d44dc59 | 402 | |
81bef015 | 403 | if (req_ctx->dst) { |
0d44dc59 | 404 | free_buf_chain(dev, req_ctx->dst, crypt->dst_buf); |
81bef015 | 405 | } |
0d44dc59 | 406 | free_buf_chain(dev, req_ctx->src, crypt->src_buf); |
81bef015 CH |
407 | req->base.complete(&req->base, failed); |
408 | break; | |
409 | } | |
410 | case CTL_FLAG_GEN_ICV: | |
411 | ctx = crypto_tfm_ctx(crypt->data.tfm); | |
412 | dma_pool_free(ctx_pool, crypt->regist_ptr, | |
413 | crypt->regist_buf->phys_addr); | |
414 | dma_pool_free(buffer_pool, crypt->regist_buf, crypt->src_buf); | |
415 | if (atomic_dec_and_test(&ctx->configuring)) | |
416 | complete(&ctx->completion); | |
417 | break; | |
418 | case CTL_FLAG_GEN_REVAES: | |
419 | ctx = crypto_tfm_ctx(crypt->data.tfm); | |
420 | *(u32*)ctx->decrypt.npe_ctx &= cpu_to_be32(~CIPH_ENCR); | |
421 | if (atomic_dec_and_test(&ctx->configuring)) | |
422 | complete(&ctx->completion); | |
423 | break; | |
424 | default: | |
425 | BUG(); | |
426 | } | |
427 | crypt->ctl_flags = CTL_FLAG_UNUSED; | |
428 | } | |
429 | ||
430 | static void irqhandler(void *_unused) | |
431 | { | |
432 | tasklet_schedule(&crypto_done_tasklet); | |
433 | } | |
434 | ||
435 | static void crypto_done_action(unsigned long arg) | |
436 | { | |
437 | int i; | |
438 | ||
439 | for(i=0; i<4; i++) { | |
440 | dma_addr_t phys = qmgr_get_entry(RECV_QID); | |
441 | if (!phys) | |
442 | return; | |
443 | one_packet(phys); | |
444 | } | |
445 | tasklet_schedule(&crypto_done_tasklet); | |
446 | } | |
447 | ||
27c1789c | 448 | static int init_ixp_crypto(struct device *dev) |
81bef015 CH |
449 | { |
450 | int ret = -ENODEV; | |
295c01f9 | 451 | u32 msg[2] = { 0, 0 }; |
81bef015 CH |
452 | |
453 | if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH | | |
454 | IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) { | |
455 | printk(KERN_ERR "ixp_crypto: No HW crypto available\n"); | |
456 | return ret; | |
457 | } | |
458 | npe_c = npe_request(NPE_ID); | |
459 | if (!npe_c) | |
460 | return ret; | |
461 | ||
462 | if (!npe_running(npe_c)) { | |
295c01f9 | 463 | ret = npe_load_firmware(npe_c, npe_name(npe_c), dev); |
b363700e | 464 | if (ret) |
c5736a40 | 465 | goto npe_release; |
295c01f9 CH |
466 | if (npe_recv_message(npe_c, msg, "STATUS_MSG")) |
467 | goto npe_error; | |
468 | } else { | |
469 | if (npe_send_message(npe_c, msg, "STATUS_MSG")) | |
470 | goto npe_error; | |
471 | ||
472 | if (npe_recv_message(npe_c, msg, "STATUS_MSG")) | |
473 | goto npe_error; | |
81bef015 CH |
474 | } |
475 | ||
295c01f9 CH |
476 | switch ((msg[1]>>16) & 0xff) { |
477 | case 3: | |
478 | printk(KERN_WARNING "Firmware of %s lacks AES support\n", | |
479 | npe_name(npe_c)); | |
480 | support_aes = 0; | |
481 | break; | |
482 | case 4: | |
483 | case 5: | |
484 | support_aes = 1; | |
485 | break; | |
486 | default: | |
487 | printk(KERN_ERR "Firmware of %s lacks crypto support\n", | |
488 | npe_name(npe_c)); | |
c5736a40 QL |
489 | ret = -ENODEV; |
490 | goto npe_release; | |
295c01f9 | 491 | } |
81bef015 CH |
492 | /* buffer_pool will also be used to sometimes store the hmac, |
493 | * so assure it is large enough | |
494 | */ | |
495 | BUILD_BUG_ON(SHA1_DIGEST_SIZE > sizeof(struct buffer_desc)); | |
496 | buffer_pool = dma_pool_create("buffer", dev, | |
497 | sizeof(struct buffer_desc), 32, 0); | |
498 | ret = -ENOMEM; | |
499 | if (!buffer_pool) { | |
500 | goto err; | |
501 | } | |
502 | ctx_pool = dma_pool_create("context", dev, | |
503 | NPE_CTX_LEN, 16, 0); | |
504 | if (!ctx_pool) { | |
505 | goto err; | |
506 | } | |
1777f1a9 KH |
507 | ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0, |
508 | "ixp_crypto:out", NULL); | |
81bef015 CH |
509 | if (ret) |
510 | goto err; | |
1777f1a9 KH |
511 | ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0, |
512 | "ixp_crypto:in", NULL); | |
81bef015 CH |
513 | if (ret) { |
514 | qmgr_release_queue(SEND_QID); | |
515 | goto err; | |
516 | } | |
517 | qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL); | |
518 | tasklet_init(&crypto_done_tasklet, crypto_done_action, 0); | |
519 | ||
520 | qmgr_enable_irq(RECV_QID); | |
521 | return 0; | |
295c01f9 CH |
522 | |
523 | npe_error: | |
524 | printk(KERN_ERR "%s not responding\n", npe_name(npe_c)); | |
525 | ret = -EIO; | |
81bef015 | 526 | err: |
f9d1293b ME |
527 | dma_pool_destroy(ctx_pool); |
528 | dma_pool_destroy(buffer_pool); | |
c5736a40 | 529 | npe_release: |
81bef015 CH |
530 | npe_release(npe_c); |
531 | return ret; | |
532 | } | |
533 | ||
27c1789c | 534 | static void release_ixp_crypto(struct device *dev) |
81bef015 CH |
535 | { |
536 | qmgr_disable_irq(RECV_QID); | |
537 | tasklet_kill(&crypto_done_tasklet); | |
538 | ||
539 | qmgr_release_queue(SEND_QID); | |
540 | qmgr_release_queue(RECV_QID); | |
541 | ||
542 | dma_pool_destroy(ctx_pool); | |
543 | dma_pool_destroy(buffer_pool); | |
544 | ||
545 | npe_release(npe_c); | |
546 | ||
547 | if (crypt_virt) { | |
548 | dma_free_coherent(dev, | |
f7ade9aa | 549 | NPE_QLEN * sizeof(struct crypt_ctl), |
81bef015 CH |
550 | crypt_virt, crypt_phys); |
551 | } | |
81bef015 CH |
552 | } |
553 | ||
554 | static void reset_sa_dir(struct ix_sa_dir *dir) | |
555 | { | |
556 | memset(dir->npe_ctx, 0, NPE_CTX_LEN); | |
557 | dir->npe_ctx_idx = 0; | |
558 | dir->npe_mode = 0; | |
559 | } | |
560 | ||
561 | static int init_sa_dir(struct ix_sa_dir *dir) | |
562 | { | |
563 | dir->npe_ctx = dma_pool_alloc(ctx_pool, GFP_KERNEL, &dir->npe_ctx_phys); | |
564 | if (!dir->npe_ctx) { | |
565 | return -ENOMEM; | |
566 | } | |
567 | reset_sa_dir(dir); | |
568 | return 0; | |
569 | } | |
570 | ||
571 | static void free_sa_dir(struct ix_sa_dir *dir) | |
572 | { | |
573 | memset(dir->npe_ctx, 0, NPE_CTX_LEN); | |
574 | dma_pool_free(ctx_pool, dir->npe_ctx, dir->npe_ctx_phys); | |
575 | } | |
576 | ||
577 | static int init_tfm(struct crypto_tfm *tfm) | |
578 | { | |
579 | struct ixp_ctx *ctx = crypto_tfm_ctx(tfm); | |
580 | int ret; | |
581 | ||
582 | atomic_set(&ctx->configuring, 0); | |
583 | ret = init_sa_dir(&ctx->encrypt); | |
584 | if (ret) | |
585 | return ret; | |
586 | ret = init_sa_dir(&ctx->decrypt); | |
587 | if (ret) { | |
588 | free_sa_dir(&ctx->encrypt); | |
589 | } | |
590 | return ret; | |
591 | } | |
592 | ||
4aaf3840 | 593 | static int init_tfm_ablk(struct crypto_skcipher *tfm) |
81bef015 | 594 | { |
dfb098d6 CL |
595 | struct crypto_tfm *ctfm = crypto_skcipher_tfm(tfm); |
596 | struct ixp_ctx *ctx = crypto_tfm_ctx(ctfm); | |
597 | const char *name = crypto_tfm_alg_name(ctfm); | |
598 | ||
599 | ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); | |
600 | if (IS_ERR(ctx->fallback_tfm)) { | |
601 | pr_err("ERROR: Cannot allocate fallback for %s %ld\n", | |
602 | name, PTR_ERR(ctx->fallback_tfm)); | |
603 | return PTR_ERR(ctx->fallback_tfm); | |
604 | } | |
605 | ||
606 | pr_info("Fallback for %s is %s\n", | |
607 | crypto_tfm_alg_driver_name(&tfm->base), | |
608 | crypto_tfm_alg_driver_name(crypto_skcipher_tfm(ctx->fallback_tfm)) | |
609 | ); | |
610 | ||
611 | crypto_skcipher_set_reqsize(tfm, sizeof(struct ablk_ctx) + crypto_skcipher_reqsize(ctx->fallback_tfm)); | |
4aaf3840 | 612 | return init_tfm(crypto_skcipher_tfm(tfm)); |
81bef015 CH |
613 | } |
614 | ||
d7295a8d | 615 | static int init_tfm_aead(struct crypto_aead *tfm) |
81bef015 | 616 | { |
d7295a8d HX |
617 | crypto_aead_set_reqsize(tfm, sizeof(struct aead_ctx)); |
618 | return init_tfm(crypto_aead_tfm(tfm)); | |
81bef015 CH |
619 | } |
620 | ||
621 | static void exit_tfm(struct crypto_tfm *tfm) | |
622 | { | |
623 | struct ixp_ctx *ctx = crypto_tfm_ctx(tfm); | |
624 | free_sa_dir(&ctx->encrypt); | |
625 | free_sa_dir(&ctx->decrypt); | |
626 | } | |
627 | ||
4aaf3840 AB |
628 | static void exit_tfm_ablk(struct crypto_skcipher *tfm) |
629 | { | |
dfb098d6 CL |
630 | struct crypto_tfm *ctfm = crypto_skcipher_tfm(tfm); |
631 | struct ixp_ctx *ctx = crypto_tfm_ctx(ctfm); | |
632 | ||
633 | crypto_free_skcipher(ctx->fallback_tfm); | |
4aaf3840 AB |
634 | exit_tfm(crypto_skcipher_tfm(tfm)); |
635 | } | |
636 | ||
d7295a8d HX |
637 | static void exit_tfm_aead(struct crypto_aead *tfm) |
638 | { | |
639 | exit_tfm(crypto_aead_tfm(tfm)); | |
640 | } | |
641 | ||
81bef015 CH |
642 | static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target, |
643 | int init_len, u32 ctx_addr, const u8 *key, int key_len) | |
644 | { | |
645 | struct ixp_ctx *ctx = crypto_tfm_ctx(tfm); | |
646 | struct crypt_ctl *crypt; | |
647 | struct buffer_desc *buf; | |
648 | int i; | |
649 | u8 *pad; | |
ff455ad9 | 650 | dma_addr_t pad_phys, buf_phys; |
81bef015 CH |
651 | |
652 | BUILD_BUG_ON(NPE_CTX_LEN < HMAC_PAD_BLOCKLEN); | |
653 | pad = dma_pool_alloc(ctx_pool, GFP_KERNEL, &pad_phys); | |
654 | if (!pad) | |
655 | return -ENOMEM; | |
656 | buf = dma_pool_alloc(buffer_pool, GFP_KERNEL, &buf_phys); | |
657 | if (!buf) { | |
658 | dma_pool_free(ctx_pool, pad, pad_phys); | |
659 | return -ENOMEM; | |
660 | } | |
661 | crypt = get_crypt_desc_emerg(); | |
662 | if (!crypt) { | |
663 | dma_pool_free(ctx_pool, pad, pad_phys); | |
664 | dma_pool_free(buffer_pool, buf, buf_phys); | |
665 | return -EAGAIN; | |
666 | } | |
667 | ||
668 | memcpy(pad, key, key_len); | |
669 | memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len); | |
670 | for (i = 0; i < HMAC_PAD_BLOCKLEN; i++) { | |
671 | pad[i] ^= xpad; | |
672 | } | |
673 | ||
674 | crypt->data.tfm = tfm; | |
675 | crypt->regist_ptr = pad; | |
676 | crypt->regist_buf = buf; | |
677 | ||
678 | crypt->auth_offs = 0; | |
679 | crypt->auth_len = HMAC_PAD_BLOCKLEN; | |
680 | crypt->crypto_ctx = ctx_addr; | |
681 | crypt->src_buf = buf_phys; | |
682 | crypt->icv_rev_aes = target; | |
683 | crypt->mode = NPE_OP_HASH_GEN_ICV; | |
684 | crypt->init_len = init_len; | |
685 | crypt->ctl_flags |= CTL_FLAG_GEN_ICV; | |
686 | ||
687 | buf->next = 0; | |
688 | buf->buf_len = HMAC_PAD_BLOCKLEN; | |
689 | buf->pkt_len = 0; | |
690 | buf->phys_addr = pad_phys; | |
691 | ||
692 | atomic_inc(&ctx->configuring); | |
693 | qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); | |
694 | BUG_ON(qmgr_stat_overflow(SEND_QID)); | |
695 | return 0; | |
696 | } | |
697 | ||
3557084e CL |
698 | static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned int authsize, |
699 | const u8 *key, int key_len, unsigned int digest_len) | |
81bef015 CH |
700 | { |
701 | u32 itarget, otarget, npe_ctx_addr; | |
702 | unsigned char *cinfo; | |
703 | int init_len, ret = 0; | |
704 | u32 cfgword; | |
705 | struct ix_sa_dir *dir; | |
706 | struct ixp_ctx *ctx = crypto_tfm_ctx(tfm); | |
707 | const struct ix_hash_algo *algo; | |
708 | ||
709 | dir = encrypt ? &ctx->encrypt : &ctx->decrypt; | |
710 | cinfo = dir->npe_ctx + dir->npe_ctx_idx; | |
711 | algo = ix_hash(tfm); | |
712 | ||
713 | /* write cfg word to cryptinfo */ | |
714 | cfgword = algo->cfgword | ( authsize << 6); /* (authsize/4) << 8 */ | |
ce057297 KH |
715 | #ifndef __ARMEB__ |
716 | cfgword ^= 0xAA000000; /* change the "byte swap" flags */ | |
717 | #endif | |
81bef015 CH |
718 | *(u32*)cinfo = cpu_to_be32(cfgword); |
719 | cinfo += sizeof(cfgword); | |
720 | ||
721 | /* write ICV to cryptinfo */ | |
722 | memcpy(cinfo, algo->icv, digest_len); | |
723 | cinfo += digest_len; | |
724 | ||
725 | itarget = dir->npe_ctx_phys + dir->npe_ctx_idx | |
726 | + sizeof(algo->cfgword); | |
727 | otarget = itarget + digest_len; | |
728 | init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx); | |
729 | npe_ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx; | |
730 | ||
731 | dir->npe_ctx_idx += init_len; | |
732 | dir->npe_mode |= NPE_OP_HASH_ENABLE; | |
733 | ||
734 | if (!encrypt) | |
735 | dir->npe_mode |= NPE_OP_HASH_VERIFY; | |
736 | ||
737 | ret = register_chain_var(tfm, HMAC_OPAD_VALUE, otarget, | |
738 | init_len, npe_ctx_addr, key, key_len); | |
739 | if (ret) | |
740 | return ret; | |
741 | return register_chain_var(tfm, HMAC_IPAD_VALUE, itarget, | |
742 | init_len, npe_ctx_addr, key, key_len); | |
743 | } | |
744 | ||
745 | static int gen_rev_aes_key(struct crypto_tfm *tfm) | |
746 | { | |
747 | struct crypt_ctl *crypt; | |
748 | struct ixp_ctx *ctx = crypto_tfm_ctx(tfm); | |
749 | struct ix_sa_dir *dir = &ctx->decrypt; | |
750 | ||
751 | crypt = get_crypt_desc_emerg(); | |
752 | if (!crypt) { | |
753 | return -EAGAIN; | |
754 | } | |
755 | *(u32*)dir->npe_ctx |= cpu_to_be32(CIPH_ENCR); | |
756 | ||
757 | crypt->data.tfm = tfm; | |
758 | crypt->crypt_offs = 0; | |
759 | crypt->crypt_len = AES_BLOCK128; | |
760 | crypt->src_buf = 0; | |
761 | crypt->crypto_ctx = dir->npe_ctx_phys; | |
762 | crypt->icv_rev_aes = dir->npe_ctx_phys + sizeof(u32); | |
763 | crypt->mode = NPE_OP_ENC_GEN_KEY; | |
764 | crypt->init_len = dir->npe_ctx_idx; | |
765 | crypt->ctl_flags |= CTL_FLAG_GEN_REVAES; | |
766 | ||
767 | atomic_inc(&ctx->configuring); | |
768 | qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); | |
769 | BUG_ON(qmgr_stat_overflow(SEND_QID)); | |
770 | return 0; | |
771 | } | |
772 | ||
773 | static int setup_cipher(struct crypto_tfm *tfm, int encrypt, | |
774 | const u8 *key, int key_len) | |
775 | { | |
776 | u8 *cinfo; | |
777 | u32 cipher_cfg; | |
778 | u32 keylen_cfg = 0; | |
779 | struct ix_sa_dir *dir; | |
780 | struct ixp_ctx *ctx = crypto_tfm_ctx(tfm); | |
c4c4db0d | 781 | int err; |
81bef015 CH |
782 | |
783 | dir = encrypt ? &ctx->encrypt : &ctx->decrypt; | |
784 | cinfo = dir->npe_ctx; | |
785 | ||
786 | if (encrypt) { | |
787 | cipher_cfg = cipher_cfg_enc(tfm); | |
788 | dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT; | |
789 | } else { | |
790 | cipher_cfg = cipher_cfg_dec(tfm); | |
791 | } | |
792 | if (cipher_cfg & MOD_AES) { | |
793 | switch (key_len) { | |
9792eb1d KH |
794 | case 16: keylen_cfg = MOD_AES128; break; |
795 | case 24: keylen_cfg = MOD_AES192; break; | |
796 | case 32: keylen_cfg = MOD_AES256; break; | |
797 | default: | |
9792eb1d | 798 | return -EINVAL; |
81bef015 CH |
799 | } |
800 | cipher_cfg |= keylen_cfg; | |
81bef015 | 801 | } else { |
c4c4db0d EB |
802 | err = crypto_des_verify_key(tfm, key); |
803 | if (err) | |
804 | return err; | |
81bef015 CH |
805 | } |
806 | /* write cfg word to cryptinfo */ | |
807 | *(u32*)cinfo = cpu_to_be32(cipher_cfg); | |
808 | cinfo += sizeof(cipher_cfg); | |
809 | ||
810 | /* write cipher key to cryptinfo */ | |
811 | memcpy(cinfo, key, key_len); | |
812 | /* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */ | |
813 | if (key_len < DES3_EDE_KEY_SIZE && !(cipher_cfg & MOD_AES)) { | |
814 | memset(cinfo + key_len, 0, DES3_EDE_KEY_SIZE -key_len); | |
815 | key_len = DES3_EDE_KEY_SIZE; | |
816 | } | |
817 | dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len; | |
818 | dir->npe_mode |= NPE_OP_CRYPT_ENABLE; | |
819 | if ((cipher_cfg & MOD_AES) && !encrypt) { | |
820 | return gen_rev_aes_key(tfm); | |
821 | } | |
822 | return 0; | |
823 | } | |
824 | ||
0d44dc59 | 825 | static struct buffer_desc *chainup_buffers(struct device *dev, |
3557084e | 826 | struct scatterlist *sg, unsigned int nbytes, |
0d44dc59 CH |
827 | struct buffer_desc *buf, gfp_t flags, |
828 | enum dma_data_direction dir) | |
81bef015 | 829 | { |
5be4d4c9 | 830 | for (; nbytes > 0; sg = sg_next(sg)) { |
3557084e | 831 | unsigned int len = min(nbytes, sg->length); |
81bef015 | 832 | struct buffer_desc *next_buf; |
ff455ad9 | 833 | dma_addr_t next_buf_phys; |
0d44dc59 | 834 | void *ptr; |
81bef015 | 835 | |
81bef015 | 836 | nbytes -= len; |
796b40c6 | 837 | ptr = sg_virt(sg); |
81bef015 | 838 | next_buf = dma_pool_alloc(buffer_pool, flags, &next_buf_phys); |
0d44dc59 CH |
839 | if (!next_buf) { |
840 | buf = NULL; | |
841 | break; | |
842 | } | |
843 | sg_dma_address(sg) = dma_map_single(dev, ptr, len, dir); | |
81bef015 CH |
844 | buf->next = next_buf; |
845 | buf->phys_next = next_buf_phys; | |
81bef015 | 846 | buf = next_buf; |
0d44dc59 | 847 | |
81bef015 CH |
848 | buf->phys_addr = sg_dma_address(sg); |
849 | buf->buf_len = len; | |
0d44dc59 | 850 | buf->dir = dir; |
81bef015 | 851 | } |
0d44dc59 CH |
852 | buf->next = NULL; |
853 | buf->phys_next = 0; | |
81bef015 CH |
854 | return buf; |
855 | } | |
856 | ||
4aaf3840 | 857 | static int ablk_setkey(struct crypto_skcipher *tfm, const u8 *key, |
81bef015 CH |
858 | unsigned int key_len) |
859 | { | |
4aaf3840 | 860 | struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm); |
81bef015 CH |
861 | int ret; |
862 | ||
863 | init_completion(&ctx->completion); | |
864 | atomic_inc(&ctx->configuring); | |
865 | ||
866 | reset_sa_dir(&ctx->encrypt); | |
867 | reset_sa_dir(&ctx->decrypt); | |
868 | ||
869 | ctx->encrypt.npe_mode = NPE_OP_HMAC_DISABLE; | |
870 | ctx->decrypt.npe_mode = NPE_OP_HMAC_DISABLE; | |
871 | ||
872 | ret = setup_cipher(&tfm->base, 0, key, key_len); | |
873 | if (ret) | |
874 | goto out; | |
875 | ret = setup_cipher(&tfm->base, 1, key, key_len); | |
81bef015 CH |
876 | out: |
877 | if (!atomic_dec_and_test(&ctx->configuring)) | |
878 | wait_for_completion(&ctx->completion); | |
dfb098d6 CL |
879 | if (ret) |
880 | return ret; | |
881 | crypto_skcipher_clear_flags(ctx->fallback_tfm, CRYPTO_TFM_REQ_MASK); | |
882 | crypto_skcipher_set_flags(ctx->fallback_tfm, tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK); | |
883 | ||
884 | return crypto_skcipher_setkey(ctx->fallback_tfm, key, key_len); | |
81bef015 CH |
885 | } |
886 | ||
4aaf3840 | 887 | static int ablk_des3_setkey(struct crypto_skcipher *tfm, const u8 *key, |
dba434a9 HX |
888 | unsigned int key_len) |
889 | { | |
4aaf3840 | 890 | return verify_skcipher_des3_key(tfm, key) ?: |
3ca20b65 | 891 | ablk_setkey(tfm, key, key_len); |
dba434a9 HX |
892 | } |
893 | ||
4aaf3840 | 894 | static int ablk_rfc3686_setkey(struct crypto_skcipher *tfm, const u8 *key, |
81bef015 CH |
895 | unsigned int key_len) |
896 | { | |
4aaf3840 | 897 | struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm); |
81bef015 CH |
898 | |
899 | /* the nonce is stored in bytes at end of key */ | |
900 | if (key_len < CTR_RFC3686_NONCE_SIZE) | |
901 | return -EINVAL; | |
902 | ||
903 | memcpy(ctx->nonce, key + (key_len - CTR_RFC3686_NONCE_SIZE), | |
904 | CTR_RFC3686_NONCE_SIZE); | |
905 | ||
906 | key_len -= CTR_RFC3686_NONCE_SIZE; | |
907 | return ablk_setkey(tfm, key, key_len); | |
908 | } | |
909 | ||
dfb098d6 CL |
910 | static int ixp4xx_cipher_fallback(struct skcipher_request *areq, int encrypt) |
911 | { | |
912 | struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq); | |
913 | struct ixp_ctx *op = crypto_skcipher_ctx(tfm); | |
914 | struct ablk_ctx *rctx = skcipher_request_ctx(areq); | |
915 | int err; | |
916 | ||
917 | skcipher_request_set_tfm(&rctx->fallback_req, op->fallback_tfm); | |
918 | skcipher_request_set_callback(&rctx->fallback_req, areq->base.flags, | |
919 | areq->base.complete, areq->base.data); | |
920 | skcipher_request_set_crypt(&rctx->fallback_req, areq->src, areq->dst, | |
921 | areq->cryptlen, areq->iv); | |
922 | if (encrypt) | |
923 | err = crypto_skcipher_encrypt(&rctx->fallback_req); | |
924 | else | |
925 | err = crypto_skcipher_decrypt(&rctx->fallback_req); | |
926 | return err; | |
927 | } | |
928 | ||
4aaf3840 | 929 | static int ablk_perform(struct skcipher_request *req, int encrypt) |
81bef015 | 930 | { |
4aaf3840 AB |
931 | struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); |
932 | struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm); | |
3557084e | 933 | unsigned int ivsize = crypto_skcipher_ivsize(tfm); |
81bef015 CH |
934 | struct ix_sa_dir *dir; |
935 | struct crypt_ctl *crypt; | |
4aaf3840 | 936 | unsigned int nbytes = req->cryptlen; |
81bef015 | 937 | enum dma_data_direction src_direction = DMA_BIDIRECTIONAL; |
4aaf3840 | 938 | struct ablk_ctx *req_ctx = skcipher_request_ctx(req); |
0d44dc59 | 939 | struct buffer_desc src_hook; |
27c1789c | 940 | struct device *dev = &pdev->dev; |
e8acf011 | 941 | unsigned int offset; |
81bef015 CH |
942 | gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? |
943 | GFP_KERNEL : GFP_ATOMIC; | |
944 | ||
dfb098d6 CL |
945 | if (sg_nents(req->src) > 1 || sg_nents(req->dst) > 1) |
946 | return ixp4xx_cipher_fallback(req, encrypt); | |
947 | ||
81bef015 CH |
948 | if (qmgr_stat_full(SEND_QID)) |
949 | return -EAGAIN; | |
950 | if (atomic_read(&ctx->configuring)) | |
951 | return -EAGAIN; | |
952 | ||
953 | dir = encrypt ? &ctx->encrypt : &ctx->decrypt; | |
e8acf011 | 954 | req_ctx->encrypt = encrypt; |
81bef015 CH |
955 | |
956 | crypt = get_crypt_desc(); | |
957 | if (!crypt) | |
0d44dc59 | 958 | return -ENOMEM; |
81bef015 CH |
959 | |
960 | crypt->data.ablk_req = req; | |
961 | crypt->crypto_ctx = dir->npe_ctx_phys; | |
962 | crypt->mode = dir->npe_mode; | |
963 | crypt->init_len = dir->npe_ctx_idx; | |
964 | ||
965 | crypt->crypt_offs = 0; | |
966 | crypt->crypt_len = nbytes; | |
967 | ||
4aaf3840 AB |
968 | BUG_ON(ivsize && !req->iv); |
969 | memcpy(crypt->iv, req->iv, ivsize); | |
e8acf011 CL |
970 | if (ivsize > 0 && !encrypt) { |
971 | offset = req->cryptlen - ivsize; | |
972 | scatterwalk_map_and_copy(req_ctx->iv, req->src, offset, ivsize, 0); | |
973 | } | |
81bef015 | 974 | if (req->src != req->dst) { |
0d44dc59 | 975 | struct buffer_desc dst_hook; |
81bef015 | 976 | crypt->mode |= NPE_OP_NOT_IN_PLACE; |
81bef015 CH |
977 | /* This was never tested by Intel |
978 | * for more than one dst buffer, I think. */ | |
0d44dc59 CH |
979 | req_ctx->dst = NULL; |
980 | if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook, | |
981 | flags, DMA_FROM_DEVICE)) | |
81bef015 CH |
982 | goto free_buf_dest; |
983 | src_direction = DMA_TO_DEVICE; | |
0d44dc59 CH |
984 | req_ctx->dst = dst_hook.next; |
985 | crypt->dst_buf = dst_hook.phys_next; | |
81bef015 CH |
986 | } else { |
987 | req_ctx->dst = NULL; | |
81bef015 | 988 | } |
0d44dc59 CH |
989 | req_ctx->src = NULL; |
990 | if (!chainup_buffers(dev, req->src, nbytes, &src_hook, | |
991 | flags, src_direction)) | |
81bef015 CH |
992 | goto free_buf_src; |
993 | ||
0d44dc59 CH |
994 | req_ctx->src = src_hook.next; |
995 | crypt->src_buf = src_hook.phys_next; | |
81bef015 CH |
996 | crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK; |
997 | qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); | |
998 | BUG_ON(qmgr_stat_overflow(SEND_QID)); | |
999 | return -EINPROGRESS; | |
1000 | ||
1001 | free_buf_src: | |
0d44dc59 | 1002 | free_buf_chain(dev, req_ctx->src, crypt->src_buf); |
81bef015 CH |
1003 | free_buf_dest: |
1004 | if (req->src != req->dst) { | |
0d44dc59 | 1005 | free_buf_chain(dev, req_ctx->dst, crypt->dst_buf); |
81bef015 CH |
1006 | } |
1007 | crypt->ctl_flags = CTL_FLAG_UNUSED; | |
0d44dc59 | 1008 | return -ENOMEM; |
81bef015 CH |
1009 | } |
1010 | ||
4aaf3840 | 1011 | static int ablk_encrypt(struct skcipher_request *req) |
81bef015 CH |
1012 | { |
1013 | return ablk_perform(req, 1); | |
1014 | } | |
1015 | ||
4aaf3840 | 1016 | static int ablk_decrypt(struct skcipher_request *req) |
81bef015 CH |
1017 | { |
1018 | return ablk_perform(req, 0); | |
1019 | } | |
1020 | ||
4aaf3840 | 1021 | static int ablk_rfc3686_crypt(struct skcipher_request *req) |
81bef015 | 1022 | { |
4aaf3840 AB |
1023 | struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); |
1024 | struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm); | |
81bef015 | 1025 | u8 iv[CTR_RFC3686_BLOCK_SIZE]; |
4aaf3840 | 1026 | u8 *info = req->iv; |
81bef015 CH |
1027 | int ret; |
1028 | ||
1029 | /* set up counter block */ | |
1030 | memcpy(iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE); | |
1031 | memcpy(iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE); | |
1032 | ||
1033 | /* initialize counter portion of counter block */ | |
1034 | *(__be32 *)(iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) = | |
1035 | cpu_to_be32(1); | |
1036 | ||
4aaf3840 | 1037 | req->iv = iv; |
81bef015 | 1038 | ret = ablk_perform(req, 1); |
4aaf3840 | 1039 | req->iv = info; |
81bef015 CH |
1040 | return ret; |
1041 | } | |
1042 | ||
81bef015 CH |
1043 | static int aead_perform(struct aead_request *req, int encrypt, |
1044 | int cryptoffset, int eff_cryptlen, u8 *iv) | |
1045 | { | |
1046 | struct crypto_aead *tfm = crypto_aead_reqtfm(req); | |
1047 | struct ixp_ctx *ctx = crypto_aead_ctx(tfm); | |
3557084e CL |
1048 | unsigned int ivsize = crypto_aead_ivsize(tfm); |
1049 | unsigned int authsize = crypto_aead_authsize(tfm); | |
81bef015 CH |
1050 | struct ix_sa_dir *dir; |
1051 | struct crypt_ctl *crypt; | |
0d44dc59 CH |
1052 | unsigned int cryptlen; |
1053 | struct buffer_desc *buf, src_hook; | |
81bef015 | 1054 | struct aead_ctx *req_ctx = aead_request_ctx(req); |
27c1789c | 1055 | struct device *dev = &pdev->dev; |
81bef015 CH |
1056 | gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? |
1057 | GFP_KERNEL : GFP_ATOMIC; | |
d7295a8d HX |
1058 | enum dma_data_direction src_direction = DMA_BIDIRECTIONAL; |
1059 | unsigned int lastlen; | |
81bef015 CH |
1060 | |
1061 | if (qmgr_stat_full(SEND_QID)) | |
1062 | return -EAGAIN; | |
1063 | if (atomic_read(&ctx->configuring)) | |
1064 | return -EAGAIN; | |
1065 | ||
1066 | if (encrypt) { | |
1067 | dir = &ctx->encrypt; | |
1068 | cryptlen = req->cryptlen; | |
1069 | } else { | |
1070 | dir = &ctx->decrypt; | |
1071 | /* req->cryptlen includes the authsize when decrypting */ | |
1072 | cryptlen = req->cryptlen -authsize; | |
1073 | eff_cryptlen -= authsize; | |
1074 | } | |
1075 | crypt = get_crypt_desc(); | |
1076 | if (!crypt) | |
0d44dc59 | 1077 | return -ENOMEM; |
81bef015 CH |
1078 | |
1079 | crypt->data.aead_req = req; | |
1080 | crypt->crypto_ctx = dir->npe_ctx_phys; | |
1081 | crypt->mode = dir->npe_mode; | |
1082 | crypt->init_len = dir->npe_ctx_idx; | |
1083 | ||
1084 | crypt->crypt_offs = cryptoffset; | |
1085 | crypt->crypt_len = eff_cryptlen; | |
1086 | ||
1087 | crypt->auth_offs = 0; | |
d7295a8d | 1088 | crypt->auth_len = req->assoclen + cryptlen; |
81bef015 CH |
1089 | BUG_ON(ivsize && !req->iv); |
1090 | memcpy(crypt->iv, req->iv, ivsize); | |
1091 | ||
0f987e25 HX |
1092 | buf = chainup_buffers(dev, req->src, crypt->auth_len, |
1093 | &src_hook, flags, src_direction); | |
1094 | req_ctx->src = src_hook.next; | |
1095 | crypt->src_buf = src_hook.phys_next; | |
1096 | if (!buf) | |
1097 | goto free_buf_src; | |
1098 | ||
1099 | lastlen = buf->buf_len; | |
1100 | if (lastlen >= authsize) | |
1101 | crypt->icv_rev_aes = buf->phys_addr + | |
1102 | buf->buf_len - authsize; | |
1103 | ||
d7295a8d HX |
1104 | req_ctx->dst = NULL; |
1105 | ||
81bef015 | 1106 | if (req->src != req->dst) { |
d7295a8d HX |
1107 | struct buffer_desc dst_hook; |
1108 | ||
1109 | crypt->mode |= NPE_OP_NOT_IN_PLACE; | |
1110 | src_direction = DMA_TO_DEVICE; | |
1111 | ||
1112 | buf = chainup_buffers(dev, req->dst, crypt->auth_len, | |
1113 | &dst_hook, flags, DMA_FROM_DEVICE); | |
1114 | req_ctx->dst = dst_hook.next; | |
1115 | crypt->dst_buf = dst_hook.phys_next; | |
1116 | ||
1117 | if (!buf) | |
1118 | goto free_buf_dst; | |
1119 | ||
1120 | if (encrypt) { | |
1121 | lastlen = buf->buf_len; | |
1122 | if (lastlen >= authsize) | |
1123 | crypt->icv_rev_aes = buf->phys_addr + | |
1124 | buf->buf_len - authsize; | |
1125 | } | |
81bef015 CH |
1126 | } |
1127 | ||
d7295a8d | 1128 | if (unlikely(lastlen < authsize)) { |
81bef015 CH |
1129 | /* The 12 hmac bytes are scattered, |
1130 | * we need to copy them into a safe buffer */ | |
1131 | req_ctx->hmac_virt = dma_pool_alloc(buffer_pool, flags, | |
1132 | &crypt->icv_rev_aes); | |
1133 | if (unlikely(!req_ctx->hmac_virt)) | |
28389575 | 1134 | goto free_buf_dst; |
81bef015 CH |
1135 | if (!encrypt) { |
1136 | scatterwalk_map_and_copy(req_ctx->hmac_virt, | |
1137 | req->src, cryptlen, authsize, 0); | |
1138 | } | |
1139 | req_ctx->encrypt = encrypt; | |
1140 | } else { | |
1141 | req_ctx->hmac_virt = NULL; | |
1142 | } | |
0d44dc59 | 1143 | |
81bef015 CH |
1144 | crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD; |
1145 | qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); | |
1146 | BUG_ON(qmgr_stat_overflow(SEND_QID)); | |
1147 | return -EINPROGRESS; | |
d7295a8d | 1148 | |
d7295a8d HX |
1149 | free_buf_dst: |
1150 | free_buf_chain(dev, req_ctx->dst, crypt->dst_buf); | |
28389575 HX |
1151 | free_buf_src: |
1152 | free_buf_chain(dev, req_ctx->src, crypt->src_buf); | |
81bef015 | 1153 | crypt->ctl_flags = CTL_FLAG_UNUSED; |
0d44dc59 | 1154 | return -ENOMEM; |
81bef015 CH |
1155 | } |
1156 | ||
1157 | static int aead_setup(struct crypto_aead *tfm, unsigned int authsize) | |
1158 | { | |
1159 | struct ixp_ctx *ctx = crypto_aead_ctx(tfm); | |
3557084e | 1160 | unsigned int digest_len = crypto_aead_maxauthsize(tfm); |
81bef015 CH |
1161 | int ret; |
1162 | ||
1163 | if (!ctx->enckey_len && !ctx->authkey_len) | |
1164 | return 0; | |
1165 | init_completion(&ctx->completion); | |
1166 | atomic_inc(&ctx->configuring); | |
1167 | ||
1168 | reset_sa_dir(&ctx->encrypt); | |
1169 | reset_sa_dir(&ctx->decrypt); | |
1170 | ||
1171 | ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len); | |
1172 | if (ret) | |
1173 | goto out; | |
1174 | ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len); | |
1175 | if (ret) | |
1176 | goto out; | |
1177 | ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey, | |
1178 | ctx->authkey_len, digest_len); | |
1179 | if (ret) | |
1180 | goto out; | |
1181 | ret = setup_auth(&tfm->base, 1, authsize, ctx->authkey, | |
1182 | ctx->authkey_len, digest_len); | |
81bef015 CH |
1183 | out: |
1184 | if (!atomic_dec_and_test(&ctx->configuring)) | |
1185 | wait_for_completion(&ctx->completion); | |
1186 | return ret; | |
1187 | } | |
1188 | ||
1189 | static int aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize) | |
1190 | { | |
6da9c233 | 1191 | int max = crypto_aead_maxauthsize(tfm) >> 2; |
81bef015 CH |
1192 | |
1193 | if ((authsize>>2) < 1 || (authsize>>2) > max || (authsize & 3)) | |
1194 | return -EINVAL; | |
1195 | return aead_setup(tfm, authsize); | |
1196 | } | |
1197 | ||
1198 | static int aead_setkey(struct crypto_aead *tfm, const u8 *key, | |
1199 | unsigned int keylen) | |
1200 | { | |
1201 | struct ixp_ctx *ctx = crypto_aead_ctx(tfm); | |
56902781 | 1202 | struct crypto_authenc_keys keys; |
81bef015 | 1203 | |
56902781 | 1204 | if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) |
81bef015 CH |
1205 | goto badkey; |
1206 | ||
56902781 MK |
1207 | if (keys.authkeylen > sizeof(ctx->authkey)) |
1208 | goto badkey; | |
81bef015 | 1209 | |
56902781 | 1210 | if (keys.enckeylen > sizeof(ctx->enckey)) |
81bef015 CH |
1211 | goto badkey; |
1212 | ||
56902781 MK |
1213 | memcpy(ctx->authkey, keys.authkey, keys.authkeylen); |
1214 | memcpy(ctx->enckey, keys.enckey, keys.enckeylen); | |
1215 | ctx->authkey_len = keys.authkeylen; | |
1216 | ctx->enckey_len = keys.enckeylen; | |
81bef015 | 1217 | |
0e7da29d | 1218 | memzero_explicit(&keys, sizeof(keys)); |
81bef015 CH |
1219 | return aead_setup(tfm, crypto_aead_authsize(tfm)); |
1220 | badkey: | |
0e7da29d | 1221 | memzero_explicit(&keys, sizeof(keys)); |
81bef015 CH |
1222 | return -EINVAL; |
1223 | } | |
1224 | ||
dba434a9 HX |
1225 | static int des3_aead_setkey(struct crypto_aead *tfm, const u8 *key, |
1226 | unsigned int keylen) | |
1227 | { | |
1228 | struct ixp_ctx *ctx = crypto_aead_ctx(tfm); | |
dba434a9 HX |
1229 | struct crypto_authenc_keys keys; |
1230 | int err; | |
1231 | ||
1232 | err = crypto_authenc_extractkeys(&keys, key, keylen); | |
1233 | if (unlikely(err)) | |
1234 | goto badkey; | |
1235 | ||
1236 | err = -EINVAL; | |
1237 | if (keys.authkeylen > sizeof(ctx->authkey)) | |
1238 | goto badkey; | |
1239 | ||
3ca20b65 AB |
1240 | err = verify_aead_des3_key(tfm, keys.enckey, keys.enckeylen); |
1241 | if (err) | |
dba434a9 HX |
1242 | goto badkey; |
1243 | ||
1244 | memcpy(ctx->authkey, keys.authkey, keys.authkeylen); | |
1245 | memcpy(ctx->enckey, keys.enckey, keys.enckeylen); | |
1246 | ctx->authkey_len = keys.authkeylen; | |
1247 | ctx->enckey_len = keys.enckeylen; | |
1248 | ||
1249 | memzero_explicit(&keys, sizeof(keys)); | |
1250 | return aead_setup(tfm, crypto_aead_authsize(tfm)); | |
1251 | badkey: | |
dba434a9 HX |
1252 | memzero_explicit(&keys, sizeof(keys)); |
1253 | return err; | |
1254 | } | |
1255 | ||
81bef015 CH |
1256 | static int aead_encrypt(struct aead_request *req) |
1257 | { | |
d7295a8d | 1258 | return aead_perform(req, 1, req->assoclen, req->cryptlen, req->iv); |
81bef015 CH |
1259 | } |
1260 | ||
1261 | static int aead_decrypt(struct aead_request *req) | |
1262 | { | |
d7295a8d | 1263 | return aead_perform(req, 0, req->assoclen, req->cryptlen, req->iv); |
81bef015 CH |
1264 | } |
1265 | ||
1266 | static struct ixp_alg ixp4xx_algos[] = { | |
1267 | { | |
1268 | .crypto = { | |
4aaf3840 AB |
1269 | .base.cra_name = "cbc(des)", |
1270 | .base.cra_blocksize = DES_BLOCK_SIZE, | |
1271 | ||
1272 | .min_keysize = DES_KEY_SIZE, | |
1273 | .max_keysize = DES_KEY_SIZE, | |
1274 | .ivsize = DES_BLOCK_SIZE, | |
81bef015 CH |
1275 | }, |
1276 | .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192, | |
1277 | .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192, | |
1278 | ||
1279 | }, { | |
1280 | .crypto = { | |
4aaf3840 AB |
1281 | .base.cra_name = "ecb(des)", |
1282 | .base.cra_blocksize = DES_BLOCK_SIZE, | |
1283 | .min_keysize = DES_KEY_SIZE, | |
1284 | .max_keysize = DES_KEY_SIZE, | |
81bef015 CH |
1285 | }, |
1286 | .cfg_enc = CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192, | |
1287 | .cfg_dec = CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192, | |
1288 | }, { | |
1289 | .crypto = { | |
4aaf3840 AB |
1290 | .base.cra_name = "cbc(des3_ede)", |
1291 | .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, | |
1292 | ||
1293 | .min_keysize = DES3_EDE_KEY_SIZE, | |
1294 | .max_keysize = DES3_EDE_KEY_SIZE, | |
1295 | .ivsize = DES3_EDE_BLOCK_SIZE, | |
1296 | .setkey = ablk_des3_setkey, | |
81bef015 CH |
1297 | }, |
1298 | .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192, | |
1299 | .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192, | |
1300 | }, { | |
1301 | .crypto = { | |
4aaf3840 AB |
1302 | .base.cra_name = "ecb(des3_ede)", |
1303 | .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, | |
1304 | ||
1305 | .min_keysize = DES3_EDE_KEY_SIZE, | |
1306 | .max_keysize = DES3_EDE_KEY_SIZE, | |
1307 | .setkey = ablk_des3_setkey, | |
81bef015 CH |
1308 | }, |
1309 | .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_ECB | KEYLEN_192, | |
1310 | .cfg_dec = CIPH_DECR | MOD_3DES | MOD_ECB | KEYLEN_192, | |
1311 | }, { | |
1312 | .crypto = { | |
4aaf3840 AB |
1313 | .base.cra_name = "cbc(aes)", |
1314 | .base.cra_blocksize = AES_BLOCK_SIZE, | |
1315 | ||
1316 | .min_keysize = AES_MIN_KEY_SIZE, | |
1317 | .max_keysize = AES_MAX_KEY_SIZE, | |
1318 | .ivsize = AES_BLOCK_SIZE, | |
81bef015 CH |
1319 | }, |
1320 | .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC, | |
1321 | .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC, | |
1322 | }, { | |
1323 | .crypto = { | |
4aaf3840 AB |
1324 | .base.cra_name = "ecb(aes)", |
1325 | .base.cra_blocksize = AES_BLOCK_SIZE, | |
1326 | ||
1327 | .min_keysize = AES_MIN_KEY_SIZE, | |
1328 | .max_keysize = AES_MAX_KEY_SIZE, | |
81bef015 CH |
1329 | }, |
1330 | .cfg_enc = CIPH_ENCR | MOD_AES | MOD_ECB, | |
1331 | .cfg_dec = CIPH_DECR | MOD_AES | MOD_ECB, | |
1332 | }, { | |
1333 | .crypto = { | |
4aaf3840 AB |
1334 | .base.cra_name = "ctr(aes)", |
1335 | .base.cra_blocksize = 1, | |
1336 | ||
1337 | .min_keysize = AES_MIN_KEY_SIZE, | |
1338 | .max_keysize = AES_MAX_KEY_SIZE, | |
1339 | .ivsize = AES_BLOCK_SIZE, | |
81bef015 CH |
1340 | }, |
1341 | .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR, | |
1342 | .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR, | |
1343 | }, { | |
1344 | .crypto = { | |
4aaf3840 AB |
1345 | .base.cra_name = "rfc3686(ctr(aes))", |
1346 | .base.cra_blocksize = 1, | |
1347 | ||
1348 | .min_keysize = AES_MIN_KEY_SIZE, | |
1349 | .max_keysize = AES_MAX_KEY_SIZE, | |
1350 | .ivsize = AES_BLOCK_SIZE, | |
1351 | .setkey = ablk_rfc3686_setkey, | |
1352 | .encrypt = ablk_rfc3686_crypt, | |
1353 | .decrypt = ablk_rfc3686_crypt, | |
81bef015 CH |
1354 | }, |
1355 | .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR, | |
1356 | .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR, | |
d7295a8d HX |
1357 | } }; |
1358 | ||
1359 | static struct ixp_aead_alg ixp4xx_aeads[] = { | |
1360 | { | |
81bef015 | 1361 | .crypto = { |
d7295a8d HX |
1362 | .base = { |
1363 | .cra_name = "authenc(hmac(md5),cbc(des))", | |
1364 | .cra_blocksize = DES_BLOCK_SIZE, | |
1365 | }, | |
1366 | .ivsize = DES_BLOCK_SIZE, | |
1367 | .maxauthsize = MD5_DIGEST_SIZE, | |
81bef015 CH |
1368 | }, |
1369 | .hash = &hash_alg_md5, | |
1370 | .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192, | |
1371 | .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192, | |
1372 | }, { | |
1373 | .crypto = { | |
d7295a8d HX |
1374 | .base = { |
1375 | .cra_name = "authenc(hmac(md5),cbc(des3_ede))", | |
1376 | .cra_blocksize = DES3_EDE_BLOCK_SIZE, | |
1377 | }, | |
1378 | .ivsize = DES3_EDE_BLOCK_SIZE, | |
1379 | .maxauthsize = MD5_DIGEST_SIZE, | |
dba434a9 | 1380 | .setkey = des3_aead_setkey, |
81bef015 CH |
1381 | }, |
1382 | .hash = &hash_alg_md5, | |
1383 | .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192, | |
1384 | .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192, | |
1385 | }, { | |
1386 | .crypto = { | |
d7295a8d HX |
1387 | .base = { |
1388 | .cra_name = "authenc(hmac(sha1),cbc(des))", | |
1389 | .cra_blocksize = DES_BLOCK_SIZE, | |
1390 | }, | |
81bef015 CH |
1391 | .ivsize = DES_BLOCK_SIZE, |
1392 | .maxauthsize = SHA1_DIGEST_SIZE, | |
81bef015 CH |
1393 | }, |
1394 | .hash = &hash_alg_sha1, | |
1395 | .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192, | |
1396 | .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192, | |
1397 | }, { | |
1398 | .crypto = { | |
d7295a8d HX |
1399 | .base = { |
1400 | .cra_name = "authenc(hmac(sha1),cbc(des3_ede))", | |
1401 | .cra_blocksize = DES3_EDE_BLOCK_SIZE, | |
1402 | }, | |
1403 | .ivsize = DES3_EDE_BLOCK_SIZE, | |
1404 | .maxauthsize = SHA1_DIGEST_SIZE, | |
dba434a9 | 1405 | .setkey = des3_aead_setkey, |
81bef015 CH |
1406 | }, |
1407 | .hash = &hash_alg_sha1, | |
1408 | .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192, | |
1409 | .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192, | |
1410 | }, { | |
1411 | .crypto = { | |
d7295a8d HX |
1412 | .base = { |
1413 | .cra_name = "authenc(hmac(md5),cbc(aes))", | |
1414 | .cra_blocksize = AES_BLOCK_SIZE, | |
1415 | }, | |
1416 | .ivsize = AES_BLOCK_SIZE, | |
1417 | .maxauthsize = MD5_DIGEST_SIZE, | |
81bef015 CH |
1418 | }, |
1419 | .hash = &hash_alg_md5, | |
1420 | .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC, | |
1421 | .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC, | |
1422 | }, { | |
1423 | .crypto = { | |
d7295a8d HX |
1424 | .base = { |
1425 | .cra_name = "authenc(hmac(sha1),cbc(aes))", | |
1426 | .cra_blocksize = AES_BLOCK_SIZE, | |
1427 | }, | |
1428 | .ivsize = AES_BLOCK_SIZE, | |
1429 | .maxauthsize = SHA1_DIGEST_SIZE, | |
81bef015 CH |
1430 | }, |
1431 | .hash = &hash_alg_sha1, | |
1432 | .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC, | |
1433 | .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC, | |
1434 | } }; | |
1435 | ||
1436 | #define IXP_POSTFIX "-ixp4xx" | |
d8cbc3f7 RK |
1437 | |
1438 | static const struct platform_device_info ixp_dev_info __initdata = { | |
1439 | .name = DRIVER_NAME, | |
1440 | .id = 0, | |
1441 | .dma_mask = DMA_BIT_MASK(32), | |
1442 | }; | |
1443 | ||
81bef015 CH |
1444 | static int __init ixp_module_init(void) |
1445 | { | |
1446 | int num = ARRAY_SIZE(ixp4xx_algos); | |
efb753b8 | 1447 | int i, err; |
81bef015 | 1448 | |
d8cbc3f7 RK |
1449 | pdev = platform_device_register_full(&ixp_dev_info); |
1450 | if (IS_ERR(pdev)) | |
1451 | return PTR_ERR(pdev); | |
1452 | ||
27c1789c | 1453 | err = init_ixp_crypto(&pdev->dev); |
81bef015 | 1454 | if (err) { |
d8cbc3f7 | 1455 | platform_device_unregister(pdev); |
81bef015 CH |
1456 | return err; |
1457 | } | |
1458 | for (i=0; i< num; i++) { | |
4aaf3840 | 1459 | struct skcipher_alg *cra = &ixp4xx_algos[i].crypto; |
81bef015 | 1460 | |
4aaf3840 AB |
1461 | if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, |
1462 | "%s"IXP_POSTFIX, cra->base.cra_name) >= | |
81bef015 CH |
1463 | CRYPTO_MAX_ALG_NAME) |
1464 | { | |
1465 | continue; | |
1466 | } | |
1467 | if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES)) { | |
1468 | continue; | |
1469 | } | |
d7295a8d HX |
1470 | |
1471 | /* block ciphers */ | |
4aaf3840 | 1472 | cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
b8aa7dc5 | 1473 | CRYPTO_ALG_ASYNC | |
dfb098d6 CL |
1474 | CRYPTO_ALG_ALLOCATES_MEMORY | |
1475 | CRYPTO_ALG_NEED_FALLBACK; | |
4aaf3840 AB |
1476 | if (!cra->setkey) |
1477 | cra->setkey = ablk_setkey; | |
1478 | if (!cra->encrypt) | |
1479 | cra->encrypt = ablk_encrypt; | |
1480 | if (!cra->decrypt) | |
1481 | cra->decrypt = ablk_decrypt; | |
1482 | cra->init = init_tfm_ablk; | |
1483 | cra->exit = exit_tfm_ablk; | |
1484 | ||
1485 | cra->base.cra_ctxsize = sizeof(struct ixp_ctx); | |
1486 | cra->base.cra_module = THIS_MODULE; | |
1487 | cra->base.cra_alignmask = 3; | |
1488 | cra->base.cra_priority = 300; | |
1489 | if (crypto_register_skcipher(cra)) | |
81bef015 | 1490 | printk(KERN_ERR "Failed to register '%s'\n", |
4aaf3840 | 1491 | cra->base.cra_name); |
81bef015 CH |
1492 | else |
1493 | ixp4xx_algos[i].registered = 1; | |
1494 | } | |
d7295a8d HX |
1495 | |
1496 | for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) { | |
1497 | struct aead_alg *cra = &ixp4xx_aeads[i].crypto; | |
1498 | ||
1499 | if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, | |
1500 | "%s"IXP_POSTFIX, cra->base.cra_name) >= | |
1501 | CRYPTO_MAX_ALG_NAME) | |
1502 | continue; | |
1503 | if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES)) | |
1504 | continue; | |
1505 | ||
1506 | /* authenc */ | |
1507 | cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | | |
b8aa7dc5 MP |
1508 | CRYPTO_ALG_ASYNC | |
1509 | CRYPTO_ALG_ALLOCATES_MEMORY; | |
dba434a9 | 1510 | cra->setkey = cra->setkey ?: aead_setkey; |
d7295a8d HX |
1511 | cra->setauthsize = aead_setauthsize; |
1512 | cra->encrypt = aead_encrypt; | |
1513 | cra->decrypt = aead_decrypt; | |
1514 | cra->init = init_tfm_aead; | |
1515 | cra->exit = exit_tfm_aead; | |
1516 | ||
1517 | cra->base.cra_ctxsize = sizeof(struct ixp_ctx); | |
1518 | cra->base.cra_module = THIS_MODULE; | |
1519 | cra->base.cra_alignmask = 3; | |
1520 | cra->base.cra_priority = 300; | |
1521 | ||
1522 | if (crypto_register_aead(cra)) | |
1523 | printk(KERN_ERR "Failed to register '%s'\n", | |
1524 | cra->base.cra_driver_name); | |
1525 | else | |
1526 | ixp4xx_aeads[i].registered = 1; | |
1527 | } | |
81bef015 CH |
1528 | return 0; |
1529 | } | |
1530 | ||
1531 | static void __exit ixp_module_exit(void) | |
1532 | { | |
1533 | int num = ARRAY_SIZE(ixp4xx_algos); | |
1534 | int i; | |
1535 | ||
d7295a8d HX |
1536 | for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) { |
1537 | if (ixp4xx_aeads[i].registered) | |
1538 | crypto_unregister_aead(&ixp4xx_aeads[i].crypto); | |
1539 | } | |
1540 | ||
81bef015 CH |
1541 | for (i=0; i< num; i++) { |
1542 | if (ixp4xx_algos[i].registered) | |
4aaf3840 | 1543 | crypto_unregister_skcipher(&ixp4xx_algos[i].crypto); |
81bef015 | 1544 | } |
27c1789c | 1545 | release_ixp_crypto(&pdev->dev); |
d8cbc3f7 | 1546 | platform_device_unregister(pdev); |
81bef015 CH |
1547 | } |
1548 | ||
1549 | module_init(ixp_module_init); | |
1550 | module_exit(ixp_module_exit); | |
1551 | ||
1552 | MODULE_LICENSE("GPL"); | |
1553 | MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>"); | |
1554 | MODULE_DESCRIPTION("IXP4xx hardware crypto"); | |
1555 |