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DMA-API: crypto: fix ixp4xx crypto platform device support
[mirror_ubuntu-jammy-kernel.git] / drivers / crypto / ixp4xx_crypto.c
CommitLineData
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1/*
2 * Intel IXP4xx NPE-C crypto driver
3 *
4 * Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/platform_device.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmapool.h>
15#include <linux/crypto.h>
16#include <linux/kernel.h>
17#include <linux/rtnetlink.h>
18#include <linux/interrupt.h>
19#include <linux/spinlock.h>
5a0e3ad6 20#include <linux/gfp.h>
75258723 21#include <linux/module.h>
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22
23#include <crypto/ctr.h>
24#include <crypto/des.h>
25#include <crypto/aes.h>
26#include <crypto/sha.h>
27#include <crypto/algapi.h>
28#include <crypto/aead.h>
29#include <crypto/authenc.h>
30#include <crypto/scatterwalk.h>
31
a09e64fb
RK
32#include <mach/npe.h>
33#include <mach/qmgr.h>
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CH
34
35#define MAX_KEYLEN 32
36
37/* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */
38#define NPE_CTX_LEN 80
39#define AES_BLOCK128 16
40
41#define NPE_OP_HASH_VERIFY 0x01
42#define NPE_OP_CCM_ENABLE 0x04
43#define NPE_OP_CRYPT_ENABLE 0x08
44#define NPE_OP_HASH_ENABLE 0x10
45#define NPE_OP_NOT_IN_PLACE 0x20
46#define NPE_OP_HMAC_DISABLE 0x40
47#define NPE_OP_CRYPT_ENCRYPT 0x80
48
49#define NPE_OP_CCM_GEN_MIC 0xcc
50#define NPE_OP_HASH_GEN_ICV 0x50
51#define NPE_OP_ENC_GEN_KEY 0xc9
52
53#define MOD_ECB 0x0000
54#define MOD_CTR 0x1000
55#define MOD_CBC_ENC 0x2000
56#define MOD_CBC_DEC 0x3000
57#define MOD_CCM_ENC 0x4000
58#define MOD_CCM_DEC 0x5000
59
60#define KEYLEN_128 4
61#define KEYLEN_192 6
62#define KEYLEN_256 8
63
64#define CIPH_DECR 0x0000
65#define CIPH_ENCR 0x0400
66
67#define MOD_DES 0x0000
68#define MOD_TDEA2 0x0100
69#define MOD_3DES 0x0200
70#define MOD_AES 0x0800
71#define MOD_AES128 (0x0800 | KEYLEN_128)
72#define MOD_AES192 (0x0900 | KEYLEN_192)
73#define MOD_AES256 (0x0a00 | KEYLEN_256)
74
75#define MAX_IVLEN 16
76#define NPE_ID 2 /* NPE C */
77#define NPE_QLEN 16
78/* Space for registering when the first
79 * NPE_QLEN crypt_ctl are busy */
80#define NPE_QLEN_TOTAL 64
81
82#define SEND_QID 29
83#define RECV_QID 30
84
85#define CTL_FLAG_UNUSED 0x0000
86#define CTL_FLAG_USED 0x1000
87#define CTL_FLAG_PERFORM_ABLK 0x0001
88#define CTL_FLAG_GEN_ICV 0x0002
89#define CTL_FLAG_GEN_REVAES 0x0004
90#define CTL_FLAG_PERFORM_AEAD 0x0008
91#define CTL_FLAG_MASK 0x000f
92
93#define HMAC_IPAD_VALUE 0x36
94#define HMAC_OPAD_VALUE 0x5C
95#define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE
96
97#define MD5_DIGEST_SIZE 16
98
99struct buffer_desc {
100 u32 phys_next;
ce057297 101#ifdef __ARMEB__
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102 u16 buf_len;
103 u16 pkt_len;
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104#else
105 u16 pkt_len;
106 u16 buf_len;
107#endif
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108 u32 phys_addr;
109 u32 __reserved[4];
110 struct buffer_desc *next;
0d44dc59 111 enum dma_data_direction dir;
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112};
113
114struct crypt_ctl {
ce057297 115#ifdef __ARMEB__
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116 u8 mode; /* NPE_OP_* operation mode */
117 u8 init_len;
118 u16 reserved;
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119#else
120 u16 reserved;
121 u8 init_len;
122 u8 mode; /* NPE_OP_* operation mode */
123#endif
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124 u8 iv[MAX_IVLEN]; /* IV for CBC mode or CTR IV for CTR mode */
125 u32 icv_rev_aes; /* icv or rev aes */
126 u32 src_buf;
127 u32 dst_buf;
ce057297 128#ifdef __ARMEB__
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129 u16 auth_offs; /* Authentication start offset */
130 u16 auth_len; /* Authentication data length */
131 u16 crypt_offs; /* Cryption start offset */
132 u16 crypt_len; /* Cryption data length */
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KH
133#else
134 u16 auth_len; /* Authentication data length */
135 u16 auth_offs; /* Authentication start offset */
136 u16 crypt_len; /* Cryption data length */
137 u16 crypt_offs; /* Cryption start offset */
138#endif
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139 u32 aadAddr; /* Additional Auth Data Addr for CCM mode */
140 u32 crypto_ctx; /* NPE Crypto Param structure address */
141
142 /* Used by Host: 4*4 bytes*/
143 unsigned ctl_flags;
144 union {
145 struct ablkcipher_request *ablk_req;
146 struct aead_request *aead_req;
147 struct crypto_tfm *tfm;
148 } data;
149 struct buffer_desc *regist_buf;
150 u8 *regist_ptr;
151};
152
153struct ablk_ctx {
154 struct buffer_desc *src;
155 struct buffer_desc *dst;
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156};
157
158struct aead_ctx {
159 struct buffer_desc *buffer;
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160 struct scatterlist ivlist;
161 /* used when the hmac is not on one sg entry */
162 u8 *hmac_virt;
163 int encrypt;
164};
165
166struct ix_hash_algo {
167 u32 cfgword;
168 unsigned char *icv;
169};
170
171struct ix_sa_dir {
172 unsigned char *npe_ctx;
173 dma_addr_t npe_ctx_phys;
174 int npe_ctx_idx;
175 u8 npe_mode;
176};
177
178struct ixp_ctx {
179 struct ix_sa_dir encrypt;
180 struct ix_sa_dir decrypt;
181 int authkey_len;
182 u8 authkey[MAX_KEYLEN];
183 int enckey_len;
184 u8 enckey[MAX_KEYLEN];
185 u8 salt[MAX_IVLEN];
186 u8 nonce[CTR_RFC3686_NONCE_SIZE];
187 unsigned salted;
188 atomic_t configuring;
189 struct completion completion;
190};
191
192struct ixp_alg {
193 struct crypto_alg crypto;
194 const struct ix_hash_algo *hash;
195 u32 cfg_enc;
196 u32 cfg_dec;
197
198 int registered;
199};
200
201static const struct ix_hash_algo hash_alg_md5 = {
202 .cfgword = 0xAA010004,
203 .icv = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
204 "\xFE\xDC\xBA\x98\x76\x54\x32\x10",
205};
206static const struct ix_hash_algo hash_alg_sha1 = {
207 .cfgword = 0x00000005,
208 .icv = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
209 "\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
210};
211
212static struct npe *npe_c;
213static struct dma_pool *buffer_pool = NULL;
214static struct dma_pool *ctx_pool = NULL;
215
216static struct crypt_ctl *crypt_virt = NULL;
217static dma_addr_t crypt_phys;
218
219static int support_aes = 1;
220
81bef015 221#define DRIVER_NAME "ixp4xx_crypto"
81bef015 222
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223static struct platform_device *pdev;
224static struct device *dev;
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225
226static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt)
227{
228 return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl);
229}
230
231static inline struct crypt_ctl *crypt_phys2virt(dma_addr_t phys)
232{
233 return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl);
234}
235
236static inline u32 cipher_cfg_enc(struct crypto_tfm *tfm)
237{
238 return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_enc;
239}
240
241static inline u32 cipher_cfg_dec(struct crypto_tfm *tfm)
242{
243 return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_dec;
244}
245
246static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm)
247{
248 return container_of(tfm->__crt_alg, struct ixp_alg, crypto)->hash;
249}
250
251static int setup_crypt_desc(void)
252{
253 BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64);
254 crypt_virt = dma_alloc_coherent(dev,
255 NPE_QLEN * sizeof(struct crypt_ctl),
e7a2577a 256 &crypt_phys, GFP_ATOMIC);
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257 if (!crypt_virt)
258 return -ENOMEM;
259 memset(crypt_virt, 0, NPE_QLEN * sizeof(struct crypt_ctl));
260 return 0;
261}
262
263static spinlock_t desc_lock;
264static struct crypt_ctl *get_crypt_desc(void)
265{
266 int i;
267 static int idx = 0;
268 unsigned long flags;
269
270 spin_lock_irqsave(&desc_lock, flags);
271
272 if (unlikely(!crypt_virt))
273 setup_crypt_desc();
274 if (unlikely(!crypt_virt)) {
275 spin_unlock_irqrestore(&desc_lock, flags);
276 return NULL;
277 }
278 i = idx;
279 if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
280 if (++idx >= NPE_QLEN)
281 idx = 0;
282 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
283 spin_unlock_irqrestore(&desc_lock, flags);
284 return crypt_virt +i;
285 } else {
286 spin_unlock_irqrestore(&desc_lock, flags);
287 return NULL;
288 }
289}
290
291static spinlock_t emerg_lock;
292static struct crypt_ctl *get_crypt_desc_emerg(void)
293{
294 int i;
295 static int idx = NPE_QLEN;
296 struct crypt_ctl *desc;
297 unsigned long flags;
298
299 desc = get_crypt_desc();
300 if (desc)
301 return desc;
302 if (unlikely(!crypt_virt))
303 return NULL;
304
305 spin_lock_irqsave(&emerg_lock, flags);
306 i = idx;
307 if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
308 if (++idx >= NPE_QLEN_TOTAL)
309 idx = NPE_QLEN;
310 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
311 spin_unlock_irqrestore(&emerg_lock, flags);
312 return crypt_virt +i;
313 } else {
314 spin_unlock_irqrestore(&emerg_lock, flags);
315 return NULL;
316 }
317}
318
0d44dc59 319static void free_buf_chain(struct device *dev, struct buffer_desc *buf,u32 phys)
81bef015
CH
320{
321 while (buf) {
322 struct buffer_desc *buf1;
323 u32 phys1;
324
325 buf1 = buf->next;
326 phys1 = buf->phys_next;
0d44dc59 327 dma_unmap_single(dev, buf->phys_next, buf->buf_len, buf->dir);
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CH
328 dma_pool_free(buffer_pool, buf, phys);
329 buf = buf1;
330 phys = phys1;
331 }
332}
333
334static struct tasklet_struct crypto_done_tasklet;
335
336static void finish_scattered_hmac(struct crypt_ctl *crypt)
337{
338 struct aead_request *req = crypt->data.aead_req;
339 struct aead_ctx *req_ctx = aead_request_ctx(req);
340 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
341 int authsize = crypto_aead_authsize(tfm);
342 int decryptlen = req->cryptlen - authsize;
343
344 if (req_ctx->encrypt) {
345 scatterwalk_map_and_copy(req_ctx->hmac_virt,
346 req->src, decryptlen, authsize, 1);
347 }
348 dma_pool_free(buffer_pool, req_ctx->hmac_virt, crypt->icv_rev_aes);
349}
350
351static void one_packet(dma_addr_t phys)
352{
353 struct crypt_ctl *crypt;
354 struct ixp_ctx *ctx;
355 int failed;
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CH
356
357 failed = phys & 0x1 ? -EBADMSG : 0;
358 phys &= ~0x3;
359 crypt = crypt_phys2virt(phys);
360
361 switch (crypt->ctl_flags & CTL_FLAG_MASK) {
362 case CTL_FLAG_PERFORM_AEAD: {
363 struct aead_request *req = crypt->data.aead_req;
364 struct aead_ctx *req_ctx = aead_request_ctx(req);
81bef015 365
0d44dc59 366 free_buf_chain(dev, req_ctx->buffer, crypt->src_buf);
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CH
367 if (req_ctx->hmac_virt) {
368 finish_scattered_hmac(crypt);
369 }
370 req->base.complete(&req->base, failed);
371 break;
372 }
373 case CTL_FLAG_PERFORM_ABLK: {
374 struct ablkcipher_request *req = crypt->data.ablk_req;
375 struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
0d44dc59 376
81bef015 377 if (req_ctx->dst) {
0d44dc59 378 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
81bef015 379 }
0d44dc59 380 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
81bef015
CH
381 req->base.complete(&req->base, failed);
382 break;
383 }
384 case CTL_FLAG_GEN_ICV:
385 ctx = crypto_tfm_ctx(crypt->data.tfm);
386 dma_pool_free(ctx_pool, crypt->regist_ptr,
387 crypt->regist_buf->phys_addr);
388 dma_pool_free(buffer_pool, crypt->regist_buf, crypt->src_buf);
389 if (atomic_dec_and_test(&ctx->configuring))
390 complete(&ctx->completion);
391 break;
392 case CTL_FLAG_GEN_REVAES:
393 ctx = crypto_tfm_ctx(crypt->data.tfm);
394 *(u32*)ctx->decrypt.npe_ctx &= cpu_to_be32(~CIPH_ENCR);
395 if (atomic_dec_and_test(&ctx->configuring))
396 complete(&ctx->completion);
397 break;
398 default:
399 BUG();
400 }
401 crypt->ctl_flags = CTL_FLAG_UNUSED;
402}
403
404static void irqhandler(void *_unused)
405{
406 tasklet_schedule(&crypto_done_tasklet);
407}
408
409static void crypto_done_action(unsigned long arg)
410{
411 int i;
412
413 for(i=0; i<4; i++) {
414 dma_addr_t phys = qmgr_get_entry(RECV_QID);
415 if (!phys)
416 return;
417 one_packet(phys);
418 }
419 tasklet_schedule(&crypto_done_tasklet);
420}
421
422static int init_ixp_crypto(void)
423{
424 int ret = -ENODEV;
295c01f9 425 u32 msg[2] = { 0, 0 };
81bef015
CH
426
427 if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
428 IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
429 printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
430 return ret;
431 }
432 npe_c = npe_request(NPE_ID);
433 if (!npe_c)
434 return ret;
435
436 if (!npe_running(npe_c)) {
295c01f9
CH
437 ret = npe_load_firmware(npe_c, npe_name(npe_c), dev);
438 if (ret) {
439 return ret;
440 }
441 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
442 goto npe_error;
443 } else {
444 if (npe_send_message(npe_c, msg, "STATUS_MSG"))
445 goto npe_error;
446
447 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
448 goto npe_error;
81bef015
CH
449 }
450
295c01f9
CH
451 switch ((msg[1]>>16) & 0xff) {
452 case 3:
453 printk(KERN_WARNING "Firmware of %s lacks AES support\n",
454 npe_name(npe_c));
455 support_aes = 0;
456 break;
457 case 4:
458 case 5:
459 support_aes = 1;
460 break;
461 default:
462 printk(KERN_ERR "Firmware of %s lacks crypto support\n",
463 npe_name(npe_c));
464 return -ENODEV;
465 }
81bef015
CH
466 /* buffer_pool will also be used to sometimes store the hmac,
467 * so assure it is large enough
468 */
469 BUILD_BUG_ON(SHA1_DIGEST_SIZE > sizeof(struct buffer_desc));
470 buffer_pool = dma_pool_create("buffer", dev,
471 sizeof(struct buffer_desc), 32, 0);
472 ret = -ENOMEM;
473 if (!buffer_pool) {
474 goto err;
475 }
476 ctx_pool = dma_pool_create("context", dev,
477 NPE_CTX_LEN, 16, 0);
478 if (!ctx_pool) {
479 goto err;
480 }
1777f1a9
KH
481 ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0,
482 "ixp_crypto:out", NULL);
81bef015
CH
483 if (ret)
484 goto err;
1777f1a9
KH
485 ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0,
486 "ixp_crypto:in", NULL);
81bef015
CH
487 if (ret) {
488 qmgr_release_queue(SEND_QID);
489 goto err;
490 }
491 qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL);
492 tasklet_init(&crypto_done_tasklet, crypto_done_action, 0);
493
494 qmgr_enable_irq(RECV_QID);
495 return 0;
295c01f9
CH
496
497npe_error:
498 printk(KERN_ERR "%s not responding\n", npe_name(npe_c));
499 ret = -EIO;
81bef015
CH
500err:
501 if (ctx_pool)
502 dma_pool_destroy(ctx_pool);
503 if (buffer_pool)
504 dma_pool_destroy(buffer_pool);
505 npe_release(npe_c);
506 return ret;
507}
508
509static void release_ixp_crypto(void)
510{
511 qmgr_disable_irq(RECV_QID);
512 tasklet_kill(&crypto_done_tasklet);
513
514 qmgr_release_queue(SEND_QID);
515 qmgr_release_queue(RECV_QID);
516
517 dma_pool_destroy(ctx_pool);
518 dma_pool_destroy(buffer_pool);
519
520 npe_release(npe_c);
521
522 if (crypt_virt) {
523 dma_free_coherent(dev,
524 NPE_QLEN_TOTAL * sizeof( struct crypt_ctl),
525 crypt_virt, crypt_phys);
526 }
527 return;
528}
529
530static void reset_sa_dir(struct ix_sa_dir *dir)
531{
532 memset(dir->npe_ctx, 0, NPE_CTX_LEN);
533 dir->npe_ctx_idx = 0;
534 dir->npe_mode = 0;
535}
536
537static int init_sa_dir(struct ix_sa_dir *dir)
538{
539 dir->npe_ctx = dma_pool_alloc(ctx_pool, GFP_KERNEL, &dir->npe_ctx_phys);
540 if (!dir->npe_ctx) {
541 return -ENOMEM;
542 }
543 reset_sa_dir(dir);
544 return 0;
545}
546
547static void free_sa_dir(struct ix_sa_dir *dir)
548{
549 memset(dir->npe_ctx, 0, NPE_CTX_LEN);
550 dma_pool_free(ctx_pool, dir->npe_ctx, dir->npe_ctx_phys);
551}
552
553static int init_tfm(struct crypto_tfm *tfm)
554{
555 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
556 int ret;
557
558 atomic_set(&ctx->configuring, 0);
559 ret = init_sa_dir(&ctx->encrypt);
560 if (ret)
561 return ret;
562 ret = init_sa_dir(&ctx->decrypt);
563 if (ret) {
564 free_sa_dir(&ctx->encrypt);
565 }
566 return ret;
567}
568
569static int init_tfm_ablk(struct crypto_tfm *tfm)
570{
571 tfm->crt_ablkcipher.reqsize = sizeof(struct ablk_ctx);
572 return init_tfm(tfm);
573}
574
575static int init_tfm_aead(struct crypto_tfm *tfm)
576{
577 tfm->crt_aead.reqsize = sizeof(struct aead_ctx);
578 return init_tfm(tfm);
579}
580
581static void exit_tfm(struct crypto_tfm *tfm)
582{
583 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
584 free_sa_dir(&ctx->encrypt);
585 free_sa_dir(&ctx->decrypt);
586}
587
588static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target,
589 int init_len, u32 ctx_addr, const u8 *key, int key_len)
590{
591 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
592 struct crypt_ctl *crypt;
593 struct buffer_desc *buf;
594 int i;
595 u8 *pad;
596 u32 pad_phys, buf_phys;
597
598 BUILD_BUG_ON(NPE_CTX_LEN < HMAC_PAD_BLOCKLEN);
599 pad = dma_pool_alloc(ctx_pool, GFP_KERNEL, &pad_phys);
600 if (!pad)
601 return -ENOMEM;
602 buf = dma_pool_alloc(buffer_pool, GFP_KERNEL, &buf_phys);
603 if (!buf) {
604 dma_pool_free(ctx_pool, pad, pad_phys);
605 return -ENOMEM;
606 }
607 crypt = get_crypt_desc_emerg();
608 if (!crypt) {
609 dma_pool_free(ctx_pool, pad, pad_phys);
610 dma_pool_free(buffer_pool, buf, buf_phys);
611 return -EAGAIN;
612 }
613
614 memcpy(pad, key, key_len);
615 memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len);
616 for (i = 0; i < HMAC_PAD_BLOCKLEN; i++) {
617 pad[i] ^= xpad;
618 }
619
620 crypt->data.tfm = tfm;
621 crypt->regist_ptr = pad;
622 crypt->regist_buf = buf;
623
624 crypt->auth_offs = 0;
625 crypt->auth_len = HMAC_PAD_BLOCKLEN;
626 crypt->crypto_ctx = ctx_addr;
627 crypt->src_buf = buf_phys;
628 crypt->icv_rev_aes = target;
629 crypt->mode = NPE_OP_HASH_GEN_ICV;
630 crypt->init_len = init_len;
631 crypt->ctl_flags |= CTL_FLAG_GEN_ICV;
632
633 buf->next = 0;
634 buf->buf_len = HMAC_PAD_BLOCKLEN;
635 buf->pkt_len = 0;
636 buf->phys_addr = pad_phys;
637
638 atomic_inc(&ctx->configuring);
639 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
640 BUG_ON(qmgr_stat_overflow(SEND_QID));
641 return 0;
642}
643
644static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned authsize,
645 const u8 *key, int key_len, unsigned digest_len)
646{
647 u32 itarget, otarget, npe_ctx_addr;
648 unsigned char *cinfo;
649 int init_len, ret = 0;
650 u32 cfgword;
651 struct ix_sa_dir *dir;
652 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
653 const struct ix_hash_algo *algo;
654
655 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
656 cinfo = dir->npe_ctx + dir->npe_ctx_idx;
657 algo = ix_hash(tfm);
658
659 /* write cfg word to cryptinfo */
660 cfgword = algo->cfgword | ( authsize << 6); /* (authsize/4) << 8 */
ce057297
KH
661#ifndef __ARMEB__
662 cfgword ^= 0xAA000000; /* change the "byte swap" flags */
663#endif
81bef015
CH
664 *(u32*)cinfo = cpu_to_be32(cfgword);
665 cinfo += sizeof(cfgword);
666
667 /* write ICV to cryptinfo */
668 memcpy(cinfo, algo->icv, digest_len);
669 cinfo += digest_len;
670
671 itarget = dir->npe_ctx_phys + dir->npe_ctx_idx
672 + sizeof(algo->cfgword);
673 otarget = itarget + digest_len;
674 init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
675 npe_ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx;
676
677 dir->npe_ctx_idx += init_len;
678 dir->npe_mode |= NPE_OP_HASH_ENABLE;
679
680 if (!encrypt)
681 dir->npe_mode |= NPE_OP_HASH_VERIFY;
682
683 ret = register_chain_var(tfm, HMAC_OPAD_VALUE, otarget,
684 init_len, npe_ctx_addr, key, key_len);
685 if (ret)
686 return ret;
687 return register_chain_var(tfm, HMAC_IPAD_VALUE, itarget,
688 init_len, npe_ctx_addr, key, key_len);
689}
690
691static int gen_rev_aes_key(struct crypto_tfm *tfm)
692{
693 struct crypt_ctl *crypt;
694 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
695 struct ix_sa_dir *dir = &ctx->decrypt;
696
697 crypt = get_crypt_desc_emerg();
698 if (!crypt) {
699 return -EAGAIN;
700 }
701 *(u32*)dir->npe_ctx |= cpu_to_be32(CIPH_ENCR);
702
703 crypt->data.tfm = tfm;
704 crypt->crypt_offs = 0;
705 crypt->crypt_len = AES_BLOCK128;
706 crypt->src_buf = 0;
707 crypt->crypto_ctx = dir->npe_ctx_phys;
708 crypt->icv_rev_aes = dir->npe_ctx_phys + sizeof(u32);
709 crypt->mode = NPE_OP_ENC_GEN_KEY;
710 crypt->init_len = dir->npe_ctx_idx;
711 crypt->ctl_flags |= CTL_FLAG_GEN_REVAES;
712
713 atomic_inc(&ctx->configuring);
714 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
715 BUG_ON(qmgr_stat_overflow(SEND_QID));
716 return 0;
717}
718
719static int setup_cipher(struct crypto_tfm *tfm, int encrypt,
720 const u8 *key, int key_len)
721{
722 u8 *cinfo;
723 u32 cipher_cfg;
724 u32 keylen_cfg = 0;
725 struct ix_sa_dir *dir;
726 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
727 u32 *flags = &tfm->crt_flags;
728
729 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
730 cinfo = dir->npe_ctx;
731
732 if (encrypt) {
733 cipher_cfg = cipher_cfg_enc(tfm);
734 dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT;
735 } else {
736 cipher_cfg = cipher_cfg_dec(tfm);
737 }
738 if (cipher_cfg & MOD_AES) {
739 switch (key_len) {
9792eb1d
KH
740 case 16: keylen_cfg = MOD_AES128; break;
741 case 24: keylen_cfg = MOD_AES192; break;
742 case 32: keylen_cfg = MOD_AES256; break;
743 default:
744 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
745 return -EINVAL;
81bef015
CH
746 }
747 cipher_cfg |= keylen_cfg;
748 } else if (cipher_cfg & MOD_3DES) {
749 const u32 *K = (const u32 *)key;
750 if (unlikely(!((K[0] ^ K[2]) | (K[1] ^ K[3])) ||
751 !((K[2] ^ K[4]) | (K[3] ^ K[5]))))
752 {
753 *flags |= CRYPTO_TFM_RES_BAD_KEY_SCHED;
754 return -EINVAL;
755 }
756 } else {
757 u32 tmp[DES_EXPKEY_WORDS];
758 if (des_ekey(tmp, key) == 0) {
759 *flags |= CRYPTO_TFM_RES_WEAK_KEY;
760 }
761 }
762 /* write cfg word to cryptinfo */
763 *(u32*)cinfo = cpu_to_be32(cipher_cfg);
764 cinfo += sizeof(cipher_cfg);
765
766 /* write cipher key to cryptinfo */
767 memcpy(cinfo, key, key_len);
768 /* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */
769 if (key_len < DES3_EDE_KEY_SIZE && !(cipher_cfg & MOD_AES)) {
770 memset(cinfo + key_len, 0, DES3_EDE_KEY_SIZE -key_len);
771 key_len = DES3_EDE_KEY_SIZE;
772 }
773 dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len;
774 dir->npe_mode |= NPE_OP_CRYPT_ENABLE;
775 if ((cipher_cfg & MOD_AES) && !encrypt) {
776 return gen_rev_aes_key(tfm);
777 }
778 return 0;
779}
780
0d44dc59
CH
781static struct buffer_desc *chainup_buffers(struct device *dev,
782 struct scatterlist *sg, unsigned nbytes,
783 struct buffer_desc *buf, gfp_t flags,
784 enum dma_data_direction dir)
81bef015 785{
0d44dc59
CH
786 for (;nbytes > 0; sg = scatterwalk_sg_next(sg)) {
787 unsigned len = min(nbytes, sg->length);
81bef015
CH
788 struct buffer_desc *next_buf;
789 u32 next_buf_phys;
0d44dc59 790 void *ptr;
81bef015 791
81bef015 792 nbytes -= len;
0d44dc59 793 ptr = page_address(sg_page(sg)) + sg->offset;
81bef015 794 next_buf = dma_pool_alloc(buffer_pool, flags, &next_buf_phys);
0d44dc59
CH
795 if (!next_buf) {
796 buf = NULL;
797 break;
798 }
799 sg_dma_address(sg) = dma_map_single(dev, ptr, len, dir);
81bef015
CH
800 buf->next = next_buf;
801 buf->phys_next = next_buf_phys;
81bef015 802 buf = next_buf;
0d44dc59 803
81bef015
CH
804 buf->phys_addr = sg_dma_address(sg);
805 buf->buf_len = len;
0d44dc59 806 buf->dir = dir;
81bef015 807 }
0d44dc59
CH
808 buf->next = NULL;
809 buf->phys_next = 0;
81bef015
CH
810 return buf;
811}
812
813static int ablk_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
814 unsigned int key_len)
815{
816 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
817 u32 *flags = &tfm->base.crt_flags;
818 int ret;
819
820 init_completion(&ctx->completion);
821 atomic_inc(&ctx->configuring);
822
823 reset_sa_dir(&ctx->encrypt);
824 reset_sa_dir(&ctx->decrypt);
825
826 ctx->encrypt.npe_mode = NPE_OP_HMAC_DISABLE;
827 ctx->decrypt.npe_mode = NPE_OP_HMAC_DISABLE;
828
829 ret = setup_cipher(&tfm->base, 0, key, key_len);
830 if (ret)
831 goto out;
832 ret = setup_cipher(&tfm->base, 1, key, key_len);
833 if (ret)
834 goto out;
835
836 if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
837 if (*flags & CRYPTO_TFM_REQ_WEAK_KEY) {
838 ret = -EINVAL;
839 } else {
840 *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
841 }
842 }
843out:
844 if (!atomic_dec_and_test(&ctx->configuring))
845 wait_for_completion(&ctx->completion);
846 return ret;
847}
848
849static int ablk_rfc3686_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
850 unsigned int key_len)
851{
852 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
853
854 /* the nonce is stored in bytes at end of key */
855 if (key_len < CTR_RFC3686_NONCE_SIZE)
856 return -EINVAL;
857
858 memcpy(ctx->nonce, key + (key_len - CTR_RFC3686_NONCE_SIZE),
859 CTR_RFC3686_NONCE_SIZE);
860
861 key_len -= CTR_RFC3686_NONCE_SIZE;
862 return ablk_setkey(tfm, key, key_len);
863}
864
865static int ablk_perform(struct ablkcipher_request *req, int encrypt)
866{
867 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
868 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
869 unsigned ivsize = crypto_ablkcipher_ivsize(tfm);
81bef015
CH
870 struct ix_sa_dir *dir;
871 struct crypt_ctl *crypt;
0d44dc59 872 unsigned int nbytes = req->nbytes;
81bef015
CH
873 enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
874 struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
0d44dc59 875 struct buffer_desc src_hook;
81bef015
CH
876 gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
877 GFP_KERNEL : GFP_ATOMIC;
878
879 if (qmgr_stat_full(SEND_QID))
880 return -EAGAIN;
881 if (atomic_read(&ctx->configuring))
882 return -EAGAIN;
883
884 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
885
886 crypt = get_crypt_desc();
887 if (!crypt)
0d44dc59 888 return -ENOMEM;
81bef015
CH
889
890 crypt->data.ablk_req = req;
891 crypt->crypto_ctx = dir->npe_ctx_phys;
892 crypt->mode = dir->npe_mode;
893 crypt->init_len = dir->npe_ctx_idx;
894
895 crypt->crypt_offs = 0;
896 crypt->crypt_len = nbytes;
897
898 BUG_ON(ivsize && !req->info);
899 memcpy(crypt->iv, req->info, ivsize);
900 if (req->src != req->dst) {
0d44dc59 901 struct buffer_desc dst_hook;
81bef015 902 crypt->mode |= NPE_OP_NOT_IN_PLACE;
81bef015
CH
903 /* This was never tested by Intel
904 * for more than one dst buffer, I think. */
0d44dc59
CH
905 BUG_ON(req->dst->length < nbytes);
906 req_ctx->dst = NULL;
907 if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,
908 flags, DMA_FROM_DEVICE))
81bef015
CH
909 goto free_buf_dest;
910 src_direction = DMA_TO_DEVICE;
0d44dc59
CH
911 req_ctx->dst = dst_hook.next;
912 crypt->dst_buf = dst_hook.phys_next;
81bef015
CH
913 } else {
914 req_ctx->dst = NULL;
81bef015 915 }
0d44dc59
CH
916 req_ctx->src = NULL;
917 if (!chainup_buffers(dev, req->src, nbytes, &src_hook,
918 flags, src_direction))
81bef015
CH
919 goto free_buf_src;
920
0d44dc59
CH
921 req_ctx->src = src_hook.next;
922 crypt->src_buf = src_hook.phys_next;
81bef015
CH
923 crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK;
924 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
925 BUG_ON(qmgr_stat_overflow(SEND_QID));
926 return -EINPROGRESS;
927
928free_buf_src:
0d44dc59 929 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
81bef015
CH
930free_buf_dest:
931 if (req->src != req->dst) {
0d44dc59 932 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
81bef015
CH
933 }
934 crypt->ctl_flags = CTL_FLAG_UNUSED;
0d44dc59 935 return -ENOMEM;
81bef015
CH
936}
937
938static int ablk_encrypt(struct ablkcipher_request *req)
939{
940 return ablk_perform(req, 1);
941}
942
943static int ablk_decrypt(struct ablkcipher_request *req)
944{
945 return ablk_perform(req, 0);
946}
947
948static int ablk_rfc3686_crypt(struct ablkcipher_request *req)
949{
950 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
951 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
952 u8 iv[CTR_RFC3686_BLOCK_SIZE];
953 u8 *info = req->info;
954 int ret;
955
956 /* set up counter block */
957 memcpy(iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
958 memcpy(iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);
959
960 /* initialize counter portion of counter block */
961 *(__be32 *)(iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
962 cpu_to_be32(1);
963
964 req->info = iv;
965 ret = ablk_perform(req, 1);
966 req->info = info;
967 return ret;
968}
969
970static int hmac_inconsistent(struct scatterlist *sg, unsigned start,
971 unsigned int nbytes)
972{
973 int offset = 0;
974
975 if (!nbytes)
976 return 0;
977
978 for (;;) {
979 if (start < offset + sg->length)
980 break;
981
982 offset += sg->length;
0d44dc59 983 sg = scatterwalk_sg_next(sg);
81bef015
CH
984 }
985 return (start + nbytes > offset + sg->length);
986}
987
988static int aead_perform(struct aead_request *req, int encrypt,
989 int cryptoffset, int eff_cryptlen, u8 *iv)
990{
991 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
992 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
993 unsigned ivsize = crypto_aead_ivsize(tfm);
994 unsigned authsize = crypto_aead_authsize(tfm);
81bef015
CH
995 struct ix_sa_dir *dir;
996 struct crypt_ctl *crypt;
0d44dc59
CH
997 unsigned int cryptlen;
998 struct buffer_desc *buf, src_hook;
81bef015
CH
999 struct aead_ctx *req_ctx = aead_request_ctx(req);
1000 gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
1001 GFP_KERNEL : GFP_ATOMIC;
1002
1003 if (qmgr_stat_full(SEND_QID))
1004 return -EAGAIN;
1005 if (atomic_read(&ctx->configuring))
1006 return -EAGAIN;
1007
1008 if (encrypt) {
1009 dir = &ctx->encrypt;
1010 cryptlen = req->cryptlen;
1011 } else {
1012 dir = &ctx->decrypt;
1013 /* req->cryptlen includes the authsize when decrypting */
1014 cryptlen = req->cryptlen -authsize;
1015 eff_cryptlen -= authsize;
1016 }
1017 crypt = get_crypt_desc();
1018 if (!crypt)
0d44dc59 1019 return -ENOMEM;
81bef015
CH
1020
1021 crypt->data.aead_req = req;
1022 crypt->crypto_ctx = dir->npe_ctx_phys;
1023 crypt->mode = dir->npe_mode;
1024 crypt->init_len = dir->npe_ctx_idx;
1025
1026 crypt->crypt_offs = cryptoffset;
1027 crypt->crypt_len = eff_cryptlen;
1028
1029 crypt->auth_offs = 0;
1030 crypt->auth_len = req->assoclen + ivsize + cryptlen;
1031 BUG_ON(ivsize && !req->iv);
1032 memcpy(crypt->iv, req->iv, ivsize);
1033
1034 if (req->src != req->dst) {
25985edc 1035 BUG(); /* -ENOTSUP because of my laziness */
81bef015
CH
1036 }
1037
81bef015 1038 /* ASSOC data */
0d44dc59
CH
1039 buf = chainup_buffers(dev, req->assoc, req->assoclen, &src_hook,
1040 flags, DMA_TO_DEVICE);
1041 req_ctx->buffer = src_hook.next;
1042 crypt->src_buf = src_hook.phys_next;
81bef015 1043 if (!buf)
0d44dc59 1044 goto out;
81bef015
CH
1045 /* IV */
1046 sg_init_table(&req_ctx->ivlist, 1);
1047 sg_set_buf(&req_ctx->ivlist, iv, ivsize);
0d44dc59
CH
1048 buf = chainup_buffers(dev, &req_ctx->ivlist, ivsize, buf, flags,
1049 DMA_BIDIRECTIONAL);
81bef015 1050 if (!buf)
0d44dc59 1051 goto free_chain;
81bef015
CH
1052 if (unlikely(hmac_inconsistent(req->src, cryptlen, authsize))) {
1053 /* The 12 hmac bytes are scattered,
1054 * we need to copy them into a safe buffer */
1055 req_ctx->hmac_virt = dma_pool_alloc(buffer_pool, flags,
1056 &crypt->icv_rev_aes);
1057 if (unlikely(!req_ctx->hmac_virt))
0d44dc59 1058 goto free_chain;
81bef015
CH
1059 if (!encrypt) {
1060 scatterwalk_map_and_copy(req_ctx->hmac_virt,
1061 req->src, cryptlen, authsize, 0);
1062 }
1063 req_ctx->encrypt = encrypt;
1064 } else {
1065 req_ctx->hmac_virt = NULL;
1066 }
1067 /* Crypt */
0d44dc59
CH
1068 buf = chainup_buffers(dev, req->src, cryptlen + authsize, buf, flags,
1069 DMA_BIDIRECTIONAL);
81bef015 1070 if (!buf)
0d44dc59 1071 goto free_hmac_virt;
81bef015
CH
1072 if (!req_ctx->hmac_virt) {
1073 crypt->icv_rev_aes = buf->phys_addr + buf->buf_len - authsize;
1074 }
0d44dc59 1075
81bef015
CH
1076 crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD;
1077 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
1078 BUG_ON(qmgr_stat_overflow(SEND_QID));
1079 return -EINPROGRESS;
0d44dc59 1080free_hmac_virt:
81bef015
CH
1081 if (req_ctx->hmac_virt) {
1082 dma_pool_free(buffer_pool, req_ctx->hmac_virt,
1083 crypt->icv_rev_aes);
1084 }
0d44dc59
CH
1085free_chain:
1086 free_buf_chain(dev, req_ctx->buffer, crypt->src_buf);
81bef015
CH
1087out:
1088 crypt->ctl_flags = CTL_FLAG_UNUSED;
0d44dc59 1089 return -ENOMEM;
81bef015
CH
1090}
1091
1092static int aead_setup(struct crypto_aead *tfm, unsigned int authsize)
1093{
1094 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1095 u32 *flags = &tfm->base.crt_flags;
1096 unsigned digest_len = crypto_aead_alg(tfm)->maxauthsize;
1097 int ret;
1098
1099 if (!ctx->enckey_len && !ctx->authkey_len)
1100 return 0;
1101 init_completion(&ctx->completion);
1102 atomic_inc(&ctx->configuring);
1103
1104 reset_sa_dir(&ctx->encrypt);
1105 reset_sa_dir(&ctx->decrypt);
1106
1107 ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len);
1108 if (ret)
1109 goto out;
1110 ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len);
1111 if (ret)
1112 goto out;
1113 ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey,
1114 ctx->authkey_len, digest_len);
1115 if (ret)
1116 goto out;
1117 ret = setup_auth(&tfm->base, 1, authsize, ctx->authkey,
1118 ctx->authkey_len, digest_len);
1119 if (ret)
1120 goto out;
1121
1122 if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
1123 if (*flags & CRYPTO_TFM_REQ_WEAK_KEY) {
1124 ret = -EINVAL;
1125 goto out;
1126 } else {
1127 *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
1128 }
1129 }
1130out:
1131 if (!atomic_dec_and_test(&ctx->configuring))
1132 wait_for_completion(&ctx->completion);
1133 return ret;
1134}
1135
1136static int aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
1137{
1138 int max = crypto_aead_alg(tfm)->maxauthsize >> 2;
1139
1140 if ((authsize>>2) < 1 || (authsize>>2) > max || (authsize & 3))
1141 return -EINVAL;
1142 return aead_setup(tfm, authsize);
1143}
1144
1145static int aead_setkey(struct crypto_aead *tfm, const u8 *key,
1146 unsigned int keylen)
1147{
1148 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1149 struct rtattr *rta = (struct rtattr *)key;
1150 struct crypto_authenc_key_param *param;
1151
1152 if (!RTA_OK(rta, keylen))
1153 goto badkey;
1154 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
1155 goto badkey;
1156 if (RTA_PAYLOAD(rta) < sizeof(*param))
1157 goto badkey;
1158
1159 param = RTA_DATA(rta);
1160 ctx->enckey_len = be32_to_cpu(param->enckeylen);
1161
1162 key += RTA_ALIGN(rta->rta_len);
1163 keylen -= RTA_ALIGN(rta->rta_len);
1164
1165 if (keylen < ctx->enckey_len)
1166 goto badkey;
1167
1168 ctx->authkey_len = keylen - ctx->enckey_len;
1169 memcpy(ctx->enckey, key + ctx->authkey_len, ctx->enckey_len);
1170 memcpy(ctx->authkey, key, ctx->authkey_len);
1171
1172 return aead_setup(tfm, crypto_aead_authsize(tfm));
1173badkey:
1174 ctx->enckey_len = 0;
1175 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1176 return -EINVAL;
1177}
1178
1179static int aead_encrypt(struct aead_request *req)
1180{
1181 unsigned ivsize = crypto_aead_ivsize(crypto_aead_reqtfm(req));
1182 return aead_perform(req, 1, req->assoclen + ivsize,
1183 req->cryptlen, req->iv);
1184}
1185
1186static int aead_decrypt(struct aead_request *req)
1187{
1188 unsigned ivsize = crypto_aead_ivsize(crypto_aead_reqtfm(req));
1189 return aead_perform(req, 0, req->assoclen + ivsize,
1190 req->cryptlen, req->iv);
1191}
1192
1193static int aead_givencrypt(struct aead_givcrypt_request *req)
1194{
1195 struct crypto_aead *tfm = aead_givcrypt_reqtfm(req);
1196 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1197 unsigned len, ivsize = crypto_aead_ivsize(tfm);
1198 __be64 seq;
1199
1200 /* copied from eseqiv.c */
1201 if (!ctx->salted) {
1202 get_random_bytes(ctx->salt, ivsize);
1203 ctx->salted = 1;
1204 }
1205 memcpy(req->areq.iv, ctx->salt, ivsize);
1206 len = ivsize;
1207 if (ivsize > sizeof(u64)) {
1208 memset(req->giv, 0, ivsize - sizeof(u64));
1209 len = sizeof(u64);
1210 }
1211 seq = cpu_to_be64(req->seq);
1212 memcpy(req->giv + ivsize - len, &seq, len);
1213 return aead_perform(&req->areq, 1, req->areq.assoclen,
1214 req->areq.cryptlen +ivsize, req->giv);
1215}
1216
1217static struct ixp_alg ixp4xx_algos[] = {
1218{
1219 .crypto = {
1220 .cra_name = "cbc(des)",
1221 .cra_blocksize = DES_BLOCK_SIZE,
1222 .cra_u = { .ablkcipher = {
1223 .min_keysize = DES_KEY_SIZE,
1224 .max_keysize = DES_KEY_SIZE,
1225 .ivsize = DES_BLOCK_SIZE,
1226 .geniv = "eseqiv",
1227 }
1228 }
1229 },
1230 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1231 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1232
1233}, {
1234 .crypto = {
1235 .cra_name = "ecb(des)",
1236 .cra_blocksize = DES_BLOCK_SIZE,
1237 .cra_u = { .ablkcipher = {
1238 .min_keysize = DES_KEY_SIZE,
1239 .max_keysize = DES_KEY_SIZE,
1240 }
1241 }
1242 },
1243 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192,
1244 .cfg_dec = CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192,
1245}, {
1246 .crypto = {
1247 .cra_name = "cbc(des3_ede)",
1248 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1249 .cra_u = { .ablkcipher = {
1250 .min_keysize = DES3_EDE_KEY_SIZE,
1251 .max_keysize = DES3_EDE_KEY_SIZE,
1252 .ivsize = DES3_EDE_BLOCK_SIZE,
1253 .geniv = "eseqiv",
1254 }
1255 }
1256 },
1257 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1258 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1259}, {
1260 .crypto = {
1261 .cra_name = "ecb(des3_ede)",
1262 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1263 .cra_u = { .ablkcipher = {
1264 .min_keysize = DES3_EDE_KEY_SIZE,
1265 .max_keysize = DES3_EDE_KEY_SIZE,
1266 }
1267 }
1268 },
1269 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_ECB | KEYLEN_192,
1270 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_ECB | KEYLEN_192,
1271}, {
1272 .crypto = {
1273 .cra_name = "cbc(aes)",
1274 .cra_blocksize = AES_BLOCK_SIZE,
1275 .cra_u = { .ablkcipher = {
1276 .min_keysize = AES_MIN_KEY_SIZE,
1277 .max_keysize = AES_MAX_KEY_SIZE,
1278 .ivsize = AES_BLOCK_SIZE,
1279 .geniv = "eseqiv",
1280 }
1281 }
1282 },
1283 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1284 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1285}, {
1286 .crypto = {
1287 .cra_name = "ecb(aes)",
1288 .cra_blocksize = AES_BLOCK_SIZE,
1289 .cra_u = { .ablkcipher = {
1290 .min_keysize = AES_MIN_KEY_SIZE,
1291 .max_keysize = AES_MAX_KEY_SIZE,
1292 }
1293 }
1294 },
1295 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_ECB,
1296 .cfg_dec = CIPH_DECR | MOD_AES | MOD_ECB,
1297}, {
1298 .crypto = {
1299 .cra_name = "ctr(aes)",
1300 .cra_blocksize = AES_BLOCK_SIZE,
1301 .cra_u = { .ablkcipher = {
1302 .min_keysize = AES_MIN_KEY_SIZE,
1303 .max_keysize = AES_MAX_KEY_SIZE,
1304 .ivsize = AES_BLOCK_SIZE,
1305 .geniv = "eseqiv",
1306 }
1307 }
1308 },
1309 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1310 .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1311}, {
1312 .crypto = {
1313 .cra_name = "rfc3686(ctr(aes))",
1314 .cra_blocksize = AES_BLOCK_SIZE,
1315 .cra_u = { .ablkcipher = {
1316 .min_keysize = AES_MIN_KEY_SIZE,
1317 .max_keysize = AES_MAX_KEY_SIZE,
1318 .ivsize = AES_BLOCK_SIZE,
1319 .geniv = "eseqiv",
1320 .setkey = ablk_rfc3686_setkey,
1321 .encrypt = ablk_rfc3686_crypt,
1322 .decrypt = ablk_rfc3686_crypt }
1323 }
1324 },
1325 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1326 .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1327}, {
1328 .crypto = {
1329 .cra_name = "authenc(hmac(md5),cbc(des))",
1330 .cra_blocksize = DES_BLOCK_SIZE,
1331 .cra_u = { .aead = {
1332 .ivsize = DES_BLOCK_SIZE,
1333 .maxauthsize = MD5_DIGEST_SIZE,
1334 }
1335 }
1336 },
1337 .hash = &hash_alg_md5,
1338 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1339 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1340}, {
1341 .crypto = {
1342 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1343 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1344 .cra_u = { .aead = {
1345 .ivsize = DES3_EDE_BLOCK_SIZE,
1346 .maxauthsize = MD5_DIGEST_SIZE,
1347 }
1348 }
1349 },
1350 .hash = &hash_alg_md5,
1351 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1352 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1353}, {
1354 .crypto = {
1355 .cra_name = "authenc(hmac(sha1),cbc(des))",
1356 .cra_blocksize = DES_BLOCK_SIZE,
1357 .cra_u = { .aead = {
1358 .ivsize = DES_BLOCK_SIZE,
1359 .maxauthsize = SHA1_DIGEST_SIZE,
1360 }
1361 }
1362 },
1363 .hash = &hash_alg_sha1,
1364 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1365 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1366}, {
1367 .crypto = {
1368 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1369 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1370 .cra_u = { .aead = {
1371 .ivsize = DES3_EDE_BLOCK_SIZE,
1372 .maxauthsize = SHA1_DIGEST_SIZE,
1373 }
1374 }
1375 },
1376 .hash = &hash_alg_sha1,
1377 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1378 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1379}, {
1380 .crypto = {
1381 .cra_name = "authenc(hmac(md5),cbc(aes))",
1382 .cra_blocksize = AES_BLOCK_SIZE,
1383 .cra_u = { .aead = {
1384 .ivsize = AES_BLOCK_SIZE,
1385 .maxauthsize = MD5_DIGEST_SIZE,
1386 }
1387 }
1388 },
1389 .hash = &hash_alg_md5,
1390 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1391 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1392}, {
1393 .crypto = {
1394 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1395 .cra_blocksize = AES_BLOCK_SIZE,
1396 .cra_u = { .aead = {
1397 .ivsize = AES_BLOCK_SIZE,
1398 .maxauthsize = SHA1_DIGEST_SIZE,
1399 }
1400 }
1401 },
1402 .hash = &hash_alg_sha1,
1403 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1404 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1405} };
1406
1407#define IXP_POSTFIX "-ixp4xx"
d8cbc3f7
RK
1408
1409static const struct platform_device_info ixp_dev_info __initdata = {
1410 .name = DRIVER_NAME,
1411 .id = 0,
1412 .dma_mask = DMA_BIT_MASK(32),
1413};
1414
81bef015
CH
1415static int __init ixp_module_init(void)
1416{
1417 int num = ARRAY_SIZE(ixp4xx_algos);
d8cbc3f7 1418 int i, err ;
81bef015 1419
d8cbc3f7
RK
1420 pdev = platform_device_register_full(&ixp_dev_info);
1421 if (IS_ERR(pdev))
1422 return PTR_ERR(pdev);
1423
1424 dev = &pdev->dev;
81bef015
CH
1425
1426 spin_lock_init(&desc_lock);
1427 spin_lock_init(&emerg_lock);
1428
1429 err = init_ixp_crypto();
1430 if (err) {
d8cbc3f7 1431 platform_device_unregister(pdev);
81bef015
CH
1432 return err;
1433 }
1434 for (i=0; i< num; i++) {
1435 struct crypto_alg *cra = &ixp4xx_algos[i].crypto;
1436
1437 if (snprintf(cra->cra_driver_name, CRYPTO_MAX_ALG_NAME,
1438 "%s"IXP_POSTFIX, cra->cra_name) >=
1439 CRYPTO_MAX_ALG_NAME)
1440 {
1441 continue;
1442 }
1443 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES)) {
1444 continue;
1445 }
1446 if (!ixp4xx_algos[i].hash) {
1447 /* block ciphers */
1448 cra->cra_type = &crypto_ablkcipher_type;
1449 cra->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
d912bb76 1450 CRYPTO_ALG_KERN_DRIVER_ONLY |
81bef015
CH
1451 CRYPTO_ALG_ASYNC;
1452 if (!cra->cra_ablkcipher.setkey)
1453 cra->cra_ablkcipher.setkey = ablk_setkey;
1454 if (!cra->cra_ablkcipher.encrypt)
1455 cra->cra_ablkcipher.encrypt = ablk_encrypt;
1456 if (!cra->cra_ablkcipher.decrypt)
1457 cra->cra_ablkcipher.decrypt = ablk_decrypt;
1458 cra->cra_init = init_tfm_ablk;
1459 } else {
1460 /* authenc */
1461 cra->cra_type = &crypto_aead_type;
1462 cra->cra_flags = CRYPTO_ALG_TYPE_AEAD |
d912bb76 1463 CRYPTO_ALG_KERN_DRIVER_ONLY |
81bef015
CH
1464 CRYPTO_ALG_ASYNC;
1465 cra->cra_aead.setkey = aead_setkey;
1466 cra->cra_aead.setauthsize = aead_setauthsize;
1467 cra->cra_aead.encrypt = aead_encrypt;
1468 cra->cra_aead.decrypt = aead_decrypt;
1469 cra->cra_aead.givencrypt = aead_givencrypt;
1470 cra->cra_init = init_tfm_aead;
1471 }
1472 cra->cra_ctxsize = sizeof(struct ixp_ctx);
1473 cra->cra_module = THIS_MODULE;
1474 cra->cra_alignmask = 3;
1475 cra->cra_priority = 300;
1476 cra->cra_exit = exit_tfm;
1477 if (crypto_register_alg(cra))
1478 printk(KERN_ERR "Failed to register '%s'\n",
1479 cra->cra_name);
1480 else
1481 ixp4xx_algos[i].registered = 1;
1482 }
1483 return 0;
1484}
1485
1486static void __exit ixp_module_exit(void)
1487{
1488 int num = ARRAY_SIZE(ixp4xx_algos);
1489 int i;
1490
1491 for (i=0; i< num; i++) {
1492 if (ixp4xx_algos[i].registered)
1493 crypto_unregister_alg(&ixp4xx_algos[i].crypto);
1494 }
1495 release_ixp_crypto();
d8cbc3f7 1496 platform_device_unregister(pdev);
81bef015
CH
1497}
1498
1499module_init(ixp_module_init);
1500module_exit(ixp_module_exit);
1501
1502MODULE_LICENSE("GPL");
1503MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
1504MODULE_DESCRIPTION("IXP4xx hardware crypto");
1505