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Merge tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
[mirror_ubuntu-focal-kernel.git] / drivers / crypto / omap-des.c
CommitLineData
e91aa9d5
JF		 1/*
2 * Support for OMAP DES and Triple DES HW acceleration.
3 *
4 * Copyright (c) 2013 Texas Instruments Incorporated
5 * Author: Joel Fernandes <joelf@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 *
11 */
12
13#define pr_fmt(fmt) "%s: " fmt, __func__
14
15#ifdef DEBUG
16#define prn(num) printk(#num "=%d\n", num)
17#define prx(num) printk(#num "=%x\n", num)
18#else
19#define prn(num) do { } while (0)
20#define prx(num) do { } while (0)
21#endif
22
23#include <linux/err.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/errno.h>
27#include <linux/kernel.h>
28#include <linux/platform_device.h>
29#include <linux/scatterlist.h>
30#include <linux/dma-mapping.h>
31#include <linux/dmaengine.h>
e91aa9d5
JF		 32#include <linux/pm_runtime.h>
33#include <linux/of.h>
34#include <linux/of_device.h>
35#include <linux/of_address.h>
36#include <linux/io.h>
37#include <linux/crypto.h>
38#include <linux/interrupt.h>
39#include <crypto/scatterwalk.h>
40#include <crypto/des.h>
f1b77aac 41#include <crypto/algapi.h>
2589ad84 42#include <crypto/engine.h>
e91aa9d5 43
9765e768
TK		 44#include "omap-crypto.h"
45
e91aa9d5
JF		 46#define DST_MAXBURST 2
47
48#define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
49
50#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
51
52#define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
53 ((x ^ 0x01) * 0x04))
54
55#define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
56
57#define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
58#define DES_REG_CTRL_CBC BIT(4)
59#define DES_REG_CTRL_TDES BIT(3)
60#define DES_REG_CTRL_DIRECTION BIT(2)
61#define DES_REG_CTRL_INPUT_READY BIT(1)
62#define DES_REG_CTRL_OUTPUT_READY BIT(0)
63
64#define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
65
66#define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
67
68#define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
69
70#define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
71
72#define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
73#define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
74#define DES_REG_IRQ_DATA_IN BIT(1)
75#define DES_REG_IRQ_DATA_OUT BIT(2)
76
77#define FLAGS_MODE_MASK 0x000f
78#define FLAGS_ENCRYPT BIT(0)
79#define FLAGS_CBC BIT(1)
80#define FLAGS_INIT BIT(4)
81#define FLAGS_BUSY BIT(6)
82
418f2a8c
TK		 83#define DEFAULT_AUTOSUSPEND_DELAY 1000
84
9765e768
TK		 85#define FLAGS_IN_DATA_ST_SHIFT 8
86#define FLAGS_OUT_DATA_ST_SHIFT 10
87
e91aa9d5 88struct omap_des_ctx {
c21c8b89 89 struct crypto_engine_ctx enginectx;
e91aa9d5
JF		 90 struct omap_des_dev *dd;
91
92 int keylen;
93 u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
94 unsigned long flags;
95};
96
97struct omap_des_reqctx {
98 unsigned long mode;
99};
100
101#define OMAP_DES_QUEUE_LENGTH 1
102#define OMAP_DES_CACHE_SIZE 0
103
104struct omap_des_algs_info {
105 struct crypto_alg *algs_list;
106 unsigned int size;
107 unsigned int registered;
108};
109
110struct omap_des_pdata {
111 struct omap_des_algs_info *algs_info;
112 unsigned int algs_info_size;
113
114 void (*trigger)(struct omap_des_dev *dd, int length);
115
116 u32 key_ofs;
117 u32 iv_ofs;
118 u32 ctrl_ofs;
119 u32 data_ofs;
120 u32 rev_ofs;
121 u32 mask_ofs;
122 u32 irq_enable_ofs;
123 u32 irq_status_ofs;
124
125 u32 dma_enable_in;
126 u32 dma_enable_out;
127 u32 dma_start;
128
129 u32 major_mask;
130 u32 major_shift;
131 u32 minor_mask;
132 u32 minor_shift;
133};
134
135struct omap_des_dev {
136 struct list_head list;
137 unsigned long phys_base;
138 void __iomem *io_base;
139 struct omap_des_ctx *ctx;
140 struct device *dev;
141 unsigned long flags;
142 int err;
143
e91aa9d5 144 struct tasklet_struct done_task;
e91aa9d5
JF		 145
146 struct ablkcipher_request *req;
f1b77aac 147 struct crypto_engine *engine;
e91aa9d5
JF		 148 /*
149 * total is used by PIO mode for book keeping so introduce
150 * variable total_save as need it to calc page_order
151 */
152 size_t total;
153 size_t total_save;
154
155 struct scatterlist *in_sg;
156 struct scatterlist *out_sg;
157
158 /* Buffers for copying for unaligned cases */
159 struct scatterlist in_sgl;
160 struct scatterlist out_sgl;
161 struct scatterlist *orig_out;
e91aa9d5
JF		 162
163 struct scatter_walk in_walk;
164 struct scatter_walk out_walk;
e91aa9d5 165 struct dma_chan *dma_lch_in;
e91aa9d5
JF		 166 struct dma_chan *dma_lch_out;
167 int in_sg_len;
168 int out_sg_len;
169 int pio_only;
170 const struct omap_des_pdata *pdata;
171};
172
173/* keep registered devices data here */
174static LIST_HEAD(dev_list);
175static DEFINE_SPINLOCK(list_lock);
176
177#ifdef DEBUG
178#define omap_des_read(dd, offset) \
179 ({ \
180 int _read_ret; \
181 _read_ret = __raw_readl(dd->io_base + offset); \
182 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
183 offset, _read_ret); \
184 _read_ret; \
185 })
186#else
187static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
188{
189 return __raw_readl(dd->io_base + offset);
190}
191#endif
192
193#ifdef DEBUG
194#define omap_des_write(dd, offset, value) \
195 do { \
196 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
197 offset, value); \
198 __raw_writel(value, dd->io_base + offset); \
199 } while (0)
200#else
201static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
202 u32 value)
203{
204 __raw_writel(value, dd->io_base + offset);
205}
206#endif
207
208static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
209 u32 value, u32 mask)
210{
211 u32 val;
212
213 val = omap_des_read(dd, offset);
214 val &= ~mask;
215 val |= value;
216 omap_des_write(dd, offset, val);
217}
218
219static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
220 u32 *value, int count)
221{
222 for (; count--; value++, offset += 4)
223 omap_des_write(dd, offset, *value);
224}
225
226static int omap_des_hw_init(struct omap_des_dev *dd)
227{
f51f593b
NM		 228 int err;
229
e91aa9d5
JF		 230 /*
231 * clocks are enabled when request starts and disabled when finished.
232 * It may be long delays between requests.
233 * Device might go to off mode to save power.
234 */
f51f593b
NM		 235 err = pm_runtime_get_sync(dd->dev);
236 if (err < 0) {
237 pm_runtime_put_noidle(dd->dev);
238 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
239 return err;
240 }
e91aa9d5
JF		 241
242 if (!(dd->flags & FLAGS_INIT)) {
243 dd->flags |= FLAGS_INIT;
244 dd->err = 0;
245 }
246
247 return 0;
248}
249
250static int omap_des_write_ctrl(struct omap_des_dev *dd)
251{
252 unsigned int key32;
253 int i, err;
254 u32 val = 0, mask = 0;
255
256 err = omap_des_hw_init(dd);
257 if (err)
258 return err;
259
260 key32 = dd->ctx->keylen / sizeof(u32);
261
262 /* it seems a key should always be set even if it has not changed */
263 for (i = 0; i < key32; i++) {
264 omap_des_write(dd, DES_REG_KEY(dd, i),
265 __le32_to_cpu(dd->ctx->key[i]));
266 }
267
268 if ((dd->flags & FLAGS_CBC) && dd->req->info)
269 omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2);
270
271 if (dd->flags & FLAGS_CBC)
272 val |= DES_REG_CTRL_CBC;
273 if (dd->flags & FLAGS_ENCRYPT)
274 val |= DES_REG_CTRL_DIRECTION;
275 if (key32 == 6)
276 val |= DES_REG_CTRL_TDES;
277
278 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
279
280 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
281
282 return 0;
283}
284
285static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
286{
287 u32 mask, val;
288
289 omap_des_write(dd, DES_REG_LENGTH_N(0), length);
290
291 val = dd->pdata->dma_start;
292
293 if (dd->dma_lch_out != NULL)
294 val |= dd->pdata->dma_enable_out;
295 if (dd->dma_lch_in != NULL)
296 val |= dd->pdata->dma_enable_in;
297
298 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
299 dd->pdata->dma_start;
300
301 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
302}
303
304static void omap_des_dma_stop(struct omap_des_dev *dd)
305{
306 u32 mask;
307
308 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
309 dd->pdata->dma_start;
310
311 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
312}
313
314static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
315{
316 struct omap_des_dev *dd = NULL, *tmp;
317
318 spin_lock_bh(&list_lock);
319 if (!ctx->dd) {
320 list_for_each_entry(tmp, &dev_list, list) {
321 /* FIXME: take fist available des core */
322 dd = tmp;
323 break;
324 }
325 ctx->dd = dd;
326 } else {
327 /* already found before */
328 dd = ctx->dd;
329 }
330 spin_unlock_bh(&list_lock);
331
332 return dd;
333}
334
335static void omap_des_dma_out_callback(void *data)
336{
337 struct omap_des_dev *dd = data;
338
339 /* dma_lch_out - completed */
340 tasklet_schedule(&dd->done_task);
341}
342
343static int omap_des_dma_init(struct omap_des_dev *dd)
344{
2f6f0680 345 int err;
e91aa9d5
JF		 346
347 dd->dma_lch_out = NULL;
348 dd->dma_lch_in = NULL;
349
2f6f0680
PU		 350 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
351 if (IS_ERR(dd->dma_lch_in)) {
e91aa9d5 352 dev_err(dd->dev, "Unable to request in DMA channel\n");
2f6f0680 353 return PTR_ERR(dd->dma_lch_in);
e91aa9d5
JF		 354 }
355
2f6f0680
PU		 356 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
357 if (IS_ERR(dd->dma_lch_out)) {
e91aa9d5 358 dev_err(dd->dev, "Unable to request out DMA channel\n");
2f6f0680 359 err = PTR_ERR(dd->dma_lch_out);
e91aa9d5
JF		 360 goto err_dma_out;
361 }
362
363 return 0;
364
365err_dma_out:
366 dma_release_channel(dd->dma_lch_in);
2f6f0680 367
e91aa9d5
JF		 368 return err;
369}
370
371static void omap_des_dma_cleanup(struct omap_des_dev *dd)
372{
2f6f0680
PU		 373 if (dd->pio_only)
374 return;
375
e91aa9d5
JF		 376 dma_release_channel(dd->dma_lch_out);
377 dma_release_channel(dd->dma_lch_in);
378}
379
e91aa9d5
JF		 380static int omap_des_crypt_dma(struct crypto_tfm *tfm,
381 struct scatterlist *in_sg, struct scatterlist *out_sg,
382 int in_sg_len, int out_sg_len)
383{
384 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
385 struct omap_des_dev *dd = ctx->dd;
386 struct dma_async_tx_descriptor *tx_in, *tx_out;
387 struct dma_slave_config cfg;
388 int ret;
389
390 if (dd->pio_only) {
391 scatterwalk_start(&dd->in_walk, dd->in_sg);
392 scatterwalk_start(&dd->out_walk, dd->out_sg);
393
394 /* Enable DATAIN interrupt and let it take
395 care of the rest */
396 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
397 return 0;
398 }
399
400 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
401
402 memset(&cfg, 0, sizeof(cfg));
403
404 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
405 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
406 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
407 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
408 cfg.src_maxburst = DST_MAXBURST;
409 cfg.dst_maxburst = DST_MAXBURST;
410
411 /* IN */
412 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
413 if (ret) {
414 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
415 ret);
416 return ret;
417 }
418
419 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
420 DMA_MEM_TO_DEV,
421 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
422 if (!tx_in) {
423 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
424 return -EINVAL;
425 }
426
427 /* No callback necessary */
428 tx_in->callback_param = dd;
429
430 /* OUT */
431 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
432 if (ret) {
433 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
434 ret);
435 return ret;
436 }
437
438 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
439 DMA_DEV_TO_MEM,
440 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
441 if (!tx_out) {
442 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
443 return -EINVAL;
444 }
445
446 tx_out->callback = omap_des_dma_out_callback;
447 tx_out->callback_param = dd;
448
449 dmaengine_submit(tx_in);
450 dmaengine_submit(tx_out);
451
452 dma_async_issue_pending(dd->dma_lch_in);
453 dma_async_issue_pending(dd->dma_lch_out);
454
455 /* start DMA */
456 dd->pdata->trigger(dd, dd->total);
457
458 return 0;
459}
460
461static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
462{
463 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
464 crypto_ablkcipher_reqtfm(dd->req));
465 int err;
466
467 pr_debug("total: %d\n", dd->total);
468
469 if (!dd->pio_only) {
470 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
471 DMA_TO_DEVICE);
472 if (!err) {
473 dev_err(dd->dev, "dma_map_sg() error\n");
474 return -EINVAL;
475 }
476
477 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
478 DMA_FROM_DEVICE);
479 if (!err) {
480 dev_err(dd->dev, "dma_map_sg() error\n");
481 return -EINVAL;
482 }
483 }
484
485 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
486 dd->out_sg_len);
487 if (err && !dd->pio_only) {
488 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
489 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
490 DMA_FROM_DEVICE);
491 }
492
493 return err;
494}
495
496static void omap_des_finish_req(struct omap_des_dev *dd, int err)
497{
498 struct ablkcipher_request *req = dd->req;
499
500 pr_debug("err: %d\n", err);
501
c21c8b89 502 crypto_finalize_ablkcipher_request(dd->engine, req, err);
418f2a8c
TK		 503
504 pm_runtime_mark_last_busy(dd->dev);
505 pm_runtime_put_autosuspend(dd->dev);
e91aa9d5
JF		 506}
507
508static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
509{
e91aa9d5
JF		 510 pr_debug("total: %d\n", dd->total);
511
512 omap_des_dma_stop(dd);
513
514 dmaengine_terminate_all(dd->dma_lch_in);
515 dmaengine_terminate_all(dd->dma_lch_out);
516
16f080aa 517 return 0;
e91aa9d5
JF		 518}
519
e91aa9d5 520static int omap_des_handle_queue(struct omap_des_dev *dd,
f1b77aac 521 struct ablkcipher_request *req)
e91aa9d5 522{
e91aa9d5 523 if (req)
c21c8b89 524 return crypto_transfer_ablkcipher_request_to_engine(dd->engine, req);
e91aa9d5 525
f1b77aac
BW		 526 return 0;
527}
e91aa9d5 528
f1b77aac 529static int omap_des_prepare_req(struct crypto_engine *engine,
c21c8b89 530 void *areq)
f1b77aac 531{
c21c8b89 532 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
f1b77aac
BW		 533 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
534 crypto_ablkcipher_reqtfm(req));
535 struct omap_des_dev *dd = omap_des_find_dev(ctx);
536 struct omap_des_reqctx *rctx;
9765e768
TK		 537 int ret;
538 u16 flags;
e91aa9d5 539
f1b77aac
BW		 540 if (!dd)
541 return -ENODEV;
e91aa9d5
JF		 542
543 /* assign new request to device */
544 dd->req = req;
545 dd->total = req->nbytes;
546 dd->total_save = req->nbytes;
547 dd->in_sg = req->src;
548 dd->out_sg = req->dst;
9765e768
TK		 549 dd->orig_out = req->dst;
550
551 flags = OMAP_CRYPTO_COPY_DATA;
552 if (req->src == req->dst)
553 flags |= OMAP_CRYPTO_FORCE_COPY;
554
555 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
556 &dd->in_sgl, flags,
557 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
558 if (ret)
559 return ret;
560
561 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
562 &dd->out_sgl, 0,
563 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
564 if (ret)
565 return ret;
e91aa9d5 566
7c001a86
HX		 567 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
568 if (dd->in_sg_len < 0)
569 return dd->in_sg_len;
570
571 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
572 if (dd->out_sg_len < 0)
573 return dd->out_sg_len;
574
e91aa9d5
JF		 575 rctx = ablkcipher_request_ctx(req);
576 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
577 rctx->mode &= FLAGS_MODE_MASK;
578 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
579
580 dd->ctx = ctx;
581 ctx->dd = dd;
582
f1b77aac
BW		 583 return omap_des_write_ctrl(dd);
584}
e91aa9d5 585
f1b77aac 586static int omap_des_crypt_req(struct crypto_engine *engine,
c21c8b89 587 void *areq)
f1b77aac 588{
c21c8b89 589 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
f1b77aac
BW		 590 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
591 crypto_ablkcipher_reqtfm(req));
592 struct omap_des_dev *dd = omap_des_find_dev(ctx);
593
594 if (!dd)
595 return -ENODEV;
596
597 return omap_des_crypt_dma_start(dd);
e91aa9d5
JF		 598}
599
600static void omap_des_done_task(unsigned long data)
601{
602 struct omap_des_dev *dd = (struct omap_des_dev *)data;
e91aa9d5
JF		 603
604 pr_debug("enter done_task\n");
605
606 if (!dd->pio_only) {
607 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
608 DMA_FROM_DEVICE);
609 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
610 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
611 DMA_FROM_DEVICE);
612 omap_des_crypt_dma_stop(dd);
613 }
614
9765e768
TK		 615 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
616 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
e91aa9d5 617
9765e768
TK		 618 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
619 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
e91aa9d5
JF		 620
621 omap_des_finish_req(dd, 0);
e91aa9d5
JF		 622
623 pr_debug("exit\n");
624}
625
e91aa9d5
JF		 626static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode)
627{
628 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
629 crypto_ablkcipher_reqtfm(req));
630 struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req);
631 struct omap_des_dev *dd;
632
633 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
634 !!(mode & FLAGS_ENCRYPT),
635 !!(mode & FLAGS_CBC));
636
637 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) {
638 pr_err("request size is not exact amount of DES blocks\n");
639 return -EINVAL;
640 }
641
642 dd = omap_des_find_dev(ctx);
643 if (!dd)
644 return -ENODEV;
645
646 rctx->mode = mode;
647
648 return omap_des_handle_queue(dd, req);
649}
650
651/* ********************** ALG API ************************************ */
652
a636fdce 653static int omap_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
e91aa9d5
JF		 654 unsigned int keylen)
655{
a636fdce
TK		 656 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(cipher);
657 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
e91aa9d5
JF		 658
659 if (keylen != DES_KEY_SIZE && keylen != (3*DES_KEY_SIZE))
660 return -EINVAL;
661
662 pr_debug("enter, keylen: %d\n", keylen);
663
a636fdce 664 /* Do we need to test against weak key? */
231baecd 665 if (tfm->crt_flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) {
a636fdce
TK		 666 u32 tmp[DES_EXPKEY_WORDS];
667 int ret = des_ekey(tmp, key);
668
669 if (!ret) {
670 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
671 return -EINVAL;
672 }
673 }
674
e91aa9d5
JF		 675 memcpy(ctx->key, key, keylen);
676 ctx->keylen = keylen;
677
678 return 0;
679}
680
681static int omap_des_ecb_encrypt(struct ablkcipher_request *req)
682{
683 return omap_des_crypt(req, FLAGS_ENCRYPT);
684}
685
686static int omap_des_ecb_decrypt(struct ablkcipher_request *req)
687{
688 return omap_des_crypt(req, 0);
689}
690
691static int omap_des_cbc_encrypt(struct ablkcipher_request *req)
692{
693 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
694}
695
696static int omap_des_cbc_decrypt(struct ablkcipher_request *req)
697{
698 return omap_des_crypt(req, FLAGS_CBC);
699}
700
c21c8b89
CL		 701static int omap_des_prepare_req(struct crypto_engine *engine,
702 void *areq);
703static int omap_des_crypt_req(struct crypto_engine *engine,
704 void *areq);
705
e91aa9d5
JF		 706static int omap_des_cra_init(struct crypto_tfm *tfm)
707{
c21c8b89
CL		 708 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
709
e91aa9d5
JF		 710 pr_debug("enter\n");
711
712 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx);
713
c21c8b89
CL		 714 ctx->enginectx.op.prepare_request = omap_des_prepare_req;
715 ctx->enginectx.op.unprepare_request = NULL;
716 ctx->enginectx.op.do_one_request = omap_des_crypt_req;
717
e91aa9d5
JF		 718 return 0;
719}
720
721static void omap_des_cra_exit(struct crypto_tfm *tfm)
722{
723 pr_debug("enter\n");
724}
725
726/* ********************** ALGS ************************************ */
727
728static struct crypto_alg algs_ecb_cbc[] = {
729{
730 .cra_name = "ecb(des)",
731 .cra_driver_name = "ecb-des-omap",
732 .cra_priority = 100,
733 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
734 CRYPTO_ALG_KERN_DRIVER_ONLY |
735 CRYPTO_ALG_ASYNC,
736 .cra_blocksize = DES_BLOCK_SIZE,
737 .cra_ctxsize = sizeof(struct omap_des_ctx),
738 .cra_alignmask = 0,
739 .cra_type = &crypto_ablkcipher_type,
740 .cra_module = THIS_MODULE,
741 .cra_init = omap_des_cra_init,
742 .cra_exit = omap_des_cra_exit,
743 .cra_u.ablkcipher = {
744 .min_keysize = DES_KEY_SIZE,
745 .max_keysize = DES_KEY_SIZE,
746 .setkey = omap_des_setkey,
747 .encrypt = omap_des_ecb_encrypt,
748 .decrypt = omap_des_ecb_decrypt,
749 }
750},
751{
752 .cra_name = "cbc(des)",
753 .cra_driver_name = "cbc-des-omap",
754 .cra_priority = 100,
755 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
756 CRYPTO_ALG_KERN_DRIVER_ONLY |
757 CRYPTO_ALG_ASYNC,
758 .cra_blocksize = DES_BLOCK_SIZE,
759 .cra_ctxsize = sizeof(struct omap_des_ctx),
760 .cra_alignmask = 0,
761 .cra_type = &crypto_ablkcipher_type,
762 .cra_module = THIS_MODULE,
763 .cra_init = omap_des_cra_init,
764 .cra_exit = omap_des_cra_exit,
765 .cra_u.ablkcipher = {
766 .min_keysize = DES_KEY_SIZE,
767 .max_keysize = DES_KEY_SIZE,
768 .ivsize = DES_BLOCK_SIZE,
769 .setkey = omap_des_setkey,
770 .encrypt = omap_des_cbc_encrypt,
771 .decrypt = omap_des_cbc_decrypt,
772 }
773},
774{
775 .cra_name = "ecb(des3_ede)",
776 .cra_driver_name = "ecb-des3-omap",
777 .cra_priority = 100,
778 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
779 CRYPTO_ALG_KERN_DRIVER_ONLY |
780 CRYPTO_ALG_ASYNC,
781 .cra_blocksize = DES_BLOCK_SIZE,
782 .cra_ctxsize = sizeof(struct omap_des_ctx),
783 .cra_alignmask = 0,
784 .cra_type = &crypto_ablkcipher_type,
785 .cra_module = THIS_MODULE,
786 .cra_init = omap_des_cra_init,
787 .cra_exit = omap_des_cra_exit,
788 .cra_u.ablkcipher = {
789 .min_keysize = 3*DES_KEY_SIZE,
790 .max_keysize = 3*DES_KEY_SIZE,
791 .setkey = omap_des_setkey,
792 .encrypt = omap_des_ecb_encrypt,
793 .decrypt = omap_des_ecb_decrypt,
794 }
795},
796{
797 .cra_name = "cbc(des3_ede)",
798 .cra_driver_name = "cbc-des3-omap",
799 .cra_priority = 100,
800 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
801 CRYPTO_ALG_KERN_DRIVER_ONLY |
802 CRYPTO_ALG_ASYNC,
803 .cra_blocksize = DES_BLOCK_SIZE,
804 .cra_ctxsize = sizeof(struct omap_des_ctx),
805 .cra_alignmask = 0,
806 .cra_type = &crypto_ablkcipher_type,
807 .cra_module = THIS_MODULE,
808 .cra_init = omap_des_cra_init,
809 .cra_exit = omap_des_cra_exit,
810 .cra_u.ablkcipher = {
811 .min_keysize = 3*DES_KEY_SIZE,
812 .max_keysize = 3*DES_KEY_SIZE,
813 .ivsize = DES_BLOCK_SIZE,
814 .setkey = omap_des_setkey,
815 .encrypt = omap_des_cbc_encrypt,
816 .decrypt = omap_des_cbc_decrypt,
817 }
818}
819};
820
821static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
822 {
823 .algs_list = algs_ecb_cbc,
824 .size = ARRAY_SIZE(algs_ecb_cbc),
825 },
826};
827
828#ifdef CONFIG_OF
829static const struct omap_des_pdata omap_des_pdata_omap4 = {
830 .algs_info = omap_des_algs_info_ecb_cbc,
831 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
832 .trigger = omap_des_dma_trigger_omap4,
833 .key_ofs = 0x14,
834 .iv_ofs = 0x18,
835 .ctrl_ofs = 0x20,
836 .data_ofs = 0x28,
837 .rev_ofs = 0x30,
838 .mask_ofs = 0x34,
839 .irq_status_ofs = 0x3c,
840 .irq_enable_ofs = 0x40,
841 .dma_enable_in = BIT(5),
842 .dma_enable_out = BIT(6),
843 .major_mask = 0x0700,
844 .major_shift = 8,
845 .minor_mask = 0x003f,
846 .minor_shift = 0,
847};
848
849static irqreturn_t omap_des_irq(int irq, void *dev_id)
850{
851 struct omap_des_dev *dd = dev_id;
852 u32 status, i;
853 u32 *src, *dst;
854
855 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
856 if (status & DES_REG_IRQ_DATA_IN) {
857 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
858
859 BUG_ON(!dd->in_sg);
860
861 BUG_ON(_calc_walked(in) > dd->in_sg->length);
862
863 src = sg_virt(dd->in_sg) + _calc_walked(in);
864
865 for (i = 0; i < DES_BLOCK_WORDS; i++) {
866 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
867
868 scatterwalk_advance(&dd->in_walk, 4);
869 if (dd->in_sg->length == _calc_walked(in)) {
5be4d4c9 870 dd->in_sg = sg_next(dd->in_sg);
e91aa9d5
JF		 871 if (dd->in_sg) {
872 scatterwalk_start(&dd->in_walk,
873 dd->in_sg);
874 src = sg_virt(dd->in_sg) +
875 _calc_walked(in);
876 }
877 } else {
878 src++;
879 }
880 }
881
882 /* Clear IRQ status */
883 status &= ~DES_REG_IRQ_DATA_IN;
884 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
885
886 /* Enable DATA_OUT interrupt */
887 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
888
889 } else if (status & DES_REG_IRQ_DATA_OUT) {
890 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
891
892 BUG_ON(!dd->out_sg);
893
894 BUG_ON(_calc_walked(out) > dd->out_sg->length);
895
896 dst = sg_virt(dd->out_sg) + _calc_walked(out);
897
898 for (i = 0; i < DES_BLOCK_WORDS; i++) {
899 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
900 scatterwalk_advance(&dd->out_walk, 4);
901 if (dd->out_sg->length == _calc_walked(out)) {
5be4d4c9 902 dd->out_sg = sg_next(dd->out_sg);
e91aa9d5
JF		 903 if (dd->out_sg) {
904 scatterwalk_start(&dd->out_walk,
905 dd->out_sg);
906 dst = sg_virt(dd->out_sg) +
907 _calc_walked(out);
908 }
909 } else {
910 dst++;
911 }
912 }
913
42d2e780 914 BUG_ON(dd->total < DES_BLOCK_SIZE);
e91aa9d5 915
42d2e780 916 dd->total -= DES_BLOCK_SIZE;
e91aa9d5
JF		 917
918 /* Clear IRQ status */
919 status &= ~DES_REG_IRQ_DATA_OUT;
920 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
921
922 if (!dd->total)
923 /* All bytes read! */
924 tasklet_schedule(&dd->done_task);
925 else
926 /* Enable DATA_IN interrupt for next block */
927 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
928 }
929
930 return IRQ_HANDLED;
931}
932
933static const struct of_device_id omap_des_of_match[] = {
934 {
935 .compatible = "ti,omap4-des",
936 .data = &omap_des_pdata_omap4,
937 },
938 {},
939};
940MODULE_DEVICE_TABLE(of, omap_des_of_match);
941
942static int omap_des_get_of(struct omap_des_dev *dd,
943 struct platform_device *pdev)
944{
e91aa9d5 945
7d556931
CL		 946 dd->pdata = of_device_get_match_data(&pdev->dev);
947 if (!dd->pdata) {
e91aa9d5
JF		 948 dev_err(&pdev->dev, "no compatible OF match\n");
949 return -EINVAL;
950 }
951
e91aa9d5
JF		 952 return 0;
953}
954#else
955static int omap_des_get_of(struct omap_des_dev *dd,
956 struct device *dev)
957{
958 return -EINVAL;
959}
960#endif
961
962static int omap_des_get_pdev(struct omap_des_dev *dd,
963 struct platform_device *pdev)
964{
e91aa9d5
JF		 965 /* non-DT devices get pdata from pdev */
966 dd->pdata = pdev->dev.platform_data;
967
2f6f0680 968 return 0;
e91aa9d5
JF		 969}
970
971static int omap_des_probe(struct platform_device *pdev)
972{
973 struct device *dev = &pdev->dev;
974 struct omap_des_dev *dd;
975 struct crypto_alg *algp;
976 struct resource *res;
977 int err = -ENOMEM, i, j, irq = -1;
978 u32 reg;
979
980 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
981 if (dd == NULL) {
982 dev_err(dev, "unable to alloc data struct.\n");
983 goto err_data;
984 }
985 dd->dev = dev;
986 platform_set_drvdata(pdev, dd);
987
e91aa9d5
JF		 988 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
989 if (!res) {
990 dev_err(dev, "no MEM resource info\n");
991 goto err_res;
992 }
993
994 err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
995 omap_des_get_pdev(dd, pdev);
996 if (err)
997 goto err_res;
998
2496be2e
JH		 999 dd->io_base = devm_ioremap_resource(dev, res);
1000 if (IS_ERR(dd->io_base)) {
1001 err = PTR_ERR(dd->io_base);
e91aa9d5
JF		 1002 goto err_res;
1003 }
1004 dd->phys_base = res->start;
1005
418f2a8c
TK		 1006 pm_runtime_use_autosuspend(dev);
1007 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1008
e91aa9d5 1009 pm_runtime_enable(dev);
f51f593b
NM		 1010 err = pm_runtime_get_sync(dev);
1011 if (err < 0) {
1012 pm_runtime_put_noidle(dev);
1013 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
1014 goto err_get;
1015 }
e91aa9d5
JF		 1016
1017 omap_des_dma_stop(dd);
1018
1019 reg = omap_des_read(dd, DES_REG_REV(dd));
1020
1021 pm_runtime_put_sync(dev);
1022
1023 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
1024 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1025 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1026
1027 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
e91aa9d5
JF		 1028
1029 err = omap_des_dma_init(dd);
2f6f0680
PU		 1030 if (err == -EPROBE_DEFER) {
1031 goto err_irq;
1032 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
e91aa9d5
JF		 1033 dd->pio_only = 1;
1034
1035 irq = platform_get_irq(pdev, 0);
1036 if (irq < 0) {
3822c331
GS		 1037 dev_err(dev, "can't get IRQ resource: %d\n", irq);
1038 err = irq;
e91aa9d5
JF		 1039 goto err_irq;
1040 }
1041
1042 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1043 dev_name(dev), dd);
1044 if (err) {
1045 dev_err(dev, "Unable to grab omap-des IRQ\n");
1046 goto err_irq;
1047 }
1048 }
1049
1050
1051 INIT_LIST_HEAD(&dd->list);
1052 spin_lock(&list_lock);
1053 list_add_tail(&dd->list, &dev_list);
1054 spin_unlock(&list_lock);
1055
1d1f98d1
TK		 1056 /* Initialize des crypto engine */
1057 dd->engine = crypto_engine_alloc_init(dev, 1);
59af1566
WY		 1058 if (!dd->engine) {
1059 err = -ENOMEM;
1d1f98d1 1060 goto err_engine;
59af1566 1061 }
1d1f98d1 1062
1d1f98d1
TK		 1063 err = crypto_engine_start(dd->engine);
1064 if (err)
1065 goto err_engine;
1066
e91aa9d5
JF		 1067 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1068 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1069 algp = &dd->pdata->algs_info[i].algs_list[j];
1070
1071 pr_debug("reg alg: %s\n", algp->cra_name);
e91aa9d5
JF		 1072
1073 err = crypto_register_alg(algp);
1074 if (err)
1075 goto err_algs;
1076
1077 dd->pdata->algs_info[i].registered++;
1078 }
1079 }
1080
1081 return 0;
f1b77aac 1082
e91aa9d5
JF		 1083err_algs:
1084 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1085 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1086 crypto_unregister_alg(
1087 &dd->pdata->algs_info[i].algs_list[j]);
2f6f0680 1088
1d1f98d1
TK		 1089err_engine:
1090 if (dd->engine)
1091 crypto_engine_exit(dd->engine);
1092
2f6f0680 1093 omap_des_dma_cleanup(dd);
e91aa9d5
JF		 1094err_irq:
1095 tasklet_kill(&dd->done_task);
f51f593b 1096err_get:
e91aa9d5
JF		 1097 pm_runtime_disable(dev);
1098err_res:
1099 dd = NULL;
1100err_data:
1101 dev_err(dev, "initialization failed.\n");
1102 return err;
1103}
1104
1105static int omap_des_remove(struct platform_device *pdev)
1106{
1107 struct omap_des_dev *dd = platform_get_drvdata(pdev);
1108 int i, j;
1109
1110 if (!dd)
1111 return -ENODEV;
1112
1113 spin_lock(&list_lock);
1114 list_del(&dd->list);
1115 spin_unlock(&list_lock);
1116
1117 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1118 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1119 crypto_unregister_alg(
1120 &dd->pdata->algs_info[i].algs_list[j]);
1121
1122 tasklet_kill(&dd->done_task);
e91aa9d5
JF		 1123 omap_des_dma_cleanup(dd);
1124 pm_runtime_disable(dd->dev);
1125 dd = NULL;
1126
1127 return 0;
1128}
1129
1130#ifdef CONFIG_PM_SLEEP
1131static int omap_des_suspend(struct device *dev)
1132{
1133 pm_runtime_put_sync(dev);
1134 return 0;
1135}
1136
1137static int omap_des_resume(struct device *dev)
1138{
f51f593b
NM		 1139 int err;
1140
1141 err = pm_runtime_get_sync(dev);
1142 if (err < 0) {
1143 pm_runtime_put_noidle(dev);
1144 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1145 return err;
1146 }
e91aa9d5
JF		 1147 return 0;
1148}
1149#endif
1150
e78f9193 1151static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
e91aa9d5
JF		 1152
1153static struct platform_driver omap_des_driver = {
1154 .probe = omap_des_probe,
1155 .remove = omap_des_remove,
1156 .driver = {
1157 .name = "omap-des",
e91aa9d5
JF		 1158 .pm = &omap_des_pm_ops,
1159 .of_match_table = of_match_ptr(omap_des_of_match),
1160 },
1161};
1162
1163module_platform_driver(omap_des_driver);
1164
1165MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1166MODULE_LICENSE("GPL v2");
1167MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");
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