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Commit | Line | Data |
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8628e7c8 DK |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for OMAP SHA1/MD5 HW acceleration. | |
5 | * | |
6 | * Copyright (c) 2010 Nokia Corporation | |
7 | * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> | |
0d373d60 | 8 | * Copyright (c) 2011 Texas Instruments Incorporated |
8628e7c8 DK |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as published | |
12 | * by the Free Software Foundation. | |
13 | * | |
14 | * Some ideas are from old omap-sha1-md5.c driver. | |
15 | */ | |
16 | ||
17 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
18 | ||
8628e7c8 DK |
19 | #include <linux/err.h> |
20 | #include <linux/device.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/kernel.h> | |
8628e7c8 DK |
26 | #include <linux/irq.h> |
27 | #include <linux/io.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/scatterlist.h> | |
30 | #include <linux/dma-mapping.h> | |
dfd061d5 | 31 | #include <linux/dmaengine.h> |
b359f034 | 32 | #include <linux/pm_runtime.h> |
03feec9c MG |
33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | |
35 | #include <linux/of_address.h> | |
36 | #include <linux/of_irq.h> | |
8628e7c8 DK |
37 | #include <linux/delay.h> |
38 | #include <linux/crypto.h> | |
39 | #include <linux/cryptohash.h> | |
40 | #include <crypto/scatterwalk.h> | |
41 | #include <crypto/algapi.h> | |
42 | #include <crypto/sha.h> | |
43 | #include <crypto/hash.h> | |
44 | #include <crypto/internal/hash.h> | |
45 | ||
8628e7c8 DK |
46 | #define MD5_DIGEST_SIZE 16 |
47 | ||
0d373d60 MG |
48 | #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) |
49 | #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) | |
50 | #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) | |
51 | ||
eaef7e3f | 52 | #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) |
8628e7c8 DK |
53 | |
54 | #define SHA_REG_CTRL 0x18 | |
55 | #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) | |
56 | #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) | |
57 | #define SHA_REG_CTRL_ALGO_CONST (1 << 3) | |
58 | #define SHA_REG_CTRL_ALGO (1 << 2) | |
59 | #define SHA_REG_CTRL_INPUT_READY (1 << 1) | |
60 | #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) | |
61 | ||
0d373d60 | 62 | #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) |
8628e7c8 | 63 | |
0d373d60 | 64 | #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) |
8628e7c8 DK |
65 | #define SHA_REG_MASK_DMA_EN (1 << 3) |
66 | #define SHA_REG_MASK_IT_EN (1 << 2) | |
67 | #define SHA_REG_MASK_SOFTRESET (1 << 1) | |
68 | #define SHA_REG_AUTOIDLE (1 << 0) | |
69 | ||
0d373d60 | 70 | #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) |
8628e7c8 DK |
71 | #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) |
72 | ||
eaef7e3f | 73 | #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) |
0d373d60 MG |
74 | #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) |
75 | #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) | |
76 | #define SHA_REG_MODE_CLOSE_HASH (1 << 4) | |
77 | #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) | |
0d373d60 | 78 | |
eaef7e3f LV |
79 | #define SHA_REG_MODE_ALGO_MASK (7 << 0) |
80 | #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) | |
81 | #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) | |
82 | #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1) | |
83 | #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1) | |
84 | #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0) | |
85 | #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0) | |
86 | ||
87 | #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) | |
0d373d60 MG |
88 | |
89 | #define SHA_REG_IRQSTATUS 0x118 | |
90 | #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) | |
91 | #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) | |
92 | #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) | |
93 | #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) | |
94 | ||
95 | #define SHA_REG_IRQENA 0x11C | |
96 | #define SHA_REG_IRQENA_CTX_RDY (1 << 3) | |
97 | #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) | |
98 | #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) | |
99 | #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) | |
100 | ||
8628e7c8 DK |
101 | #define DEFAULT_TIMEOUT_INTERVAL HZ |
102 | ||
e93f767b TK |
103 | #define DEFAULT_AUTOSUSPEND_DELAY 1000 |
104 | ||
ea1fd224 DK |
105 | /* mostly device flags */ |
106 | #define FLAGS_BUSY 0 | |
107 | #define FLAGS_FINAL 1 | |
108 | #define FLAGS_DMA_ACTIVE 2 | |
109 | #define FLAGS_OUTPUT_READY 3 | |
110 | #define FLAGS_INIT 4 | |
111 | #define FLAGS_CPU 5 | |
6c63db82 | 112 | #define FLAGS_DMA_READY 6 |
0d373d60 MG |
113 | #define FLAGS_AUTO_XOR 7 |
114 | #define FLAGS_BE32_SHA1 8 | |
f19de1bc TK |
115 | #define FLAGS_SGS_COPIED 9 |
116 | #define FLAGS_SGS_ALLOCED 10 | |
ea1fd224 DK |
117 | /* context flags */ |
118 | #define FLAGS_FINUP 16 | |
119 | #define FLAGS_SG 17 | |
8628e7c8 | 120 | |
0d373d60 | 121 | #define FLAGS_MODE_SHIFT 18 |
eaef7e3f LV |
122 | #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT) |
123 | #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT) | |
124 | #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT) | |
125 | #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT) | |
126 | #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT) | |
127 | #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT) | |
128 | #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT) | |
129 | ||
130 | #define FLAGS_HMAC 21 | |
131 | #define FLAGS_ERROR 22 | |
0d373d60 MG |
132 | |
133 | #define OP_UPDATE 1 | |
134 | #define OP_FINAL 2 | |
8628e7c8 | 135 | |
798eed5d DK |
136 | #define OMAP_ALIGN_MASK (sizeof(u32)-1) |
137 | #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) | |
138 | ||
0d373d60 | 139 | #define BUFLEN PAGE_SIZE |
2c5bd1ef | 140 | #define OMAP_SHA_DMA_THRESHOLD 256 |
798eed5d | 141 | |
8628e7c8 DK |
142 | struct omap_sham_dev; |
143 | ||
144 | struct omap_sham_reqctx { | |
145 | struct omap_sham_dev *dd; | |
146 | unsigned long flags; | |
147 | unsigned long op; | |
148 | ||
eaef7e3f | 149 | u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED; |
8628e7c8 | 150 | size_t digcnt; |
8628e7c8 DK |
151 | size_t bufcnt; |
152 | size_t buflen; | |
153 | dma_addr_t dma_addr; | |
154 | ||
155 | /* walk state */ | |
156 | struct scatterlist *sg; | |
f19de1bc | 157 | struct scatterlist sgl[2]; |
8addf571 | 158 | struct scatterlist sgl_tmp; |
8628e7c8 | 159 | unsigned int offset; /* offset in current sg */ |
f19de1bc | 160 | int sg_len; |
8628e7c8 | 161 | unsigned int total; /* total request */ |
798eed5d DK |
162 | |
163 | u8 buffer[0] OMAP_ALIGNED; | |
8628e7c8 DK |
164 | }; |
165 | ||
166 | struct omap_sham_hmac_ctx { | |
167 | struct crypto_shash *shash; | |
eaef7e3f LV |
168 | u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; |
169 | u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; | |
8628e7c8 DK |
170 | }; |
171 | ||
172 | struct omap_sham_ctx { | |
173 | struct omap_sham_dev *dd; | |
174 | ||
175 | unsigned long flags; | |
176 | ||
177 | /* fallback stuff */ | |
178 | struct crypto_shash *fallback; | |
179 | ||
180 | struct omap_sham_hmac_ctx base[0]; | |
181 | }; | |
182 | ||
65e7a549 | 183 | #define OMAP_SHAM_QUEUE_LENGTH 10 |
8628e7c8 | 184 | |
d20fb18b MG |
185 | struct omap_sham_algs_info { |
186 | struct ahash_alg *algs_list; | |
187 | unsigned int size; | |
188 | unsigned int registered; | |
189 | }; | |
190 | ||
0d373d60 | 191 | struct omap_sham_pdata { |
d20fb18b MG |
192 | struct omap_sham_algs_info *algs_info; |
193 | unsigned int algs_info_size; | |
0d373d60 MG |
194 | unsigned long flags; |
195 | int digest_size; | |
196 | ||
197 | void (*copy_hash)(struct ahash_request *req, int out); | |
198 | void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, | |
199 | int final, int dma); | |
200 | void (*trigger)(struct omap_sham_dev *dd, size_t length); | |
201 | int (*poll_irq)(struct omap_sham_dev *dd); | |
202 | irqreturn_t (*intr_hdlr)(int irq, void *dev_id); | |
203 | ||
204 | u32 odigest_ofs; | |
205 | u32 idigest_ofs; | |
206 | u32 din_ofs; | |
207 | u32 digcnt_ofs; | |
208 | u32 rev_ofs; | |
209 | u32 mask_ofs; | |
210 | u32 sysstatus_ofs; | |
eaef7e3f LV |
211 | u32 mode_ofs; |
212 | u32 length_ofs; | |
0d373d60 MG |
213 | |
214 | u32 major_mask; | |
215 | u32 major_shift; | |
216 | u32 minor_mask; | |
217 | u32 minor_shift; | |
218 | }; | |
219 | ||
8628e7c8 DK |
220 | struct omap_sham_dev { |
221 | struct list_head list; | |
222 | unsigned long phys_base; | |
223 | struct device *dev; | |
224 | void __iomem *io_base; | |
225 | int irq; | |
8628e7c8 | 226 | spinlock_t lock; |
3e133c8b | 227 | int err; |
dfd061d5 | 228 | struct dma_chan *dma_lch; |
8628e7c8 | 229 | struct tasklet_struct done_task; |
b8411ccd | 230 | u8 polling_mode; |
f19de1bc | 231 | u8 xmit_buf[BUFLEN]; |
8628e7c8 DK |
232 | |
233 | unsigned long flags; | |
234 | struct crypto_queue queue; | |
235 | struct ahash_request *req; | |
0d373d60 MG |
236 | |
237 | const struct omap_sham_pdata *pdata; | |
8628e7c8 DK |
238 | }; |
239 | ||
240 | struct omap_sham_drv { | |
241 | struct list_head dev_list; | |
242 | spinlock_t lock; | |
243 | unsigned long flags; | |
244 | }; | |
245 | ||
246 | static struct omap_sham_drv sham = { | |
247 | .dev_list = LIST_HEAD_INIT(sham.dev_list), | |
248 | .lock = __SPIN_LOCK_UNLOCKED(sham.lock), | |
249 | }; | |
250 | ||
251 | static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) | |
252 | { | |
253 | return __raw_readl(dd->io_base + offset); | |
254 | } | |
255 | ||
256 | static inline void omap_sham_write(struct omap_sham_dev *dd, | |
257 | u32 offset, u32 value) | |
258 | { | |
259 | __raw_writel(value, dd->io_base + offset); | |
260 | } | |
261 | ||
262 | static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, | |
263 | u32 value, u32 mask) | |
264 | { | |
265 | u32 val; | |
266 | ||
267 | val = omap_sham_read(dd, address); | |
268 | val &= ~mask; | |
269 | val |= value; | |
270 | omap_sham_write(dd, address, val); | |
271 | } | |
272 | ||
273 | static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) | |
274 | { | |
275 | unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; | |
276 | ||
277 | while (!(omap_sham_read(dd, offset) & bit)) { | |
278 | if (time_is_before_jiffies(timeout)) | |
279 | return -ETIMEDOUT; | |
280 | } | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
0d373d60 | 285 | static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) |
8628e7c8 DK |
286 | { |
287 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
0d373d60 | 288 | struct omap_sham_dev *dd = ctx->dd; |
0c3cf4cc | 289 | u32 *hash = (u32 *)ctx->digest; |
8628e7c8 DK |
290 | int i; |
291 | ||
0d373d60 | 292 | for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { |
3c8d758a | 293 | if (out) |
0d373d60 | 294 | hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); |
3c8d758a | 295 | else |
0d373d60 MG |
296 | omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); |
297 | } | |
298 | } | |
299 | ||
300 | static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) | |
301 | { | |
302 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
303 | struct omap_sham_dev *dd = ctx->dd; | |
304 | int i; | |
305 | ||
306 | if (ctx->flags & BIT(FLAGS_HMAC)) { | |
307 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); | |
308 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
309 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
310 | u32 *opad = (u32 *)bctx->opad; | |
311 | ||
312 | for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { | |
313 | if (out) | |
314 | opad[i] = omap_sham_read(dd, | |
eaef7e3f | 315 | SHA_REG_ODIGEST(dd, i)); |
0d373d60 | 316 | else |
eaef7e3f | 317 | omap_sham_write(dd, SHA_REG_ODIGEST(dd, i), |
0d373d60 MG |
318 | opad[i]); |
319 | } | |
3c8d758a | 320 | } |
0d373d60 MG |
321 | |
322 | omap_sham_copy_hash_omap2(req, out); | |
3c8d758a DK |
323 | } |
324 | ||
325 | static void omap_sham_copy_ready_hash(struct ahash_request *req) | |
326 | { | |
327 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
328 | u32 *in = (u32 *)ctx->digest; | |
329 | u32 *hash = (u32 *)req->result; | |
0d373d60 | 330 | int i, d, big_endian = 0; |
3c8d758a DK |
331 | |
332 | if (!hash) | |
333 | return; | |
334 | ||
0d373d60 MG |
335 | switch (ctx->flags & FLAGS_MODE_MASK) { |
336 | case FLAGS_MODE_MD5: | |
337 | d = MD5_DIGEST_SIZE / sizeof(u32); | |
338 | break; | |
339 | case FLAGS_MODE_SHA1: | |
340 | /* OMAP2 SHA1 is big endian */ | |
341 | if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) | |
342 | big_endian = 1; | |
343 | d = SHA1_DIGEST_SIZE / sizeof(u32); | |
344 | break; | |
d20fb18b MG |
345 | case FLAGS_MODE_SHA224: |
346 | d = SHA224_DIGEST_SIZE / sizeof(u32); | |
347 | break; | |
348 | case FLAGS_MODE_SHA256: | |
349 | d = SHA256_DIGEST_SIZE / sizeof(u32); | |
350 | break; | |
eaef7e3f LV |
351 | case FLAGS_MODE_SHA384: |
352 | d = SHA384_DIGEST_SIZE / sizeof(u32); | |
353 | break; | |
354 | case FLAGS_MODE_SHA512: | |
355 | d = SHA512_DIGEST_SIZE / sizeof(u32); | |
356 | break; | |
0d373d60 MG |
357 | default: |
358 | d = 0; | |
359 | } | |
360 | ||
361 | if (big_endian) | |
362 | for (i = 0; i < d; i++) | |
3c8d758a | 363 | hash[i] = be32_to_cpu(in[i]); |
0d373d60 MG |
364 | else |
365 | for (i = 0; i < d; i++) | |
3c8d758a | 366 | hash[i] = le32_to_cpu(in[i]); |
8628e7c8 DK |
367 | } |
368 | ||
798eed5d | 369 | static int omap_sham_hw_init(struct omap_sham_dev *dd) |
8628e7c8 | 370 | { |
604c3103 PR |
371 | int err; |
372 | ||
373 | err = pm_runtime_get_sync(dd->dev); | |
374 | if (err < 0) { | |
375 | dev_err(dd->dev, "failed to get sync: %d\n", err); | |
376 | return err; | |
377 | } | |
8628e7c8 | 378 | |
a929cbee | 379 | if (!test_bit(FLAGS_INIT, &dd->flags)) { |
a929cbee | 380 | set_bit(FLAGS_INIT, &dd->flags); |
798eed5d DK |
381 | dd->err = 0; |
382 | } | |
8628e7c8 | 383 | |
798eed5d DK |
384 | return 0; |
385 | } | |
386 | ||
0d373d60 | 387 | static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, |
798eed5d DK |
388 | int final, int dma) |
389 | { | |
390 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
391 | u32 val = length << 5, mask; | |
392 | ||
393 | if (likely(ctx->digcnt)) | |
0d373d60 | 394 | omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); |
8628e7c8 | 395 | |
0d373d60 | 396 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), |
8628e7c8 DK |
397 | SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), |
398 | SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); | |
399 | /* | |
400 | * Setting ALGO_CONST only for the first iteration | |
401 | * and CLOSE_HASH only for the last one. | |
402 | */ | |
0d373d60 | 403 | if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) |
8628e7c8 DK |
404 | val |= SHA_REG_CTRL_ALGO; |
405 | if (!ctx->digcnt) | |
406 | val |= SHA_REG_CTRL_ALGO_CONST; | |
407 | if (final) | |
408 | val |= SHA_REG_CTRL_CLOSE_HASH; | |
409 | ||
410 | mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | | |
411 | SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; | |
412 | ||
413 | omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); | |
8628e7c8 DK |
414 | } |
415 | ||
0d373d60 MG |
416 | static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) |
417 | { | |
418 | } | |
419 | ||
420 | static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) | |
421 | { | |
422 | return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); | |
423 | } | |
424 | ||
eaef7e3f LV |
425 | static int get_block_size(struct omap_sham_reqctx *ctx) |
426 | { | |
427 | int d; | |
428 | ||
429 | switch (ctx->flags & FLAGS_MODE_MASK) { | |
430 | case FLAGS_MODE_MD5: | |
431 | case FLAGS_MODE_SHA1: | |
432 | d = SHA1_BLOCK_SIZE; | |
433 | break; | |
434 | case FLAGS_MODE_SHA224: | |
435 | case FLAGS_MODE_SHA256: | |
436 | d = SHA256_BLOCK_SIZE; | |
437 | break; | |
438 | case FLAGS_MODE_SHA384: | |
439 | case FLAGS_MODE_SHA512: | |
440 | d = SHA512_BLOCK_SIZE; | |
441 | break; | |
442 | default: | |
443 | d = 0; | |
444 | } | |
445 | ||
446 | return d; | |
447 | } | |
448 | ||
0d373d60 MG |
449 | static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, |
450 | u32 *value, int count) | |
451 | { | |
452 | for (; count--; value++, offset += 4) | |
453 | omap_sham_write(dd, offset, *value); | |
454 | } | |
455 | ||
456 | static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, | |
457 | int final, int dma) | |
458 | { | |
459 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
460 | u32 val, mask; | |
461 | ||
462 | /* | |
463 | * Setting ALGO_CONST only for the first iteration and | |
464 | * CLOSE_HASH only for the last one. Note that flags mode bits | |
465 | * correspond to algorithm encoding in mode register. | |
466 | */ | |
eaef7e3f | 467 | val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); |
0d373d60 MG |
468 | if (!ctx->digcnt) { |
469 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); | |
470 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
471 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
eaef7e3f | 472 | int bs, nr_dr; |
0d373d60 MG |
473 | |
474 | val |= SHA_REG_MODE_ALGO_CONSTANT; | |
475 | ||
476 | if (ctx->flags & BIT(FLAGS_HMAC)) { | |
eaef7e3f LV |
477 | bs = get_block_size(ctx); |
478 | nr_dr = bs / (2 * sizeof(u32)); | |
0d373d60 | 479 | val |= SHA_REG_MODE_HMAC_KEY_PROC; |
eaef7e3f LV |
480 | omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0), |
481 | (u32 *)bctx->ipad, nr_dr); | |
482 | omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0), | |
483 | (u32 *)bctx->ipad + nr_dr, nr_dr); | |
484 | ctx->digcnt += bs; | |
0d373d60 MG |
485 | } |
486 | } | |
487 | ||
488 | if (final) { | |
489 | val |= SHA_REG_MODE_CLOSE_HASH; | |
490 | ||
491 | if (ctx->flags & BIT(FLAGS_HMAC)) | |
492 | val |= SHA_REG_MODE_HMAC_OUTER_HASH; | |
493 | } | |
494 | ||
495 | mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | | |
496 | SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | | |
497 | SHA_REG_MODE_HMAC_KEY_PROC; | |
498 | ||
499 | dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); | |
eaef7e3f | 500 | omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); |
0d373d60 MG |
501 | omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); |
502 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), | |
503 | SHA_REG_MASK_IT_EN | | |
504 | (dma ? SHA_REG_MASK_DMA_EN : 0), | |
505 | SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); | |
506 | } | |
507 | ||
508 | static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) | |
509 | { | |
eaef7e3f | 510 | omap_sham_write(dd, SHA_REG_LENGTH(dd), length); |
0d373d60 MG |
511 | } |
512 | ||
513 | static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) | |
514 | { | |
515 | return omap_sham_wait(dd, SHA_REG_IRQSTATUS, | |
516 | SHA_REG_IRQSTATUS_INPUT_RDY); | |
517 | } | |
518 | ||
8628e7c8 DK |
519 | static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf, |
520 | size_t length, int final) | |
521 | { | |
522 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
b8411ccd | 523 | int count, len32, bs32, offset = 0; |
8628e7c8 DK |
524 | const u32 *buffer = (const u32 *)buf; |
525 | ||
526 | dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n", | |
527 | ctx->digcnt, length, final); | |
528 | ||
0d373d60 MG |
529 | dd->pdata->write_ctrl(dd, length, final, 0); |
530 | dd->pdata->trigger(dd, length); | |
8628e7c8 | 531 | |
3e133c8b DK |
532 | /* should be non-zero before next lines to disable clocks later */ |
533 | ctx->digcnt += length; | |
534 | ||
8628e7c8 | 535 | if (final) |
ed3ea9a8 | 536 | set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ |
8628e7c8 | 537 | |
6c63db82 DK |
538 | set_bit(FLAGS_CPU, &dd->flags); |
539 | ||
8628e7c8 | 540 | len32 = DIV_ROUND_UP(length, sizeof(u32)); |
b8411ccd LV |
541 | bs32 = get_block_size(ctx) / sizeof(u32); |
542 | ||
543 | while (len32) { | |
544 | if (dd->pdata->poll_irq(dd)) | |
545 | return -ETIMEDOUT; | |
8628e7c8 | 546 | |
b8411ccd LV |
547 | for (count = 0; count < min(len32, bs32); count++, offset++) |
548 | omap_sham_write(dd, SHA_REG_DIN(dd, count), | |
549 | buffer[offset]); | |
550 | len32 -= min(len32, bs32); | |
551 | } | |
8628e7c8 DK |
552 | |
553 | return -EINPROGRESS; | |
554 | } | |
555 | ||
dfd061d5 MG |
556 | static void omap_sham_dma_callback(void *param) |
557 | { | |
558 | struct omap_sham_dev *dd = param; | |
559 | ||
560 | set_bit(FLAGS_DMA_READY, &dd->flags); | |
561 | tasklet_schedule(&dd->done_task); | |
562 | } | |
dfd061d5 | 563 | |
8628e7c8 | 564 | static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr, |
dfd061d5 | 565 | size_t length, int final, int is_sg) |
8628e7c8 DK |
566 | { |
567 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
dfd061d5 MG |
568 | struct dma_async_tx_descriptor *tx; |
569 | struct dma_slave_config cfg; | |
f5e46260 | 570 | int len32, ret, dma_min = get_block_size(ctx); |
8628e7c8 DK |
571 | |
572 | dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n", | |
573 | ctx->digcnt, length, final); | |
8628e7c8 | 574 | |
dfd061d5 MG |
575 | memset(&cfg, 0, sizeof(cfg)); |
576 | ||
0d373d60 | 577 | cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); |
dfd061d5 | 578 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
f5e46260 | 579 | cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES; |
dfd061d5 MG |
580 | |
581 | ret = dmaengine_slave_config(dd->dma_lch, &cfg); | |
582 | if (ret) { | |
583 | pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); | |
584 | return ret; | |
585 | } | |
586 | ||
f5e46260 | 587 | len32 = DIV_ROUND_UP(length, dma_min) * dma_min; |
dfd061d5 MG |
588 | |
589 | if (is_sg) { | |
590 | /* | |
591 | * The SG entry passed in may not have the 'length' member | |
8addf571 | 592 | * set correctly so use a local SG entry (sgl_tmp) with the |
dfd061d5 MG |
593 | * proper value for 'length' instead. If this is not done, |
594 | * the dmaengine may try to DMA the incorrect amount of data. | |
595 | */ | |
8addf571 TK |
596 | sg_init_table(&ctx->sgl_tmp, 1); |
597 | sg_assign_page(&ctx->sgl_tmp, sg_page(ctx->sg)); | |
598 | ctx->sgl_tmp.offset = ctx->sg->offset; | |
599 | sg_dma_len(&ctx->sgl_tmp) = len32; | |
600 | sg_dma_address(&ctx->sgl_tmp) = sg_dma_address(ctx->sg); | |
601 | ||
602 | tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl_tmp, 1, | |
603 | DMA_MEM_TO_DEV, | |
604 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
dfd061d5 MG |
605 | } else { |
606 | tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32, | |
607 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
608 | } | |
8628e7c8 | 609 | |
dfd061d5 MG |
610 | if (!tx) { |
611 | dev_err(dd->dev, "prep_slave_sg/single() failed\n"); | |
612 | return -EINVAL; | |
613 | } | |
8628e7c8 | 614 | |
dfd061d5 MG |
615 | tx->callback = omap_sham_dma_callback; |
616 | tx->callback_param = dd; | |
8628e7c8 | 617 | |
0d373d60 | 618 | dd->pdata->write_ctrl(dd, length, final, 1); |
8628e7c8 DK |
619 | |
620 | ctx->digcnt += length; | |
621 | ||
622 | if (final) | |
ed3ea9a8 | 623 | set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ |
8628e7c8 | 624 | |
a929cbee | 625 | set_bit(FLAGS_DMA_ACTIVE, &dd->flags); |
8628e7c8 | 626 | |
dfd061d5 MG |
627 | dmaengine_submit(tx); |
628 | dma_async_issue_pending(dd->dma_lch); | |
8628e7c8 | 629 | |
0d373d60 | 630 | dd->pdata->trigger(dd, length); |
8628e7c8 DK |
631 | |
632 | return -EINPROGRESS; | |
633 | } | |
634 | ||
f19de1bc TK |
635 | static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx, |
636 | struct scatterlist *sg, int bs, int new_len) | |
637 | { | |
638 | int n = sg_nents(sg); | |
639 | struct scatterlist *tmp; | |
640 | int offset = ctx->offset; | |
641 | ||
642 | if (ctx->bufcnt) | |
643 | n++; | |
644 | ||
645 | ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL); | |
646 | if (!ctx->sg) | |
647 | return -ENOMEM; | |
648 | ||
649 | sg_init_table(ctx->sg, n); | |
650 | ||
651 | tmp = ctx->sg; | |
652 | ||
653 | ctx->sg_len = 0; | |
654 | ||
655 | if (ctx->bufcnt) { | |
656 | sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); | |
657 | tmp = sg_next(tmp); | |
658 | ctx->sg_len++; | |
659 | } | |
660 | ||
661 | while (sg && new_len) { | |
662 | int len = sg->length - offset; | |
663 | ||
664 | if (offset) { | |
665 | offset -= sg->length; | |
666 | if (offset < 0) | |
667 | offset = 0; | |
668 | } | |
669 | ||
670 | if (new_len < len) | |
671 | len = new_len; | |
672 | ||
673 | if (len > 0) { | |
674 | new_len -= len; | |
675 | sg_set_page(tmp, sg_page(sg), len, sg->offset); | |
676 | if (new_len <= 0) | |
677 | sg_mark_end(tmp); | |
678 | tmp = sg_next(tmp); | |
679 | ctx->sg_len++; | |
680 | } | |
681 | ||
682 | sg = sg_next(sg); | |
683 | } | |
684 | ||
685 | set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags); | |
686 | ||
687 | ctx->bufcnt = 0; | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
692 | static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx, | |
693 | struct scatterlist *sg, int bs, int new_len) | |
694 | { | |
695 | int pages; | |
696 | void *buf; | |
697 | int len; | |
698 | ||
699 | len = new_len + ctx->bufcnt; | |
700 | ||
701 | pages = get_order(ctx->total); | |
702 | ||
703 | buf = (void *)__get_free_pages(GFP_ATOMIC, pages); | |
704 | if (!buf) { | |
705 | pr_err("Couldn't allocate pages for unaligned cases.\n"); | |
706 | return -ENOMEM; | |
707 | } | |
708 | ||
709 | if (ctx->bufcnt) | |
710 | memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); | |
711 | ||
712 | scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset, | |
713 | ctx->total - ctx->bufcnt, 0); | |
714 | sg_init_table(ctx->sgl, 1); | |
715 | sg_set_buf(ctx->sgl, buf, len); | |
716 | ctx->sg = ctx->sgl; | |
717 | set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags); | |
718 | ctx->sg_len = 1; | |
719 | ctx->bufcnt = 0; | |
720 | ctx->offset = 0; | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
725 | static int omap_sham_align_sgs(struct scatterlist *sg, | |
726 | int nbytes, int bs, bool final, | |
727 | struct omap_sham_reqctx *rctx) | |
728 | { | |
729 | int n = 0; | |
730 | bool aligned = true; | |
731 | bool list_ok = true; | |
732 | struct scatterlist *sg_tmp = sg; | |
733 | int new_len; | |
734 | int offset = rctx->offset; | |
735 | ||
736 | if (!sg || !sg->length || !nbytes) | |
737 | return 0; | |
738 | ||
739 | new_len = nbytes; | |
740 | ||
741 | if (offset) | |
742 | list_ok = false; | |
743 | ||
744 | if (final) | |
745 | new_len = DIV_ROUND_UP(new_len, bs) * bs; | |
746 | else | |
747 | new_len = new_len / bs * bs; | |
748 | ||
749 | while (nbytes > 0 && sg_tmp) { | |
750 | n++; | |
751 | ||
752 | if (offset < sg_tmp->length) { | |
753 | if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) { | |
754 | aligned = false; | |
755 | break; | |
756 | } | |
757 | ||
758 | if (!IS_ALIGNED(sg_tmp->length - offset, bs)) { | |
759 | aligned = false; | |
760 | break; | |
761 | } | |
762 | } | |
763 | ||
764 | if (offset) { | |
765 | offset -= sg_tmp->length; | |
766 | if (offset < 0) { | |
767 | nbytes += offset; | |
768 | offset = 0; | |
769 | } | |
770 | } else { | |
771 | nbytes -= sg_tmp->length; | |
772 | } | |
773 | ||
774 | sg_tmp = sg_next(sg_tmp); | |
775 | ||
776 | if (nbytes < 0) { | |
777 | list_ok = false; | |
778 | break; | |
779 | } | |
780 | } | |
781 | ||
782 | if (!aligned) | |
783 | return omap_sham_copy_sgs(rctx, sg, bs, new_len); | |
784 | else if (!list_ok) | |
785 | return omap_sham_copy_sg_lists(rctx, sg, bs, new_len); | |
786 | ||
787 | rctx->sg_len = n; | |
788 | rctx->sg = sg; | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
793 | static int omap_sham_prepare_request(struct ahash_request *req, bool update) | |
794 | { | |
795 | struct omap_sham_reqctx *rctx = ahash_request_ctx(req); | |
796 | int bs; | |
797 | int ret; | |
798 | int nbytes; | |
799 | bool final = rctx->flags & BIT(FLAGS_FINUP); | |
800 | int xmit_len, hash_later; | |
801 | ||
802 | if (!req) | |
803 | return 0; | |
804 | ||
805 | bs = get_block_size(rctx); | |
806 | ||
807 | if (update) | |
808 | nbytes = req->nbytes; | |
809 | else | |
810 | nbytes = 0; | |
811 | ||
812 | rctx->total = nbytes + rctx->bufcnt; | |
813 | ||
814 | if (!rctx->total) | |
815 | return 0; | |
816 | ||
817 | if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) { | |
818 | int len = bs - rctx->bufcnt % bs; | |
819 | ||
820 | if (len > nbytes) | |
821 | len = nbytes; | |
822 | scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src, | |
823 | 0, len, 0); | |
824 | rctx->bufcnt += len; | |
825 | nbytes -= len; | |
826 | rctx->offset = len; | |
827 | } | |
828 | ||
829 | if (rctx->bufcnt) | |
830 | memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt); | |
831 | ||
832 | ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx); | |
833 | if (ret) | |
834 | return ret; | |
835 | ||
836 | xmit_len = rctx->total; | |
837 | ||
838 | if (!IS_ALIGNED(xmit_len, bs)) { | |
839 | if (final) | |
840 | xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs; | |
841 | else | |
842 | xmit_len = xmit_len / bs * bs; | |
843 | } | |
844 | ||
845 | hash_later = rctx->total - xmit_len; | |
846 | if (hash_later < 0) | |
847 | hash_later = 0; | |
848 | ||
849 | if (rctx->bufcnt && nbytes) { | |
850 | /* have data from previous operation and current */ | |
851 | sg_init_table(rctx->sgl, 2); | |
852 | sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt); | |
853 | ||
854 | sg_chain(rctx->sgl, 2, req->src); | |
855 | ||
856 | rctx->sg = rctx->sgl; | |
857 | ||
858 | rctx->sg_len++; | |
859 | } else if (rctx->bufcnt) { | |
860 | /* have buffered data only */ | |
861 | sg_init_table(rctx->sgl, 1); | |
862 | sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len); | |
863 | ||
864 | rctx->sg = rctx->sgl; | |
865 | ||
866 | rctx->sg_len = 1; | |
867 | } | |
868 | ||
869 | if (hash_later) { | |
870 | if (req->nbytes) { | |
871 | scatterwalk_map_and_copy(rctx->buffer, req->src, | |
872 | req->nbytes - hash_later, | |
873 | hash_later, 0); | |
874 | } else { | |
875 | memcpy(rctx->buffer, rctx->buffer + xmit_len, | |
876 | hash_later); | |
877 | } | |
878 | rctx->bufcnt = hash_later; | |
879 | } else { | |
880 | rctx->bufcnt = 0; | |
881 | } | |
882 | ||
883 | if (!final) | |
884 | rctx->total = xmit_len; | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
8628e7c8 DK |
889 | static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx, |
890 | const u8 *data, size_t length) | |
891 | { | |
892 | size_t count = min(length, ctx->buflen - ctx->bufcnt); | |
893 | ||
894 | count = min(count, ctx->total); | |
895 | if (count <= 0) | |
896 | return 0; | |
897 | memcpy(ctx->buffer + ctx->bufcnt, data, count); | |
898 | ctx->bufcnt += count; | |
899 | ||
900 | return count; | |
901 | } | |
902 | ||
903 | static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx) | |
904 | { | |
905 | size_t count; | |
26a05489 | 906 | const u8 *vaddr; |
8628e7c8 DK |
907 | |
908 | while (ctx->sg) { | |
26a05489 | 909 | vaddr = kmap_atomic(sg_page(ctx->sg)); |
13cf394c | 910 | vaddr += ctx->sg->offset; |
26a05489 | 911 | |
8628e7c8 | 912 | count = omap_sham_append_buffer(ctx, |
26a05489 | 913 | vaddr + ctx->offset, |
8628e7c8 | 914 | ctx->sg->length - ctx->offset); |
26a05489 JF |
915 | |
916 | kunmap_atomic((void *)vaddr); | |
917 | ||
8628e7c8 DK |
918 | if (!count) |
919 | break; | |
920 | ctx->offset += count; | |
921 | ctx->total -= count; | |
922 | if (ctx->offset == ctx->sg->length) { | |
923 | ctx->sg = sg_next(ctx->sg); | |
924 | if (ctx->sg) | |
925 | ctx->offset = 0; | |
926 | else | |
927 | ctx->total = 0; | |
928 | } | |
929 | } | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
798eed5d DK |
934 | static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd, |
935 | struct omap_sham_reqctx *ctx, | |
936 | size_t length, int final) | |
937 | { | |
dfd061d5 MG |
938 | int ret; |
939 | ||
798eed5d DK |
940 | ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen, |
941 | DMA_TO_DEVICE); | |
942 | if (dma_mapping_error(dd->dev, ctx->dma_addr)) { | |
943 | dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen); | |
944 | return -EINVAL; | |
945 | } | |
946 | ||
ea1fd224 | 947 | ctx->flags &= ~BIT(FLAGS_SG); |
887c883e | 948 | |
dfd061d5 | 949 | ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0); |
0d373d60 | 950 | if (ret != -EINPROGRESS) |
dfd061d5 MG |
951 | dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen, |
952 | DMA_TO_DEVICE); | |
953 | ||
954 | return ret; | |
798eed5d DK |
955 | } |
956 | ||
8628e7c8 DK |
957 | static int omap_sham_update_dma_slow(struct omap_sham_dev *dd) |
958 | { | |
959 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
960 | unsigned int final; | |
961 | size_t count; | |
962 | ||
8628e7c8 DK |
963 | omap_sham_append_sg(ctx); |
964 | ||
ea1fd224 | 965 | final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; |
8628e7c8 DK |
966 | |
967 | dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n", | |
968 | ctx->bufcnt, ctx->digcnt, final); | |
969 | ||
970 | if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) { | |
971 | count = ctx->bufcnt; | |
972 | ctx->bufcnt = 0; | |
798eed5d | 973 | return omap_sham_xmit_dma_map(dd, ctx, count, final); |
8628e7c8 DK |
974 | } |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
887c883e DK |
979 | /* Start address alignment */ |
980 | #define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32))) | |
981 | /* SHA1 block size alignment */ | |
eaef7e3f | 982 | #define SG_SA(sg, bs) (IS_ALIGNED(sg->length, bs)) |
887c883e DK |
983 | |
984 | static int omap_sham_update_dma_start(struct omap_sham_dev *dd) | |
8628e7c8 DK |
985 | { |
986 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
887c883e DK |
987 | unsigned int length, final, tail; |
988 | struct scatterlist *sg; | |
eaef7e3f | 989 | int ret, bs; |
887c883e DK |
990 | |
991 | if (!ctx->total) | |
992 | return 0; | |
993 | ||
994 | if (ctx->bufcnt || ctx->offset) | |
995 | return omap_sham_update_dma_slow(dd); | |
996 | ||
dfd061d5 MG |
997 | /* |
998 | * Don't use the sg interface when the transfer size is less | |
999 | * than the number of elements in a DMA frame. Otherwise, | |
1000 | * the dmaengine infrastructure will calculate that it needs | |
1001 | * to transfer 0 frames which ultimately fails. | |
1002 | */ | |
f5e46260 | 1003 | if (ctx->total < get_block_size(ctx)) |
dfd061d5 | 1004 | return omap_sham_update_dma_slow(dd); |
dfd061d5 | 1005 | |
887c883e DK |
1006 | dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n", |
1007 | ctx->digcnt, ctx->bufcnt, ctx->total); | |
1008 | ||
1009 | sg = ctx->sg; | |
eaef7e3f | 1010 | bs = get_block_size(ctx); |
8628e7c8 | 1011 | |
887c883e DK |
1012 | if (!SG_AA(sg)) |
1013 | return omap_sham_update_dma_slow(dd); | |
8628e7c8 | 1014 | |
eaef7e3f LV |
1015 | if (!sg_is_last(sg) && !SG_SA(sg, bs)) |
1016 | /* size is not BLOCK_SIZE aligned */ | |
887c883e DK |
1017 | return omap_sham_update_dma_slow(dd); |
1018 | ||
1019 | length = min(ctx->total, sg->length); | |
1020 | ||
1021 | if (sg_is_last(sg)) { | |
ea1fd224 | 1022 | if (!(ctx->flags & BIT(FLAGS_FINUP))) { |
eaef7e3f LV |
1023 | /* not last sg must be BLOCK_SIZE aligned */ |
1024 | tail = length & (bs - 1); | |
887c883e DK |
1025 | /* without finup() we need one block to close hash */ |
1026 | if (!tail) | |
eaef7e3f | 1027 | tail = bs; |
887c883e DK |
1028 | length -= tail; |
1029 | } | |
1030 | } | |
8628e7c8 DK |
1031 | |
1032 | if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) { | |
1033 | dev_err(dd->dev, "dma_map_sg error\n"); | |
1034 | return -EINVAL; | |
1035 | } | |
1036 | ||
ea1fd224 | 1037 | ctx->flags |= BIT(FLAGS_SG); |
887c883e | 1038 | |
8628e7c8 | 1039 | ctx->total -= length; |
887c883e DK |
1040 | ctx->offset = length; /* offset where to start slow */ |
1041 | ||
ea1fd224 | 1042 | final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; |
8628e7c8 | 1043 | |
dfd061d5 | 1044 | ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1); |
0d373d60 | 1045 | if (ret != -EINPROGRESS) |
dfd061d5 MG |
1046 | dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); |
1047 | ||
1048 | return ret; | |
8628e7c8 DK |
1049 | } |
1050 | ||
1051 | static int omap_sham_update_cpu(struct omap_sham_dev *dd) | |
1052 | { | |
1053 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
b8411ccd LV |
1054 | int bufcnt, final; |
1055 | ||
1056 | if (!ctx->total) | |
1057 | return 0; | |
8628e7c8 DK |
1058 | |
1059 | omap_sham_append_sg(ctx); | |
b8411ccd LV |
1060 | |
1061 | final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; | |
1062 | ||
1063 | dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n", | |
1064 | ctx->bufcnt, ctx->digcnt, final); | |
1065 | ||
acef7b0f LV |
1066 | if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) { |
1067 | bufcnt = ctx->bufcnt; | |
1068 | ctx->bufcnt = 0; | |
1069 | return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final); | |
1070 | } | |
8628e7c8 | 1071 | |
acef7b0f | 1072 | return 0; |
8628e7c8 DK |
1073 | } |
1074 | ||
1075 | static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) | |
1076 | { | |
1077 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
1078 | ||
dfd061d5 | 1079 | |
ea1fd224 | 1080 | if (ctx->flags & BIT(FLAGS_SG)) { |
8628e7c8 | 1081 | dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); |
887c883e DK |
1082 | if (ctx->sg->length == ctx->offset) { |
1083 | ctx->sg = sg_next(ctx->sg); | |
1084 | if (ctx->sg) | |
1085 | ctx->offset = 0; | |
1086 | } | |
1087 | } else { | |
798eed5d DK |
1088 | dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen, |
1089 | DMA_TO_DEVICE); | |
887c883e | 1090 | } |
8628e7c8 DK |
1091 | |
1092 | return 0; | |
1093 | } | |
1094 | ||
8628e7c8 DK |
1095 | static int omap_sham_init(struct ahash_request *req) |
1096 | { | |
1097 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
1098 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
1099 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1100 | struct omap_sham_dev *dd = NULL, *tmp; | |
eaef7e3f | 1101 | int bs = 0; |
8628e7c8 DK |
1102 | |
1103 | spin_lock_bh(&sham.lock); | |
1104 | if (!tctx->dd) { | |
1105 | list_for_each_entry(tmp, &sham.dev_list, list) { | |
1106 | dd = tmp; | |
1107 | break; | |
1108 | } | |
1109 | tctx->dd = dd; | |
1110 | } else { | |
1111 | dd = tctx->dd; | |
1112 | } | |
1113 | spin_unlock_bh(&sham.lock); | |
1114 | ||
1115 | ctx->dd = dd; | |
1116 | ||
1117 | ctx->flags = 0; | |
1118 | ||
8628e7c8 DK |
1119 | dev_dbg(dd->dev, "init: digest size: %d\n", |
1120 | crypto_ahash_digestsize(tfm)); | |
1121 | ||
0d373d60 MG |
1122 | switch (crypto_ahash_digestsize(tfm)) { |
1123 | case MD5_DIGEST_SIZE: | |
1124 | ctx->flags |= FLAGS_MODE_MD5; | |
eaef7e3f | 1125 | bs = SHA1_BLOCK_SIZE; |
0d373d60 MG |
1126 | break; |
1127 | case SHA1_DIGEST_SIZE: | |
1128 | ctx->flags |= FLAGS_MODE_SHA1; | |
eaef7e3f | 1129 | bs = SHA1_BLOCK_SIZE; |
0d373d60 | 1130 | break; |
d20fb18b MG |
1131 | case SHA224_DIGEST_SIZE: |
1132 | ctx->flags |= FLAGS_MODE_SHA224; | |
eaef7e3f | 1133 | bs = SHA224_BLOCK_SIZE; |
d20fb18b MG |
1134 | break; |
1135 | case SHA256_DIGEST_SIZE: | |
1136 | ctx->flags |= FLAGS_MODE_SHA256; | |
eaef7e3f LV |
1137 | bs = SHA256_BLOCK_SIZE; |
1138 | break; | |
1139 | case SHA384_DIGEST_SIZE: | |
1140 | ctx->flags |= FLAGS_MODE_SHA384; | |
1141 | bs = SHA384_BLOCK_SIZE; | |
1142 | break; | |
1143 | case SHA512_DIGEST_SIZE: | |
1144 | ctx->flags |= FLAGS_MODE_SHA512; | |
1145 | bs = SHA512_BLOCK_SIZE; | |
d20fb18b | 1146 | break; |
0d373d60 | 1147 | } |
8628e7c8 DK |
1148 | |
1149 | ctx->bufcnt = 0; | |
1150 | ctx->digcnt = 0; | |
798eed5d | 1151 | ctx->buflen = BUFLEN; |
8628e7c8 | 1152 | |
ea1fd224 | 1153 | if (tctx->flags & BIT(FLAGS_HMAC)) { |
0d373d60 MG |
1154 | if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { |
1155 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
1156 | ||
eaef7e3f LV |
1157 | memcpy(ctx->buffer, bctx->ipad, bs); |
1158 | ctx->bufcnt = bs; | |
0d373d60 | 1159 | } |
8628e7c8 | 1160 | |
ea1fd224 | 1161 | ctx->flags |= BIT(FLAGS_HMAC); |
8628e7c8 DK |
1162 | } |
1163 | ||
1164 | return 0; | |
1165 | ||
1166 | } | |
1167 | ||
1168 | static int omap_sham_update_req(struct omap_sham_dev *dd) | |
1169 | { | |
1170 | struct ahash_request *req = dd->req; | |
1171 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1172 | int err; | |
1173 | ||
1174 | dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n", | |
ea1fd224 | 1175 | ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0); |
8628e7c8 | 1176 | |
ea1fd224 | 1177 | if (ctx->flags & BIT(FLAGS_CPU)) |
8628e7c8 | 1178 | err = omap_sham_update_cpu(dd); |
8628e7c8 | 1179 | else |
887c883e | 1180 | err = omap_sham_update_dma_start(dd); |
8628e7c8 DK |
1181 | |
1182 | /* wait for dma completion before can take more data */ | |
1183 | dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt); | |
1184 | ||
1185 | return err; | |
1186 | } | |
1187 | ||
1188 | static int omap_sham_final_req(struct omap_sham_dev *dd) | |
1189 | { | |
1190 | struct ahash_request *req = dd->req; | |
1191 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1192 | int err = 0, use_dma = 1; | |
1193 | ||
b8411ccd LV |
1194 | if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode) |
1195 | /* | |
1196 | * faster to handle last block with cpu or | |
1197 | * use cpu when dma is not present. | |
1198 | */ | |
8628e7c8 DK |
1199 | use_dma = 0; |
1200 | ||
1201 | if (use_dma) | |
798eed5d | 1202 | err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1); |
8628e7c8 DK |
1203 | else |
1204 | err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1); | |
1205 | ||
1206 | ctx->bufcnt = 0; | |
1207 | ||
8628e7c8 DK |
1208 | dev_dbg(dd->dev, "final_req: err: %d\n", err); |
1209 | ||
1210 | return err; | |
1211 | } | |
1212 | ||
bf362759 | 1213 | static int omap_sham_finish_hmac(struct ahash_request *req) |
8628e7c8 DK |
1214 | { |
1215 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1216 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
1217 | int bs = crypto_shash_blocksize(bctx->shash); | |
1218 | int ds = crypto_shash_digestsize(bctx->shash); | |
7bc53c3f | 1219 | SHASH_DESC_ON_STACK(shash, bctx->shash); |
8628e7c8 | 1220 | |
7bc53c3f BW |
1221 | shash->tfm = bctx->shash; |
1222 | shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */ | |
8628e7c8 | 1223 | |
7bc53c3f BW |
1224 | return crypto_shash_init(shash) ?: |
1225 | crypto_shash_update(shash, bctx->opad, bs) ?: | |
1226 | crypto_shash_finup(shash, req->result, ds, req->result); | |
bf362759 DK |
1227 | } |
1228 | ||
1229 | static int omap_sham_finish(struct ahash_request *req) | |
1230 | { | |
1231 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1232 | struct omap_sham_dev *dd = ctx->dd; | |
1233 | int err = 0; | |
1234 | ||
1235 | if (ctx->digcnt) { | |
1236 | omap_sham_copy_ready_hash(req); | |
0d373d60 MG |
1237 | if ((ctx->flags & BIT(FLAGS_HMAC)) && |
1238 | !test_bit(FLAGS_AUTO_XOR, &dd->flags)) | |
bf362759 DK |
1239 | err = omap_sham_finish_hmac(req); |
1240 | } | |
1241 | ||
1242 | dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt); | |
1243 | ||
1244 | return err; | |
8628e7c8 DK |
1245 | } |
1246 | ||
1247 | static void omap_sham_finish_req(struct ahash_request *req, int err) | |
1248 | { | |
1249 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
798eed5d | 1250 | struct omap_sham_dev *dd = ctx->dd; |
8628e7c8 DK |
1251 | |
1252 | if (!err) { | |
0d373d60 | 1253 | dd->pdata->copy_hash(req, 1); |
ed3ea9a8 | 1254 | if (test_bit(FLAGS_FINAL, &dd->flags)) |
bf362759 | 1255 | err = omap_sham_finish(req); |
3e133c8b | 1256 | } else { |
ea1fd224 | 1257 | ctx->flags |= BIT(FLAGS_ERROR); |
8628e7c8 DK |
1258 | } |
1259 | ||
0efd4d8a DK |
1260 | /* atomic operation is not needed here */ |
1261 | dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | | |
1262 | BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); | |
b359f034 | 1263 | |
e93f767b TK |
1264 | pm_runtime_mark_last_busy(dd->dev); |
1265 | pm_runtime_put_autosuspend(dd->dev); | |
8628e7c8 DK |
1266 | |
1267 | if (req->base.complete) | |
1268 | req->base.complete(&req->base, err); | |
1269 | } | |
1270 | ||
a5d87237 DK |
1271 | static int omap_sham_handle_queue(struct omap_sham_dev *dd, |
1272 | struct ahash_request *req) | |
8628e7c8 | 1273 | { |
6c39d116 | 1274 | struct crypto_async_request *async_req, *backlog; |
8628e7c8 | 1275 | struct omap_sham_reqctx *ctx; |
8628e7c8 | 1276 | unsigned long flags; |
a5d87237 | 1277 | int err = 0, ret = 0; |
8628e7c8 | 1278 | |
4e7813a0 | 1279 | retry: |
8628e7c8 | 1280 | spin_lock_irqsave(&dd->lock, flags); |
a5d87237 DK |
1281 | if (req) |
1282 | ret = ahash_enqueue_request(&dd->queue, req); | |
a929cbee | 1283 | if (test_bit(FLAGS_BUSY, &dd->flags)) { |
a5d87237 DK |
1284 | spin_unlock_irqrestore(&dd->lock, flags); |
1285 | return ret; | |
1286 | } | |
6c39d116 | 1287 | backlog = crypto_get_backlog(&dd->queue); |
8628e7c8 | 1288 | async_req = crypto_dequeue_request(&dd->queue); |
6c39d116 | 1289 | if (async_req) |
a929cbee | 1290 | set_bit(FLAGS_BUSY, &dd->flags); |
8628e7c8 DK |
1291 | spin_unlock_irqrestore(&dd->lock, flags); |
1292 | ||
1293 | if (!async_req) | |
a5d87237 | 1294 | return ret; |
8628e7c8 DK |
1295 | |
1296 | if (backlog) | |
1297 | backlog->complete(backlog, -EINPROGRESS); | |
1298 | ||
1299 | req = ahash_request_cast(async_req); | |
8628e7c8 | 1300 | dd->req = req; |
8628e7c8 DK |
1301 | ctx = ahash_request_ctx(req); |
1302 | ||
f19de1bc TK |
1303 | err = omap_sham_prepare_request(NULL, ctx->op == OP_UPDATE); |
1304 | if (err) | |
1305 | goto err1; | |
1306 | ||
8628e7c8 DK |
1307 | dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", |
1308 | ctx->op, req->nbytes); | |
1309 | ||
798eed5d DK |
1310 | err = omap_sham_hw_init(dd); |
1311 | if (err) | |
1312 | goto err1; | |
1313 | ||
798eed5d | 1314 | if (ctx->digcnt) |
8628e7c8 | 1315 | /* request has changed - restore hash */ |
0d373d60 | 1316 | dd->pdata->copy_hash(req, 0); |
8628e7c8 DK |
1317 | |
1318 | if (ctx->op == OP_UPDATE) { | |
1319 | err = omap_sham_update_req(dd); | |
ea1fd224 | 1320 | if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP))) |
8628e7c8 DK |
1321 | /* no final() after finup() */ |
1322 | err = omap_sham_final_req(dd); | |
1323 | } else if (ctx->op == OP_FINAL) { | |
1324 | err = omap_sham_final_req(dd); | |
1325 | } | |
798eed5d | 1326 | err1: |
4e7813a0 TK |
1327 | dev_dbg(dd->dev, "exit, err: %d\n", err); |
1328 | ||
1329 | if (err != -EINPROGRESS) { | |
8628e7c8 DK |
1330 | /* done_task will not finish it, so do it here */ |
1331 | omap_sham_finish_req(req, err); | |
4e7813a0 | 1332 | req = NULL; |
8628e7c8 | 1333 | |
4e7813a0 TK |
1334 | /* |
1335 | * Execute next request immediately if there is anything | |
1336 | * in queue. | |
1337 | */ | |
1338 | goto retry; | |
1339 | } | |
8628e7c8 | 1340 | |
a5d87237 | 1341 | return ret; |
8628e7c8 DK |
1342 | } |
1343 | ||
1344 | static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) | |
1345 | { | |
1346 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1347 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1348 | struct omap_sham_dev *dd = tctx->dd; | |
8628e7c8 DK |
1349 | |
1350 | ctx->op = op; | |
1351 | ||
a5d87237 | 1352 | return omap_sham_handle_queue(dd, req); |
8628e7c8 DK |
1353 | } |
1354 | ||
1355 | static int omap_sham_update(struct ahash_request *req) | |
1356 | { | |
1357 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
b8411ccd | 1358 | struct omap_sham_dev *dd = ctx->dd; |
eaef7e3f | 1359 | int bs = get_block_size(ctx); |
8628e7c8 DK |
1360 | |
1361 | if (!req->nbytes) | |
1362 | return 0; | |
1363 | ||
1364 | ctx->total = req->nbytes; | |
1365 | ctx->sg = req->src; | |
1366 | ctx->offset = 0; | |
1367 | ||
ea1fd224 | 1368 | if (ctx->flags & BIT(FLAGS_FINUP)) { |
85e0687f | 1369 | if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 240) { |
8628e7c8 DK |
1370 | /* |
1371 | * OMAP HW accel works only with buffers >= 9 | |
1372 | * will switch to bypass in final() | |
1373 | * final has the same request and data | |
1374 | */ | |
1375 | omap_sham_append_sg(ctx); | |
1376 | return 0; | |
b8411ccd LV |
1377 | } else if ((ctx->bufcnt + ctx->total <= bs) || |
1378 | dd->polling_mode) { | |
887c883e | 1379 | /* |
b8411ccd LV |
1380 | * faster to use CPU for short transfers or |
1381 | * use cpu when dma is not present. | |
1382 | */ | |
ea1fd224 | 1383 | ctx->flags |= BIT(FLAGS_CPU); |
8628e7c8 | 1384 | } |
887c883e | 1385 | } else if (ctx->bufcnt + ctx->total < ctx->buflen) { |
8628e7c8 DK |
1386 | omap_sham_append_sg(ctx); |
1387 | return 0; | |
1388 | } | |
1389 | ||
acef7b0f LV |
1390 | if (dd->polling_mode) |
1391 | ctx->flags |= BIT(FLAGS_CPU); | |
1392 | ||
8628e7c8 DK |
1393 | return omap_sham_enqueue(req, OP_UPDATE); |
1394 | } | |
1395 | ||
7bc53c3f | 1396 | static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags, |
8628e7c8 DK |
1397 | const u8 *data, unsigned int len, u8 *out) |
1398 | { | |
7bc53c3f | 1399 | SHASH_DESC_ON_STACK(shash, tfm); |
8628e7c8 | 1400 | |
7bc53c3f BW |
1401 | shash->tfm = tfm; |
1402 | shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP; | |
8628e7c8 | 1403 | |
7bc53c3f | 1404 | return crypto_shash_digest(shash, data, len, out); |
8628e7c8 DK |
1405 | } |
1406 | ||
1407 | static int omap_sham_final_shash(struct ahash_request *req) | |
1408 | { | |
1409 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1410 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
cb8d5c83 TK |
1411 | int offset = 0; |
1412 | ||
1413 | /* | |
1414 | * If we are running HMAC on limited hardware support, skip | |
1415 | * the ipad in the beginning of the buffer if we are going for | |
1416 | * software fallback algorithm. | |
1417 | */ | |
1418 | if (test_bit(FLAGS_HMAC, &ctx->flags) && | |
1419 | !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags)) | |
1420 | offset = get_block_size(ctx); | |
8628e7c8 DK |
1421 | |
1422 | return omap_sham_shash_digest(tctx->fallback, req->base.flags, | |
cb8d5c83 TK |
1423 | ctx->buffer + offset, |
1424 | ctx->bufcnt - offset, req->result); | |
8628e7c8 DK |
1425 | } |
1426 | ||
1427 | static int omap_sham_final(struct ahash_request *req) | |
1428 | { | |
1429 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
8628e7c8 | 1430 | |
ea1fd224 | 1431 | ctx->flags |= BIT(FLAGS_FINUP); |
8628e7c8 | 1432 | |
ea1fd224 | 1433 | if (ctx->flags & BIT(FLAGS_ERROR)) |
bf362759 | 1434 | return 0; /* uncompleted hash is not needed */ |
8628e7c8 | 1435 | |
85e0687f BL |
1436 | /* |
1437 | * OMAP HW accel works only with buffers >= 9. | |
1438 | * HMAC is always >= 9 because ipad == block size. | |
2c5bd1ef TK |
1439 | * If buffersize is less than DMA_THRESHOLD, we use fallback |
1440 | * SW encoding, as using DMA + HW in this case doesn't provide | |
1441 | * any benefit. | |
85e0687f | 1442 | */ |
2c5bd1ef | 1443 | if (!ctx->digcnt && ctx->bufcnt < OMAP_SHA_DMA_THRESHOLD) |
bf362759 DK |
1444 | return omap_sham_final_shash(req); |
1445 | else if (ctx->bufcnt) | |
1446 | return omap_sham_enqueue(req, OP_FINAL); | |
8628e7c8 | 1447 | |
bf362759 DK |
1448 | /* copy ready hash (+ finalize hmac) */ |
1449 | return omap_sham_finish(req); | |
8628e7c8 DK |
1450 | } |
1451 | ||
1452 | static int omap_sham_finup(struct ahash_request *req) | |
1453 | { | |
1454 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1455 | int err1, err2; | |
1456 | ||
ea1fd224 | 1457 | ctx->flags |= BIT(FLAGS_FINUP); |
8628e7c8 DK |
1458 | |
1459 | err1 = omap_sham_update(req); | |
455e3389 | 1460 | if (err1 == -EINPROGRESS || err1 == -EBUSY) |
8628e7c8 DK |
1461 | return err1; |
1462 | /* | |
1463 | * final() has to be always called to cleanup resources | |
1464 | * even if udpate() failed, except EINPROGRESS | |
1465 | */ | |
1466 | err2 = omap_sham_final(req); | |
1467 | ||
1468 | return err1 ?: err2; | |
1469 | } | |
1470 | ||
1471 | static int omap_sham_digest(struct ahash_request *req) | |
1472 | { | |
1473 | return omap_sham_init(req) ?: omap_sham_finup(req); | |
1474 | } | |
1475 | ||
1476 | static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, | |
1477 | unsigned int keylen) | |
1478 | { | |
1479 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
1480 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
1481 | int bs = crypto_shash_blocksize(bctx->shash); | |
1482 | int ds = crypto_shash_digestsize(bctx->shash); | |
0d373d60 | 1483 | struct omap_sham_dev *dd = NULL, *tmp; |
8628e7c8 | 1484 | int err, i; |
0d373d60 MG |
1485 | |
1486 | spin_lock_bh(&sham.lock); | |
1487 | if (!tctx->dd) { | |
1488 | list_for_each_entry(tmp, &sham.dev_list, list) { | |
1489 | dd = tmp; | |
1490 | break; | |
1491 | } | |
1492 | tctx->dd = dd; | |
1493 | } else { | |
1494 | dd = tctx->dd; | |
1495 | } | |
1496 | spin_unlock_bh(&sham.lock); | |
1497 | ||
8628e7c8 DK |
1498 | err = crypto_shash_setkey(tctx->fallback, key, keylen); |
1499 | if (err) | |
1500 | return err; | |
1501 | ||
1502 | if (keylen > bs) { | |
1503 | err = omap_sham_shash_digest(bctx->shash, | |
1504 | crypto_shash_get_flags(bctx->shash), | |
1505 | key, keylen, bctx->ipad); | |
1506 | if (err) | |
1507 | return err; | |
1508 | keylen = ds; | |
1509 | } else { | |
1510 | memcpy(bctx->ipad, key, keylen); | |
1511 | } | |
1512 | ||
1513 | memset(bctx->ipad + keylen, 0, bs - keylen); | |
8628e7c8 | 1514 | |
0d373d60 MG |
1515 | if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { |
1516 | memcpy(bctx->opad, bctx->ipad, bs); | |
1517 | ||
1518 | for (i = 0; i < bs; i++) { | |
1519 | bctx->ipad[i] ^= 0x36; | |
1520 | bctx->opad[i] ^= 0x5c; | |
1521 | } | |
8628e7c8 DK |
1522 | } |
1523 | ||
1524 | return err; | |
1525 | } | |
1526 | ||
1527 | static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) | |
1528 | { | |
1529 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); | |
1530 | const char *alg_name = crypto_tfm_alg_name(tfm); | |
1531 | ||
1532 | /* Allocate a fallback and abort if it failed. */ | |
1533 | tctx->fallback = crypto_alloc_shash(alg_name, 0, | |
1534 | CRYPTO_ALG_NEED_FALLBACK); | |
1535 | if (IS_ERR(tctx->fallback)) { | |
1536 | pr_err("omap-sham: fallback driver '%s' " | |
1537 | "could not be loaded.\n", alg_name); | |
1538 | return PTR_ERR(tctx->fallback); | |
1539 | } | |
1540 | ||
1541 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
798eed5d | 1542 | sizeof(struct omap_sham_reqctx) + BUFLEN); |
8628e7c8 DK |
1543 | |
1544 | if (alg_base) { | |
1545 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
ea1fd224 | 1546 | tctx->flags |= BIT(FLAGS_HMAC); |
8628e7c8 DK |
1547 | bctx->shash = crypto_alloc_shash(alg_base, 0, |
1548 | CRYPTO_ALG_NEED_FALLBACK); | |
1549 | if (IS_ERR(bctx->shash)) { | |
1550 | pr_err("omap-sham: base driver '%s' " | |
1551 | "could not be loaded.\n", alg_base); | |
1552 | crypto_free_shash(tctx->fallback); | |
1553 | return PTR_ERR(bctx->shash); | |
1554 | } | |
1555 | ||
1556 | } | |
1557 | ||
1558 | return 0; | |
1559 | } | |
1560 | ||
1561 | static int omap_sham_cra_init(struct crypto_tfm *tfm) | |
1562 | { | |
1563 | return omap_sham_cra_init_alg(tfm, NULL); | |
1564 | } | |
1565 | ||
1566 | static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) | |
1567 | { | |
1568 | return omap_sham_cra_init_alg(tfm, "sha1"); | |
1569 | } | |
1570 | ||
d20fb18b MG |
1571 | static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm) |
1572 | { | |
1573 | return omap_sham_cra_init_alg(tfm, "sha224"); | |
1574 | } | |
1575 | ||
1576 | static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm) | |
1577 | { | |
1578 | return omap_sham_cra_init_alg(tfm, "sha256"); | |
1579 | } | |
1580 | ||
8628e7c8 DK |
1581 | static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) |
1582 | { | |
1583 | return omap_sham_cra_init_alg(tfm, "md5"); | |
1584 | } | |
1585 | ||
eaef7e3f LV |
1586 | static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm) |
1587 | { | |
1588 | return omap_sham_cra_init_alg(tfm, "sha384"); | |
1589 | } | |
1590 | ||
1591 | static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm) | |
1592 | { | |
1593 | return omap_sham_cra_init_alg(tfm, "sha512"); | |
1594 | } | |
1595 | ||
8628e7c8 DK |
1596 | static void omap_sham_cra_exit(struct crypto_tfm *tfm) |
1597 | { | |
1598 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); | |
1599 | ||
1600 | crypto_free_shash(tctx->fallback); | |
1601 | tctx->fallback = NULL; | |
1602 | ||
ea1fd224 | 1603 | if (tctx->flags & BIT(FLAGS_HMAC)) { |
8628e7c8 DK |
1604 | struct omap_sham_hmac_ctx *bctx = tctx->base; |
1605 | crypto_free_shash(bctx->shash); | |
1606 | } | |
1607 | } | |
1608 | ||
99a7ffff TK |
1609 | static int omap_sham_export(struct ahash_request *req, void *out) |
1610 | { | |
1611 | return -ENOTSUPP; | |
1612 | } | |
1613 | ||
1614 | static int omap_sham_import(struct ahash_request *req, const void *in) | |
1615 | { | |
1616 | return -ENOTSUPP; | |
1617 | } | |
1618 | ||
d20fb18b | 1619 | static struct ahash_alg algs_sha1_md5[] = { |
8628e7c8 DK |
1620 | { |
1621 | .init = omap_sham_init, | |
1622 | .update = omap_sham_update, | |
1623 | .final = omap_sham_final, | |
1624 | .finup = omap_sham_finup, | |
1625 | .digest = omap_sham_digest, | |
1626 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
1627 | .halg.base = { | |
1628 | .cra_name = "sha1", | |
1629 | .cra_driver_name = "omap-sha1", | |
eb354785 | 1630 | .cra_priority = 400, |
8628e7c8 | 1631 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
d912bb76 | 1632 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1633 | CRYPTO_ALG_ASYNC | |
1634 | CRYPTO_ALG_NEED_FALLBACK, | |
1635 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1636 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1637 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1638 | .cra_module = THIS_MODULE, |
1639 | .cra_init = omap_sham_cra_init, | |
1640 | .cra_exit = omap_sham_cra_exit, | |
1641 | } | |
1642 | }, | |
1643 | { | |
1644 | .init = omap_sham_init, | |
1645 | .update = omap_sham_update, | |
1646 | .final = omap_sham_final, | |
1647 | .finup = omap_sham_finup, | |
1648 | .digest = omap_sham_digest, | |
1649 | .halg.digestsize = MD5_DIGEST_SIZE, | |
1650 | .halg.base = { | |
1651 | .cra_name = "md5", | |
1652 | .cra_driver_name = "omap-md5", | |
eb354785 | 1653 | .cra_priority = 400, |
8628e7c8 | 1654 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
d912bb76 | 1655 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1656 | CRYPTO_ALG_ASYNC | |
1657 | CRYPTO_ALG_NEED_FALLBACK, | |
1658 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1659 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
798eed5d | 1660 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1661 | .cra_module = THIS_MODULE, |
1662 | .cra_init = omap_sham_cra_init, | |
1663 | .cra_exit = omap_sham_cra_exit, | |
1664 | } | |
1665 | }, | |
1666 | { | |
1667 | .init = omap_sham_init, | |
1668 | .update = omap_sham_update, | |
1669 | .final = omap_sham_final, | |
1670 | .finup = omap_sham_finup, | |
1671 | .digest = omap_sham_digest, | |
1672 | .setkey = omap_sham_setkey, | |
1673 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
1674 | .halg.base = { | |
1675 | .cra_name = "hmac(sha1)", | |
1676 | .cra_driver_name = "omap-hmac-sha1", | |
eb354785 | 1677 | .cra_priority = 400, |
8628e7c8 | 1678 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
d912bb76 | 1679 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1680 | CRYPTO_ALG_ASYNC | |
1681 | CRYPTO_ALG_NEED_FALLBACK, | |
1682 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1683 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1684 | sizeof(struct omap_sham_hmac_ctx), | |
798eed5d | 1685 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1686 | .cra_module = THIS_MODULE, |
1687 | .cra_init = omap_sham_cra_sha1_init, | |
1688 | .cra_exit = omap_sham_cra_exit, | |
1689 | } | |
1690 | }, | |
1691 | { | |
1692 | .init = omap_sham_init, | |
1693 | .update = omap_sham_update, | |
1694 | .final = omap_sham_final, | |
1695 | .finup = omap_sham_finup, | |
1696 | .digest = omap_sham_digest, | |
1697 | .setkey = omap_sham_setkey, | |
1698 | .halg.digestsize = MD5_DIGEST_SIZE, | |
1699 | .halg.base = { | |
1700 | .cra_name = "hmac(md5)", | |
1701 | .cra_driver_name = "omap-hmac-md5", | |
eb354785 | 1702 | .cra_priority = 400, |
8628e7c8 | 1703 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
d912bb76 | 1704 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1705 | CRYPTO_ALG_ASYNC | |
1706 | CRYPTO_ALG_NEED_FALLBACK, | |
1707 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1708 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1709 | sizeof(struct omap_sham_hmac_ctx), | |
798eed5d | 1710 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1711 | .cra_module = THIS_MODULE, |
1712 | .cra_init = omap_sham_cra_md5_init, | |
1713 | .cra_exit = omap_sham_cra_exit, | |
1714 | } | |
1715 | } | |
1716 | }; | |
1717 | ||
d20fb18b MG |
1718 | /* OMAP4 has some algs in addition to what OMAP2 has */ |
1719 | static struct ahash_alg algs_sha224_sha256[] = { | |
1720 | { | |
1721 | .init = omap_sham_init, | |
1722 | .update = omap_sham_update, | |
1723 | .final = omap_sham_final, | |
1724 | .finup = omap_sham_finup, | |
1725 | .digest = omap_sham_digest, | |
1726 | .halg.digestsize = SHA224_DIGEST_SIZE, | |
1727 | .halg.base = { | |
1728 | .cra_name = "sha224", | |
1729 | .cra_driver_name = "omap-sha224", | |
eb354785 | 1730 | .cra_priority = 400, |
d20fb18b MG |
1731 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
1732 | CRYPTO_ALG_ASYNC | | |
1733 | CRYPTO_ALG_NEED_FALLBACK, | |
1734 | .cra_blocksize = SHA224_BLOCK_SIZE, | |
1735 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1736 | .cra_alignmask = OMAP_ALIGN_MASK, |
d20fb18b MG |
1737 | .cra_module = THIS_MODULE, |
1738 | .cra_init = omap_sham_cra_init, | |
1739 | .cra_exit = omap_sham_cra_exit, | |
1740 | } | |
1741 | }, | |
1742 | { | |
1743 | .init = omap_sham_init, | |
1744 | .update = omap_sham_update, | |
1745 | .final = omap_sham_final, | |
1746 | .finup = omap_sham_finup, | |
1747 | .digest = omap_sham_digest, | |
1748 | .halg.digestsize = SHA256_DIGEST_SIZE, | |
1749 | .halg.base = { | |
1750 | .cra_name = "sha256", | |
1751 | .cra_driver_name = "omap-sha256", | |
eb354785 | 1752 | .cra_priority = 400, |
d20fb18b MG |
1753 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
1754 | CRYPTO_ALG_ASYNC | | |
1755 | CRYPTO_ALG_NEED_FALLBACK, | |
1756 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
1757 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1758 | .cra_alignmask = OMAP_ALIGN_MASK, |
d20fb18b MG |
1759 | .cra_module = THIS_MODULE, |
1760 | .cra_init = omap_sham_cra_init, | |
1761 | .cra_exit = omap_sham_cra_exit, | |
1762 | } | |
1763 | }, | |
1764 | { | |
1765 | .init = omap_sham_init, | |
1766 | .update = omap_sham_update, | |
1767 | .final = omap_sham_final, | |
1768 | .finup = omap_sham_finup, | |
1769 | .digest = omap_sham_digest, | |
1770 | .setkey = omap_sham_setkey, | |
1771 | .halg.digestsize = SHA224_DIGEST_SIZE, | |
1772 | .halg.base = { | |
1773 | .cra_name = "hmac(sha224)", | |
1774 | .cra_driver_name = "omap-hmac-sha224", | |
eb354785 | 1775 | .cra_priority = 400, |
d20fb18b MG |
1776 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
1777 | CRYPTO_ALG_ASYNC | | |
1778 | CRYPTO_ALG_NEED_FALLBACK, | |
1779 | .cra_blocksize = SHA224_BLOCK_SIZE, | |
1780 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1781 | sizeof(struct omap_sham_hmac_ctx), | |
1782 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1783 | .cra_module = THIS_MODULE, | |
1784 | .cra_init = omap_sham_cra_sha224_init, | |
1785 | .cra_exit = omap_sham_cra_exit, | |
1786 | } | |
1787 | }, | |
1788 | { | |
1789 | .init = omap_sham_init, | |
1790 | .update = omap_sham_update, | |
1791 | .final = omap_sham_final, | |
1792 | .finup = omap_sham_finup, | |
1793 | .digest = omap_sham_digest, | |
1794 | .setkey = omap_sham_setkey, | |
1795 | .halg.digestsize = SHA256_DIGEST_SIZE, | |
1796 | .halg.base = { | |
1797 | .cra_name = "hmac(sha256)", | |
1798 | .cra_driver_name = "omap-hmac-sha256", | |
eb354785 | 1799 | .cra_priority = 400, |
d20fb18b MG |
1800 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
1801 | CRYPTO_ALG_ASYNC | | |
1802 | CRYPTO_ALG_NEED_FALLBACK, | |
1803 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
1804 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1805 | sizeof(struct omap_sham_hmac_ctx), | |
1806 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1807 | .cra_module = THIS_MODULE, | |
1808 | .cra_init = omap_sham_cra_sha256_init, | |
1809 | .cra_exit = omap_sham_cra_exit, | |
1810 | } | |
1811 | }, | |
1812 | }; | |
1813 | ||
eaef7e3f LV |
1814 | static struct ahash_alg algs_sha384_sha512[] = { |
1815 | { | |
1816 | .init = omap_sham_init, | |
1817 | .update = omap_sham_update, | |
1818 | .final = omap_sham_final, | |
1819 | .finup = omap_sham_finup, | |
1820 | .digest = omap_sham_digest, | |
1821 | .halg.digestsize = SHA384_DIGEST_SIZE, | |
1822 | .halg.base = { | |
1823 | .cra_name = "sha384", | |
1824 | .cra_driver_name = "omap-sha384", | |
eb354785 | 1825 | .cra_priority = 400, |
eaef7e3f LV |
1826 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
1827 | CRYPTO_ALG_ASYNC | | |
1828 | CRYPTO_ALG_NEED_FALLBACK, | |
1829 | .cra_blocksize = SHA384_BLOCK_SIZE, | |
1830 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1831 | .cra_alignmask = OMAP_ALIGN_MASK, |
eaef7e3f LV |
1832 | .cra_module = THIS_MODULE, |
1833 | .cra_init = omap_sham_cra_init, | |
1834 | .cra_exit = omap_sham_cra_exit, | |
1835 | } | |
1836 | }, | |
1837 | { | |
1838 | .init = omap_sham_init, | |
1839 | .update = omap_sham_update, | |
1840 | .final = omap_sham_final, | |
1841 | .finup = omap_sham_finup, | |
1842 | .digest = omap_sham_digest, | |
1843 | .halg.digestsize = SHA512_DIGEST_SIZE, | |
1844 | .halg.base = { | |
1845 | .cra_name = "sha512", | |
1846 | .cra_driver_name = "omap-sha512", | |
eb354785 | 1847 | .cra_priority = 400, |
eaef7e3f LV |
1848 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
1849 | CRYPTO_ALG_ASYNC | | |
1850 | CRYPTO_ALG_NEED_FALLBACK, | |
1851 | .cra_blocksize = SHA512_BLOCK_SIZE, | |
1852 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1853 | .cra_alignmask = OMAP_ALIGN_MASK, |
eaef7e3f LV |
1854 | .cra_module = THIS_MODULE, |
1855 | .cra_init = omap_sham_cra_init, | |
1856 | .cra_exit = omap_sham_cra_exit, | |
1857 | } | |
1858 | }, | |
1859 | { | |
1860 | .init = omap_sham_init, | |
1861 | .update = omap_sham_update, | |
1862 | .final = omap_sham_final, | |
1863 | .finup = omap_sham_finup, | |
1864 | .digest = omap_sham_digest, | |
1865 | .setkey = omap_sham_setkey, | |
1866 | .halg.digestsize = SHA384_DIGEST_SIZE, | |
1867 | .halg.base = { | |
1868 | .cra_name = "hmac(sha384)", | |
1869 | .cra_driver_name = "omap-hmac-sha384", | |
eb354785 | 1870 | .cra_priority = 400, |
eaef7e3f LV |
1871 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
1872 | CRYPTO_ALG_ASYNC | | |
1873 | CRYPTO_ALG_NEED_FALLBACK, | |
1874 | .cra_blocksize = SHA384_BLOCK_SIZE, | |
1875 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1876 | sizeof(struct omap_sham_hmac_ctx), | |
1877 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1878 | .cra_module = THIS_MODULE, | |
1879 | .cra_init = omap_sham_cra_sha384_init, | |
1880 | .cra_exit = omap_sham_cra_exit, | |
1881 | } | |
1882 | }, | |
1883 | { | |
1884 | .init = omap_sham_init, | |
1885 | .update = omap_sham_update, | |
1886 | .final = omap_sham_final, | |
1887 | .finup = omap_sham_finup, | |
1888 | .digest = omap_sham_digest, | |
1889 | .setkey = omap_sham_setkey, | |
1890 | .halg.digestsize = SHA512_DIGEST_SIZE, | |
1891 | .halg.base = { | |
1892 | .cra_name = "hmac(sha512)", | |
1893 | .cra_driver_name = "omap-hmac-sha512", | |
eb354785 | 1894 | .cra_priority = 400, |
eaef7e3f LV |
1895 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | |
1896 | CRYPTO_ALG_ASYNC | | |
1897 | CRYPTO_ALG_NEED_FALLBACK, | |
1898 | .cra_blocksize = SHA512_BLOCK_SIZE, | |
1899 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1900 | sizeof(struct omap_sham_hmac_ctx), | |
1901 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1902 | .cra_module = THIS_MODULE, | |
1903 | .cra_init = omap_sham_cra_sha512_init, | |
1904 | .cra_exit = omap_sham_cra_exit, | |
1905 | } | |
1906 | }, | |
1907 | }; | |
1908 | ||
8628e7c8 DK |
1909 | static void omap_sham_done_task(unsigned long data) |
1910 | { | |
1911 | struct omap_sham_dev *dd = (struct omap_sham_dev *)data; | |
6c63db82 | 1912 | int err = 0; |
8628e7c8 | 1913 | |
6cb3ffe1 DK |
1914 | if (!test_bit(FLAGS_BUSY, &dd->flags)) { |
1915 | omap_sham_handle_queue(dd, NULL); | |
1916 | return; | |
1917 | } | |
1918 | ||
6c63db82 | 1919 | if (test_bit(FLAGS_CPU, &dd->flags)) { |
b8411ccd LV |
1920 | if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { |
1921 | /* hash or semi-hash ready */ | |
1922 | err = omap_sham_update_cpu(dd); | |
1923 | if (err != -EINPROGRESS) | |
1924 | goto finish; | |
1925 | } | |
6c63db82 DK |
1926 | } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { |
1927 | if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { | |
1928 | omap_sham_update_dma_stop(dd); | |
1929 | if (dd->err) { | |
1930 | err = dd->err; | |
1931 | goto finish; | |
1932 | } | |
1933 | } | |
1934 | if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { | |
1935 | /* hash or semi-hash ready */ | |
1936 | clear_bit(FLAGS_DMA_READY, &dd->flags); | |
887c883e | 1937 | err = omap_sham_update_dma_start(dd); |
6c63db82 DK |
1938 | if (err != -EINPROGRESS) |
1939 | goto finish; | |
1940 | } | |
8628e7c8 DK |
1941 | } |
1942 | ||
6c63db82 | 1943 | return; |
3e133c8b | 1944 | |
6c63db82 DK |
1945 | finish: |
1946 | dev_dbg(dd->dev, "update done: err: %d\n", err); | |
1947 | /* finish curent request */ | |
1948 | omap_sham_finish_req(dd->req, err); | |
4e7813a0 TK |
1949 | |
1950 | /* If we are not busy, process next req */ | |
1951 | if (!test_bit(FLAGS_BUSY, &dd->flags)) | |
1952 | omap_sham_handle_queue(dd, NULL); | |
8628e7c8 DK |
1953 | } |
1954 | ||
0d373d60 MG |
1955 | static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) |
1956 | { | |
1957 | if (!test_bit(FLAGS_BUSY, &dd->flags)) { | |
1958 | dev_warn(dd->dev, "Interrupt when no active requests.\n"); | |
1959 | } else { | |
1960 | set_bit(FLAGS_OUTPUT_READY, &dd->flags); | |
1961 | tasklet_schedule(&dd->done_task); | |
1962 | } | |
1963 | ||
1964 | return IRQ_HANDLED; | |
1965 | } | |
1966 | ||
1967 | static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) | |
8628e7c8 DK |
1968 | { |
1969 | struct omap_sham_dev *dd = dev_id; | |
8628e7c8 | 1970 | |
ed3ea9a8 | 1971 | if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) |
8628e7c8 DK |
1972 | /* final -> allow device to go to power-saving mode */ |
1973 | omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); | |
1974 | ||
1975 | omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, | |
1976 | SHA_REG_CTRL_OUTPUT_READY); | |
1977 | omap_sham_read(dd, SHA_REG_CTRL); | |
1978 | ||
0d373d60 MG |
1979 | return omap_sham_irq_common(dd); |
1980 | } | |
cd3f1d54 | 1981 | |
0d373d60 MG |
1982 | static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) |
1983 | { | |
1984 | struct omap_sham_dev *dd = dev_id; | |
8628e7c8 | 1985 | |
0d373d60 MG |
1986 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); |
1987 | ||
1988 | return omap_sham_irq_common(dd); | |
8628e7c8 DK |
1989 | } |
1990 | ||
d20fb18b MG |
1991 | static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = { |
1992 | { | |
1993 | .algs_list = algs_sha1_md5, | |
1994 | .size = ARRAY_SIZE(algs_sha1_md5), | |
1995 | }, | |
1996 | }; | |
1997 | ||
0d373d60 | 1998 | static const struct omap_sham_pdata omap_sham_pdata_omap2 = { |
d20fb18b MG |
1999 | .algs_info = omap_sham_algs_info_omap2, |
2000 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2), | |
0d373d60 MG |
2001 | .flags = BIT(FLAGS_BE32_SHA1), |
2002 | .digest_size = SHA1_DIGEST_SIZE, | |
2003 | .copy_hash = omap_sham_copy_hash_omap2, | |
2004 | .write_ctrl = omap_sham_write_ctrl_omap2, | |
2005 | .trigger = omap_sham_trigger_omap2, | |
2006 | .poll_irq = omap_sham_poll_irq_omap2, | |
2007 | .intr_hdlr = omap_sham_irq_omap2, | |
2008 | .idigest_ofs = 0x00, | |
2009 | .din_ofs = 0x1c, | |
2010 | .digcnt_ofs = 0x14, | |
2011 | .rev_ofs = 0x5c, | |
2012 | .mask_ofs = 0x60, | |
2013 | .sysstatus_ofs = 0x64, | |
2014 | .major_mask = 0xf0, | |
2015 | .major_shift = 4, | |
2016 | .minor_mask = 0x0f, | |
2017 | .minor_shift = 0, | |
2018 | }; | |
2019 | ||
03feec9c | 2020 | #ifdef CONFIG_OF |
d20fb18b MG |
2021 | static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = { |
2022 | { | |
2023 | .algs_list = algs_sha1_md5, | |
2024 | .size = ARRAY_SIZE(algs_sha1_md5), | |
2025 | }, | |
2026 | { | |
2027 | .algs_list = algs_sha224_sha256, | |
2028 | .size = ARRAY_SIZE(algs_sha224_sha256), | |
2029 | }, | |
2030 | }; | |
2031 | ||
0d373d60 | 2032 | static const struct omap_sham_pdata omap_sham_pdata_omap4 = { |
d20fb18b MG |
2033 | .algs_info = omap_sham_algs_info_omap4, |
2034 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4), | |
0d373d60 MG |
2035 | .flags = BIT(FLAGS_AUTO_XOR), |
2036 | .digest_size = SHA256_DIGEST_SIZE, | |
2037 | .copy_hash = omap_sham_copy_hash_omap4, | |
2038 | .write_ctrl = omap_sham_write_ctrl_omap4, | |
2039 | .trigger = omap_sham_trigger_omap4, | |
2040 | .poll_irq = omap_sham_poll_irq_omap4, | |
2041 | .intr_hdlr = omap_sham_irq_omap4, | |
2042 | .idigest_ofs = 0x020, | |
eaef7e3f | 2043 | .odigest_ofs = 0x0, |
0d373d60 MG |
2044 | .din_ofs = 0x080, |
2045 | .digcnt_ofs = 0x040, | |
2046 | .rev_ofs = 0x100, | |
2047 | .mask_ofs = 0x110, | |
2048 | .sysstatus_ofs = 0x114, | |
eaef7e3f LV |
2049 | .mode_ofs = 0x44, |
2050 | .length_ofs = 0x48, | |
0d373d60 MG |
2051 | .major_mask = 0x0700, |
2052 | .major_shift = 8, | |
2053 | .minor_mask = 0x003f, | |
2054 | .minor_shift = 0, | |
2055 | }; | |
2056 | ||
7d7c704d LV |
2057 | static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = { |
2058 | { | |
2059 | .algs_list = algs_sha1_md5, | |
2060 | .size = ARRAY_SIZE(algs_sha1_md5), | |
2061 | }, | |
2062 | { | |
2063 | .algs_list = algs_sha224_sha256, | |
2064 | .size = ARRAY_SIZE(algs_sha224_sha256), | |
2065 | }, | |
2066 | { | |
2067 | .algs_list = algs_sha384_sha512, | |
2068 | .size = ARRAY_SIZE(algs_sha384_sha512), | |
2069 | }, | |
2070 | }; | |
2071 | ||
2072 | static const struct omap_sham_pdata omap_sham_pdata_omap5 = { | |
2073 | .algs_info = omap_sham_algs_info_omap5, | |
2074 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5), | |
2075 | .flags = BIT(FLAGS_AUTO_XOR), | |
2076 | .digest_size = SHA512_DIGEST_SIZE, | |
2077 | .copy_hash = omap_sham_copy_hash_omap4, | |
2078 | .write_ctrl = omap_sham_write_ctrl_omap4, | |
2079 | .trigger = omap_sham_trigger_omap4, | |
2080 | .poll_irq = omap_sham_poll_irq_omap4, | |
2081 | .intr_hdlr = omap_sham_irq_omap4, | |
2082 | .idigest_ofs = 0x240, | |
2083 | .odigest_ofs = 0x200, | |
2084 | .din_ofs = 0x080, | |
2085 | .digcnt_ofs = 0x280, | |
2086 | .rev_ofs = 0x100, | |
2087 | .mask_ofs = 0x110, | |
2088 | .sysstatus_ofs = 0x114, | |
2089 | .mode_ofs = 0x284, | |
2090 | .length_ofs = 0x288, | |
2091 | .major_mask = 0x0700, | |
2092 | .major_shift = 8, | |
2093 | .minor_mask = 0x003f, | |
2094 | .minor_shift = 0, | |
2095 | }; | |
2096 | ||
03feec9c MG |
2097 | static const struct of_device_id omap_sham_of_match[] = { |
2098 | { | |
2099 | .compatible = "ti,omap2-sham", | |
0d373d60 MG |
2100 | .data = &omap_sham_pdata_omap2, |
2101 | }, | |
eddca85b PR |
2102 | { |
2103 | .compatible = "ti,omap3-sham", | |
2104 | .data = &omap_sham_pdata_omap2, | |
2105 | }, | |
0d373d60 MG |
2106 | { |
2107 | .compatible = "ti,omap4-sham", | |
2108 | .data = &omap_sham_pdata_omap4, | |
03feec9c | 2109 | }, |
7d7c704d LV |
2110 | { |
2111 | .compatible = "ti,omap5-sham", | |
2112 | .data = &omap_sham_pdata_omap5, | |
2113 | }, | |
03feec9c MG |
2114 | {}, |
2115 | }; | |
2116 | MODULE_DEVICE_TABLE(of, omap_sham_of_match); | |
2117 | ||
2118 | static int omap_sham_get_res_of(struct omap_sham_dev *dd, | |
2119 | struct device *dev, struct resource *res) | |
8628e7c8 | 2120 | { |
03feec9c MG |
2121 | struct device_node *node = dev->of_node; |
2122 | const struct of_device_id *match; | |
2123 | int err = 0; | |
8628e7c8 | 2124 | |
03feec9c MG |
2125 | match = of_match_device(of_match_ptr(omap_sham_of_match), dev); |
2126 | if (!match) { | |
2127 | dev_err(dev, "no compatible OF match\n"); | |
2128 | err = -EINVAL; | |
2129 | goto err; | |
3e133c8b DK |
2130 | } |
2131 | ||
03feec9c MG |
2132 | err = of_address_to_resource(node, 0, res); |
2133 | if (err < 0) { | |
2134 | dev_err(dev, "can't translate OF node address\n"); | |
2135 | err = -EINVAL; | |
2136 | goto err; | |
2137 | } | |
2138 | ||
f7578496 | 2139 | dd->irq = irq_of_parse_and_map(node, 0); |
03feec9c MG |
2140 | if (!dd->irq) { |
2141 | dev_err(dev, "can't translate OF irq value\n"); | |
2142 | err = -EINVAL; | |
2143 | goto err; | |
2144 | } | |
2145 | ||
0d373d60 | 2146 | dd->pdata = match->data; |
03feec9c MG |
2147 | |
2148 | err: | |
2149 | return err; | |
8628e7c8 | 2150 | } |
03feec9c | 2151 | #else |
c3c3b329 MG |
2152 | static const struct of_device_id omap_sham_of_match[] = { |
2153 | {}, | |
2154 | }; | |
8628e7c8 | 2155 | |
c3c3b329 | 2156 | static int omap_sham_get_res_of(struct omap_sham_dev *dd, |
03feec9c | 2157 | struct device *dev, struct resource *res) |
8628e7c8 | 2158 | { |
03feec9c MG |
2159 | return -EINVAL; |
2160 | } | |
2161 | #endif | |
8628e7c8 | 2162 | |
03feec9c MG |
2163 | static int omap_sham_get_res_pdev(struct omap_sham_dev *dd, |
2164 | struct platform_device *pdev, struct resource *res) | |
2165 | { | |
2166 | struct device *dev = &pdev->dev; | |
2167 | struct resource *r; | |
2168 | int err = 0; | |
8628e7c8 | 2169 | |
03feec9c MG |
2170 | /* Get the base address */ |
2171 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2172 | if (!r) { | |
2173 | dev_err(dev, "no MEM resource info\n"); | |
2174 | err = -ENODEV; | |
2175 | goto err; | |
8628e7c8 | 2176 | } |
03feec9c | 2177 | memcpy(res, r, sizeof(*res)); |
584db6a1 | 2178 | |
03feec9c MG |
2179 | /* Get the IRQ */ |
2180 | dd->irq = platform_get_irq(pdev, 0); | |
2181 | if (dd->irq < 0) { | |
2182 | dev_err(dev, "no IRQ resource info\n"); | |
2183 | err = dd->irq; | |
2184 | goto err; | |
2185 | } | |
8628e7c8 | 2186 | |
0d373d60 MG |
2187 | /* Only OMAP2/3 can be non-DT */ |
2188 | dd->pdata = &omap_sham_pdata_omap2; | |
2189 | ||
03feec9c MG |
2190 | err: |
2191 | return err; | |
8628e7c8 DK |
2192 | } |
2193 | ||
49cfe4db | 2194 | static int omap_sham_probe(struct platform_device *pdev) |
8628e7c8 DK |
2195 | { |
2196 | struct omap_sham_dev *dd; | |
2197 | struct device *dev = &pdev->dev; | |
03feec9c | 2198 | struct resource res; |
dfd061d5 | 2199 | dma_cap_mask_t mask; |
8628e7c8 | 2200 | int err, i, j; |
0d373d60 | 2201 | u32 rev; |
8628e7c8 | 2202 | |
7a7e4b73 | 2203 | dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL); |
8628e7c8 DK |
2204 | if (dd == NULL) { |
2205 | dev_err(dev, "unable to alloc data struct.\n"); | |
2206 | err = -ENOMEM; | |
2207 | goto data_err; | |
2208 | } | |
2209 | dd->dev = dev; | |
2210 | platform_set_drvdata(pdev, dd); | |
2211 | ||
2212 | INIT_LIST_HEAD(&dd->list); | |
2213 | spin_lock_init(&dd->lock); | |
2214 | tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd); | |
8628e7c8 DK |
2215 | crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); |
2216 | ||
03feec9c MG |
2217 | err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) : |
2218 | omap_sham_get_res_pdev(dd, pdev, &res); | |
2219 | if (err) | |
7a7e4b73 | 2220 | goto data_err; |
8628e7c8 | 2221 | |
30862281 LN |
2222 | dd->io_base = devm_ioremap_resource(dev, &res); |
2223 | if (IS_ERR(dd->io_base)) { | |
2224 | err = PTR_ERR(dd->io_base); | |
7a7e4b73 | 2225 | goto data_err; |
8628e7c8 | 2226 | } |
03feec9c | 2227 | dd->phys_base = res.start; |
8628e7c8 | 2228 | |
0de9c387 LV |
2229 | err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr, |
2230 | IRQF_TRIGGER_NONE, dev_name(dev), dd); | |
8628e7c8 | 2231 | if (err) { |
0de9c387 LV |
2232 | dev_err(dev, "unable to request irq %d, err = %d\n", |
2233 | dd->irq, err); | |
7a7e4b73 | 2234 | goto data_err; |
8628e7c8 DK |
2235 | } |
2236 | ||
dfd061d5 MG |
2237 | dma_cap_zero(mask); |
2238 | dma_cap_set(DMA_SLAVE, mask); | |
8628e7c8 | 2239 | |
dbe24620 PU |
2240 | dd->dma_lch = dma_request_chan(dev, "rx"); |
2241 | if (IS_ERR(dd->dma_lch)) { | |
2242 | err = PTR_ERR(dd->dma_lch); | |
2243 | if (err == -EPROBE_DEFER) | |
2244 | goto data_err; | |
2245 | ||
b8411ccd LV |
2246 | dd->polling_mode = 1; |
2247 | dev_dbg(dev, "using polling mode instead of dma\n"); | |
8628e7c8 DK |
2248 | } |
2249 | ||
0d373d60 | 2250 | dd->flags |= dd->pdata->flags; |
8628e7c8 | 2251 | |
e93f767b TK |
2252 | pm_runtime_use_autosuspend(dev); |
2253 | pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); | |
2254 | ||
b359f034 | 2255 | pm_runtime_enable(dev); |
b0a3d898 | 2256 | pm_runtime_irq_safe(dev); |
604c3103 PR |
2257 | |
2258 | err = pm_runtime_get_sync(dev); | |
2259 | if (err < 0) { | |
2260 | dev_err(dev, "failed to get sync: %d\n", err); | |
2261 | goto err_pm; | |
2262 | } | |
2263 | ||
0d373d60 MG |
2264 | rev = omap_sham_read(dd, SHA_REG_REV(dd)); |
2265 | pm_runtime_put_sync(&pdev->dev); | |
8628e7c8 | 2266 | |
8628e7c8 | 2267 | dev_info(dev, "hw accel on OMAP rev %u.%u\n", |
0d373d60 MG |
2268 | (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, |
2269 | (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); | |
8628e7c8 DK |
2270 | |
2271 | spin_lock(&sham.lock); | |
2272 | list_add_tail(&dd->list, &sham.dev_list); | |
2273 | spin_unlock(&sham.lock); | |
2274 | ||
d20fb18b MG |
2275 | for (i = 0; i < dd->pdata->algs_info_size; i++) { |
2276 | for (j = 0; j < dd->pdata->algs_info[i].size; j++) { | |
99a7ffff TK |
2277 | struct ahash_alg *alg; |
2278 | ||
2279 | alg = &dd->pdata->algs_info[i].algs_list[j]; | |
2280 | alg->export = omap_sham_export; | |
2281 | alg->import = omap_sham_import; | |
2282 | alg->halg.statesize = sizeof(struct omap_sham_reqctx); | |
2283 | err = crypto_register_ahash(alg); | |
d20fb18b MG |
2284 | if (err) |
2285 | goto err_algs; | |
2286 | ||
2287 | dd->pdata->algs_info[i].registered++; | |
2288 | } | |
8628e7c8 DK |
2289 | } |
2290 | ||
2291 | return 0; | |
2292 | ||
2293 | err_algs: | |
d20fb18b MG |
2294 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
2295 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
2296 | crypto_unregister_ahash( | |
2297 | &dd->pdata->algs_info[i].algs_list[j]); | |
604c3103 | 2298 | err_pm: |
b359f034 | 2299 | pm_runtime_disable(dev); |
d462e322 | 2300 | if (!dd->polling_mode) |
f13ab86a | 2301 | dma_release_channel(dd->dma_lch); |
8628e7c8 DK |
2302 | data_err: |
2303 | dev_err(dev, "initialization failed.\n"); | |
2304 | ||
2305 | return err; | |
2306 | } | |
2307 | ||
49cfe4db | 2308 | static int omap_sham_remove(struct platform_device *pdev) |
8628e7c8 DK |
2309 | { |
2310 | static struct omap_sham_dev *dd; | |
d20fb18b | 2311 | int i, j; |
8628e7c8 DK |
2312 | |
2313 | dd = platform_get_drvdata(pdev); | |
2314 | if (!dd) | |
2315 | return -ENODEV; | |
2316 | spin_lock(&sham.lock); | |
2317 | list_del(&dd->list); | |
2318 | spin_unlock(&sham.lock); | |
d20fb18b MG |
2319 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
2320 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
2321 | crypto_unregister_ahash( | |
2322 | &dd->pdata->algs_info[i].algs_list[j]); | |
8628e7c8 | 2323 | tasklet_kill(&dd->done_task); |
b359f034 | 2324 | pm_runtime_disable(&pdev->dev); |
f13ab86a | 2325 | |
dbe24620 | 2326 | if (!dd->polling_mode) |
f13ab86a | 2327 | dma_release_channel(dd->dma_lch); |
8628e7c8 DK |
2328 | |
2329 | return 0; | |
2330 | } | |
2331 | ||
3b3f4400 MG |
2332 | #ifdef CONFIG_PM_SLEEP |
2333 | static int omap_sham_suspend(struct device *dev) | |
2334 | { | |
2335 | pm_runtime_put_sync(dev); | |
2336 | return 0; | |
2337 | } | |
2338 | ||
2339 | static int omap_sham_resume(struct device *dev) | |
2340 | { | |
604c3103 PR |
2341 | int err = pm_runtime_get_sync(dev); |
2342 | if (err < 0) { | |
2343 | dev_err(dev, "failed to get sync: %d\n", err); | |
2344 | return err; | |
2345 | } | |
3b3f4400 MG |
2346 | return 0; |
2347 | } | |
2348 | #endif | |
2349 | ||
ae12fe28 | 2350 | static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume); |
3b3f4400 | 2351 | |
8628e7c8 DK |
2352 | static struct platform_driver omap_sham_driver = { |
2353 | .probe = omap_sham_probe, | |
2354 | .remove = omap_sham_remove, | |
2355 | .driver = { | |
2356 | .name = "omap-sham", | |
3b3f4400 | 2357 | .pm = &omap_sham_pm_ops, |
03feec9c | 2358 | .of_match_table = omap_sham_of_match, |
8628e7c8 DK |
2359 | }, |
2360 | }; | |
2361 | ||
02613702 | 2362 | module_platform_driver(omap_sham_driver); |
8628e7c8 DK |
2363 | |
2364 | MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); | |
2365 | MODULE_LICENSE("GPL v2"); | |
2366 | MODULE_AUTHOR("Dmitry Kasatkin"); | |
718249d7 | 2367 | MODULE_ALIAS("platform:omap-sham"); |