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Commit | Line | Data |
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8628e7c8 DK |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for OMAP SHA1/MD5 HW acceleration. | |
5 | * | |
6 | * Copyright (c) 2010 Nokia Corporation | |
7 | * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> | |
0d373d60 | 8 | * Copyright (c) 2011 Texas Instruments Incorporated |
8628e7c8 DK |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as published | |
12 | * by the Free Software Foundation. | |
13 | * | |
14 | * Some ideas are from old omap-sha1-md5.c driver. | |
15 | */ | |
16 | ||
17 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
18 | ||
8628e7c8 DK |
19 | #include <linux/err.h> |
20 | #include <linux/device.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/kernel.h> | |
8628e7c8 DK |
26 | #include <linux/irq.h> |
27 | #include <linux/io.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/scatterlist.h> | |
30 | #include <linux/dma-mapping.h> | |
dfd061d5 MG |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/omap-dma.h> | |
b359f034 | 33 | #include <linux/pm_runtime.h> |
03feec9c MG |
34 | #include <linux/of.h> |
35 | #include <linux/of_device.h> | |
36 | #include <linux/of_address.h> | |
37 | #include <linux/of_irq.h> | |
8628e7c8 DK |
38 | #include <linux/delay.h> |
39 | #include <linux/crypto.h> | |
40 | #include <linux/cryptohash.h> | |
41 | #include <crypto/scatterwalk.h> | |
42 | #include <crypto/algapi.h> | |
43 | #include <crypto/sha.h> | |
44 | #include <crypto/hash.h> | |
45 | #include <crypto/internal/hash.h> | |
46 | ||
8628e7c8 DK |
47 | #define MD5_DIGEST_SIZE 16 |
48 | ||
dfd061d5 MG |
49 | #define DST_MAXBURST 16 |
50 | #define DMA_MIN (DST_MAXBURST * sizeof(u32)) | |
51 | ||
0d373d60 MG |
52 | #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) |
53 | #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) | |
54 | #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) | |
55 | ||
eaef7e3f | 56 | #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) |
8628e7c8 DK |
57 | |
58 | #define SHA_REG_CTRL 0x18 | |
59 | #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) | |
60 | #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) | |
61 | #define SHA_REG_CTRL_ALGO_CONST (1 << 3) | |
62 | #define SHA_REG_CTRL_ALGO (1 << 2) | |
63 | #define SHA_REG_CTRL_INPUT_READY (1 << 1) | |
64 | #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) | |
65 | ||
0d373d60 | 66 | #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) |
8628e7c8 | 67 | |
0d373d60 | 68 | #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) |
8628e7c8 DK |
69 | #define SHA_REG_MASK_DMA_EN (1 << 3) |
70 | #define SHA_REG_MASK_IT_EN (1 << 2) | |
71 | #define SHA_REG_MASK_SOFTRESET (1 << 1) | |
72 | #define SHA_REG_AUTOIDLE (1 << 0) | |
73 | ||
0d373d60 | 74 | #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) |
8628e7c8 DK |
75 | #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) |
76 | ||
eaef7e3f | 77 | #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) |
0d373d60 MG |
78 | #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) |
79 | #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) | |
80 | #define SHA_REG_MODE_CLOSE_HASH (1 << 4) | |
81 | #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) | |
0d373d60 | 82 | |
eaef7e3f LV |
83 | #define SHA_REG_MODE_ALGO_MASK (7 << 0) |
84 | #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) | |
85 | #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) | |
86 | #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1) | |
87 | #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1) | |
88 | #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0) | |
89 | #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0) | |
90 | ||
91 | #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) | |
0d373d60 MG |
92 | |
93 | #define SHA_REG_IRQSTATUS 0x118 | |
94 | #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) | |
95 | #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) | |
96 | #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) | |
97 | #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) | |
98 | ||
99 | #define SHA_REG_IRQENA 0x11C | |
100 | #define SHA_REG_IRQENA_CTX_RDY (1 << 3) | |
101 | #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) | |
102 | #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) | |
103 | #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) | |
104 | ||
8628e7c8 DK |
105 | #define DEFAULT_TIMEOUT_INTERVAL HZ |
106 | ||
ea1fd224 DK |
107 | /* mostly device flags */ |
108 | #define FLAGS_BUSY 0 | |
109 | #define FLAGS_FINAL 1 | |
110 | #define FLAGS_DMA_ACTIVE 2 | |
111 | #define FLAGS_OUTPUT_READY 3 | |
112 | #define FLAGS_INIT 4 | |
113 | #define FLAGS_CPU 5 | |
6c63db82 | 114 | #define FLAGS_DMA_READY 6 |
0d373d60 MG |
115 | #define FLAGS_AUTO_XOR 7 |
116 | #define FLAGS_BE32_SHA1 8 | |
ea1fd224 DK |
117 | /* context flags */ |
118 | #define FLAGS_FINUP 16 | |
119 | #define FLAGS_SG 17 | |
8628e7c8 | 120 | |
0d373d60 | 121 | #define FLAGS_MODE_SHIFT 18 |
eaef7e3f LV |
122 | #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT) |
123 | #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT) | |
124 | #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT) | |
125 | #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT) | |
126 | #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT) | |
127 | #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT) | |
128 | #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT) | |
129 | ||
130 | #define FLAGS_HMAC 21 | |
131 | #define FLAGS_ERROR 22 | |
0d373d60 MG |
132 | |
133 | #define OP_UPDATE 1 | |
134 | #define OP_FINAL 2 | |
8628e7c8 | 135 | |
798eed5d DK |
136 | #define OMAP_ALIGN_MASK (sizeof(u32)-1) |
137 | #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) | |
138 | ||
0d373d60 | 139 | #define BUFLEN PAGE_SIZE |
798eed5d | 140 | |
8628e7c8 DK |
141 | struct omap_sham_dev; |
142 | ||
143 | struct omap_sham_reqctx { | |
144 | struct omap_sham_dev *dd; | |
145 | unsigned long flags; | |
146 | unsigned long op; | |
147 | ||
eaef7e3f | 148 | u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED; |
8628e7c8 | 149 | size_t digcnt; |
8628e7c8 DK |
150 | size_t bufcnt; |
151 | size_t buflen; | |
152 | dma_addr_t dma_addr; | |
153 | ||
154 | /* walk state */ | |
155 | struct scatterlist *sg; | |
dfd061d5 | 156 | struct scatterlist sgl; |
8628e7c8 DK |
157 | unsigned int offset; /* offset in current sg */ |
158 | unsigned int total; /* total request */ | |
798eed5d DK |
159 | |
160 | u8 buffer[0] OMAP_ALIGNED; | |
8628e7c8 DK |
161 | }; |
162 | ||
163 | struct omap_sham_hmac_ctx { | |
164 | struct crypto_shash *shash; | |
eaef7e3f LV |
165 | u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; |
166 | u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; | |
8628e7c8 DK |
167 | }; |
168 | ||
169 | struct omap_sham_ctx { | |
170 | struct omap_sham_dev *dd; | |
171 | ||
172 | unsigned long flags; | |
173 | ||
174 | /* fallback stuff */ | |
175 | struct crypto_shash *fallback; | |
176 | ||
177 | struct omap_sham_hmac_ctx base[0]; | |
178 | }; | |
179 | ||
180 | #define OMAP_SHAM_QUEUE_LENGTH 1 | |
181 | ||
d20fb18b MG |
182 | struct omap_sham_algs_info { |
183 | struct ahash_alg *algs_list; | |
184 | unsigned int size; | |
185 | unsigned int registered; | |
186 | }; | |
187 | ||
0d373d60 | 188 | struct omap_sham_pdata { |
d20fb18b MG |
189 | struct omap_sham_algs_info *algs_info; |
190 | unsigned int algs_info_size; | |
0d373d60 MG |
191 | unsigned long flags; |
192 | int digest_size; | |
193 | ||
194 | void (*copy_hash)(struct ahash_request *req, int out); | |
195 | void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, | |
196 | int final, int dma); | |
197 | void (*trigger)(struct omap_sham_dev *dd, size_t length); | |
198 | int (*poll_irq)(struct omap_sham_dev *dd); | |
199 | irqreturn_t (*intr_hdlr)(int irq, void *dev_id); | |
200 | ||
201 | u32 odigest_ofs; | |
202 | u32 idigest_ofs; | |
203 | u32 din_ofs; | |
204 | u32 digcnt_ofs; | |
205 | u32 rev_ofs; | |
206 | u32 mask_ofs; | |
207 | u32 sysstatus_ofs; | |
eaef7e3f LV |
208 | u32 mode_ofs; |
209 | u32 length_ofs; | |
0d373d60 MG |
210 | |
211 | u32 major_mask; | |
212 | u32 major_shift; | |
213 | u32 minor_mask; | |
214 | u32 minor_shift; | |
215 | }; | |
216 | ||
8628e7c8 DK |
217 | struct omap_sham_dev { |
218 | struct list_head list; | |
219 | unsigned long phys_base; | |
220 | struct device *dev; | |
221 | void __iomem *io_base; | |
222 | int irq; | |
8628e7c8 | 223 | spinlock_t lock; |
3e133c8b | 224 | int err; |
03feec9c | 225 | unsigned int dma; |
dfd061d5 | 226 | struct dma_chan *dma_lch; |
8628e7c8 | 227 | struct tasklet_struct done_task; |
8628e7c8 DK |
228 | |
229 | unsigned long flags; | |
230 | struct crypto_queue queue; | |
231 | struct ahash_request *req; | |
0d373d60 MG |
232 | |
233 | const struct omap_sham_pdata *pdata; | |
8628e7c8 DK |
234 | }; |
235 | ||
236 | struct omap_sham_drv { | |
237 | struct list_head dev_list; | |
238 | spinlock_t lock; | |
239 | unsigned long flags; | |
240 | }; | |
241 | ||
242 | static struct omap_sham_drv sham = { | |
243 | .dev_list = LIST_HEAD_INIT(sham.dev_list), | |
244 | .lock = __SPIN_LOCK_UNLOCKED(sham.lock), | |
245 | }; | |
246 | ||
247 | static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) | |
248 | { | |
249 | return __raw_readl(dd->io_base + offset); | |
250 | } | |
251 | ||
252 | static inline void omap_sham_write(struct omap_sham_dev *dd, | |
253 | u32 offset, u32 value) | |
254 | { | |
255 | __raw_writel(value, dd->io_base + offset); | |
256 | } | |
257 | ||
258 | static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, | |
259 | u32 value, u32 mask) | |
260 | { | |
261 | u32 val; | |
262 | ||
263 | val = omap_sham_read(dd, address); | |
264 | val &= ~mask; | |
265 | val |= value; | |
266 | omap_sham_write(dd, address, val); | |
267 | } | |
268 | ||
269 | static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) | |
270 | { | |
271 | unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; | |
272 | ||
273 | while (!(omap_sham_read(dd, offset) & bit)) { | |
274 | if (time_is_before_jiffies(timeout)) | |
275 | return -ETIMEDOUT; | |
276 | } | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
0d373d60 | 281 | static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) |
8628e7c8 DK |
282 | { |
283 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
0d373d60 | 284 | struct omap_sham_dev *dd = ctx->dd; |
0c3cf4cc | 285 | u32 *hash = (u32 *)ctx->digest; |
8628e7c8 DK |
286 | int i; |
287 | ||
0d373d60 | 288 | for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { |
3c8d758a | 289 | if (out) |
0d373d60 | 290 | hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); |
3c8d758a | 291 | else |
0d373d60 MG |
292 | omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); |
293 | } | |
294 | } | |
295 | ||
296 | static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) | |
297 | { | |
298 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
299 | struct omap_sham_dev *dd = ctx->dd; | |
300 | int i; | |
301 | ||
302 | if (ctx->flags & BIT(FLAGS_HMAC)) { | |
303 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); | |
304 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
305 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
306 | u32 *opad = (u32 *)bctx->opad; | |
307 | ||
308 | for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { | |
309 | if (out) | |
310 | opad[i] = omap_sham_read(dd, | |
eaef7e3f | 311 | SHA_REG_ODIGEST(dd, i)); |
0d373d60 | 312 | else |
eaef7e3f | 313 | omap_sham_write(dd, SHA_REG_ODIGEST(dd, i), |
0d373d60 MG |
314 | opad[i]); |
315 | } | |
3c8d758a | 316 | } |
0d373d60 MG |
317 | |
318 | omap_sham_copy_hash_omap2(req, out); | |
3c8d758a DK |
319 | } |
320 | ||
321 | static void omap_sham_copy_ready_hash(struct ahash_request *req) | |
322 | { | |
323 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
324 | u32 *in = (u32 *)ctx->digest; | |
325 | u32 *hash = (u32 *)req->result; | |
0d373d60 | 326 | int i, d, big_endian = 0; |
3c8d758a DK |
327 | |
328 | if (!hash) | |
329 | return; | |
330 | ||
0d373d60 MG |
331 | switch (ctx->flags & FLAGS_MODE_MASK) { |
332 | case FLAGS_MODE_MD5: | |
333 | d = MD5_DIGEST_SIZE / sizeof(u32); | |
334 | break; | |
335 | case FLAGS_MODE_SHA1: | |
336 | /* OMAP2 SHA1 is big endian */ | |
337 | if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) | |
338 | big_endian = 1; | |
339 | d = SHA1_DIGEST_SIZE / sizeof(u32); | |
340 | break; | |
d20fb18b MG |
341 | case FLAGS_MODE_SHA224: |
342 | d = SHA224_DIGEST_SIZE / sizeof(u32); | |
343 | break; | |
344 | case FLAGS_MODE_SHA256: | |
345 | d = SHA256_DIGEST_SIZE / sizeof(u32); | |
346 | break; | |
eaef7e3f LV |
347 | case FLAGS_MODE_SHA384: |
348 | d = SHA384_DIGEST_SIZE / sizeof(u32); | |
349 | break; | |
350 | case FLAGS_MODE_SHA512: | |
351 | d = SHA512_DIGEST_SIZE / sizeof(u32); | |
352 | break; | |
0d373d60 MG |
353 | default: |
354 | d = 0; | |
355 | } | |
356 | ||
357 | if (big_endian) | |
358 | for (i = 0; i < d; i++) | |
3c8d758a | 359 | hash[i] = be32_to_cpu(in[i]); |
0d373d60 MG |
360 | else |
361 | for (i = 0; i < d; i++) | |
3c8d758a | 362 | hash[i] = le32_to_cpu(in[i]); |
8628e7c8 DK |
363 | } |
364 | ||
798eed5d | 365 | static int omap_sham_hw_init(struct omap_sham_dev *dd) |
8628e7c8 | 366 | { |
b359f034 | 367 | pm_runtime_get_sync(dd->dev); |
8628e7c8 | 368 | |
a929cbee | 369 | if (!test_bit(FLAGS_INIT, &dd->flags)) { |
a929cbee | 370 | set_bit(FLAGS_INIT, &dd->flags); |
798eed5d DK |
371 | dd->err = 0; |
372 | } | |
8628e7c8 | 373 | |
798eed5d DK |
374 | return 0; |
375 | } | |
376 | ||
0d373d60 | 377 | static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, |
798eed5d DK |
378 | int final, int dma) |
379 | { | |
380 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
381 | u32 val = length << 5, mask; | |
382 | ||
383 | if (likely(ctx->digcnt)) | |
0d373d60 | 384 | omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); |
8628e7c8 | 385 | |
0d373d60 | 386 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), |
8628e7c8 DK |
387 | SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), |
388 | SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); | |
389 | /* | |
390 | * Setting ALGO_CONST only for the first iteration | |
391 | * and CLOSE_HASH only for the last one. | |
392 | */ | |
0d373d60 | 393 | if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) |
8628e7c8 DK |
394 | val |= SHA_REG_CTRL_ALGO; |
395 | if (!ctx->digcnt) | |
396 | val |= SHA_REG_CTRL_ALGO_CONST; | |
397 | if (final) | |
398 | val |= SHA_REG_CTRL_CLOSE_HASH; | |
399 | ||
400 | mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | | |
401 | SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; | |
402 | ||
403 | omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); | |
8628e7c8 DK |
404 | } |
405 | ||
0d373d60 MG |
406 | static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) |
407 | { | |
408 | } | |
409 | ||
410 | static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) | |
411 | { | |
412 | return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); | |
413 | } | |
414 | ||
eaef7e3f LV |
415 | static int get_block_size(struct omap_sham_reqctx *ctx) |
416 | { | |
417 | int d; | |
418 | ||
419 | switch (ctx->flags & FLAGS_MODE_MASK) { | |
420 | case FLAGS_MODE_MD5: | |
421 | case FLAGS_MODE_SHA1: | |
422 | d = SHA1_BLOCK_SIZE; | |
423 | break; | |
424 | case FLAGS_MODE_SHA224: | |
425 | case FLAGS_MODE_SHA256: | |
426 | d = SHA256_BLOCK_SIZE; | |
427 | break; | |
428 | case FLAGS_MODE_SHA384: | |
429 | case FLAGS_MODE_SHA512: | |
430 | d = SHA512_BLOCK_SIZE; | |
431 | break; | |
432 | default: | |
433 | d = 0; | |
434 | } | |
435 | ||
436 | return d; | |
437 | } | |
438 | ||
0d373d60 MG |
439 | static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, |
440 | u32 *value, int count) | |
441 | { | |
442 | for (; count--; value++, offset += 4) | |
443 | omap_sham_write(dd, offset, *value); | |
444 | } | |
445 | ||
446 | static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, | |
447 | int final, int dma) | |
448 | { | |
449 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
450 | u32 val, mask; | |
451 | ||
452 | /* | |
453 | * Setting ALGO_CONST only for the first iteration and | |
454 | * CLOSE_HASH only for the last one. Note that flags mode bits | |
455 | * correspond to algorithm encoding in mode register. | |
456 | */ | |
eaef7e3f | 457 | val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); |
0d373d60 MG |
458 | if (!ctx->digcnt) { |
459 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); | |
460 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
461 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
eaef7e3f | 462 | int bs, nr_dr; |
0d373d60 MG |
463 | |
464 | val |= SHA_REG_MODE_ALGO_CONSTANT; | |
465 | ||
466 | if (ctx->flags & BIT(FLAGS_HMAC)) { | |
eaef7e3f LV |
467 | bs = get_block_size(ctx); |
468 | nr_dr = bs / (2 * sizeof(u32)); | |
0d373d60 | 469 | val |= SHA_REG_MODE_HMAC_KEY_PROC; |
eaef7e3f LV |
470 | omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0), |
471 | (u32 *)bctx->ipad, nr_dr); | |
472 | omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0), | |
473 | (u32 *)bctx->ipad + nr_dr, nr_dr); | |
474 | ctx->digcnt += bs; | |
0d373d60 MG |
475 | } |
476 | } | |
477 | ||
478 | if (final) { | |
479 | val |= SHA_REG_MODE_CLOSE_HASH; | |
480 | ||
481 | if (ctx->flags & BIT(FLAGS_HMAC)) | |
482 | val |= SHA_REG_MODE_HMAC_OUTER_HASH; | |
483 | } | |
484 | ||
485 | mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | | |
486 | SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | | |
487 | SHA_REG_MODE_HMAC_KEY_PROC; | |
488 | ||
489 | dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); | |
eaef7e3f | 490 | omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); |
0d373d60 MG |
491 | omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); |
492 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), | |
493 | SHA_REG_MASK_IT_EN | | |
494 | (dma ? SHA_REG_MASK_DMA_EN : 0), | |
495 | SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); | |
496 | } | |
497 | ||
498 | static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) | |
499 | { | |
eaef7e3f | 500 | omap_sham_write(dd, SHA_REG_LENGTH(dd), length); |
0d373d60 MG |
501 | } |
502 | ||
503 | static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) | |
504 | { | |
505 | return omap_sham_wait(dd, SHA_REG_IRQSTATUS, | |
506 | SHA_REG_IRQSTATUS_INPUT_RDY); | |
507 | } | |
508 | ||
8628e7c8 DK |
509 | static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf, |
510 | size_t length, int final) | |
511 | { | |
512 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
798eed5d | 513 | int count, len32; |
8628e7c8 DK |
514 | const u32 *buffer = (const u32 *)buf; |
515 | ||
516 | dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n", | |
517 | ctx->digcnt, length, final); | |
518 | ||
0d373d60 MG |
519 | dd->pdata->write_ctrl(dd, length, final, 0); |
520 | dd->pdata->trigger(dd, length); | |
8628e7c8 | 521 | |
3e133c8b DK |
522 | /* should be non-zero before next lines to disable clocks later */ |
523 | ctx->digcnt += length; | |
524 | ||
0d373d60 | 525 | if (dd->pdata->poll_irq(dd)) |
8628e7c8 DK |
526 | return -ETIMEDOUT; |
527 | ||
8628e7c8 | 528 | if (final) |
ed3ea9a8 | 529 | set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ |
8628e7c8 | 530 | |
6c63db82 DK |
531 | set_bit(FLAGS_CPU, &dd->flags); |
532 | ||
8628e7c8 DK |
533 | len32 = DIV_ROUND_UP(length, sizeof(u32)); |
534 | ||
535 | for (count = 0; count < len32; count++) | |
0d373d60 | 536 | omap_sham_write(dd, SHA_REG_DIN(dd, count), buffer[count]); |
8628e7c8 DK |
537 | |
538 | return -EINPROGRESS; | |
539 | } | |
540 | ||
dfd061d5 MG |
541 | static void omap_sham_dma_callback(void *param) |
542 | { | |
543 | struct omap_sham_dev *dd = param; | |
544 | ||
545 | set_bit(FLAGS_DMA_READY, &dd->flags); | |
546 | tasklet_schedule(&dd->done_task); | |
547 | } | |
dfd061d5 | 548 | |
8628e7c8 | 549 | static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr, |
dfd061d5 | 550 | size_t length, int final, int is_sg) |
8628e7c8 DK |
551 | { |
552 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
dfd061d5 MG |
553 | struct dma_async_tx_descriptor *tx; |
554 | struct dma_slave_config cfg; | |
555 | int len32, ret; | |
8628e7c8 DK |
556 | |
557 | dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n", | |
558 | ctx->digcnt, length, final); | |
8628e7c8 | 559 | |
dfd061d5 MG |
560 | memset(&cfg, 0, sizeof(cfg)); |
561 | ||
0d373d60 | 562 | cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); |
dfd061d5 MG |
563 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
564 | cfg.dst_maxburst = DST_MAXBURST; | |
565 | ||
566 | ret = dmaengine_slave_config(dd->dma_lch, &cfg); | |
567 | if (ret) { | |
568 | pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); | |
569 | return ret; | |
570 | } | |
571 | ||
572 | len32 = DIV_ROUND_UP(length, DMA_MIN) * DMA_MIN; | |
573 | ||
574 | if (is_sg) { | |
575 | /* | |
576 | * The SG entry passed in may not have the 'length' member | |
577 | * set correctly so use a local SG entry (sgl) with the | |
578 | * proper value for 'length' instead. If this is not done, | |
579 | * the dmaengine may try to DMA the incorrect amount of data. | |
580 | */ | |
581 | sg_init_table(&ctx->sgl, 1); | |
582 | ctx->sgl.page_link = ctx->sg->page_link; | |
583 | ctx->sgl.offset = ctx->sg->offset; | |
584 | sg_dma_len(&ctx->sgl) = len32; | |
585 | sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg); | |
586 | ||
587 | tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1, | |
588 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
589 | } else { | |
590 | tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32, | |
591 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
592 | } | |
8628e7c8 | 593 | |
dfd061d5 MG |
594 | if (!tx) { |
595 | dev_err(dd->dev, "prep_slave_sg/single() failed\n"); | |
596 | return -EINVAL; | |
597 | } | |
8628e7c8 | 598 | |
dfd061d5 MG |
599 | tx->callback = omap_sham_dma_callback; |
600 | tx->callback_param = dd; | |
8628e7c8 | 601 | |
0d373d60 | 602 | dd->pdata->write_ctrl(dd, length, final, 1); |
8628e7c8 DK |
603 | |
604 | ctx->digcnt += length; | |
605 | ||
606 | if (final) | |
ed3ea9a8 | 607 | set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ |
8628e7c8 | 608 | |
a929cbee | 609 | set_bit(FLAGS_DMA_ACTIVE, &dd->flags); |
8628e7c8 | 610 | |
dfd061d5 MG |
611 | dmaengine_submit(tx); |
612 | dma_async_issue_pending(dd->dma_lch); | |
8628e7c8 | 613 | |
0d373d60 | 614 | dd->pdata->trigger(dd, length); |
8628e7c8 DK |
615 | |
616 | return -EINPROGRESS; | |
617 | } | |
618 | ||
619 | static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx, | |
620 | const u8 *data, size_t length) | |
621 | { | |
622 | size_t count = min(length, ctx->buflen - ctx->bufcnt); | |
623 | ||
624 | count = min(count, ctx->total); | |
625 | if (count <= 0) | |
626 | return 0; | |
627 | memcpy(ctx->buffer + ctx->bufcnt, data, count); | |
628 | ctx->bufcnt += count; | |
629 | ||
630 | return count; | |
631 | } | |
632 | ||
633 | static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx) | |
634 | { | |
635 | size_t count; | |
636 | ||
637 | while (ctx->sg) { | |
638 | count = omap_sham_append_buffer(ctx, | |
639 | sg_virt(ctx->sg) + ctx->offset, | |
640 | ctx->sg->length - ctx->offset); | |
641 | if (!count) | |
642 | break; | |
643 | ctx->offset += count; | |
644 | ctx->total -= count; | |
645 | if (ctx->offset == ctx->sg->length) { | |
646 | ctx->sg = sg_next(ctx->sg); | |
647 | if (ctx->sg) | |
648 | ctx->offset = 0; | |
649 | else | |
650 | ctx->total = 0; | |
651 | } | |
652 | } | |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
798eed5d DK |
657 | static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd, |
658 | struct omap_sham_reqctx *ctx, | |
659 | size_t length, int final) | |
660 | { | |
dfd061d5 MG |
661 | int ret; |
662 | ||
798eed5d DK |
663 | ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen, |
664 | DMA_TO_DEVICE); | |
665 | if (dma_mapping_error(dd->dev, ctx->dma_addr)) { | |
666 | dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen); | |
667 | return -EINVAL; | |
668 | } | |
669 | ||
ea1fd224 | 670 | ctx->flags &= ~BIT(FLAGS_SG); |
887c883e | 671 | |
dfd061d5 | 672 | ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0); |
0d373d60 | 673 | if (ret != -EINPROGRESS) |
dfd061d5 MG |
674 | dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen, |
675 | DMA_TO_DEVICE); | |
676 | ||
677 | return ret; | |
798eed5d DK |
678 | } |
679 | ||
8628e7c8 DK |
680 | static int omap_sham_update_dma_slow(struct omap_sham_dev *dd) |
681 | { | |
682 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
683 | unsigned int final; | |
684 | size_t count; | |
685 | ||
8628e7c8 DK |
686 | omap_sham_append_sg(ctx); |
687 | ||
ea1fd224 | 688 | final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; |
8628e7c8 DK |
689 | |
690 | dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n", | |
691 | ctx->bufcnt, ctx->digcnt, final); | |
692 | ||
693 | if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) { | |
694 | count = ctx->bufcnt; | |
695 | ctx->bufcnt = 0; | |
798eed5d | 696 | return omap_sham_xmit_dma_map(dd, ctx, count, final); |
8628e7c8 DK |
697 | } |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
887c883e DK |
702 | /* Start address alignment */ |
703 | #define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32))) | |
704 | /* SHA1 block size alignment */ | |
eaef7e3f | 705 | #define SG_SA(sg, bs) (IS_ALIGNED(sg->length, bs)) |
887c883e DK |
706 | |
707 | static int omap_sham_update_dma_start(struct omap_sham_dev *dd) | |
8628e7c8 DK |
708 | { |
709 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
887c883e DK |
710 | unsigned int length, final, tail; |
711 | struct scatterlist *sg; | |
eaef7e3f | 712 | int ret, bs; |
887c883e DK |
713 | |
714 | if (!ctx->total) | |
715 | return 0; | |
716 | ||
717 | if (ctx->bufcnt || ctx->offset) | |
718 | return omap_sham_update_dma_slow(dd); | |
719 | ||
dfd061d5 MG |
720 | /* |
721 | * Don't use the sg interface when the transfer size is less | |
722 | * than the number of elements in a DMA frame. Otherwise, | |
723 | * the dmaengine infrastructure will calculate that it needs | |
724 | * to transfer 0 frames which ultimately fails. | |
725 | */ | |
726 | if (ctx->total < (DST_MAXBURST * sizeof(u32))) | |
727 | return omap_sham_update_dma_slow(dd); | |
dfd061d5 | 728 | |
887c883e DK |
729 | dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n", |
730 | ctx->digcnt, ctx->bufcnt, ctx->total); | |
731 | ||
732 | sg = ctx->sg; | |
eaef7e3f | 733 | bs = get_block_size(ctx); |
8628e7c8 | 734 | |
887c883e DK |
735 | if (!SG_AA(sg)) |
736 | return omap_sham_update_dma_slow(dd); | |
8628e7c8 | 737 | |
eaef7e3f LV |
738 | if (!sg_is_last(sg) && !SG_SA(sg, bs)) |
739 | /* size is not BLOCK_SIZE aligned */ | |
887c883e DK |
740 | return omap_sham_update_dma_slow(dd); |
741 | ||
742 | length = min(ctx->total, sg->length); | |
743 | ||
744 | if (sg_is_last(sg)) { | |
ea1fd224 | 745 | if (!(ctx->flags & BIT(FLAGS_FINUP))) { |
eaef7e3f LV |
746 | /* not last sg must be BLOCK_SIZE aligned */ |
747 | tail = length & (bs - 1); | |
887c883e DK |
748 | /* without finup() we need one block to close hash */ |
749 | if (!tail) | |
eaef7e3f | 750 | tail = bs; |
887c883e DK |
751 | length -= tail; |
752 | } | |
753 | } | |
8628e7c8 DK |
754 | |
755 | if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) { | |
756 | dev_err(dd->dev, "dma_map_sg error\n"); | |
757 | return -EINVAL; | |
758 | } | |
759 | ||
ea1fd224 | 760 | ctx->flags |= BIT(FLAGS_SG); |
887c883e | 761 | |
8628e7c8 | 762 | ctx->total -= length; |
887c883e DK |
763 | ctx->offset = length; /* offset where to start slow */ |
764 | ||
ea1fd224 | 765 | final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; |
8628e7c8 | 766 | |
dfd061d5 | 767 | ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1); |
0d373d60 | 768 | if (ret != -EINPROGRESS) |
dfd061d5 MG |
769 | dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); |
770 | ||
771 | return ret; | |
8628e7c8 DK |
772 | } |
773 | ||
774 | static int omap_sham_update_cpu(struct omap_sham_dev *dd) | |
775 | { | |
776 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
777 | int bufcnt; | |
778 | ||
779 | omap_sham_append_sg(ctx); | |
780 | bufcnt = ctx->bufcnt; | |
781 | ctx->bufcnt = 0; | |
782 | ||
783 | return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, 1); | |
784 | } | |
785 | ||
786 | static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) | |
787 | { | |
788 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
789 | ||
dfd061d5 | 790 | dmaengine_terminate_all(dd->dma_lch); |
dfd061d5 | 791 | |
ea1fd224 | 792 | if (ctx->flags & BIT(FLAGS_SG)) { |
8628e7c8 | 793 | dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); |
887c883e DK |
794 | if (ctx->sg->length == ctx->offset) { |
795 | ctx->sg = sg_next(ctx->sg); | |
796 | if (ctx->sg) | |
797 | ctx->offset = 0; | |
798 | } | |
799 | } else { | |
798eed5d DK |
800 | dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen, |
801 | DMA_TO_DEVICE); | |
887c883e | 802 | } |
8628e7c8 DK |
803 | |
804 | return 0; | |
805 | } | |
806 | ||
8628e7c8 DK |
807 | static int omap_sham_init(struct ahash_request *req) |
808 | { | |
809 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
810 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
811 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
812 | struct omap_sham_dev *dd = NULL, *tmp; | |
eaef7e3f | 813 | int bs = 0; |
8628e7c8 DK |
814 | |
815 | spin_lock_bh(&sham.lock); | |
816 | if (!tctx->dd) { | |
817 | list_for_each_entry(tmp, &sham.dev_list, list) { | |
818 | dd = tmp; | |
819 | break; | |
820 | } | |
821 | tctx->dd = dd; | |
822 | } else { | |
823 | dd = tctx->dd; | |
824 | } | |
825 | spin_unlock_bh(&sham.lock); | |
826 | ||
827 | ctx->dd = dd; | |
828 | ||
829 | ctx->flags = 0; | |
830 | ||
8628e7c8 DK |
831 | dev_dbg(dd->dev, "init: digest size: %d\n", |
832 | crypto_ahash_digestsize(tfm)); | |
833 | ||
0d373d60 MG |
834 | switch (crypto_ahash_digestsize(tfm)) { |
835 | case MD5_DIGEST_SIZE: | |
836 | ctx->flags |= FLAGS_MODE_MD5; | |
eaef7e3f | 837 | bs = SHA1_BLOCK_SIZE; |
0d373d60 MG |
838 | break; |
839 | case SHA1_DIGEST_SIZE: | |
840 | ctx->flags |= FLAGS_MODE_SHA1; | |
eaef7e3f | 841 | bs = SHA1_BLOCK_SIZE; |
0d373d60 | 842 | break; |
d20fb18b MG |
843 | case SHA224_DIGEST_SIZE: |
844 | ctx->flags |= FLAGS_MODE_SHA224; | |
eaef7e3f | 845 | bs = SHA224_BLOCK_SIZE; |
d20fb18b MG |
846 | break; |
847 | case SHA256_DIGEST_SIZE: | |
848 | ctx->flags |= FLAGS_MODE_SHA256; | |
eaef7e3f LV |
849 | bs = SHA256_BLOCK_SIZE; |
850 | break; | |
851 | case SHA384_DIGEST_SIZE: | |
852 | ctx->flags |= FLAGS_MODE_SHA384; | |
853 | bs = SHA384_BLOCK_SIZE; | |
854 | break; | |
855 | case SHA512_DIGEST_SIZE: | |
856 | ctx->flags |= FLAGS_MODE_SHA512; | |
857 | bs = SHA512_BLOCK_SIZE; | |
d20fb18b | 858 | break; |
0d373d60 | 859 | } |
8628e7c8 DK |
860 | |
861 | ctx->bufcnt = 0; | |
862 | ctx->digcnt = 0; | |
798eed5d | 863 | ctx->buflen = BUFLEN; |
8628e7c8 | 864 | |
ea1fd224 | 865 | if (tctx->flags & BIT(FLAGS_HMAC)) { |
0d373d60 MG |
866 | if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { |
867 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
868 | ||
eaef7e3f LV |
869 | memcpy(ctx->buffer, bctx->ipad, bs); |
870 | ctx->bufcnt = bs; | |
0d373d60 | 871 | } |
8628e7c8 | 872 | |
ea1fd224 | 873 | ctx->flags |= BIT(FLAGS_HMAC); |
8628e7c8 DK |
874 | } |
875 | ||
876 | return 0; | |
877 | ||
878 | } | |
879 | ||
880 | static int omap_sham_update_req(struct omap_sham_dev *dd) | |
881 | { | |
882 | struct ahash_request *req = dd->req; | |
883 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
884 | int err; | |
885 | ||
886 | dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n", | |
ea1fd224 | 887 | ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0); |
8628e7c8 | 888 | |
ea1fd224 | 889 | if (ctx->flags & BIT(FLAGS_CPU)) |
8628e7c8 | 890 | err = omap_sham_update_cpu(dd); |
8628e7c8 | 891 | else |
887c883e | 892 | err = omap_sham_update_dma_start(dd); |
8628e7c8 DK |
893 | |
894 | /* wait for dma completion before can take more data */ | |
895 | dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt); | |
896 | ||
897 | return err; | |
898 | } | |
899 | ||
900 | static int omap_sham_final_req(struct omap_sham_dev *dd) | |
901 | { | |
902 | struct ahash_request *req = dd->req; | |
903 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
904 | int err = 0, use_dma = 1; | |
905 | ||
dfd061d5 | 906 | if (ctx->bufcnt <= DMA_MIN) |
8628e7c8 DK |
907 | /* faster to handle last block with cpu */ |
908 | use_dma = 0; | |
909 | ||
910 | if (use_dma) | |
798eed5d | 911 | err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1); |
8628e7c8 DK |
912 | else |
913 | err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1); | |
914 | ||
915 | ctx->bufcnt = 0; | |
916 | ||
8628e7c8 DK |
917 | dev_dbg(dd->dev, "final_req: err: %d\n", err); |
918 | ||
919 | return err; | |
920 | } | |
921 | ||
bf362759 | 922 | static int omap_sham_finish_hmac(struct ahash_request *req) |
8628e7c8 DK |
923 | { |
924 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
925 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
926 | int bs = crypto_shash_blocksize(bctx->shash); | |
927 | int ds = crypto_shash_digestsize(bctx->shash); | |
928 | struct { | |
929 | struct shash_desc shash; | |
930 | char ctx[crypto_shash_descsize(bctx->shash)]; | |
931 | } desc; | |
932 | ||
933 | desc.shash.tfm = bctx->shash; | |
934 | desc.shash.flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */ | |
935 | ||
936 | return crypto_shash_init(&desc.shash) ?: | |
937 | crypto_shash_update(&desc.shash, bctx->opad, bs) ?: | |
bf362759 DK |
938 | crypto_shash_finup(&desc.shash, req->result, ds, req->result); |
939 | } | |
940 | ||
941 | static int omap_sham_finish(struct ahash_request *req) | |
942 | { | |
943 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
944 | struct omap_sham_dev *dd = ctx->dd; | |
945 | int err = 0; | |
946 | ||
947 | if (ctx->digcnt) { | |
948 | omap_sham_copy_ready_hash(req); | |
0d373d60 MG |
949 | if ((ctx->flags & BIT(FLAGS_HMAC)) && |
950 | !test_bit(FLAGS_AUTO_XOR, &dd->flags)) | |
bf362759 DK |
951 | err = omap_sham_finish_hmac(req); |
952 | } | |
953 | ||
954 | dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt); | |
955 | ||
956 | return err; | |
8628e7c8 DK |
957 | } |
958 | ||
959 | static void omap_sham_finish_req(struct ahash_request *req, int err) | |
960 | { | |
961 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
798eed5d | 962 | struct omap_sham_dev *dd = ctx->dd; |
8628e7c8 DK |
963 | |
964 | if (!err) { | |
0d373d60 | 965 | dd->pdata->copy_hash(req, 1); |
ed3ea9a8 | 966 | if (test_bit(FLAGS_FINAL, &dd->flags)) |
bf362759 | 967 | err = omap_sham_finish(req); |
3e133c8b | 968 | } else { |
ea1fd224 | 969 | ctx->flags |= BIT(FLAGS_ERROR); |
8628e7c8 DK |
970 | } |
971 | ||
0efd4d8a DK |
972 | /* atomic operation is not needed here */ |
973 | dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | | |
974 | BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); | |
b359f034 | 975 | |
e68af482 | 976 | pm_runtime_put(dd->dev); |
8628e7c8 DK |
977 | |
978 | if (req->base.complete) | |
979 | req->base.complete(&req->base, err); | |
6cb3ffe1 DK |
980 | |
981 | /* handle new request */ | |
982 | tasklet_schedule(&dd->done_task); | |
8628e7c8 DK |
983 | } |
984 | ||
a5d87237 DK |
985 | static int omap_sham_handle_queue(struct omap_sham_dev *dd, |
986 | struct ahash_request *req) | |
8628e7c8 | 987 | { |
6c39d116 | 988 | struct crypto_async_request *async_req, *backlog; |
8628e7c8 | 989 | struct omap_sham_reqctx *ctx; |
8628e7c8 | 990 | unsigned long flags; |
a5d87237 | 991 | int err = 0, ret = 0; |
8628e7c8 DK |
992 | |
993 | spin_lock_irqsave(&dd->lock, flags); | |
a5d87237 DK |
994 | if (req) |
995 | ret = ahash_enqueue_request(&dd->queue, req); | |
a929cbee | 996 | if (test_bit(FLAGS_BUSY, &dd->flags)) { |
a5d87237 DK |
997 | spin_unlock_irqrestore(&dd->lock, flags); |
998 | return ret; | |
999 | } | |
6c39d116 | 1000 | backlog = crypto_get_backlog(&dd->queue); |
8628e7c8 | 1001 | async_req = crypto_dequeue_request(&dd->queue); |
6c39d116 | 1002 | if (async_req) |
a929cbee | 1003 | set_bit(FLAGS_BUSY, &dd->flags); |
8628e7c8 DK |
1004 | spin_unlock_irqrestore(&dd->lock, flags); |
1005 | ||
1006 | if (!async_req) | |
a5d87237 | 1007 | return ret; |
8628e7c8 DK |
1008 | |
1009 | if (backlog) | |
1010 | backlog->complete(backlog, -EINPROGRESS); | |
1011 | ||
1012 | req = ahash_request_cast(async_req); | |
8628e7c8 | 1013 | dd->req = req; |
8628e7c8 DK |
1014 | ctx = ahash_request_ctx(req); |
1015 | ||
1016 | dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", | |
1017 | ctx->op, req->nbytes); | |
1018 | ||
798eed5d DK |
1019 | err = omap_sham_hw_init(dd); |
1020 | if (err) | |
1021 | goto err1; | |
1022 | ||
798eed5d | 1023 | if (ctx->digcnt) |
8628e7c8 | 1024 | /* request has changed - restore hash */ |
0d373d60 | 1025 | dd->pdata->copy_hash(req, 0); |
8628e7c8 DK |
1026 | |
1027 | if (ctx->op == OP_UPDATE) { | |
1028 | err = omap_sham_update_req(dd); | |
ea1fd224 | 1029 | if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP))) |
8628e7c8 DK |
1030 | /* no final() after finup() */ |
1031 | err = omap_sham_final_req(dd); | |
1032 | } else if (ctx->op == OP_FINAL) { | |
1033 | err = omap_sham_final_req(dd); | |
1034 | } | |
798eed5d | 1035 | err1: |
6cb3ffe1 | 1036 | if (err != -EINPROGRESS) |
8628e7c8 DK |
1037 | /* done_task will not finish it, so do it here */ |
1038 | omap_sham_finish_req(req, err); | |
8628e7c8 DK |
1039 | |
1040 | dev_dbg(dd->dev, "exit, err: %d\n", err); | |
1041 | ||
a5d87237 | 1042 | return ret; |
8628e7c8 DK |
1043 | } |
1044 | ||
1045 | static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) | |
1046 | { | |
1047 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1048 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1049 | struct omap_sham_dev *dd = tctx->dd; | |
8628e7c8 DK |
1050 | |
1051 | ctx->op = op; | |
1052 | ||
a5d87237 | 1053 | return omap_sham_handle_queue(dd, req); |
8628e7c8 DK |
1054 | } |
1055 | ||
1056 | static int omap_sham_update(struct ahash_request *req) | |
1057 | { | |
1058 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
eaef7e3f | 1059 | int bs = get_block_size(ctx); |
8628e7c8 DK |
1060 | |
1061 | if (!req->nbytes) | |
1062 | return 0; | |
1063 | ||
1064 | ctx->total = req->nbytes; | |
1065 | ctx->sg = req->src; | |
1066 | ctx->offset = 0; | |
1067 | ||
ea1fd224 | 1068 | if (ctx->flags & BIT(FLAGS_FINUP)) { |
8628e7c8 DK |
1069 | if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) { |
1070 | /* | |
1071 | * OMAP HW accel works only with buffers >= 9 | |
1072 | * will switch to bypass in final() | |
1073 | * final has the same request and data | |
1074 | */ | |
1075 | omap_sham_append_sg(ctx); | |
1076 | return 0; | |
eaef7e3f | 1077 | } else if (ctx->bufcnt + ctx->total <= bs) { |
887c883e DK |
1078 | /* |
1079 | * faster to use CPU for short transfers | |
1080 | */ | |
ea1fd224 | 1081 | ctx->flags |= BIT(FLAGS_CPU); |
8628e7c8 | 1082 | } |
887c883e | 1083 | } else if (ctx->bufcnt + ctx->total < ctx->buflen) { |
8628e7c8 DK |
1084 | omap_sham_append_sg(ctx); |
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | return omap_sham_enqueue(req, OP_UPDATE); | |
1089 | } | |
1090 | ||
1091 | static int omap_sham_shash_digest(struct crypto_shash *shash, u32 flags, | |
1092 | const u8 *data, unsigned int len, u8 *out) | |
1093 | { | |
1094 | struct { | |
1095 | struct shash_desc shash; | |
1096 | char ctx[crypto_shash_descsize(shash)]; | |
1097 | } desc; | |
1098 | ||
1099 | desc.shash.tfm = shash; | |
1100 | desc.shash.flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP; | |
1101 | ||
1102 | return crypto_shash_digest(&desc.shash, data, len, out); | |
1103 | } | |
1104 | ||
1105 | static int omap_sham_final_shash(struct ahash_request *req) | |
1106 | { | |
1107 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1108 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1109 | ||
1110 | return omap_sham_shash_digest(tctx->fallback, req->base.flags, | |
1111 | ctx->buffer, ctx->bufcnt, req->result); | |
1112 | } | |
1113 | ||
1114 | static int omap_sham_final(struct ahash_request *req) | |
1115 | { | |
1116 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
8628e7c8 | 1117 | |
ea1fd224 | 1118 | ctx->flags |= BIT(FLAGS_FINUP); |
8628e7c8 | 1119 | |
ea1fd224 | 1120 | if (ctx->flags & BIT(FLAGS_ERROR)) |
bf362759 | 1121 | return 0; /* uncompleted hash is not needed */ |
8628e7c8 | 1122 | |
bf362759 DK |
1123 | /* OMAP HW accel works only with buffers >= 9 */ |
1124 | /* HMAC is always >= 9 because ipad == block size */ | |
1125 | if ((ctx->digcnt + ctx->bufcnt) < 9) | |
1126 | return omap_sham_final_shash(req); | |
1127 | else if (ctx->bufcnt) | |
1128 | return omap_sham_enqueue(req, OP_FINAL); | |
8628e7c8 | 1129 | |
bf362759 DK |
1130 | /* copy ready hash (+ finalize hmac) */ |
1131 | return omap_sham_finish(req); | |
8628e7c8 DK |
1132 | } |
1133 | ||
1134 | static int omap_sham_finup(struct ahash_request *req) | |
1135 | { | |
1136 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1137 | int err1, err2; | |
1138 | ||
ea1fd224 | 1139 | ctx->flags |= BIT(FLAGS_FINUP); |
8628e7c8 DK |
1140 | |
1141 | err1 = omap_sham_update(req); | |
455e3389 | 1142 | if (err1 == -EINPROGRESS || err1 == -EBUSY) |
8628e7c8 DK |
1143 | return err1; |
1144 | /* | |
1145 | * final() has to be always called to cleanup resources | |
1146 | * even if udpate() failed, except EINPROGRESS | |
1147 | */ | |
1148 | err2 = omap_sham_final(req); | |
1149 | ||
1150 | return err1 ?: err2; | |
1151 | } | |
1152 | ||
1153 | static int omap_sham_digest(struct ahash_request *req) | |
1154 | { | |
1155 | return omap_sham_init(req) ?: omap_sham_finup(req); | |
1156 | } | |
1157 | ||
1158 | static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, | |
1159 | unsigned int keylen) | |
1160 | { | |
1161 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
1162 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
1163 | int bs = crypto_shash_blocksize(bctx->shash); | |
1164 | int ds = crypto_shash_digestsize(bctx->shash); | |
0d373d60 | 1165 | struct omap_sham_dev *dd = NULL, *tmp; |
8628e7c8 | 1166 | int err, i; |
0d373d60 MG |
1167 | |
1168 | spin_lock_bh(&sham.lock); | |
1169 | if (!tctx->dd) { | |
1170 | list_for_each_entry(tmp, &sham.dev_list, list) { | |
1171 | dd = tmp; | |
1172 | break; | |
1173 | } | |
1174 | tctx->dd = dd; | |
1175 | } else { | |
1176 | dd = tctx->dd; | |
1177 | } | |
1178 | spin_unlock_bh(&sham.lock); | |
1179 | ||
8628e7c8 DK |
1180 | err = crypto_shash_setkey(tctx->fallback, key, keylen); |
1181 | if (err) | |
1182 | return err; | |
1183 | ||
1184 | if (keylen > bs) { | |
1185 | err = omap_sham_shash_digest(bctx->shash, | |
1186 | crypto_shash_get_flags(bctx->shash), | |
1187 | key, keylen, bctx->ipad); | |
1188 | if (err) | |
1189 | return err; | |
1190 | keylen = ds; | |
1191 | } else { | |
1192 | memcpy(bctx->ipad, key, keylen); | |
1193 | } | |
1194 | ||
1195 | memset(bctx->ipad + keylen, 0, bs - keylen); | |
8628e7c8 | 1196 | |
0d373d60 MG |
1197 | if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { |
1198 | memcpy(bctx->opad, bctx->ipad, bs); | |
1199 | ||
1200 | for (i = 0; i < bs; i++) { | |
1201 | bctx->ipad[i] ^= 0x36; | |
1202 | bctx->opad[i] ^= 0x5c; | |
1203 | } | |
8628e7c8 DK |
1204 | } |
1205 | ||
1206 | return err; | |
1207 | } | |
1208 | ||
1209 | static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) | |
1210 | { | |
1211 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); | |
1212 | const char *alg_name = crypto_tfm_alg_name(tfm); | |
1213 | ||
1214 | /* Allocate a fallback and abort if it failed. */ | |
1215 | tctx->fallback = crypto_alloc_shash(alg_name, 0, | |
1216 | CRYPTO_ALG_NEED_FALLBACK); | |
1217 | if (IS_ERR(tctx->fallback)) { | |
1218 | pr_err("omap-sham: fallback driver '%s' " | |
1219 | "could not be loaded.\n", alg_name); | |
1220 | return PTR_ERR(tctx->fallback); | |
1221 | } | |
1222 | ||
1223 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
798eed5d | 1224 | sizeof(struct omap_sham_reqctx) + BUFLEN); |
8628e7c8 DK |
1225 | |
1226 | if (alg_base) { | |
1227 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
ea1fd224 | 1228 | tctx->flags |= BIT(FLAGS_HMAC); |
8628e7c8 DK |
1229 | bctx->shash = crypto_alloc_shash(alg_base, 0, |
1230 | CRYPTO_ALG_NEED_FALLBACK); | |
1231 | if (IS_ERR(bctx->shash)) { | |
1232 | pr_err("omap-sham: base driver '%s' " | |
1233 | "could not be loaded.\n", alg_base); | |
1234 | crypto_free_shash(tctx->fallback); | |
1235 | return PTR_ERR(bctx->shash); | |
1236 | } | |
1237 | ||
1238 | } | |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | static int omap_sham_cra_init(struct crypto_tfm *tfm) | |
1244 | { | |
1245 | return omap_sham_cra_init_alg(tfm, NULL); | |
1246 | } | |
1247 | ||
1248 | static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) | |
1249 | { | |
1250 | return omap_sham_cra_init_alg(tfm, "sha1"); | |
1251 | } | |
1252 | ||
d20fb18b MG |
1253 | static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm) |
1254 | { | |
1255 | return omap_sham_cra_init_alg(tfm, "sha224"); | |
1256 | } | |
1257 | ||
1258 | static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm) | |
1259 | { | |
1260 | return omap_sham_cra_init_alg(tfm, "sha256"); | |
1261 | } | |
1262 | ||
8628e7c8 DK |
1263 | static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) |
1264 | { | |
1265 | return omap_sham_cra_init_alg(tfm, "md5"); | |
1266 | } | |
1267 | ||
eaef7e3f LV |
1268 | static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm) |
1269 | { | |
1270 | return omap_sham_cra_init_alg(tfm, "sha384"); | |
1271 | } | |
1272 | ||
1273 | static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm) | |
1274 | { | |
1275 | return omap_sham_cra_init_alg(tfm, "sha512"); | |
1276 | } | |
1277 | ||
8628e7c8 DK |
1278 | static void omap_sham_cra_exit(struct crypto_tfm *tfm) |
1279 | { | |
1280 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); | |
1281 | ||
1282 | crypto_free_shash(tctx->fallback); | |
1283 | tctx->fallback = NULL; | |
1284 | ||
ea1fd224 | 1285 | if (tctx->flags & BIT(FLAGS_HMAC)) { |
8628e7c8 DK |
1286 | struct omap_sham_hmac_ctx *bctx = tctx->base; |
1287 | crypto_free_shash(bctx->shash); | |
1288 | } | |
1289 | } | |
1290 | ||
d20fb18b | 1291 | static struct ahash_alg algs_sha1_md5[] = { |
8628e7c8 DK |
1292 | { |
1293 | .init = omap_sham_init, | |
1294 | .update = omap_sham_update, | |
1295 | .final = omap_sham_final, | |
1296 | .finup = omap_sham_finup, | |
1297 | .digest = omap_sham_digest, | |
1298 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
1299 | .halg.base = { | |
1300 | .cra_name = "sha1", | |
1301 | .cra_driver_name = "omap-sha1", | |
1302 | .cra_priority = 100, | |
1303 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
d912bb76 | 1304 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1305 | CRYPTO_ALG_ASYNC | |
1306 | CRYPTO_ALG_NEED_FALLBACK, | |
1307 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1308 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
1309 | .cra_alignmask = 0, | |
1310 | .cra_module = THIS_MODULE, | |
1311 | .cra_init = omap_sham_cra_init, | |
1312 | .cra_exit = omap_sham_cra_exit, | |
1313 | } | |
1314 | }, | |
1315 | { | |
1316 | .init = omap_sham_init, | |
1317 | .update = omap_sham_update, | |
1318 | .final = omap_sham_final, | |
1319 | .finup = omap_sham_finup, | |
1320 | .digest = omap_sham_digest, | |
1321 | .halg.digestsize = MD5_DIGEST_SIZE, | |
1322 | .halg.base = { | |
1323 | .cra_name = "md5", | |
1324 | .cra_driver_name = "omap-md5", | |
1325 | .cra_priority = 100, | |
1326 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
d912bb76 | 1327 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1328 | CRYPTO_ALG_ASYNC | |
1329 | CRYPTO_ALG_NEED_FALLBACK, | |
1330 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1331 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
798eed5d | 1332 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1333 | .cra_module = THIS_MODULE, |
1334 | .cra_init = omap_sham_cra_init, | |
1335 | .cra_exit = omap_sham_cra_exit, | |
1336 | } | |
1337 | }, | |
1338 | { | |
1339 | .init = omap_sham_init, | |
1340 | .update = omap_sham_update, | |
1341 | .final = omap_sham_final, | |
1342 | .finup = omap_sham_finup, | |
1343 | .digest = omap_sham_digest, | |
1344 | .setkey = omap_sham_setkey, | |
1345 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
1346 | .halg.base = { | |
1347 | .cra_name = "hmac(sha1)", | |
1348 | .cra_driver_name = "omap-hmac-sha1", | |
1349 | .cra_priority = 100, | |
1350 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
d912bb76 | 1351 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1352 | CRYPTO_ALG_ASYNC | |
1353 | CRYPTO_ALG_NEED_FALLBACK, | |
1354 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1355 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1356 | sizeof(struct omap_sham_hmac_ctx), | |
798eed5d | 1357 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1358 | .cra_module = THIS_MODULE, |
1359 | .cra_init = omap_sham_cra_sha1_init, | |
1360 | .cra_exit = omap_sham_cra_exit, | |
1361 | } | |
1362 | }, | |
1363 | { | |
1364 | .init = omap_sham_init, | |
1365 | .update = omap_sham_update, | |
1366 | .final = omap_sham_final, | |
1367 | .finup = omap_sham_finup, | |
1368 | .digest = omap_sham_digest, | |
1369 | .setkey = omap_sham_setkey, | |
1370 | .halg.digestsize = MD5_DIGEST_SIZE, | |
1371 | .halg.base = { | |
1372 | .cra_name = "hmac(md5)", | |
1373 | .cra_driver_name = "omap-hmac-md5", | |
1374 | .cra_priority = 100, | |
1375 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
d912bb76 | 1376 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1377 | CRYPTO_ALG_ASYNC | |
1378 | CRYPTO_ALG_NEED_FALLBACK, | |
1379 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1380 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1381 | sizeof(struct omap_sham_hmac_ctx), | |
798eed5d | 1382 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1383 | .cra_module = THIS_MODULE, |
1384 | .cra_init = omap_sham_cra_md5_init, | |
1385 | .cra_exit = omap_sham_cra_exit, | |
1386 | } | |
1387 | } | |
1388 | }; | |
1389 | ||
d20fb18b MG |
1390 | /* OMAP4 has some algs in addition to what OMAP2 has */ |
1391 | static struct ahash_alg algs_sha224_sha256[] = { | |
1392 | { | |
1393 | .init = omap_sham_init, | |
1394 | .update = omap_sham_update, | |
1395 | .final = omap_sham_final, | |
1396 | .finup = omap_sham_finup, | |
1397 | .digest = omap_sham_digest, | |
1398 | .halg.digestsize = SHA224_DIGEST_SIZE, | |
1399 | .halg.base = { | |
1400 | .cra_name = "sha224", | |
1401 | .cra_driver_name = "omap-sha224", | |
1402 | .cra_priority = 100, | |
1403 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
1404 | CRYPTO_ALG_ASYNC | | |
1405 | CRYPTO_ALG_NEED_FALLBACK, | |
1406 | .cra_blocksize = SHA224_BLOCK_SIZE, | |
1407 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
1408 | .cra_alignmask = 0, | |
1409 | .cra_module = THIS_MODULE, | |
1410 | .cra_init = omap_sham_cra_init, | |
1411 | .cra_exit = omap_sham_cra_exit, | |
1412 | } | |
1413 | }, | |
1414 | { | |
1415 | .init = omap_sham_init, | |
1416 | .update = omap_sham_update, | |
1417 | .final = omap_sham_final, | |
1418 | .finup = omap_sham_finup, | |
1419 | .digest = omap_sham_digest, | |
1420 | .halg.digestsize = SHA256_DIGEST_SIZE, | |
1421 | .halg.base = { | |
1422 | .cra_name = "sha256", | |
1423 | .cra_driver_name = "omap-sha256", | |
1424 | .cra_priority = 100, | |
1425 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
1426 | CRYPTO_ALG_ASYNC | | |
1427 | CRYPTO_ALG_NEED_FALLBACK, | |
1428 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
1429 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
1430 | .cra_alignmask = 0, | |
1431 | .cra_module = THIS_MODULE, | |
1432 | .cra_init = omap_sham_cra_init, | |
1433 | .cra_exit = omap_sham_cra_exit, | |
1434 | } | |
1435 | }, | |
1436 | { | |
1437 | .init = omap_sham_init, | |
1438 | .update = omap_sham_update, | |
1439 | .final = omap_sham_final, | |
1440 | .finup = omap_sham_finup, | |
1441 | .digest = omap_sham_digest, | |
1442 | .setkey = omap_sham_setkey, | |
1443 | .halg.digestsize = SHA224_DIGEST_SIZE, | |
1444 | .halg.base = { | |
1445 | .cra_name = "hmac(sha224)", | |
1446 | .cra_driver_name = "omap-hmac-sha224", | |
1447 | .cra_priority = 100, | |
1448 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
1449 | CRYPTO_ALG_ASYNC | | |
1450 | CRYPTO_ALG_NEED_FALLBACK, | |
1451 | .cra_blocksize = SHA224_BLOCK_SIZE, | |
1452 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1453 | sizeof(struct omap_sham_hmac_ctx), | |
1454 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1455 | .cra_module = THIS_MODULE, | |
1456 | .cra_init = omap_sham_cra_sha224_init, | |
1457 | .cra_exit = omap_sham_cra_exit, | |
1458 | } | |
1459 | }, | |
1460 | { | |
1461 | .init = omap_sham_init, | |
1462 | .update = omap_sham_update, | |
1463 | .final = omap_sham_final, | |
1464 | .finup = omap_sham_finup, | |
1465 | .digest = omap_sham_digest, | |
1466 | .setkey = omap_sham_setkey, | |
1467 | .halg.digestsize = SHA256_DIGEST_SIZE, | |
1468 | .halg.base = { | |
1469 | .cra_name = "hmac(sha256)", | |
1470 | .cra_driver_name = "omap-hmac-sha256", | |
1471 | .cra_priority = 100, | |
1472 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
1473 | CRYPTO_ALG_ASYNC | | |
1474 | CRYPTO_ALG_NEED_FALLBACK, | |
1475 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
1476 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1477 | sizeof(struct omap_sham_hmac_ctx), | |
1478 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1479 | .cra_module = THIS_MODULE, | |
1480 | .cra_init = omap_sham_cra_sha256_init, | |
1481 | .cra_exit = omap_sham_cra_exit, | |
1482 | } | |
1483 | }, | |
1484 | }; | |
1485 | ||
eaef7e3f LV |
1486 | static struct ahash_alg algs_sha384_sha512[] = { |
1487 | { | |
1488 | .init = omap_sham_init, | |
1489 | .update = omap_sham_update, | |
1490 | .final = omap_sham_final, | |
1491 | .finup = omap_sham_finup, | |
1492 | .digest = omap_sham_digest, | |
1493 | .halg.digestsize = SHA384_DIGEST_SIZE, | |
1494 | .halg.base = { | |
1495 | .cra_name = "sha384", | |
1496 | .cra_driver_name = "omap-sha384", | |
1497 | .cra_priority = 100, | |
1498 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
1499 | CRYPTO_ALG_ASYNC | | |
1500 | CRYPTO_ALG_NEED_FALLBACK, | |
1501 | .cra_blocksize = SHA384_BLOCK_SIZE, | |
1502 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
1503 | .cra_alignmask = 0, | |
1504 | .cra_module = THIS_MODULE, | |
1505 | .cra_init = omap_sham_cra_init, | |
1506 | .cra_exit = omap_sham_cra_exit, | |
1507 | } | |
1508 | }, | |
1509 | { | |
1510 | .init = omap_sham_init, | |
1511 | .update = omap_sham_update, | |
1512 | .final = omap_sham_final, | |
1513 | .finup = omap_sham_finup, | |
1514 | .digest = omap_sham_digest, | |
1515 | .halg.digestsize = SHA512_DIGEST_SIZE, | |
1516 | .halg.base = { | |
1517 | .cra_name = "sha512", | |
1518 | .cra_driver_name = "omap-sha512", | |
1519 | .cra_priority = 100, | |
1520 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
1521 | CRYPTO_ALG_ASYNC | | |
1522 | CRYPTO_ALG_NEED_FALLBACK, | |
1523 | .cra_blocksize = SHA512_BLOCK_SIZE, | |
1524 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
1525 | .cra_alignmask = 0, | |
1526 | .cra_module = THIS_MODULE, | |
1527 | .cra_init = omap_sham_cra_init, | |
1528 | .cra_exit = omap_sham_cra_exit, | |
1529 | } | |
1530 | }, | |
1531 | { | |
1532 | .init = omap_sham_init, | |
1533 | .update = omap_sham_update, | |
1534 | .final = omap_sham_final, | |
1535 | .finup = omap_sham_finup, | |
1536 | .digest = omap_sham_digest, | |
1537 | .setkey = omap_sham_setkey, | |
1538 | .halg.digestsize = SHA384_DIGEST_SIZE, | |
1539 | .halg.base = { | |
1540 | .cra_name = "hmac(sha384)", | |
1541 | .cra_driver_name = "omap-hmac-sha384", | |
1542 | .cra_priority = 100, | |
1543 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
1544 | CRYPTO_ALG_ASYNC | | |
1545 | CRYPTO_ALG_NEED_FALLBACK, | |
1546 | .cra_blocksize = SHA384_BLOCK_SIZE, | |
1547 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1548 | sizeof(struct omap_sham_hmac_ctx), | |
1549 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1550 | .cra_module = THIS_MODULE, | |
1551 | .cra_init = omap_sham_cra_sha384_init, | |
1552 | .cra_exit = omap_sham_cra_exit, | |
1553 | } | |
1554 | }, | |
1555 | { | |
1556 | .init = omap_sham_init, | |
1557 | .update = omap_sham_update, | |
1558 | .final = omap_sham_final, | |
1559 | .finup = omap_sham_finup, | |
1560 | .digest = omap_sham_digest, | |
1561 | .setkey = omap_sham_setkey, | |
1562 | .halg.digestsize = SHA512_DIGEST_SIZE, | |
1563 | .halg.base = { | |
1564 | .cra_name = "hmac(sha512)", | |
1565 | .cra_driver_name = "omap-hmac-sha512", | |
1566 | .cra_priority = 100, | |
1567 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
1568 | CRYPTO_ALG_ASYNC | | |
1569 | CRYPTO_ALG_NEED_FALLBACK, | |
1570 | .cra_blocksize = SHA512_BLOCK_SIZE, | |
1571 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1572 | sizeof(struct omap_sham_hmac_ctx), | |
1573 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1574 | .cra_module = THIS_MODULE, | |
1575 | .cra_init = omap_sham_cra_sha512_init, | |
1576 | .cra_exit = omap_sham_cra_exit, | |
1577 | } | |
1578 | }, | |
1579 | }; | |
1580 | ||
8628e7c8 DK |
1581 | static void omap_sham_done_task(unsigned long data) |
1582 | { | |
1583 | struct omap_sham_dev *dd = (struct omap_sham_dev *)data; | |
6c63db82 | 1584 | int err = 0; |
8628e7c8 | 1585 | |
6cb3ffe1 DK |
1586 | if (!test_bit(FLAGS_BUSY, &dd->flags)) { |
1587 | omap_sham_handle_queue(dd, NULL); | |
1588 | return; | |
1589 | } | |
1590 | ||
6c63db82 DK |
1591 | if (test_bit(FLAGS_CPU, &dd->flags)) { |
1592 | if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) | |
1593 | goto finish; | |
1594 | } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { | |
1595 | if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { | |
1596 | omap_sham_update_dma_stop(dd); | |
1597 | if (dd->err) { | |
1598 | err = dd->err; | |
1599 | goto finish; | |
1600 | } | |
1601 | } | |
1602 | if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { | |
1603 | /* hash or semi-hash ready */ | |
1604 | clear_bit(FLAGS_DMA_READY, &dd->flags); | |
887c883e | 1605 | err = omap_sham_update_dma_start(dd); |
6c63db82 DK |
1606 | if (err != -EINPROGRESS) |
1607 | goto finish; | |
1608 | } | |
8628e7c8 DK |
1609 | } |
1610 | ||
6c63db82 | 1611 | return; |
3e133c8b | 1612 | |
6c63db82 DK |
1613 | finish: |
1614 | dev_dbg(dd->dev, "update done: err: %d\n", err); | |
1615 | /* finish curent request */ | |
1616 | omap_sham_finish_req(dd->req, err); | |
8628e7c8 DK |
1617 | } |
1618 | ||
0d373d60 MG |
1619 | static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) |
1620 | { | |
1621 | if (!test_bit(FLAGS_BUSY, &dd->flags)) { | |
1622 | dev_warn(dd->dev, "Interrupt when no active requests.\n"); | |
1623 | } else { | |
1624 | set_bit(FLAGS_OUTPUT_READY, &dd->flags); | |
1625 | tasklet_schedule(&dd->done_task); | |
1626 | } | |
1627 | ||
1628 | return IRQ_HANDLED; | |
1629 | } | |
1630 | ||
1631 | static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) | |
8628e7c8 DK |
1632 | { |
1633 | struct omap_sham_dev *dd = dev_id; | |
8628e7c8 | 1634 | |
ed3ea9a8 | 1635 | if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) |
8628e7c8 DK |
1636 | /* final -> allow device to go to power-saving mode */ |
1637 | omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); | |
1638 | ||
1639 | omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, | |
1640 | SHA_REG_CTRL_OUTPUT_READY); | |
1641 | omap_sham_read(dd, SHA_REG_CTRL); | |
1642 | ||
0d373d60 MG |
1643 | return omap_sham_irq_common(dd); |
1644 | } | |
cd3f1d54 | 1645 | |
0d373d60 MG |
1646 | static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) |
1647 | { | |
1648 | struct omap_sham_dev *dd = dev_id; | |
8628e7c8 | 1649 | |
0d373d60 MG |
1650 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); |
1651 | ||
1652 | return omap_sham_irq_common(dd); | |
8628e7c8 DK |
1653 | } |
1654 | ||
d20fb18b MG |
1655 | static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = { |
1656 | { | |
1657 | .algs_list = algs_sha1_md5, | |
1658 | .size = ARRAY_SIZE(algs_sha1_md5), | |
1659 | }, | |
1660 | }; | |
1661 | ||
0d373d60 | 1662 | static const struct omap_sham_pdata omap_sham_pdata_omap2 = { |
d20fb18b MG |
1663 | .algs_info = omap_sham_algs_info_omap2, |
1664 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2), | |
0d373d60 MG |
1665 | .flags = BIT(FLAGS_BE32_SHA1), |
1666 | .digest_size = SHA1_DIGEST_SIZE, | |
1667 | .copy_hash = omap_sham_copy_hash_omap2, | |
1668 | .write_ctrl = omap_sham_write_ctrl_omap2, | |
1669 | .trigger = omap_sham_trigger_omap2, | |
1670 | .poll_irq = omap_sham_poll_irq_omap2, | |
1671 | .intr_hdlr = omap_sham_irq_omap2, | |
1672 | .idigest_ofs = 0x00, | |
1673 | .din_ofs = 0x1c, | |
1674 | .digcnt_ofs = 0x14, | |
1675 | .rev_ofs = 0x5c, | |
1676 | .mask_ofs = 0x60, | |
1677 | .sysstatus_ofs = 0x64, | |
1678 | .major_mask = 0xf0, | |
1679 | .major_shift = 4, | |
1680 | .minor_mask = 0x0f, | |
1681 | .minor_shift = 0, | |
1682 | }; | |
1683 | ||
03feec9c | 1684 | #ifdef CONFIG_OF |
d20fb18b MG |
1685 | static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = { |
1686 | { | |
1687 | .algs_list = algs_sha1_md5, | |
1688 | .size = ARRAY_SIZE(algs_sha1_md5), | |
1689 | }, | |
1690 | { | |
1691 | .algs_list = algs_sha224_sha256, | |
1692 | .size = ARRAY_SIZE(algs_sha224_sha256), | |
1693 | }, | |
1694 | }; | |
1695 | ||
0d373d60 | 1696 | static const struct omap_sham_pdata omap_sham_pdata_omap4 = { |
d20fb18b MG |
1697 | .algs_info = omap_sham_algs_info_omap4, |
1698 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4), | |
0d373d60 MG |
1699 | .flags = BIT(FLAGS_AUTO_XOR), |
1700 | .digest_size = SHA256_DIGEST_SIZE, | |
1701 | .copy_hash = omap_sham_copy_hash_omap4, | |
1702 | .write_ctrl = omap_sham_write_ctrl_omap4, | |
1703 | .trigger = omap_sham_trigger_omap4, | |
1704 | .poll_irq = omap_sham_poll_irq_omap4, | |
1705 | .intr_hdlr = omap_sham_irq_omap4, | |
1706 | .idigest_ofs = 0x020, | |
eaef7e3f | 1707 | .odigest_ofs = 0x0, |
0d373d60 MG |
1708 | .din_ofs = 0x080, |
1709 | .digcnt_ofs = 0x040, | |
1710 | .rev_ofs = 0x100, | |
1711 | .mask_ofs = 0x110, | |
1712 | .sysstatus_ofs = 0x114, | |
eaef7e3f LV |
1713 | .mode_ofs = 0x44, |
1714 | .length_ofs = 0x48, | |
0d373d60 MG |
1715 | .major_mask = 0x0700, |
1716 | .major_shift = 8, | |
1717 | .minor_mask = 0x003f, | |
1718 | .minor_shift = 0, | |
1719 | }; | |
1720 | ||
7d7c704d LV |
1721 | static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = { |
1722 | { | |
1723 | .algs_list = algs_sha1_md5, | |
1724 | .size = ARRAY_SIZE(algs_sha1_md5), | |
1725 | }, | |
1726 | { | |
1727 | .algs_list = algs_sha224_sha256, | |
1728 | .size = ARRAY_SIZE(algs_sha224_sha256), | |
1729 | }, | |
1730 | { | |
1731 | .algs_list = algs_sha384_sha512, | |
1732 | .size = ARRAY_SIZE(algs_sha384_sha512), | |
1733 | }, | |
1734 | }; | |
1735 | ||
1736 | static const struct omap_sham_pdata omap_sham_pdata_omap5 = { | |
1737 | .algs_info = omap_sham_algs_info_omap5, | |
1738 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5), | |
1739 | .flags = BIT(FLAGS_AUTO_XOR), | |
1740 | .digest_size = SHA512_DIGEST_SIZE, | |
1741 | .copy_hash = omap_sham_copy_hash_omap4, | |
1742 | .write_ctrl = omap_sham_write_ctrl_omap4, | |
1743 | .trigger = omap_sham_trigger_omap4, | |
1744 | .poll_irq = omap_sham_poll_irq_omap4, | |
1745 | .intr_hdlr = omap_sham_irq_omap4, | |
1746 | .idigest_ofs = 0x240, | |
1747 | .odigest_ofs = 0x200, | |
1748 | .din_ofs = 0x080, | |
1749 | .digcnt_ofs = 0x280, | |
1750 | .rev_ofs = 0x100, | |
1751 | .mask_ofs = 0x110, | |
1752 | .sysstatus_ofs = 0x114, | |
1753 | .mode_ofs = 0x284, | |
1754 | .length_ofs = 0x288, | |
1755 | .major_mask = 0x0700, | |
1756 | .major_shift = 8, | |
1757 | .minor_mask = 0x003f, | |
1758 | .minor_shift = 0, | |
1759 | }; | |
1760 | ||
03feec9c MG |
1761 | static const struct of_device_id omap_sham_of_match[] = { |
1762 | { | |
1763 | .compatible = "ti,omap2-sham", | |
0d373d60 MG |
1764 | .data = &omap_sham_pdata_omap2, |
1765 | }, | |
1766 | { | |
1767 | .compatible = "ti,omap4-sham", | |
1768 | .data = &omap_sham_pdata_omap4, | |
03feec9c | 1769 | }, |
7d7c704d LV |
1770 | { |
1771 | .compatible = "ti,omap5-sham", | |
1772 | .data = &omap_sham_pdata_omap5, | |
1773 | }, | |
03feec9c MG |
1774 | {}, |
1775 | }; | |
1776 | MODULE_DEVICE_TABLE(of, omap_sham_of_match); | |
1777 | ||
1778 | static int omap_sham_get_res_of(struct omap_sham_dev *dd, | |
1779 | struct device *dev, struct resource *res) | |
8628e7c8 | 1780 | { |
03feec9c MG |
1781 | struct device_node *node = dev->of_node; |
1782 | const struct of_device_id *match; | |
1783 | int err = 0; | |
8628e7c8 | 1784 | |
03feec9c MG |
1785 | match = of_match_device(of_match_ptr(omap_sham_of_match), dev); |
1786 | if (!match) { | |
1787 | dev_err(dev, "no compatible OF match\n"); | |
1788 | err = -EINVAL; | |
1789 | goto err; | |
3e133c8b DK |
1790 | } |
1791 | ||
03feec9c MG |
1792 | err = of_address_to_resource(node, 0, res); |
1793 | if (err < 0) { | |
1794 | dev_err(dev, "can't translate OF node address\n"); | |
1795 | err = -EINVAL; | |
1796 | goto err; | |
1797 | } | |
1798 | ||
1799 | dd->irq = of_irq_to_resource(node, 0, NULL); | |
1800 | if (!dd->irq) { | |
1801 | dev_err(dev, "can't translate OF irq value\n"); | |
1802 | err = -EINVAL; | |
1803 | goto err; | |
1804 | } | |
1805 | ||
1806 | dd->dma = -1; /* Dummy value that's unused */ | |
0d373d60 | 1807 | dd->pdata = match->data; |
03feec9c MG |
1808 | |
1809 | err: | |
1810 | return err; | |
8628e7c8 | 1811 | } |
03feec9c | 1812 | #else |
c3c3b329 MG |
1813 | static const struct of_device_id omap_sham_of_match[] = { |
1814 | {}, | |
1815 | }; | |
8628e7c8 | 1816 | |
c3c3b329 | 1817 | static int omap_sham_get_res_of(struct omap_sham_dev *dd, |
03feec9c | 1818 | struct device *dev, struct resource *res) |
8628e7c8 | 1819 | { |
03feec9c MG |
1820 | return -EINVAL; |
1821 | } | |
1822 | #endif | |
8628e7c8 | 1823 | |
03feec9c MG |
1824 | static int omap_sham_get_res_pdev(struct omap_sham_dev *dd, |
1825 | struct platform_device *pdev, struct resource *res) | |
1826 | { | |
1827 | struct device *dev = &pdev->dev; | |
1828 | struct resource *r; | |
1829 | int err = 0; | |
8628e7c8 | 1830 | |
03feec9c MG |
1831 | /* Get the base address */ |
1832 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1833 | if (!r) { | |
1834 | dev_err(dev, "no MEM resource info\n"); | |
1835 | err = -ENODEV; | |
1836 | goto err; | |
8628e7c8 | 1837 | } |
03feec9c | 1838 | memcpy(res, r, sizeof(*res)); |
584db6a1 | 1839 | |
03feec9c MG |
1840 | /* Get the IRQ */ |
1841 | dd->irq = platform_get_irq(pdev, 0); | |
1842 | if (dd->irq < 0) { | |
1843 | dev_err(dev, "no IRQ resource info\n"); | |
1844 | err = dd->irq; | |
1845 | goto err; | |
1846 | } | |
8628e7c8 | 1847 | |
03feec9c MG |
1848 | /* Get the DMA */ |
1849 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1850 | if (!r) { | |
1851 | dev_err(dev, "no DMA resource info\n"); | |
1852 | err = -ENODEV; | |
1853 | goto err; | |
8628e7c8 | 1854 | } |
03feec9c MG |
1855 | dd->dma = r->start; |
1856 | ||
0d373d60 MG |
1857 | /* Only OMAP2/3 can be non-DT */ |
1858 | dd->pdata = &omap_sham_pdata_omap2; | |
1859 | ||
03feec9c MG |
1860 | err: |
1861 | return err; | |
8628e7c8 DK |
1862 | } |
1863 | ||
49cfe4db | 1864 | static int omap_sham_probe(struct platform_device *pdev) |
8628e7c8 DK |
1865 | { |
1866 | struct omap_sham_dev *dd; | |
1867 | struct device *dev = &pdev->dev; | |
03feec9c | 1868 | struct resource res; |
dfd061d5 | 1869 | dma_cap_mask_t mask; |
8628e7c8 | 1870 | int err, i, j; |
0d373d60 | 1871 | u32 rev; |
8628e7c8 | 1872 | |
7a7e4b73 | 1873 | dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL); |
8628e7c8 DK |
1874 | if (dd == NULL) { |
1875 | dev_err(dev, "unable to alloc data struct.\n"); | |
1876 | err = -ENOMEM; | |
1877 | goto data_err; | |
1878 | } | |
1879 | dd->dev = dev; | |
1880 | platform_set_drvdata(pdev, dd); | |
1881 | ||
1882 | INIT_LIST_HEAD(&dd->list); | |
1883 | spin_lock_init(&dd->lock); | |
1884 | tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd); | |
8628e7c8 DK |
1885 | crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); |
1886 | ||
03feec9c MG |
1887 | err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) : |
1888 | omap_sham_get_res_pdev(dd, pdev, &res); | |
1889 | if (err) | |
7a7e4b73 | 1890 | goto data_err; |
8628e7c8 | 1891 | |
30862281 LN |
1892 | dd->io_base = devm_ioremap_resource(dev, &res); |
1893 | if (IS_ERR(dd->io_base)) { | |
1894 | err = PTR_ERR(dd->io_base); | |
7a7e4b73 | 1895 | goto data_err; |
8628e7c8 | 1896 | } |
03feec9c | 1897 | dd->phys_base = res.start; |
8628e7c8 | 1898 | |
0de9c387 LV |
1899 | err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr, |
1900 | IRQF_TRIGGER_NONE, dev_name(dev), dd); | |
8628e7c8 | 1901 | if (err) { |
0de9c387 LV |
1902 | dev_err(dev, "unable to request irq %d, err = %d\n", |
1903 | dd->irq, err); | |
7a7e4b73 | 1904 | goto data_err; |
8628e7c8 DK |
1905 | } |
1906 | ||
dfd061d5 MG |
1907 | dma_cap_zero(mask); |
1908 | dma_cap_set(DMA_SLAVE, mask); | |
8628e7c8 | 1909 | |
0e87e73f MG |
1910 | dd->dma_lch = dma_request_slave_channel_compat(mask, omap_dma_filter_fn, |
1911 | &dd->dma, dev, "rx"); | |
dfd061d5 MG |
1912 | if (!dd->dma_lch) { |
1913 | dev_err(dev, "unable to obtain RX DMA engine channel %u\n", | |
03feec9c | 1914 | dd->dma); |
dfd061d5 | 1915 | err = -ENXIO; |
7a7e4b73 | 1916 | goto data_err; |
8628e7c8 DK |
1917 | } |
1918 | ||
0d373d60 | 1919 | dd->flags |= dd->pdata->flags; |
8628e7c8 | 1920 | |
b359f034 MG |
1921 | pm_runtime_enable(dev); |
1922 | pm_runtime_get_sync(dev); | |
0d373d60 MG |
1923 | rev = omap_sham_read(dd, SHA_REG_REV(dd)); |
1924 | pm_runtime_put_sync(&pdev->dev); | |
8628e7c8 | 1925 | |
8628e7c8 | 1926 | dev_info(dev, "hw accel on OMAP rev %u.%u\n", |
0d373d60 MG |
1927 | (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, |
1928 | (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); | |
8628e7c8 DK |
1929 | |
1930 | spin_lock(&sham.lock); | |
1931 | list_add_tail(&dd->list, &sham.dev_list); | |
1932 | spin_unlock(&sham.lock); | |
1933 | ||
d20fb18b MG |
1934 | for (i = 0; i < dd->pdata->algs_info_size; i++) { |
1935 | for (j = 0; j < dd->pdata->algs_info[i].size; j++) { | |
1936 | err = crypto_register_ahash( | |
1937 | &dd->pdata->algs_info[i].algs_list[j]); | |
1938 | if (err) | |
1939 | goto err_algs; | |
1940 | ||
1941 | dd->pdata->algs_info[i].registered++; | |
1942 | } | |
8628e7c8 DK |
1943 | } |
1944 | ||
1945 | return 0; | |
1946 | ||
1947 | err_algs: | |
d20fb18b MG |
1948 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
1949 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
1950 | crypto_unregister_ahash( | |
1951 | &dd->pdata->algs_info[i].algs_list[j]); | |
b359f034 | 1952 | pm_runtime_disable(dev); |
dfd061d5 | 1953 | dma_release_channel(dd->dma_lch); |
8628e7c8 DK |
1954 | data_err: |
1955 | dev_err(dev, "initialization failed.\n"); | |
1956 | ||
1957 | return err; | |
1958 | } | |
1959 | ||
49cfe4db | 1960 | static int omap_sham_remove(struct platform_device *pdev) |
8628e7c8 DK |
1961 | { |
1962 | static struct omap_sham_dev *dd; | |
d20fb18b | 1963 | int i, j; |
8628e7c8 DK |
1964 | |
1965 | dd = platform_get_drvdata(pdev); | |
1966 | if (!dd) | |
1967 | return -ENODEV; | |
1968 | spin_lock(&sham.lock); | |
1969 | list_del(&dd->list); | |
1970 | spin_unlock(&sham.lock); | |
d20fb18b MG |
1971 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
1972 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
1973 | crypto_unregister_ahash( | |
1974 | &dd->pdata->algs_info[i].algs_list[j]); | |
8628e7c8 | 1975 | tasklet_kill(&dd->done_task); |
b359f034 | 1976 | pm_runtime_disable(&pdev->dev); |
dfd061d5 | 1977 | dma_release_channel(dd->dma_lch); |
8628e7c8 DK |
1978 | |
1979 | return 0; | |
1980 | } | |
1981 | ||
3b3f4400 MG |
1982 | #ifdef CONFIG_PM_SLEEP |
1983 | static int omap_sham_suspend(struct device *dev) | |
1984 | { | |
1985 | pm_runtime_put_sync(dev); | |
1986 | return 0; | |
1987 | } | |
1988 | ||
1989 | static int omap_sham_resume(struct device *dev) | |
1990 | { | |
1991 | pm_runtime_get_sync(dev); | |
1992 | return 0; | |
1993 | } | |
1994 | #endif | |
1995 | ||
1996 | static const struct dev_pm_ops omap_sham_pm_ops = { | |
1997 | SET_SYSTEM_SLEEP_PM_OPS(omap_sham_suspend, omap_sham_resume) | |
1998 | }; | |
1999 | ||
8628e7c8 DK |
2000 | static struct platform_driver omap_sham_driver = { |
2001 | .probe = omap_sham_probe, | |
2002 | .remove = omap_sham_remove, | |
2003 | .driver = { | |
2004 | .name = "omap-sham", | |
2005 | .owner = THIS_MODULE, | |
3b3f4400 | 2006 | .pm = &omap_sham_pm_ops, |
03feec9c | 2007 | .of_match_table = omap_sham_of_match, |
8628e7c8 DK |
2008 | }, |
2009 | }; | |
2010 | ||
02613702 | 2011 | module_platform_driver(omap_sham_driver); |
8628e7c8 DK |
2012 | |
2013 | MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); | |
2014 | MODULE_LICENSE("GPL v2"); | |
2015 | MODULE_AUTHOR("Dmitry Kasatkin"); |