[mirror_ubuntu-bionic-kernel.git] / drivers / crypto / padlock-sha.c

/*
 * Cryptographic API.
 *
 * Support for VIA PadLock hardware crypto engine.
 *
 * Copyright (c) 2006  Michal Ludvig <michal@logix.cz>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <crypto/internal/hash.h>
#include <crypto/padlock.h>
#include <crypto/sha.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/scatterlist.h>
#include <asm/cpu_device_id.h>
#include <asm/fpu/api.h>

struct padlock_sha_desc {
	struct shash_desc fallback;
};

struct padlock_sha_ctx {
	struct crypto_shash *fallback;
};

static int padlock_sha_init(struct shash_desc *desc)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);

	dctx->fallback.tfm = ctx->fallback;
	dctx->fallback.flags = desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP;
	return crypto_shash_init(&dctx->fallback);
}

static int padlock_sha_update(struct shash_desc *desc,
			      const u8 *data, unsigned int length)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);

	dctx->fallback.flags = desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP;
	return crypto_shash_update(&dctx->fallback, data, length);
}

static int padlock_sha_export(struct shash_desc *desc, void *out)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);

	return crypto_shash_export(&dctx->fallback, out);
}

static int padlock_sha_import(struct shash_desc *desc, const void *in)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);

	dctx->fallback.tfm = ctx->fallback;
	dctx->fallback.flags = desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP;
	return crypto_shash_import(&dctx->fallback, in);
}

static inline void padlock_output_block(uint32_t *src,
		 	uint32_t *dst, size_t count)
{
	while (count--)
		*dst++ = swab32(*src++);
}

static int padlock_sha1_finup(struct shash_desc *desc, const u8 *in,
			      unsigned int count, u8 *out)
{
	/* We can't store directly to *out as it may be unaligned. */
	/* BTW Don't reduce the buffer size below 128 Bytes!
	 *     PadLock microcode needs it that big. */
	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct sha1_state state;
	unsigned int space;
	unsigned int leftover;
	int err;

	dctx->fallback.flags = desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP;
	err = crypto_shash_export(&dctx->fallback, &state);
	if (err)
		goto out;

	if (state.count + count > ULONG_MAX)
		return crypto_shash_finup(&dctx->fallback, in, count, out);

	leftover = ((state.count - 1) & (SHA1_BLOCK_SIZE - 1)) + 1;
	space =  SHA1_BLOCK_SIZE - leftover;
	if (space) {
		if (count > space) {
			err = crypto_shash_update(&dctx->fallback, in, space) ?:
			      crypto_shash_export(&dctx->fallback, &state);
			if (err)
				goto out;
			count -= space;
			in += space;
		} else {
			memcpy(state.buffer + leftover, in, count);
			in = state.buffer;
			count += leftover;
			state.count &= ~(SHA1_BLOCK_SIZE - 1);
		}
	}

	memcpy(result, &state.state, SHA1_DIGEST_SIZE);

	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8" /* rep xsha1 */
		      : \
		      : "c"((unsigned long)state.count + count), \
			"a"((unsigned long)state.count), \
			"S"(in), "D"(result));

	padlock_output_block((uint32_t *)result, (uint32_t *)out, 5);

out:
	return err;
}

static int padlock_sha1_final(struct shash_desc *desc, u8 *out)
{
	u8 buf[4];

	return padlock_sha1_finup(desc, buf, 0, out);
}

static int padlock_sha256_finup(struct shash_desc *desc, const u8 *in,
				unsigned int count, u8 *out)
{
	/* We can't store directly to *out as it may be unaligned. */
	/* BTW Don't reduce the buffer size below 128 Bytes!
	 *     PadLock microcode needs it that big. */
	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct sha256_state state;
	unsigned int space;
	unsigned int leftover;
	int err;

	dctx->fallback.flags = desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP;
	err = crypto_shash_export(&dctx->fallback, &state);
	if (err)
		goto out;

	if (state.count + count > ULONG_MAX)
		return crypto_shash_finup(&dctx->fallback, in, count, out);

	leftover = ((state.count - 1) & (SHA256_BLOCK_SIZE - 1)) + 1;
	space =  SHA256_BLOCK_SIZE - leftover;
	if (space) {
		if (count > space) {
			err = crypto_shash_update(&dctx->fallback, in, space) ?:
			      crypto_shash_export(&dctx->fallback, &state);
			if (err)
				goto out;
			count -= space;
			in += space;
		} else {
			memcpy(state.buf + leftover, in, count);
			in = state.buf;
			count += leftover;
			state.count &= ~(SHA1_BLOCK_SIZE - 1);
		}
	}

	memcpy(result, &state.state, SHA256_DIGEST_SIZE);

	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0" /* rep xsha256 */
		      : \
		      : "c"((unsigned long)state.count + count), \
			"a"((unsigned long)state.count), \
			"S"(in), "D"(result));

	padlock_output_block((uint32_t *)result, (uint32_t *)out, 8);

out:
	return err;
}

static int padlock_sha256_final(struct shash_desc *desc, u8 *out)
{
	u8 buf[4];

	return padlock_sha256_finup(desc, buf, 0, out);
}

static int padlock_cra_init(struct crypto_tfm *tfm)
{
	struct crypto_shash *hash = __crypto_shash_cast(tfm);
	const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
	struct padlock_sha_ctx *ctx = crypto_tfm_ctx(tfm);
	struct crypto_shash *fallback_tfm;
	int err = -ENOMEM;

	/* Allocate a fallback and abort if it failed. */
	fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
					  CRYPTO_ALG_NEED_FALLBACK);
	if (IS_ERR(fallback_tfm)) {
		printk(KERN_WARNING PFX "Fallback driver '%s' could not be loaded!\n",
		       fallback_driver_name);
		err = PTR_ERR(fallback_tfm);
		goto out;
	}

	ctx->fallback = fallback_tfm;
	hash->descsize += crypto_shash_descsize(fallback_tfm);
	return 0;

out:
	return err;
}

static void padlock_cra_exit(struct crypto_tfm *tfm)
{
	struct padlock_sha_ctx *ctx = crypto_tfm_ctx(tfm);

	crypto_free_shash(ctx->fallback);
}

static struct shash_alg sha1_alg = {
	.digestsize	=	SHA1_DIGEST_SIZE,
	.init   	= 	padlock_sha_init,
	.update 	=	padlock_sha_update,
	.finup  	=	padlock_sha1_finup,
	.final  	=	padlock_sha1_final,
	.export		=	padlock_sha_export,
	.import		=	padlock_sha_import,
	.descsize	=	sizeof(struct padlock_sha_desc),
	.statesize	=	sizeof(struct sha1_state),
	.base		=	{
		.cra_name		=	"sha1",
		.cra_driver_name	=	"sha1-padlock",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_flags		=	CRYPTO_ALG_TYPE_SHASH |
						CRYPTO_ALG_NEED_FALLBACK,
		.cra_blocksize		=	SHA1_BLOCK_SIZE,
		.cra_ctxsize		=	sizeof(struct padlock_sha_ctx),
		.cra_module		=	THIS_MODULE,
		.cra_init		=	padlock_cra_init,
		.cra_exit		=	padlock_cra_exit,
	}
};

static struct shash_alg sha256_alg = {
	.digestsize	=	SHA256_DIGEST_SIZE,
	.init   	= 	padlock_sha_init,
	.update 	=	padlock_sha_update,
	.finup  	=	padlock_sha256_finup,
	.final  	=	padlock_sha256_final,
	.export		=	padlock_sha_export,
	.import		=	padlock_sha_import,
	.descsize	=	sizeof(struct padlock_sha_desc),
	.statesize	=	sizeof(struct sha256_state),
	.base		=	{
		.cra_name		=	"sha256",
		.cra_driver_name	=	"sha256-padlock",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_flags		=	CRYPTO_ALG_TYPE_SHASH |
						CRYPTO_ALG_NEED_FALLBACK,
		.cra_blocksize		=	SHA256_BLOCK_SIZE,
		.cra_ctxsize		=	sizeof(struct padlock_sha_ctx),
		.cra_module		=	THIS_MODULE,
		.cra_init		=	padlock_cra_init,
		.cra_exit		=	padlock_cra_exit,
	}
};

/* Add two shash_alg instance for hardware-implemented *
* multiple-parts hash supported by VIA Nano Processor.*/
static int padlock_sha1_init_nano(struct shash_desc *desc)
{
	struct sha1_state *sctx = shash_desc_ctx(desc);

	*sctx = (struct sha1_state){
		.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
	};

	return 0;
}

static int padlock_sha1_update_nano(struct shash_desc *desc,
			const u8 *data,	unsigned int len)
{
	struct sha1_state *sctx = shash_desc_ctx(desc);
	unsigned int partial, done;
	const u8 *src;
	/*The PHE require the out buffer must 128 bytes and 16-bytes aligned*/
	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

	partial = sctx->count & 0x3f;
	sctx->count += len;
	done = 0;
	src = data;
	memcpy(dst, (u8 *)(sctx->state), SHA1_DIGEST_SIZE);

	if ((partial + len) >= SHA1_BLOCK_SIZE) {

		/* Append the bytes in state's buffer to a block to handle */
		if (partial) {
			done = -partial;
			memcpy(sctx->buffer + partial, data,
				done + SHA1_BLOCK_SIZE);
			src = sctx->buffer;
			asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
			: "+S"(src), "+D"(dst) \
			: "a"((long)-1), "c"((unsigned long)1));
			done += SHA1_BLOCK_SIZE;
			src = data + done;
		}

		/* Process the left bytes from the input data */
		if (len - done >= SHA1_BLOCK_SIZE) {
			asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
			: "+S"(src), "+D"(dst)
			: "a"((long)-1),
			"c"((unsigned long)((len - done) / SHA1_BLOCK_SIZE)));
			done += ((len - done) - (len - done) % SHA1_BLOCK_SIZE);
			src = data + done;
		}
		partial = 0;
	}
	memcpy((u8 *)(sctx->state), dst, SHA1_DIGEST_SIZE);
	memcpy(sctx->buffer + partial, src, len - done);

	return 0;
}

static int padlock_sha1_final_nano(struct shash_desc *desc, u8 *out)
{
	struct sha1_state *state = (struct sha1_state *)shash_desc_ctx(desc);
	unsigned int partial, padlen;
	__be64 bits;
	static const u8 padding[64] = { 0x80, };

	bits = cpu_to_be64(state->count << 3);

	/* Pad out to 56 mod 64 */
	partial = state->count & 0x3f;
	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	padlock_sha1_update_nano(desc, padding, padlen);

	/* Append length field bytes */
	padlock_sha1_update_nano(desc, (const u8 *)&bits, sizeof(bits));

	/* Swap to output */
	padlock_output_block((uint32_t *)(state->state), (uint32_t *)out, 5);

	return 0;
}

static int padlock_sha256_init_nano(struct shash_desc *desc)
{
	struct sha256_state *sctx = shash_desc_ctx(desc);

	*sctx = (struct sha256_state){
		.state = { SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, \
				SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7},
	};

	return 0;
}

static int padlock_sha256_update_nano(struct shash_desc *desc, const u8 *data,
			  unsigned int len)
{
	struct sha256_state *sctx = shash_desc_ctx(desc);
	unsigned int partial, done;
	const u8 *src;
	/*The PHE require the out buffer must 128 bytes and 16-bytes aligned*/
	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

	partial = sctx->count & 0x3f;
	sctx->count += len;
	done = 0;
	src = data;
	memcpy(dst, (u8 *)(sctx->state), SHA256_DIGEST_SIZE);

	if ((partial + len) >= SHA256_BLOCK_SIZE) {

		/* Append the bytes in state's buffer to a block to handle */
		if (partial) {
			done = -partial;
			memcpy(sctx->buf + partial, data,
				done + SHA256_BLOCK_SIZE);
			src = sctx->buf;
			asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
			: "+S"(src), "+D"(dst)
			: "a"((long)-1), "c"((unsigned long)1));
			done += SHA256_BLOCK_SIZE;
			src = data + done;
		}

		/* Process the left bytes from input data*/
		if (len - done >= SHA256_BLOCK_SIZE) {
			asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
			: "+S"(src), "+D"(dst)
			: "a"((long)-1),
			"c"((unsigned long)((len - done) / 64)));
			done += ((len - done) - (len - done) % 64);
			src = data + done;
		}
		partial = 0;
	}
	memcpy((u8 *)(sctx->state), dst, SHA256_DIGEST_SIZE);
	memcpy(sctx->buf + partial, src, len - done);

	return 0;
}

static int padlock_sha256_final_nano(struct shash_desc *desc, u8 *out)
{
	struct sha256_state *state =
		(struct sha256_state *)shash_desc_ctx(desc);
	unsigned int partial, padlen;
	__be64 bits;
	static const u8 padding[64] = { 0x80, };

	bits = cpu_to_be64(state->count << 3);

	/* Pad out to 56 mod 64 */
	partial = state->count & 0x3f;
	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	padlock_sha256_update_nano(desc, padding, padlen);

	/* Append length field bytes */
	padlock_sha256_update_nano(desc, (const u8 *)&bits, sizeof(bits));

	/* Swap to output */
	padlock_output_block((uint32_t *)(state->state), (uint32_t *)out, 8);

	return 0;
}

static int padlock_sha_export_nano(struct shash_desc *desc,
				void *out)
{
	int statesize = crypto_shash_statesize(desc->tfm);
	void *sctx = shash_desc_ctx(desc);

	memcpy(out, sctx, statesize);
	return 0;
}

static int padlock_sha_import_nano(struct shash_desc *desc,
				const void *in)
{
	int statesize = crypto_shash_statesize(desc->tfm);
	void *sctx = shash_desc_ctx(desc);

	memcpy(sctx, in, statesize);
	return 0;
}

static struct shash_alg sha1_alg_nano = {
	.digestsize	=	SHA1_DIGEST_SIZE,
	.init		=	padlock_sha1_init_nano,
	.update		=	padlock_sha1_update_nano,
	.final		=	padlock_sha1_final_nano,
	.export		=	padlock_sha_export_nano,
	.import		=	padlock_sha_import_nano,
	.descsize	=	sizeof(struct sha1_state),
	.statesize	=	sizeof(struct sha1_state),
	.base		=	{
		.cra_name		=	"sha1",
		.cra_driver_name	=	"sha1-padlock-nano",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_flags		=	CRYPTO_ALG_TYPE_SHASH,
		.cra_blocksize		=	SHA1_BLOCK_SIZE,
		.cra_module		=	THIS_MODULE,
	}
};

static struct shash_alg sha256_alg_nano = {
	.digestsize	=	SHA256_DIGEST_SIZE,
	.init		=	padlock_sha256_init_nano,
	.update		=	padlock_sha256_update_nano,
	.final		=	padlock_sha256_final_nano,
	.export		=	padlock_sha_export_nano,
	.import		=	padlock_sha_import_nano,
	.descsize	=	sizeof(struct sha256_state),
	.statesize	=	sizeof(struct sha256_state),
	.base		=	{
		.cra_name		=	"sha256",
		.cra_driver_name	=	"sha256-padlock-nano",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_flags		=	CRYPTO_ALG_TYPE_SHASH,
		.cra_blocksize		=	SHA256_BLOCK_SIZE,
		.cra_module		=	THIS_MODULE,
	}
};

static struct x86_cpu_id padlock_sha_ids[] = {
	X86_FEATURE_MATCH(X86_FEATURE_PHE),
	{}
};
MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids);

static int __init padlock_init(void)
{
	int rc = -ENODEV;
	struct cpuinfo_x86 *c = &cpu_data(0);
	struct shash_alg *sha1;
	struct shash_alg *sha256;

	if (!x86_match_cpu(padlock_sha_ids) || !boot_cpu_has(X86_FEATURE_PHE_EN))
		return -ENODEV;

	/* Register the newly added algorithm module if on *
	* VIA Nano processor, or else just do as before */
	if (c->x86_model < 0x0f) {
		sha1 = &sha1_alg;
		sha256 = &sha256_alg;
	} else {
		sha1 = &sha1_alg_nano;
		sha256 = &sha256_alg_nano;
	}

	rc = crypto_register_shash(sha1);
	if (rc)
		goto out;

	rc = crypto_register_shash(sha256);
	if (rc)
		goto out_unreg1;

	printk(KERN_NOTICE PFX "Using VIA PadLock ACE for SHA1/SHA256 algorithms.\n");

	return 0;

out_unreg1:
	crypto_unregister_shash(sha1);

out:
	printk(KERN_ERR PFX "VIA PadLock SHA1/SHA256 initialization failed.\n");
	return rc;
}

static void __exit padlock_fini(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);

	if (c->x86_model >= 0x0f) {
		crypto_unregister_shash(&sha1_alg_nano);
		crypto_unregister_shash(&sha256_alg_nano);
	} else {
		crypto_unregister_shash(&sha1_alg);
		crypto_unregister_shash(&sha256_alg);
	}
}

module_init(padlock_init);
module_exit(padlock_fini);

MODULE_DESCRIPTION("VIA PadLock SHA1/SHA256 algorithms support.");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Michal Ludvig");

MODULE_ALIAS_CRYPTO("sha1-all");
MODULE_ALIAS_CRYPTO("sha256-all");
MODULE_ALIAS_CRYPTO("sha1-padlock");
MODULE_ALIAS_CRYPTO("sha256-padlock");
Commit	Line	Data
6c833275 ML	1	/*
	2	* Cryptographic API.
	3	*
	4	* Support for VIA PadLock hardware crypto engine.
	5	*
	6	* Copyright (c) 2006 Michal Ludvig <michal@logix.cz>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	*/
	14
7d024608	15	#include <crypto/internal/hash.h>
21493088	16	#include <crypto/padlock.h>
5265eeb2	17	#include <crypto/sha.h>
6010439f	18	#include <linux/err.h>
6c833275 ML	19	#include <linux/module.h>
	20	#include <linux/init.h>
	21	#include <linux/errno.h>
6c833275 ML	22	#include <linux/interrupt.h>
	23	#include <linux/kernel.h>
	24	#include <linux/scatterlist.h>
3bd391f0	25	#include <asm/cpu_device_id.h>
df6b35f4	26	#include <asm/fpu/api.h>
4c6ab3ee	27
bbbee467 HX	28	struct padlock_sha_desc {
bbbee467 HX	29	struct shash_desc fallback;
6c833275 ML	30	};
6c833275 ML	31
bbbee467 HX	32	struct padlock_sha_ctx {
	33	struct crypto_shash *fallback;
	34	};
6c833275	35
bbbee467	36	static int padlock_sha_init(struct shash_desc *desc)
6c833275	37	{
bbbee467 HX	38	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
bbbee467 HX	39	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);
6c833275	40
bbbee467 HX	41	dctx->fallback.tfm = ctx->fallback;
	42	dctx->fallback.flags = desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP;
	43	return crypto_shash_init(&dctx->fallback);
6c833275 ML	44	}
6c833275 ML	45
bbbee467 HX	46	static int padlock_sha_update(struct shash_desc *desc,
bbbee467 HX	47	const u8 *data, unsigned int length)
6c833275	48	{
bbbee467	49	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
6c833275	50
bbbee467 HX	51	dctx->fallback.flags = desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP;
bbbee467 HX	52	return crypto_shash_update(&dctx->fallback, data, length);
6c833275 ML	53	}
6c833275 ML	54
a8d7ac27 HX	55	static int padlock_sha_export(struct shash_desc desc, void out)
	56	{
	57	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	58
	59	return crypto_shash_export(&dctx->fallback, out);
	60	}
	61
	62	static int padlock_sha_import(struct shash_desc desc, const void in)
	63	{
	64	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	65	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);
	66
	67	dctx->fallback.tfm = ctx->fallback;
	68	dctx->fallback.flags = desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP;
	69	return crypto_shash_import(&dctx->fallback, in);
	70	}
	71
6c833275 ML	72	static inline void padlock_output_block(uint32_t *src,
	73	uint32_t *dst, size_t count)
	74	{
	75	while (count--)
	76	dst++ = swab32(src++);
	77	}
	78
bbbee467 HX	79	static int padlock_sha1_finup(struct shash_desc desc, const u8 in,
bbbee467 HX	80	unsigned int count, u8 *out)
6c833275 ML	81	{
	82	/* We can't store directly to out as it may be unaligned. /
	83	/* BTW Don't reduce the buffer size below 128 Bytes!
	84	* PadLock microcode needs it that big. */
4c6ab3ee HX	85	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	86	((aligned(STACK_ALIGN)));
	87	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
bbbee467 HX	88	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	89	struct sha1_state state;
	90	unsigned int space;
	91	unsigned int leftover;
bbbee467 HX	92	int err;
	93
	94	dctx->fallback.flags = desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP;
	95	err = crypto_shash_export(&dctx->fallback, &state);
	96	if (err)
	97	goto out;
	98
	99	if (state.count + count > ULONG_MAX)
	100	return crypto_shash_finup(&dctx->fallback, in, count, out);
	101
	102	leftover = ((state.count - 1) & (SHA1_BLOCK_SIZE - 1)) + 1;
	103	space = SHA1_BLOCK_SIZE - leftover;
	104	if (space) {
	105	if (count > space) {
	106	err = crypto_shash_update(&dctx->fallback, in, space) ?:
	107	crypto_shash_export(&dctx->fallback, &state);
	108	if (err)
	109	goto out;
	110	count -= space;
	111	in += space;
	112	} else {
	113	memcpy(state.buffer + leftover, in, count);
	114	in = state.buffer;
	115	count += leftover;
e9b25f16	116	state.count &= ~(SHA1_BLOCK_SIZE - 1);
bbbee467 HX	117	}
	118	}
	119
	120	memcpy(result, &state.state, SHA1_DIGEST_SIZE);
6c833275	121
6c833275	122	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8" /* rep xsha1 */
bbbee467	123	: \
faae8908 HX	124	: "c"((unsigned long)state.count + count), \
faae8908 HX	125	"a"((unsigned long)state.count), \
bbbee467	126	"S"(in), "D"(result));
6c833275 ML	127
6c833275 ML	128	padlock_output_block((uint32_t )result, (uint32_t )out, 5);
bbbee467 HX	129
	130	out:
	131	return err;
6c833275 ML	132	}
6c833275 ML	133
bbbee467 HX	134	static int padlock_sha1_final(struct shash_desc desc, u8 out)
	135	{
	136	u8 buf[4];
	137
	138	return padlock_sha1_finup(desc, buf, 0, out);
	139	}
	140
	141	static int padlock_sha256_finup(struct shash_desc desc, const u8 in,
	142	unsigned int count, u8 *out)
6c833275 ML	143	{
	144	/* We can't store directly to out as it may be unaligned. /
	145	/* BTW Don't reduce the buffer size below 128 Bytes!
	146	* PadLock microcode needs it that big. */
4c6ab3ee HX	147	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	148	((aligned(STACK_ALIGN)));
	149	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
bbbee467 HX	150	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	151	struct sha256_state state;
	152	unsigned int space;
	153	unsigned int leftover;
bbbee467	154	int err;
6c833275	155
bbbee467 HX	156	dctx->fallback.flags = desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP;
	157	err = crypto_shash_export(&dctx->fallback, &state);
	158	if (err)
	159	goto out;
	160
	161	if (state.count + count > ULONG_MAX)
	162	return crypto_shash_finup(&dctx->fallback, in, count, out);
	163
	164	leftover = ((state.count - 1) & (SHA256_BLOCK_SIZE - 1)) + 1;
	165	space = SHA256_BLOCK_SIZE - leftover;
	166	if (space) {
	167	if (count > space) {
	168	err = crypto_shash_update(&dctx->fallback, in, space) ?:
	169	crypto_shash_export(&dctx->fallback, &state);
	170	if (err)
	171	goto out;
	172	count -= space;
	173	in += space;
	174	} else {
	175	memcpy(state.buf + leftover, in, count);
	176	in = state.buf;
	177	count += leftover;
e9b25f16	178	state.count &= ~(SHA1_BLOCK_SIZE - 1);
bbbee467 HX	179	}
	180	}
	181
	182	memcpy(result, &state.state, SHA256_DIGEST_SIZE);
6c833275 ML	183
6c833275 ML	184	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0" /* rep xsha256 */
bbbee467	185	: \
faae8908 HX	186	: "c"((unsigned long)state.count + count), \
faae8908 HX	187	"a"((unsigned long)state.count), \
bbbee467	188	"S"(in), "D"(result));
6c833275 ML	189
6c833275 ML	190	padlock_output_block((uint32_t )result, (uint32_t )out, 8);
bbbee467 HX	191
	192	out:
	193	return err;
6c833275 ML	194	}
6c833275 ML	195
bbbee467	196	static int padlock_sha256_final(struct shash_desc desc, u8 out)
6c833275	197	{
bbbee467	198	u8 buf[4];
6c833275	199
bbbee467	200	return padlock_sha256_finup(desc, buf, 0, out);
6c833275 ML	201	}
6c833275 ML	202
6010439f	203	static int padlock_cra_init(struct crypto_tfm *tfm)
6c833275	204	{
bbbee467	205	struct crypto_shash *hash = __crypto_shash_cast(tfm);
1f4fe5a3	206	const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
bbbee467	207	struct padlock_sha_ctx *ctx = crypto_tfm_ctx(tfm);
7d024608 HX	208	struct crypto_shash *fallback_tfm;
7d024608 HX	209	int err = -ENOMEM;
6010439f	210
6c833275	211	/* Allocate a fallback and abort if it failed. */
7d024608 HX	212	fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
7d024608 HX	213	CRYPTO_ALG_NEED_FALLBACK);
6010439f	214	if (IS_ERR(fallback_tfm)) {
6c833275 ML	215	printk(KERN_WARNING PFX "Fallback driver '%s' could not be loaded!\n",
6c833275 ML	216	fallback_driver_name);
7d024608	217	err = PTR_ERR(fallback_tfm);
bbbee467	218	goto out;
6c833275 ML	219	}
6c833275 ML	220
bbbee467 HX	221	ctx->fallback = fallback_tfm;
bbbee467 HX	222	hash->descsize += crypto_shash_descsize(fallback_tfm);
6c833275	223	return 0;
7d024608	224
7d024608 HX	225	out:
7d024608 HX	226	return err;
6c833275 ML	227	}
6c833275 ML	228
6c833275 ML	229	static void padlock_cra_exit(struct crypto_tfm *tfm)
6c833275 ML	230	{
bbbee467	231	struct padlock_sha_ctx *ctx = crypto_tfm_ctx(tfm);
7d024608	232
bbbee467	233	crypto_free_shash(ctx->fallback);
6c833275 ML	234	}
6c833275 ML	235
bbbee467 HX	236	static struct shash_alg sha1_alg = {
	237	.digestsize = SHA1_DIGEST_SIZE,
	238	.init = padlock_sha_init,
	239	.update = padlock_sha_update,
	240	.finup = padlock_sha1_finup,
	241	.final = padlock_sha1_final,
a8d7ac27 HX	242	.export = padlock_sha_export,
a8d7ac27 HX	243	.import = padlock_sha_import,
bbbee467	244	.descsize = sizeof(struct padlock_sha_desc),
a8d7ac27	245	.statesize = sizeof(struct sha1_state),
bbbee467 HX	246	.base = {
	247	.cra_name = "sha1",
	248	.cra_driver_name = "sha1-padlock",
	249	.cra_priority = PADLOCK_CRA_PRIORITY,
	250	.cra_flags = CRYPTO_ALG_TYPE_SHASH \|
	251	CRYPTO_ALG_NEED_FALLBACK,
	252	.cra_blocksize = SHA1_BLOCK_SIZE,
	253	.cra_ctxsize = sizeof(struct padlock_sha_ctx),
	254	.cra_module = THIS_MODULE,
	255	.cra_init = padlock_cra_init,
	256	.cra_exit = padlock_cra_exit,
6c833275 ML	257	}
	258	};
	259
bbbee467 HX	260	static struct shash_alg sha256_alg = {
	261	.digestsize = SHA256_DIGEST_SIZE,
	262	.init = padlock_sha_init,
	263	.update = padlock_sha_update,
	264	.finup = padlock_sha256_finup,
	265	.final = padlock_sha256_final,
a8d7ac27 HX	266	.export = padlock_sha_export,
a8d7ac27 HX	267	.import = padlock_sha_import,
bbbee467	268	.descsize = sizeof(struct padlock_sha_desc),
a8d7ac27	269	.statesize = sizeof(struct sha256_state),
bbbee467 HX	270	.base = {
	271	.cra_name = "sha256",
	272	.cra_driver_name = "sha256-padlock",
	273	.cra_priority = PADLOCK_CRA_PRIORITY,
	274	.cra_flags = CRYPTO_ALG_TYPE_SHASH \|
	275	CRYPTO_ALG_NEED_FALLBACK,
	276	.cra_blocksize = SHA256_BLOCK_SIZE,
	277	.cra_ctxsize = sizeof(struct padlock_sha_ctx),
	278	.cra_module = THIS_MODULE,
	279	.cra_init = padlock_cra_init,
	280	.cra_exit = padlock_cra_exit,
6c833275 ML	281	}
	282	};
	283
0475add3 BW	284	/* Add two shash_alg instance for hardware-implemented *
	285	* multiple-parts hash supported by VIA Nano Processor.*/
	286	static int padlock_sha1_init_nano(struct shash_desc *desc)
	287	{
	288	struct sha1_state *sctx = shash_desc_ctx(desc);
	289
	290	*sctx = (struct sha1_state){
	291	.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
	292	};
	293
	294	return 0;
	295	}
	296
	297	static int padlock_sha1_update_nano(struct shash_desc *desc,
	298	const u8 *data, unsigned int len)
	299	{
	300	struct sha1_state *sctx = shash_desc_ctx(desc);
	301	unsigned int partial, done;
	302	const u8 *src;
	303	/The PHE require the out buffer must 128 bytes and 16-bytes aligned/
	304	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	305	((aligned(STACK_ALIGN)));
	306	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
0475add3 BW	307
	308	partial = sctx->count & 0x3f;
	309	sctx->count += len;
	310	done = 0;
	311	src = data;
	312	memcpy(dst, (u8 *)(sctx->state), SHA1_DIGEST_SIZE);
	313
	314	if ((partial + len) >= SHA1_BLOCK_SIZE) {
	315
	316	/* Append the bytes in state's buffer to a block to handle */
	317	if (partial) {
	318	done = -partial;
	319	memcpy(sctx->buffer + partial, data,
	320	done + SHA1_BLOCK_SIZE);
	321	src = sctx->buffer;
0475add3 BW	322	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
	323	: "+S"(src), "+D"(dst) \
	324	: "a"((long)-1), "c"((unsigned long)1));
0475add3 BW	325	done += SHA1_BLOCK_SIZE;
	326	src = data + done;
	327	}
	328
	329	/* Process the left bytes from the input data */
	330	if (len - done >= SHA1_BLOCK_SIZE) {
0475add3 BW	331	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
	332	: "+S"(src), "+D"(dst)
	333	: "a"((long)-1),
	334	"c"((unsigned long)((len - done) / SHA1_BLOCK_SIZE)));
0475add3 BW	335	done += ((len - done) - (len - done) % SHA1_BLOCK_SIZE);
	336	src = data + done;
	337	}
	338	partial = 0;
	339	}
	340	memcpy((u8 *)(sctx->state), dst, SHA1_DIGEST_SIZE);
	341	memcpy(sctx->buffer + partial, src, len - done);
	342
	343	return 0;
	344	}
	345
	346	static int padlock_sha1_final_nano(struct shash_desc desc, u8 out)
	347	{
	348	struct sha1_state state = (struct sha1_state )shash_desc_ctx(desc);
	349	unsigned int partial, padlen;
	350	__be64 bits;
	351	static const u8 padding[64] = { 0x80, };
	352
	353	bits = cpu_to_be64(state->count << 3);
	354
	355	/* Pad out to 56 mod 64 */
	356	partial = state->count & 0x3f;
	357	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	358	padlock_sha1_update_nano(desc, padding, padlen);
	359
	360	/* Append length field bytes */
	361	padlock_sha1_update_nano(desc, (const u8 *)&bits, sizeof(bits));
	362
	363	/* Swap to output */
	364	padlock_output_block((uint32_t )(state->state), (uint32_t )out, 5);
	365
	366	return 0;
	367	}
	368
	369	static int padlock_sha256_init_nano(struct shash_desc *desc)
	370	{
	371	struct sha256_state *sctx = shash_desc_ctx(desc);
	372
	373	*sctx = (struct sha256_state){
	374	.state = { SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, \
	375	SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7},
	376	};
	377
	378	return 0;
	379	}
	380
	381	static int padlock_sha256_update_nano(struct shash_desc desc, const u8 data,
	382	unsigned int len)
	383	{
	384	struct sha256_state *sctx = shash_desc_ctx(desc);
	385	unsigned int partial, done;
	386	const u8 *src;
	387	/The PHE require the out buffer must 128 bytes and 16-bytes aligned/
	388	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	389	((aligned(STACK_ALIGN)));
	390	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
0475add3 BW	391
	392	partial = sctx->count & 0x3f;
	393	sctx->count += len;
	394	done = 0;
	395	src = data;
	396	memcpy(dst, (u8 *)(sctx->state), SHA256_DIGEST_SIZE);
	397
	398	if ((partial + len) >= SHA256_BLOCK_SIZE) {
	399
	400	/* Append the bytes in state's buffer to a block to handle */
	401	if (partial) {
	402	done = -partial;
	403	memcpy(sctx->buf + partial, data,
	404	done + SHA256_BLOCK_SIZE);
	405	src = sctx->buf;
0475add3 BW	406	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
	407	: "+S"(src), "+D"(dst)
	408	: "a"((long)-1), "c"((unsigned long)1));
0475add3 BW	409	done += SHA256_BLOCK_SIZE;
	410	src = data + done;
	411	}
	412
	413	/* Process the left bytes from input data*/
	414	if (len - done >= SHA256_BLOCK_SIZE) {
0475add3 BW	415	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
	416	: "+S"(src), "+D"(dst)
	417	: "a"((long)-1),
	418	"c"((unsigned long)((len - done) / 64)));
0475add3 BW	419	done += ((len - done) - (len - done) % 64);
	420	src = data + done;
	421	}
	422	partial = 0;
	423	}
	424	memcpy((u8 *)(sctx->state), dst, SHA256_DIGEST_SIZE);
	425	memcpy(sctx->buf + partial, src, len - done);
	426
	427	return 0;
	428	}
	429
	430	static int padlock_sha256_final_nano(struct shash_desc desc, u8 out)
	431	{
	432	struct sha256_state *state =
	433	(struct sha256_state *)shash_desc_ctx(desc);
	434	unsigned int partial, padlen;
	435	__be64 bits;
	436	static const u8 padding[64] = { 0x80, };
	437
	438	bits = cpu_to_be64(state->count << 3);
	439
	440	/* Pad out to 56 mod 64 */
	441	partial = state->count & 0x3f;
	442	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	443	padlock_sha256_update_nano(desc, padding, padlen);
	444
	445	/* Append length field bytes */
	446	padlock_sha256_update_nano(desc, (const u8 *)&bits, sizeof(bits));
	447
	448	/* Swap to output */
	449	padlock_output_block((uint32_t )(state->state), (uint32_t )out, 8);
	450
	451	return 0;
	452	}
	453
	454	static int padlock_sha_export_nano(struct shash_desc *desc,
	455	void *out)
	456	{
	457	int statesize = crypto_shash_statesize(desc->tfm);
	458	void *sctx = shash_desc_ctx(desc);
	459
	460	memcpy(out, sctx, statesize);
	461	return 0;
	462	}
	463
	464	static int padlock_sha_import_nano(struct shash_desc *desc,
	465	const void *in)
	466	{
	467	int statesize = crypto_shash_statesize(desc->tfm);
	468	void *sctx = shash_desc_ctx(desc);
	469
	470	memcpy(sctx, in, statesize);
	471	return 0;
	472	}
	473
	474	static struct shash_alg sha1_alg_nano = {
	475	.digestsize = SHA1_DIGEST_SIZE,
	476	.init = padlock_sha1_init_nano,
	477	.update = padlock_sha1_update_nano,
	478	.final = padlock_sha1_final_nano,
	479	.export = padlock_sha_export_nano,
	480	.import = padlock_sha_import_nano,
	481	.descsize = sizeof(struct sha1_state),
	482	.statesize = sizeof(struct sha1_state),
483	.base = {
484	.cra_name = "sha1",
485	.cra_driver_name = "sha1-padlock-nano",
486	.cra_priority = PADLOCK_CRA_PRIORITY,
487	.cra_flags = CRYPTO_ALG_TYPE_SHASH,
488	.cra_blocksize = SHA1_BLOCK_SIZE,
489	.cra_module = THIS_MODULE,
490	}
491	};
492
493	static struct shash_alg sha256_alg_nano = {
494	.digestsize = SHA256_DIGEST_SIZE,
495	.init = padlock_sha256_init_nano,
496	.update = padlock_sha256_update_nano,
497	.final = padlock_sha256_final_nano,
498	.export = padlock_sha_export_nano,
499	.import = padlock_sha_import_nano,
500	.descsize = sizeof(struct sha256_state),
501	.statesize = sizeof(struct sha256_state),
502	.base = {
503	.cra_name = "sha256",
504	.cra_driver_name = "sha256-padlock-nano",
505	.cra_priority = PADLOCK_CRA_PRIORITY,
506	.cra_flags = CRYPTO_ALG_TYPE_SHASH,
507	.cra_blocksize = SHA256_BLOCK_SIZE,
508	.cra_module = THIS_MODULE,
509	}
510	};
511
3bd391f0 AK	512	static struct x86_cpu_id padlock_sha_ids[] = {
	513	X86_FEATURE_MATCH(X86_FEATURE_PHE),
	514	{}
	515	};
	516	MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids);
	517
6c833275 ML	518	static int __init padlock_init(void)
	519	{
	520	int rc = -ENODEV;
0475add3 BW	521	struct cpuinfo_x86 *c = &cpu_data(0);
	522	struct shash_alg *sha1;
	523	struct shash_alg *sha256;
6c833275	524
362f924b	525	if (!x86_match_cpu(padlock_sha_ids) \|\| !boot_cpu_has(X86_FEATURE_PHE_EN))
6c833275	526	return -ENODEV;
6c833275	527
0475add3 BW	528	/* Register the newly added algorithm module if on *
	529	* VIA Nano processor, or else just do as before */
	530	if (c->x86_model < 0x0f) {
	531	sha1 = &sha1_alg;
	532	sha256 = &sha256_alg;
	533	} else {
	534	sha1 = &sha1_alg_nano;
	535	sha256 = &sha256_alg_nano;
	536	}
	537
	538	rc = crypto_register_shash(sha1);
6c833275 ML	539	if (rc)
	540	goto out;
	541
0475add3	542	rc = crypto_register_shash(sha256);
6c833275 ML	543	if (rc)
	544	goto out_unreg1;
	545
	546	printk(KERN_NOTICE PFX "Using VIA PadLock ACE for SHA1/SHA256 algorithms.\n");
	547
	548	return 0;
	549
	550	out_unreg1:
0475add3 BW	551	crypto_unregister_shash(sha1);
0475add3 BW	552
6c833275 ML	553	out:
	554	printk(KERN_ERR PFX "VIA PadLock SHA1/SHA256 initialization failed.\n");
	555	return rc;
	556	}
	557
	558	static void __exit padlock_fini(void)
	559	{
0475add3 BW	560	struct cpuinfo_x86 *c = &cpu_data(0);
	561
	562	if (c->x86_model >= 0x0f) {
	563	crypto_unregister_shash(&sha1_alg_nano);
	564	crypto_unregister_shash(&sha256_alg_nano);
	565	} else {
	566	crypto_unregister_shash(&sha1_alg);
	567	crypto_unregister_shash(&sha256_alg);
	568	}
6c833275 ML	569	}
	570
	571	module_init(padlock_init);
	572	module_exit(padlock_fini);
	573
	574	MODULE_DESCRIPTION("VIA PadLock SHA1/SHA256 algorithms support.");
	575	MODULE_LICENSE("GPL");
	576	MODULE_AUTHOR("Michal Ludvig");
	577
5d26a105 KC	578	MODULE_ALIAS_CRYPTO("sha1-all");
	579	MODULE_ALIAS_CRYPTO("sha256-all");
	580	MODULE_ALIAS_CRYPTO("sha1-padlock");
	581	MODULE_ALIAS_CRYPTO("sha256-padlock");