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ce921368 JI |
1 | /* |
2 | * Copyright (c) 2010-2011 Picochip Ltd., Jamie Iles | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
2d78db09 | 18 | #include <crypto/internal/aead.h> |
ce921368 JI |
19 | #include <crypto/aes.h> |
20 | #include <crypto/algapi.h> | |
21 | #include <crypto/authenc.h> | |
22 | #include <crypto/des.h> | |
23 | #include <crypto/md5.h> | |
24 | #include <crypto/sha.h> | |
25 | #include <crypto/internal/skcipher.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/crypto.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/dma-mapping.h> | |
30 | #include <linux/dmapool.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/io.h> | |
35 | #include <linux/list.h> | |
36 | #include <linux/module.h> | |
30343ef1 | 37 | #include <linux/of.h> |
ce921368 JI |
38 | #include <linux/platform_device.h> |
39 | #include <linux/pm.h> | |
40 | #include <linux/rtnetlink.h> | |
41 | #include <linux/scatterlist.h> | |
42 | #include <linux/sched.h> | |
72071fe4 | 43 | #include <linux/sizes.h> |
ce921368 JI |
44 | #include <linux/slab.h> |
45 | #include <linux/timer.h> | |
46 | ||
47 | #include "picoxcell_crypto_regs.h" | |
48 | ||
49 | /* | |
50 | * The threshold for the number of entries in the CMD FIFO available before | |
51 | * the CMD0_CNT interrupt is raised. Increasing this value will reduce the | |
52 | * number of interrupts raised to the CPU. | |
53 | */ | |
54 | #define CMD0_IRQ_THRESHOLD 1 | |
55 | ||
56 | /* | |
57 | * The timeout period (in jiffies) for a PDU. When the the number of PDUs in | |
58 | * flight is greater than the STAT_IRQ_THRESHOLD or 0 the timer is disabled. | |
59 | * When there are packets in flight but lower than the threshold, we enable | |
60 | * the timer and at expiry, attempt to remove any processed packets from the | |
61 | * queue and if there are still packets left, schedule the timer again. | |
62 | */ | |
63 | #define PACKET_TIMEOUT 1 | |
64 | ||
65 | /* The priority to register each algorithm with. */ | |
66 | #define SPACC_CRYPTO_ALG_PRIORITY 10000 | |
67 | ||
68 | #define SPACC_CRYPTO_KASUMI_F8_KEY_LEN 16 | |
69 | #define SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ 64 | |
70 | #define SPACC_CRYPTO_IPSEC_HASH_PG_SZ 64 | |
71 | #define SPACC_CRYPTO_IPSEC_MAX_CTXS 32 | |
72 | #define SPACC_CRYPTO_IPSEC_FIFO_SZ 32 | |
73 | #define SPACC_CRYPTO_L2_CIPHER_PG_SZ 64 | |
74 | #define SPACC_CRYPTO_L2_HASH_PG_SZ 64 | |
75 | #define SPACC_CRYPTO_L2_MAX_CTXS 128 | |
76 | #define SPACC_CRYPTO_L2_FIFO_SZ 128 | |
77 | ||
78 | #define MAX_DDT_LEN 16 | |
79 | ||
80 | /* DDT format. This must match the hardware DDT format exactly. */ | |
81 | struct spacc_ddt { | |
82 | dma_addr_t p; | |
83 | u32 len; | |
84 | }; | |
85 | ||
86 | /* | |
87 | * Asynchronous crypto request structure. | |
88 | * | |
89 | * This structure defines a request that is either queued for processing or | |
90 | * being processed. | |
91 | */ | |
92 | struct spacc_req { | |
93 | struct list_head list; | |
94 | struct spacc_engine *engine; | |
95 | struct crypto_async_request *req; | |
96 | int result; | |
97 | bool is_encrypt; | |
98 | unsigned ctx_id; | |
99 | dma_addr_t src_addr, dst_addr; | |
100 | struct spacc_ddt *src_ddt, *dst_ddt; | |
101 | void (*complete)(struct spacc_req *req); | |
c1359495 | 102 | }; |
ce921368 | 103 | |
c1359495 HX |
104 | struct spacc_aead { |
105 | unsigned long ctrl_default; | |
106 | unsigned long type; | |
107 | struct aead_alg alg; | |
108 | struct spacc_engine *engine; | |
109 | struct list_head entry; | |
110 | int key_offs; | |
111 | int iv_offs; | |
ce921368 JI |
112 | }; |
113 | ||
114 | struct spacc_engine { | |
115 | void __iomem *regs; | |
116 | struct list_head pending; | |
117 | int next_ctx; | |
118 | spinlock_t hw_lock; | |
119 | int in_flight; | |
120 | struct list_head completed; | |
121 | struct list_head in_progress; | |
122 | struct tasklet_struct complete; | |
123 | unsigned long fifo_sz; | |
124 | void __iomem *cipher_ctx_base; | |
125 | void __iomem *hash_key_base; | |
126 | struct spacc_alg *algs; | |
127 | unsigned num_algs; | |
128 | struct list_head registered_algs; | |
c1359495 HX |
129 | struct spacc_aead *aeads; |
130 | unsigned num_aeads; | |
131 | struct list_head registered_aeads; | |
ce921368 JI |
132 | size_t cipher_pg_sz; |
133 | size_t hash_pg_sz; | |
134 | const char *name; | |
135 | struct clk *clk; | |
136 | struct device *dev; | |
137 | unsigned max_ctxs; | |
138 | struct timer_list packet_timeout; | |
139 | unsigned stat_irq_thresh; | |
140 | struct dma_pool *req_pool; | |
141 | }; | |
142 | ||
143 | /* Algorithm type mask. */ | |
144 | #define SPACC_CRYPTO_ALG_MASK 0x7 | |
145 | ||
146 | /* SPACC definition of a crypto algorithm. */ | |
147 | struct spacc_alg { | |
148 | unsigned long ctrl_default; | |
149 | unsigned long type; | |
150 | struct crypto_alg alg; | |
151 | struct spacc_engine *engine; | |
152 | struct list_head entry; | |
153 | int key_offs; | |
154 | int iv_offs; | |
155 | }; | |
156 | ||
157 | /* Generic context structure for any algorithm type. */ | |
158 | struct spacc_generic_ctx { | |
159 | struct spacc_engine *engine; | |
160 | int flags; | |
161 | int key_offs; | |
162 | int iv_offs; | |
163 | }; | |
164 | ||
165 | /* Block cipher context. */ | |
166 | struct spacc_ablk_ctx { | |
167 | struct spacc_generic_ctx generic; | |
168 | u8 key[AES_MAX_KEY_SIZE]; | |
169 | u8 key_len; | |
170 | /* | |
171 | * The fallback cipher. If the operation can't be done in hardware, | |
172 | * fallback to a software version. | |
173 | */ | |
174 | struct crypto_ablkcipher *sw_cipher; | |
175 | }; | |
176 | ||
177 | /* AEAD cipher context. */ | |
178 | struct spacc_aead_ctx { | |
179 | struct spacc_generic_ctx generic; | |
180 | u8 cipher_key[AES_MAX_KEY_SIZE]; | |
181 | u8 hash_ctx[SPACC_CRYPTO_IPSEC_HASH_PG_SZ]; | |
182 | u8 cipher_key_len; | |
183 | u8 hash_key_len; | |
184 | struct crypto_aead *sw_cipher; | |
ce921368 JI |
185 | }; |
186 | ||
40bfc14f JI |
187 | static int spacc_ablk_submit(struct spacc_req *req); |
188 | ||
ce921368 JI |
189 | static inline struct spacc_alg *to_spacc_alg(struct crypto_alg *alg) |
190 | { | |
191 | return alg ? container_of(alg, struct spacc_alg, alg) : NULL; | |
192 | } | |
193 | ||
c1359495 HX |
194 | static inline struct spacc_aead *to_spacc_aead(struct aead_alg *alg) |
195 | { | |
196 | return container_of(alg, struct spacc_aead, alg); | |
197 | } | |
198 | ||
ce921368 JI |
199 | static inline int spacc_fifo_cmd_full(struct spacc_engine *engine) |
200 | { | |
201 | u32 fifo_stat = readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET); | |
202 | ||
203 | return fifo_stat & SPA_FIFO_CMD_FULL; | |
204 | } | |
205 | ||
206 | /* | |
207 | * Given a cipher context, and a context number, get the base address of the | |
208 | * context page. | |
209 | * | |
210 | * Returns the address of the context page where the key/context may | |
211 | * be written. | |
212 | */ | |
213 | static inline void __iomem *spacc_ctx_page_addr(struct spacc_generic_ctx *ctx, | |
214 | unsigned indx, | |
215 | bool is_cipher_ctx) | |
216 | { | |
217 | return is_cipher_ctx ? ctx->engine->cipher_ctx_base + | |
218 | (indx * ctx->engine->cipher_pg_sz) : | |
219 | ctx->engine->hash_key_base + (indx * ctx->engine->hash_pg_sz); | |
220 | } | |
221 | ||
222 | /* The context pages can only be written with 32-bit accesses. */ | |
223 | static inline void memcpy_toio32(u32 __iomem *dst, const void *src, | |
224 | unsigned count) | |
225 | { | |
226 | const u32 *src32 = (const u32 *) src; | |
227 | ||
228 | while (count--) | |
229 | writel(*src32++, dst++); | |
230 | } | |
231 | ||
232 | static void spacc_cipher_write_ctx(struct spacc_generic_ctx *ctx, | |
233 | void __iomem *page_addr, const u8 *key, | |
234 | size_t key_len, const u8 *iv, size_t iv_len) | |
235 | { | |
236 | void __iomem *key_ptr = page_addr + ctx->key_offs; | |
237 | void __iomem *iv_ptr = page_addr + ctx->iv_offs; | |
238 | ||
239 | memcpy_toio32(key_ptr, key, key_len / 4); | |
240 | memcpy_toio32(iv_ptr, iv, iv_len / 4); | |
241 | } | |
242 | ||
243 | /* | |
244 | * Load a context into the engines context memory. | |
245 | * | |
246 | * Returns the index of the context page where the context was loaded. | |
247 | */ | |
248 | static unsigned spacc_load_ctx(struct spacc_generic_ctx *ctx, | |
249 | const u8 *ciph_key, size_t ciph_len, | |
250 | const u8 *iv, size_t ivlen, const u8 *hash_key, | |
251 | size_t hash_len) | |
252 | { | |
253 | unsigned indx = ctx->engine->next_ctx++; | |
254 | void __iomem *ciph_page_addr, *hash_page_addr; | |
255 | ||
256 | ciph_page_addr = spacc_ctx_page_addr(ctx, indx, 1); | |
257 | hash_page_addr = spacc_ctx_page_addr(ctx, indx, 0); | |
258 | ||
259 | ctx->engine->next_ctx &= ctx->engine->fifo_sz - 1; | |
260 | spacc_cipher_write_ctx(ctx, ciph_page_addr, ciph_key, ciph_len, iv, | |
261 | ivlen); | |
262 | writel(ciph_len | (indx << SPA_KEY_SZ_CTX_INDEX_OFFSET) | | |
263 | (1 << SPA_KEY_SZ_CIPHER_OFFSET), | |
264 | ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET); | |
265 | ||
266 | if (hash_key) { | |
267 | memcpy_toio32(hash_page_addr, hash_key, hash_len / 4); | |
268 | writel(hash_len | (indx << SPA_KEY_SZ_CTX_INDEX_OFFSET), | |
269 | ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET); | |
270 | } | |
271 | ||
272 | return indx; | |
273 | } | |
274 | ||
ce921368 JI |
275 | static inline void ddt_set(struct spacc_ddt *ddt, dma_addr_t phys, size_t len) |
276 | { | |
277 | ddt->p = phys; | |
278 | ddt->len = len; | |
279 | } | |
280 | ||
281 | /* | |
282 | * Take a crypto request and scatterlists for the data and turn them into DDTs | |
283 | * for passing to the crypto engines. This also DMA maps the data so that the | |
284 | * crypto engines can DMA to/from them. | |
285 | */ | |
286 | static struct spacc_ddt *spacc_sg_to_ddt(struct spacc_engine *engine, | |
287 | struct scatterlist *payload, | |
288 | unsigned nbytes, | |
289 | enum dma_data_direction dir, | |
290 | dma_addr_t *ddt_phys) | |
291 | { | |
f53e38af | 292 | unsigned mapped_ents; |
ce921368 JI |
293 | struct scatterlist *cur; |
294 | struct spacc_ddt *ddt; | |
295 | int i; | |
f53e38af | 296 | int nents; |
ce921368 | 297 | |
f051f95e LC |
298 | nents = sg_nents_for_len(payload, nbytes); |
299 | if (nents < 0) { | |
300 | dev_err(engine->dev, "Invalid numbers of SG.\n"); | |
301 | return NULL; | |
302 | } | |
ce921368 JI |
303 | mapped_ents = dma_map_sg(engine->dev, payload, nents, dir); |
304 | ||
305 | if (mapped_ents + 1 > MAX_DDT_LEN) | |
306 | goto out; | |
307 | ||
308 | ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, ddt_phys); | |
309 | if (!ddt) | |
310 | goto out; | |
311 | ||
312 | for_each_sg(payload, cur, mapped_ents, i) | |
313 | ddt_set(&ddt[i], sg_dma_address(cur), sg_dma_len(cur)); | |
314 | ddt_set(&ddt[mapped_ents], 0, 0); | |
315 | ||
316 | return ddt; | |
317 | ||
318 | out: | |
319 | dma_unmap_sg(engine->dev, payload, nents, dir); | |
320 | return NULL; | |
321 | } | |
322 | ||
c1359495 | 323 | static int spacc_aead_make_ddts(struct aead_request *areq) |
ce921368 | 324 | { |
c1359495 HX |
325 | struct crypto_aead *aead = crypto_aead_reqtfm(areq); |
326 | struct spacc_req *req = aead_request_ctx(areq); | |
ce921368 JI |
327 | struct spacc_engine *engine = req->engine; |
328 | struct spacc_ddt *src_ddt, *dst_ddt; | |
81781e68 | 329 | unsigned total; |
f53e38af | 330 | int src_nents, dst_nents; |
ce921368 | 331 | struct scatterlist *cur; |
c1359495 HX |
332 | int i, dst_ents, src_ents; |
333 | ||
334 | total = areq->assoclen + areq->cryptlen; | |
335 | if (req->is_encrypt) | |
336 | total += crypto_aead_authsize(aead); | |
337 | ||
f051f95e LC |
338 | src_nents = sg_nents_for_len(areq->src, total); |
339 | if (src_nents < 0) { | |
340 | dev_err(engine->dev, "Invalid numbers of src SG.\n"); | |
341 | return src_nents; | |
342 | } | |
c1359495 HX |
343 | if (src_nents + 1 > MAX_DDT_LEN) |
344 | return -E2BIG; | |
345 | ||
346 | dst_nents = 0; | |
347 | if (areq->src != areq->dst) { | |
f051f95e LC |
348 | dst_nents = sg_nents_for_len(areq->dst, total); |
349 | if (dst_nents < 0) { | |
350 | dev_err(engine->dev, "Invalid numbers of dst SG.\n"); | |
351 | return dst_nents; | |
352 | } | |
c1359495 HX |
353 | if (src_nents + 1 > MAX_DDT_LEN) |
354 | return -E2BIG; | |
355 | } | |
ce921368 JI |
356 | |
357 | src_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->src_addr); | |
358 | if (!src_ddt) | |
c1359495 | 359 | goto err; |
ce921368 JI |
360 | |
361 | dst_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->dst_addr); | |
c1359495 HX |
362 | if (!dst_ddt) |
363 | goto err_free_src; | |
ce921368 JI |
364 | |
365 | req->src_ddt = src_ddt; | |
366 | req->dst_ddt = dst_ddt; | |
367 | ||
c1359495 HX |
368 | if (dst_nents) { |
369 | src_ents = dma_map_sg(engine->dev, areq->src, src_nents, | |
ce921368 | 370 | DMA_TO_DEVICE); |
c1359495 HX |
371 | if (!src_ents) |
372 | goto err_free_dst; | |
373 | ||
374 | dst_ents = dma_map_sg(engine->dev, areq->dst, dst_nents, | |
ce921368 | 375 | DMA_FROM_DEVICE); |
c1359495 HX |
376 | |
377 | if (!dst_ents) { | |
378 | dma_unmap_sg(engine->dev, areq->src, src_nents, | |
379 | DMA_TO_DEVICE); | |
380 | goto err_free_dst; | |
381 | } | |
ce921368 | 382 | } else { |
c1359495 | 383 | src_ents = dma_map_sg(engine->dev, areq->src, src_nents, |
ce921368 | 384 | DMA_BIDIRECTIONAL); |
c1359495 HX |
385 | if (!src_ents) |
386 | goto err_free_dst; | |
387 | dst_ents = src_ents; | |
ce921368 JI |
388 | } |
389 | ||
390 | /* | |
c1359495 HX |
391 | * Now map in the payload for the source and destination and terminate |
392 | * with the NULL pointers. | |
ce921368 | 393 | */ |
c1359495 HX |
394 | for_each_sg(areq->src, cur, src_ents, i) |
395 | ddt_set(src_ddt++, sg_dma_address(cur), sg_dma_len(cur)); | |
ce921368 | 396 | |
c1359495 HX |
397 | /* For decryption we need to skip the associated data. */ |
398 | total = req->is_encrypt ? 0 : areq->assoclen; | |
399 | for_each_sg(areq->dst, cur, dst_ents, i) { | |
81781e68 HX |
400 | unsigned len = sg_dma_len(cur); |
401 | ||
c1359495 HX |
402 | if (len <= total) { |
403 | total -= len; | |
404 | continue; | |
405 | } | |
81781e68 | 406 | |
c1359495 | 407 | ddt_set(dst_ddt++, sg_dma_address(cur) + total, len - total); |
ce921368 | 408 | } |
ce921368 JI |
409 | |
410 | ddt_set(src_ddt, 0, 0); | |
411 | ddt_set(dst_ddt, 0, 0); | |
412 | ||
413 | return 0; | |
c1359495 HX |
414 | |
415 | err_free_dst: | |
416 | dma_pool_free(engine->req_pool, dst_ddt, req->dst_addr); | |
417 | err_free_src: | |
418 | dma_pool_free(engine->req_pool, src_ddt, req->src_addr); | |
419 | err: | |
420 | return -ENOMEM; | |
ce921368 JI |
421 | } |
422 | ||
423 | static void spacc_aead_free_ddts(struct spacc_req *req) | |
424 | { | |
425 | struct aead_request *areq = container_of(req->req, struct aead_request, | |
426 | base); | |
c1359495 HX |
427 | struct crypto_aead *aead = crypto_aead_reqtfm(areq); |
428 | unsigned total = areq->assoclen + areq->cryptlen + | |
429 | (req->is_encrypt ? crypto_aead_authsize(aead) : 0); | |
430 | struct spacc_aead_ctx *aead_ctx = crypto_aead_ctx(aead); | |
ce921368 | 431 | struct spacc_engine *engine = aead_ctx->generic.engine; |
f051f95e LC |
432 | int nents = sg_nents_for_len(areq->src, total); |
433 | ||
434 | /* sg_nents_for_len should not fail since it works when mapping sg */ | |
435 | if (unlikely(nents < 0)) { | |
436 | dev_err(engine->dev, "Invalid numbers of src SG.\n"); | |
437 | return; | |
438 | } | |
ce921368 JI |
439 | |
440 | if (areq->src != areq->dst) { | |
441 | dma_unmap_sg(engine->dev, areq->src, nents, DMA_TO_DEVICE); | |
f051f95e LC |
442 | nents = sg_nents_for_len(areq->dst, total); |
443 | if (unlikely(nents < 0)) { | |
444 | dev_err(engine->dev, "Invalid numbers of dst SG.\n"); | |
445 | return; | |
446 | } | |
447 | dma_unmap_sg(engine->dev, areq->dst, nents, DMA_FROM_DEVICE); | |
ce921368 JI |
448 | } else |
449 | dma_unmap_sg(engine->dev, areq->src, nents, DMA_BIDIRECTIONAL); | |
450 | ||
ce921368 JI |
451 | dma_pool_free(engine->req_pool, req->src_ddt, req->src_addr); |
452 | dma_pool_free(engine->req_pool, req->dst_ddt, req->dst_addr); | |
453 | } | |
454 | ||
455 | static void spacc_free_ddt(struct spacc_req *req, struct spacc_ddt *ddt, | |
456 | dma_addr_t ddt_addr, struct scatterlist *payload, | |
457 | unsigned nbytes, enum dma_data_direction dir) | |
458 | { | |
f051f95e LC |
459 | int nents = sg_nents_for_len(payload, nbytes); |
460 | ||
461 | if (nents < 0) { | |
462 | dev_err(req->engine->dev, "Invalid numbers of SG.\n"); | |
463 | return; | |
464 | } | |
ce921368 JI |
465 | |
466 | dma_unmap_sg(req->engine->dev, payload, nents, dir); | |
467 | dma_pool_free(req->engine->req_pool, ddt, ddt_addr); | |
468 | } | |
469 | ||
ce921368 JI |
470 | static int spacc_aead_setkey(struct crypto_aead *tfm, const u8 *key, |
471 | unsigned int keylen) | |
472 | { | |
473 | struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm); | |
ab827fb3 | 474 | struct crypto_authenc_keys keys; |
c1359495 HX |
475 | int err; |
476 | ||
477 | crypto_aead_clear_flags(ctx->sw_cipher, CRYPTO_TFM_REQ_MASK); | |
478 | crypto_aead_set_flags(ctx->sw_cipher, crypto_aead_get_flags(tfm) & | |
479 | CRYPTO_TFM_REQ_MASK); | |
480 | err = crypto_aead_setkey(ctx->sw_cipher, key, keylen); | |
481 | crypto_aead_clear_flags(tfm, CRYPTO_TFM_RES_MASK); | |
482 | crypto_aead_set_flags(tfm, crypto_aead_get_flags(ctx->sw_cipher) & | |
483 | CRYPTO_TFM_RES_MASK); | |
484 | if (err) | |
485 | return err; | |
ce921368 | 486 | |
ab827fb3 | 487 | if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) |
ce921368 JI |
488 | goto badkey; |
489 | ||
ab827fb3 | 490 | if (keys.enckeylen > AES_MAX_KEY_SIZE) |
ce921368 JI |
491 | goto badkey; |
492 | ||
ab827fb3 | 493 | if (keys.authkeylen > sizeof(ctx->hash_ctx)) |
ce921368 JI |
494 | goto badkey; |
495 | ||
c1359495 HX |
496 | memcpy(ctx->cipher_key, keys.enckey, keys.enckeylen); |
497 | ctx->cipher_key_len = keys.enckeylen; | |
ce921368 | 498 | |
ab827fb3 MK |
499 | memcpy(ctx->hash_ctx, keys.authkey, keys.authkeylen); |
500 | ctx->hash_key_len = keys.authkeylen; | |
ce921368 JI |
501 | |
502 | return 0; | |
503 | ||
504 | badkey: | |
505 | crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
506 | return -EINVAL; | |
507 | } | |
508 | ||
509 | static int spacc_aead_setauthsize(struct crypto_aead *tfm, | |
510 | unsigned int authsize) | |
511 | { | |
512 | struct spacc_aead_ctx *ctx = crypto_tfm_ctx(crypto_aead_tfm(tfm)); | |
513 | ||
c1359495 | 514 | return crypto_aead_setauthsize(ctx->sw_cipher, authsize); |
ce921368 JI |
515 | } |
516 | ||
517 | /* | |
518 | * Check if an AEAD request requires a fallback operation. Some requests can't | |
519 | * be completed in hardware because the hardware may not support certain key | |
520 | * sizes. In these cases we need to complete the request in software. | |
521 | */ | |
c1359495 | 522 | static int spacc_aead_need_fallback(struct aead_request *aead_req) |
ce921368 | 523 | { |
c1359495 HX |
524 | struct crypto_aead *aead = crypto_aead_reqtfm(aead_req); |
525 | struct aead_alg *alg = crypto_aead_alg(aead); | |
526 | struct spacc_aead *spacc_alg = to_spacc_aead(alg); | |
527 | struct spacc_aead_ctx *ctx = crypto_aead_ctx(aead); | |
ce921368 | 528 | |
ce921368 JI |
529 | /* |
530 | * If we have a non-supported key-length, then we need to do a | |
531 | * software fallback. | |
532 | */ | |
533 | if ((spacc_alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) == | |
534 | SPA_CTRL_CIPH_ALG_AES && | |
535 | ctx->cipher_key_len != AES_KEYSIZE_128 && | |
536 | ctx->cipher_key_len != AES_KEYSIZE_256) | |
537 | return 1; | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | static int spacc_aead_do_fallback(struct aead_request *req, unsigned alg_type, | |
543 | bool is_encrypt) | |
544 | { | |
545 | struct crypto_tfm *old_tfm = crypto_aead_tfm(crypto_aead_reqtfm(req)); | |
546 | struct spacc_aead_ctx *ctx = crypto_tfm_ctx(old_tfm); | |
c1359495 | 547 | struct aead_request *subreq = aead_request_ctx(req); |
ce921368 | 548 | |
c1359495 HX |
549 | aead_request_set_tfm(subreq, ctx->sw_cipher); |
550 | aead_request_set_callback(subreq, req->base.flags, | |
551 | req->base.complete, req->base.data); | |
552 | aead_request_set_crypt(subreq, req->src, req->dst, req->cryptlen, | |
553 | req->iv); | |
554 | aead_request_set_ad(subreq, req->assoclen); | |
ce921368 | 555 | |
c1359495 HX |
556 | return is_encrypt ? crypto_aead_encrypt(subreq) : |
557 | crypto_aead_decrypt(subreq); | |
ce921368 JI |
558 | } |
559 | ||
560 | static void spacc_aead_complete(struct spacc_req *req) | |
561 | { | |
562 | spacc_aead_free_ddts(req); | |
563 | req->req->complete(req->req, req->result); | |
564 | } | |
565 | ||
566 | static int spacc_aead_submit(struct spacc_req *req) | |
567 | { | |
ce921368 JI |
568 | struct aead_request *aead_req = |
569 | container_of(req->req, struct aead_request, base); | |
c1359495 HX |
570 | struct crypto_aead *aead = crypto_aead_reqtfm(aead_req); |
571 | unsigned int authsize = crypto_aead_authsize(aead); | |
572 | struct spacc_aead_ctx *ctx = crypto_aead_ctx(aead); | |
573 | struct aead_alg *alg = crypto_aead_alg(aead); | |
574 | struct spacc_aead *spacc_alg = to_spacc_aead(alg); | |
575 | struct spacc_engine *engine = ctx->generic.engine; | |
576 | u32 ctrl, proc_len, assoc_len; | |
ce921368 JI |
577 | |
578 | req->result = -EINPROGRESS; | |
579 | req->ctx_id = spacc_load_ctx(&ctx->generic, ctx->cipher_key, | |
c1359495 | 580 | ctx->cipher_key_len, aead_req->iv, crypto_aead_ivsize(aead), |
ce921368 JI |
581 | ctx->hash_ctx, ctx->hash_key_len); |
582 | ||
583 | /* Set the source and destination DDT pointers. */ | |
584 | writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET); | |
585 | writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET); | |
586 | writel(0, engine->regs + SPA_OFFSET_REG_OFFSET); | |
587 | ||
588 | assoc_len = aead_req->assoclen; | |
589 | proc_len = aead_req->cryptlen + assoc_len; | |
590 | ||
ce921368 JI |
591 | /* |
592 | * If we are decrypting, we need to take the length of the ICV out of | |
593 | * the processing length. | |
594 | */ | |
595 | if (!req->is_encrypt) | |
c1359495 | 596 | proc_len -= authsize; |
ce921368 JI |
597 | |
598 | writel(proc_len, engine->regs + SPA_PROC_LEN_REG_OFFSET); | |
599 | writel(assoc_len, engine->regs + SPA_AAD_LEN_REG_OFFSET); | |
c1359495 | 600 | writel(authsize, engine->regs + SPA_ICV_LEN_REG_OFFSET); |
ce921368 JI |
601 | writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET); |
602 | writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET); | |
603 | ||
604 | ctrl = spacc_alg->ctrl_default | (req->ctx_id << SPA_CTRL_CTX_IDX) | | |
605 | (1 << SPA_CTRL_ICV_APPEND); | |
606 | if (req->is_encrypt) | |
607 | ctrl |= (1 << SPA_CTRL_ENCRYPT_IDX) | (1 << SPA_CTRL_AAD_COPY); | |
608 | else | |
609 | ctrl |= (1 << SPA_CTRL_KEY_EXP); | |
610 | ||
611 | mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT); | |
612 | ||
613 | writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET); | |
614 | ||
615 | return -EINPROGRESS; | |
616 | } | |
617 | ||
40bfc14f JI |
618 | static int spacc_req_submit(struct spacc_req *req); |
619 | ||
620 | static void spacc_push(struct spacc_engine *engine) | |
621 | { | |
622 | struct spacc_req *req; | |
623 | ||
624 | while (!list_empty(&engine->pending) && | |
625 | engine->in_flight + 1 <= engine->fifo_sz) { | |
626 | ||
627 | ++engine->in_flight; | |
628 | req = list_first_entry(&engine->pending, struct spacc_req, | |
629 | list); | |
630 | list_move_tail(&req->list, &engine->in_progress); | |
631 | ||
632 | req->result = spacc_req_submit(req); | |
633 | } | |
634 | } | |
635 | ||
ce921368 JI |
636 | /* |
637 | * Setup an AEAD request for processing. This will configure the engine, load | |
638 | * the context and then start the packet processing. | |
ce921368 | 639 | */ |
c1359495 | 640 | static int spacc_aead_setup(struct aead_request *req, |
ce921368 JI |
641 | unsigned alg_type, bool is_encrypt) |
642 | { | |
c1359495 HX |
643 | struct crypto_aead *aead = crypto_aead_reqtfm(req); |
644 | struct aead_alg *alg = crypto_aead_alg(aead); | |
645 | struct spacc_engine *engine = to_spacc_aead(alg)->engine; | |
ce921368 | 646 | struct spacc_req *dev_req = aead_request_ctx(req); |
c1359495 | 647 | int err; |
ce921368 | 648 | unsigned long flags; |
ce921368 | 649 | |
ce921368 JI |
650 | dev_req->req = &req->base; |
651 | dev_req->is_encrypt = is_encrypt; | |
652 | dev_req->result = -EBUSY; | |
653 | dev_req->engine = engine; | |
654 | dev_req->complete = spacc_aead_complete; | |
655 | ||
c1359495 HX |
656 | if (unlikely(spacc_aead_need_fallback(req) || |
657 | ((err = spacc_aead_make_ddts(req)) == -E2BIG))) | |
ce921368 JI |
658 | return spacc_aead_do_fallback(req, alg_type, is_encrypt); |
659 | ||
c1359495 HX |
660 | if (err) |
661 | goto out; | |
ce921368 JI |
662 | |
663 | err = -EINPROGRESS; | |
664 | spin_lock_irqsave(&engine->hw_lock, flags); | |
40bfc14f JI |
665 | if (unlikely(spacc_fifo_cmd_full(engine)) || |
666 | engine->in_flight + 1 > engine->fifo_sz) { | |
ce921368 JI |
667 | if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { |
668 | err = -EBUSY; | |
669 | spin_unlock_irqrestore(&engine->hw_lock, flags); | |
670 | goto out_free_ddts; | |
671 | } | |
672 | list_add_tail(&dev_req->list, &engine->pending); | |
673 | } else { | |
40bfc14f JI |
674 | list_add_tail(&dev_req->list, &engine->pending); |
675 | spacc_push(engine); | |
ce921368 JI |
676 | } |
677 | spin_unlock_irqrestore(&engine->hw_lock, flags); | |
678 | ||
679 | goto out; | |
680 | ||
681 | out_free_ddts: | |
682 | spacc_aead_free_ddts(dev_req); | |
683 | out: | |
684 | return err; | |
685 | } | |
686 | ||
687 | static int spacc_aead_encrypt(struct aead_request *req) | |
688 | { | |
689 | struct crypto_aead *aead = crypto_aead_reqtfm(req); | |
c1359495 | 690 | struct spacc_aead *alg = to_spacc_aead(crypto_aead_alg(aead)); |
ce921368 | 691 | |
c1359495 | 692 | return spacc_aead_setup(req, alg->type, 1); |
ce921368 JI |
693 | } |
694 | ||
695 | static int spacc_aead_decrypt(struct aead_request *req) | |
696 | { | |
697 | struct crypto_aead *aead = crypto_aead_reqtfm(req); | |
c1359495 | 698 | struct spacc_aead *alg = to_spacc_aead(crypto_aead_alg(aead)); |
ce921368 | 699 | |
c1359495 | 700 | return spacc_aead_setup(req, alg->type, 0); |
ce921368 JI |
701 | } |
702 | ||
703 | /* | |
704 | * Initialise a new AEAD context. This is responsible for allocating the | |
705 | * fallback cipher and initialising the context. | |
706 | */ | |
c1359495 | 707 | static int spacc_aead_cra_init(struct crypto_aead *tfm) |
ce921368 | 708 | { |
c1359495 HX |
709 | struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm); |
710 | struct aead_alg *alg = crypto_aead_alg(tfm); | |
711 | struct spacc_aead *spacc_alg = to_spacc_aead(alg); | |
ce921368 JI |
712 | struct spacc_engine *engine = spacc_alg->engine; |
713 | ||
714 | ctx->generic.flags = spacc_alg->type; | |
715 | ctx->generic.engine = engine; | |
c1359495 | 716 | ctx->sw_cipher = crypto_alloc_aead(alg->base.cra_name, 0, |
ce921368 | 717 | CRYPTO_ALG_NEED_FALLBACK); |
c1359495 HX |
718 | if (IS_ERR(ctx->sw_cipher)) |
719 | return PTR_ERR(ctx->sw_cipher); | |
ce921368 JI |
720 | ctx->generic.key_offs = spacc_alg->key_offs; |
721 | ctx->generic.iv_offs = spacc_alg->iv_offs; | |
722 | ||
c1359495 HX |
723 | crypto_aead_set_reqsize( |
724 | tfm, | |
725 | max(sizeof(struct spacc_req), | |
726 | sizeof(struct aead_request) + | |
727 | crypto_aead_reqsize(ctx->sw_cipher))); | |
ce921368 JI |
728 | |
729 | return 0; | |
730 | } | |
731 | ||
732 | /* | |
733 | * Destructor for an AEAD context. This is called when the transform is freed | |
734 | * and must free the fallback cipher. | |
735 | */ | |
c1359495 | 736 | static void spacc_aead_cra_exit(struct crypto_aead *tfm) |
ce921368 | 737 | { |
c1359495 | 738 | struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm); |
ce921368 | 739 | |
c1359495 | 740 | crypto_free_aead(ctx->sw_cipher); |
ce921368 JI |
741 | } |
742 | ||
743 | /* | |
744 | * Set the DES key for a block cipher transform. This also performs weak key | |
745 | * checking if the transform has requested it. | |
746 | */ | |
747 | static int spacc_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key, | |
748 | unsigned int len) | |
749 | { | |
750 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
751 | struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm); | |
752 | u32 tmp[DES_EXPKEY_WORDS]; | |
753 | ||
754 | if (len > DES3_EDE_KEY_SIZE) { | |
755 | crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
756 | return -EINVAL; | |
757 | } | |
758 | ||
759 | if (unlikely(!des_ekey(tmp, key)) && | |
760 | (crypto_ablkcipher_get_flags(cipher) & CRYPTO_TFM_REQ_WEAK_KEY)) { | |
761 | tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY; | |
762 | return -EINVAL; | |
763 | } | |
764 | ||
765 | memcpy(ctx->key, key, len); | |
766 | ctx->key_len = len; | |
767 | ||
768 | return 0; | |
769 | } | |
770 | ||
771 | /* | |
772 | * Set the key for an AES block cipher. Some key lengths are not supported in | |
773 | * hardware so this must also check whether a fallback is needed. | |
774 | */ | |
775 | static int spacc_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key, | |
776 | unsigned int len) | |
777 | { | |
778 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
779 | struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm); | |
780 | int err = 0; | |
781 | ||
782 | if (len > AES_MAX_KEY_SIZE) { | |
783 | crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
784 | return -EINVAL; | |
785 | } | |
786 | ||
787 | /* | |
788 | * IPSec engine only supports 128 and 256 bit AES keys. If we get a | |
789 | * request for any other size (192 bits) then we need to do a software | |
790 | * fallback. | |
791 | */ | |
a9c57a9c | 792 | if (len != AES_KEYSIZE_128 && len != AES_KEYSIZE_256 && |
ce921368 JI |
793 | ctx->sw_cipher) { |
794 | /* | |
795 | * Set the fallback transform to use the same request flags as | |
796 | * the hardware transform. | |
797 | */ | |
798 | ctx->sw_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; | |
799 | ctx->sw_cipher->base.crt_flags |= | |
800 | cipher->base.crt_flags & CRYPTO_TFM_REQ_MASK; | |
801 | ||
802 | err = crypto_ablkcipher_setkey(ctx->sw_cipher, key, len); | |
803 | if (err) | |
804 | goto sw_setkey_failed; | |
a9c57a9c | 805 | } else if (len != AES_KEYSIZE_128 && len != AES_KEYSIZE_256 && |
ce921368 JI |
806 | !ctx->sw_cipher) |
807 | err = -EINVAL; | |
808 | ||
809 | memcpy(ctx->key, key, len); | |
810 | ctx->key_len = len; | |
811 | ||
812 | sw_setkey_failed: | |
813 | if (err && ctx->sw_cipher) { | |
814 | tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK; | |
815 | tfm->crt_flags |= | |
816 | ctx->sw_cipher->base.crt_flags & CRYPTO_TFM_RES_MASK; | |
817 | } | |
818 | ||
819 | return err; | |
820 | } | |
821 | ||
822 | static int spacc_kasumi_f8_setkey(struct crypto_ablkcipher *cipher, | |
823 | const u8 *key, unsigned int len) | |
824 | { | |
825 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
826 | struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm); | |
827 | int err = 0; | |
828 | ||
829 | if (len > AES_MAX_KEY_SIZE) { | |
830 | crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
831 | err = -EINVAL; | |
832 | goto out; | |
833 | } | |
834 | ||
835 | memcpy(ctx->key, key, len); | |
836 | ctx->key_len = len; | |
837 | ||
838 | out: | |
839 | return err; | |
840 | } | |
841 | ||
842 | static int spacc_ablk_need_fallback(struct spacc_req *req) | |
843 | { | |
844 | struct spacc_ablk_ctx *ctx; | |
845 | struct crypto_tfm *tfm = req->req->tfm; | |
846 | struct crypto_alg *alg = req->req->tfm->__crt_alg; | |
847 | struct spacc_alg *spacc_alg = to_spacc_alg(alg); | |
848 | ||
849 | ctx = crypto_tfm_ctx(tfm); | |
850 | ||
851 | return (spacc_alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) == | |
852 | SPA_CTRL_CIPH_ALG_AES && | |
853 | ctx->key_len != AES_KEYSIZE_128 && | |
854 | ctx->key_len != AES_KEYSIZE_256; | |
855 | } | |
856 | ||
857 | static void spacc_ablk_complete(struct spacc_req *req) | |
858 | { | |
48d62764 | 859 | struct ablkcipher_request *ablk_req = ablkcipher_request_cast(req->req); |
ce921368 JI |
860 | |
861 | if (ablk_req->src != ablk_req->dst) { | |
862 | spacc_free_ddt(req, req->src_ddt, req->src_addr, ablk_req->src, | |
863 | ablk_req->nbytes, DMA_TO_DEVICE); | |
864 | spacc_free_ddt(req, req->dst_ddt, req->dst_addr, ablk_req->dst, | |
865 | ablk_req->nbytes, DMA_FROM_DEVICE); | |
866 | } else | |
867 | spacc_free_ddt(req, req->dst_ddt, req->dst_addr, ablk_req->dst, | |
868 | ablk_req->nbytes, DMA_BIDIRECTIONAL); | |
869 | ||
870 | req->req->complete(req->req, req->result); | |
871 | } | |
872 | ||
873 | static int spacc_ablk_submit(struct spacc_req *req) | |
874 | { | |
875 | struct crypto_tfm *tfm = req->req->tfm; | |
876 | struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm); | |
877 | struct ablkcipher_request *ablk_req = ablkcipher_request_cast(req->req); | |
878 | struct crypto_alg *alg = req->req->tfm->__crt_alg; | |
879 | struct spacc_alg *spacc_alg = to_spacc_alg(alg); | |
880 | struct spacc_engine *engine = ctx->generic.engine; | |
881 | u32 ctrl; | |
882 | ||
883 | req->ctx_id = spacc_load_ctx(&ctx->generic, ctx->key, | |
884 | ctx->key_len, ablk_req->info, alg->cra_ablkcipher.ivsize, | |
885 | NULL, 0); | |
886 | ||
887 | writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET); | |
888 | writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET); | |
889 | writel(0, engine->regs + SPA_OFFSET_REG_OFFSET); | |
890 | ||
891 | writel(ablk_req->nbytes, engine->regs + SPA_PROC_LEN_REG_OFFSET); | |
892 | writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET); | |
893 | writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET); | |
894 | writel(0, engine->regs + SPA_AAD_LEN_REG_OFFSET); | |
895 | ||
896 | ctrl = spacc_alg->ctrl_default | (req->ctx_id << SPA_CTRL_CTX_IDX) | | |
897 | (req->is_encrypt ? (1 << SPA_CTRL_ENCRYPT_IDX) : | |
898 | (1 << SPA_CTRL_KEY_EXP)); | |
899 | ||
900 | mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT); | |
901 | ||
902 | writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET); | |
903 | ||
904 | return -EINPROGRESS; | |
905 | } | |
906 | ||
907 | static int spacc_ablk_do_fallback(struct ablkcipher_request *req, | |
908 | unsigned alg_type, bool is_encrypt) | |
909 | { | |
910 | struct crypto_tfm *old_tfm = | |
911 | crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req)); | |
912 | struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(old_tfm); | |
913 | int err; | |
914 | ||
915 | if (!ctx->sw_cipher) | |
916 | return -EINVAL; | |
917 | ||
918 | /* | |
919 | * Change the request to use the software fallback transform, and once | |
920 | * the ciphering has completed, put the old transform back into the | |
921 | * request. | |
922 | */ | |
923 | ablkcipher_request_set_tfm(req, ctx->sw_cipher); | |
924 | err = is_encrypt ? crypto_ablkcipher_encrypt(req) : | |
925 | crypto_ablkcipher_decrypt(req); | |
926 | ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(old_tfm)); | |
927 | ||
928 | return err; | |
929 | } | |
930 | ||
931 | static int spacc_ablk_setup(struct ablkcipher_request *req, unsigned alg_type, | |
932 | bool is_encrypt) | |
933 | { | |
934 | struct crypto_alg *alg = req->base.tfm->__crt_alg; | |
935 | struct spacc_engine *engine = to_spacc_alg(alg)->engine; | |
936 | struct spacc_req *dev_req = ablkcipher_request_ctx(req); | |
937 | unsigned long flags; | |
938 | int err = -ENOMEM; | |
939 | ||
940 | dev_req->req = &req->base; | |
941 | dev_req->is_encrypt = is_encrypt; | |
942 | dev_req->engine = engine; | |
943 | dev_req->complete = spacc_ablk_complete; | |
944 | dev_req->result = -EINPROGRESS; | |
945 | ||
946 | if (unlikely(spacc_ablk_need_fallback(dev_req))) | |
947 | return spacc_ablk_do_fallback(req, alg_type, is_encrypt); | |
948 | ||
949 | /* | |
950 | * Create the DDT's for the engine. If we share the same source and | |
951 | * destination then we can optimize by reusing the DDT's. | |
952 | */ | |
953 | if (req->src != req->dst) { | |
954 | dev_req->src_ddt = spacc_sg_to_ddt(engine, req->src, | |
955 | req->nbytes, DMA_TO_DEVICE, &dev_req->src_addr); | |
956 | if (!dev_req->src_ddt) | |
957 | goto out; | |
958 | ||
959 | dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst, | |
960 | req->nbytes, DMA_FROM_DEVICE, &dev_req->dst_addr); | |
961 | if (!dev_req->dst_ddt) | |
962 | goto out_free_src; | |
963 | } else { | |
964 | dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst, | |
965 | req->nbytes, DMA_BIDIRECTIONAL, &dev_req->dst_addr); | |
966 | if (!dev_req->dst_ddt) | |
967 | goto out; | |
968 | ||
969 | dev_req->src_ddt = NULL; | |
970 | dev_req->src_addr = dev_req->dst_addr; | |
971 | } | |
972 | ||
973 | err = -EINPROGRESS; | |
974 | spin_lock_irqsave(&engine->hw_lock, flags); | |
975 | /* | |
976 | * Check if the engine will accept the operation now. If it won't then | |
977 | * we either stick it on the end of a pending list if we can backlog, | |
978 | * or bailout with an error if not. | |
979 | */ | |
40bfc14f JI |
980 | if (unlikely(spacc_fifo_cmd_full(engine)) || |
981 | engine->in_flight + 1 > engine->fifo_sz) { | |
ce921368 JI |
982 | if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { |
983 | err = -EBUSY; | |
984 | spin_unlock_irqrestore(&engine->hw_lock, flags); | |
985 | goto out_free_ddts; | |
986 | } | |
987 | list_add_tail(&dev_req->list, &engine->pending); | |
988 | } else { | |
40bfc14f JI |
989 | list_add_tail(&dev_req->list, &engine->pending); |
990 | spacc_push(engine); | |
ce921368 JI |
991 | } |
992 | spin_unlock_irqrestore(&engine->hw_lock, flags); | |
993 | ||
994 | goto out; | |
995 | ||
996 | out_free_ddts: | |
997 | spacc_free_ddt(dev_req, dev_req->dst_ddt, dev_req->dst_addr, req->dst, | |
998 | req->nbytes, req->src == req->dst ? | |
999 | DMA_BIDIRECTIONAL : DMA_FROM_DEVICE); | |
1000 | out_free_src: | |
1001 | if (req->src != req->dst) | |
1002 | spacc_free_ddt(dev_req, dev_req->src_ddt, dev_req->src_addr, | |
1003 | req->src, req->nbytes, DMA_TO_DEVICE); | |
1004 | out: | |
1005 | return err; | |
1006 | } | |
1007 | ||
1008 | static int spacc_ablk_cra_init(struct crypto_tfm *tfm) | |
1009 | { | |
1010 | struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm); | |
1011 | struct crypto_alg *alg = tfm->__crt_alg; | |
1012 | struct spacc_alg *spacc_alg = to_spacc_alg(alg); | |
1013 | struct spacc_engine *engine = spacc_alg->engine; | |
1014 | ||
1015 | ctx->generic.flags = spacc_alg->type; | |
1016 | ctx->generic.engine = engine; | |
1017 | if (alg->cra_flags & CRYPTO_ALG_NEED_FALLBACK) { | |
1018 | ctx->sw_cipher = crypto_alloc_ablkcipher(alg->cra_name, 0, | |
1019 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK); | |
1020 | if (IS_ERR(ctx->sw_cipher)) { | |
1021 | dev_warn(engine->dev, "failed to allocate fallback for %s\n", | |
1022 | alg->cra_name); | |
1023 | ctx->sw_cipher = NULL; | |
1024 | } | |
1025 | } | |
1026 | ctx->generic.key_offs = spacc_alg->key_offs; | |
1027 | ctx->generic.iv_offs = spacc_alg->iv_offs; | |
1028 | ||
1029 | tfm->crt_ablkcipher.reqsize = sizeof(struct spacc_req); | |
1030 | ||
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | static void spacc_ablk_cra_exit(struct crypto_tfm *tfm) | |
1035 | { | |
1036 | struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm); | |
1037 | ||
1038 | if (ctx->sw_cipher) | |
1039 | crypto_free_ablkcipher(ctx->sw_cipher); | |
1040 | ctx->sw_cipher = NULL; | |
1041 | } | |
1042 | ||
1043 | static int spacc_ablk_encrypt(struct ablkcipher_request *req) | |
1044 | { | |
1045 | struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req); | |
1046 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
1047 | struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg); | |
1048 | ||
1049 | return spacc_ablk_setup(req, alg->type, 1); | |
1050 | } | |
1051 | ||
1052 | static int spacc_ablk_decrypt(struct ablkcipher_request *req) | |
1053 | { | |
1054 | struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req); | |
1055 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
1056 | struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg); | |
1057 | ||
1058 | return spacc_ablk_setup(req, alg->type, 0); | |
1059 | } | |
1060 | ||
1061 | static inline int spacc_fifo_stat_empty(struct spacc_engine *engine) | |
1062 | { | |
1063 | return readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET) & | |
1064 | SPA_FIFO_STAT_EMPTY; | |
1065 | } | |
1066 | ||
1067 | static void spacc_process_done(struct spacc_engine *engine) | |
1068 | { | |
1069 | struct spacc_req *req; | |
1070 | unsigned long flags; | |
1071 | ||
1072 | spin_lock_irqsave(&engine->hw_lock, flags); | |
1073 | ||
1074 | while (!spacc_fifo_stat_empty(engine)) { | |
1075 | req = list_first_entry(&engine->in_progress, struct spacc_req, | |
1076 | list); | |
1077 | list_move_tail(&req->list, &engine->completed); | |
40bfc14f | 1078 | --engine->in_flight; |
ce921368 JI |
1079 | |
1080 | /* POP the status register. */ | |
1081 | writel(~0, engine->regs + SPA_STAT_POP_REG_OFFSET); | |
1082 | req->result = (readl(engine->regs + SPA_STATUS_REG_OFFSET) & | |
1083 | SPA_STATUS_RES_CODE_MASK) >> SPA_STATUS_RES_CODE_OFFSET; | |
1084 | ||
1085 | /* | |
1086 | * Convert the SPAcc error status into the standard POSIX error | |
1087 | * codes. | |
1088 | */ | |
1089 | if (unlikely(req->result)) { | |
1090 | switch (req->result) { | |
1091 | case SPA_STATUS_ICV_FAIL: | |
1092 | req->result = -EBADMSG; | |
1093 | break; | |
1094 | ||
1095 | case SPA_STATUS_MEMORY_ERROR: | |
1096 | dev_warn(engine->dev, | |
1097 | "memory error triggered\n"); | |
1098 | req->result = -EFAULT; | |
1099 | break; | |
1100 | ||
1101 | case SPA_STATUS_BLOCK_ERROR: | |
1102 | dev_warn(engine->dev, | |
1103 | "block error triggered\n"); | |
1104 | req->result = -EIO; | |
1105 | break; | |
1106 | } | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | tasklet_schedule(&engine->complete); | |
1111 | ||
1112 | spin_unlock_irqrestore(&engine->hw_lock, flags); | |
1113 | } | |
1114 | ||
1115 | static irqreturn_t spacc_spacc_irq(int irq, void *dev) | |
1116 | { | |
1117 | struct spacc_engine *engine = (struct spacc_engine *)dev; | |
1118 | u32 spacc_irq_stat = readl(engine->regs + SPA_IRQ_STAT_REG_OFFSET); | |
1119 | ||
1120 | writel(spacc_irq_stat, engine->regs + SPA_IRQ_STAT_REG_OFFSET); | |
1121 | spacc_process_done(engine); | |
1122 | ||
1123 | return IRQ_HANDLED; | |
1124 | } | |
1125 | ||
1126 | static void spacc_packet_timeout(unsigned long data) | |
1127 | { | |
1128 | struct spacc_engine *engine = (struct spacc_engine *)data; | |
1129 | ||
1130 | spacc_process_done(engine); | |
1131 | } | |
1132 | ||
1133 | static int spacc_req_submit(struct spacc_req *req) | |
1134 | { | |
1135 | struct crypto_alg *alg = req->req->tfm->__crt_alg; | |
1136 | ||
1137 | if (CRYPTO_ALG_TYPE_AEAD == (CRYPTO_ALG_TYPE_MASK & alg->cra_flags)) | |
1138 | return spacc_aead_submit(req); | |
1139 | else | |
1140 | return spacc_ablk_submit(req); | |
1141 | } | |
1142 | ||
1143 | static void spacc_spacc_complete(unsigned long data) | |
1144 | { | |
1145 | struct spacc_engine *engine = (struct spacc_engine *)data; | |
1146 | struct spacc_req *req, *tmp; | |
1147 | unsigned long flags; | |
ce921368 JI |
1148 | LIST_HEAD(completed); |
1149 | ||
1150 | spin_lock_irqsave(&engine->hw_lock, flags); | |
40bfc14f | 1151 | |
ce921368 | 1152 | list_splice_init(&engine->completed, &completed); |
40bfc14f JI |
1153 | spacc_push(engine); |
1154 | if (engine->in_flight) | |
1155 | mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT); | |
1156 | ||
ce921368 JI |
1157 | spin_unlock_irqrestore(&engine->hw_lock, flags); |
1158 | ||
1159 | list_for_each_entry_safe(req, tmp, &completed, list) { | |
40bfc14f | 1160 | list_del(&req->list); |
b64dc04b | 1161 | req->complete(req); |
ce921368 | 1162 | } |
ce921368 JI |
1163 | } |
1164 | ||
1165 | #ifdef CONFIG_PM | |
1166 | static int spacc_suspend(struct device *dev) | |
1167 | { | |
1168 | struct platform_device *pdev = to_platform_device(dev); | |
1169 | struct spacc_engine *engine = platform_get_drvdata(pdev); | |
1170 | ||
1171 | /* | |
1172 | * We only support standby mode. All we have to do is gate the clock to | |
1173 | * the spacc. The hardware will preserve state until we turn it back | |
1174 | * on again. | |
1175 | */ | |
1176 | clk_disable(engine->clk); | |
1177 | ||
1178 | return 0; | |
1179 | } | |
1180 | ||
1181 | static int spacc_resume(struct device *dev) | |
1182 | { | |
1183 | struct platform_device *pdev = to_platform_device(dev); | |
1184 | struct spacc_engine *engine = platform_get_drvdata(pdev); | |
1185 | ||
1186 | return clk_enable(engine->clk); | |
1187 | } | |
1188 | ||
1189 | static const struct dev_pm_ops spacc_pm_ops = { | |
1190 | .suspend = spacc_suspend, | |
1191 | .resume = spacc_resume, | |
1192 | }; | |
1193 | #endif /* CONFIG_PM */ | |
1194 | ||
1195 | static inline struct spacc_engine *spacc_dev_to_engine(struct device *dev) | |
1196 | { | |
1197 | return dev ? platform_get_drvdata(to_platform_device(dev)) : NULL; | |
1198 | } | |
1199 | ||
1200 | static ssize_t spacc_stat_irq_thresh_show(struct device *dev, | |
1201 | struct device_attribute *attr, | |
1202 | char *buf) | |
1203 | { | |
1204 | struct spacc_engine *engine = spacc_dev_to_engine(dev); | |
1205 | ||
1206 | return snprintf(buf, PAGE_SIZE, "%u\n", engine->stat_irq_thresh); | |
1207 | } | |
1208 | ||
1209 | static ssize_t spacc_stat_irq_thresh_store(struct device *dev, | |
1210 | struct device_attribute *attr, | |
1211 | const char *buf, size_t len) | |
1212 | { | |
1213 | struct spacc_engine *engine = spacc_dev_to_engine(dev); | |
1214 | unsigned long thresh; | |
1215 | ||
61e2d1a9 | 1216 | if (kstrtoul(buf, 0, &thresh)) |
ce921368 JI |
1217 | return -EINVAL; |
1218 | ||
1219 | thresh = clamp(thresh, 1UL, engine->fifo_sz - 1); | |
1220 | ||
1221 | engine->stat_irq_thresh = thresh; | |
1222 | writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET, | |
1223 | engine->regs + SPA_IRQ_CTRL_REG_OFFSET); | |
1224 | ||
1225 | return len; | |
1226 | } | |
1227 | static DEVICE_ATTR(stat_irq_thresh, 0644, spacc_stat_irq_thresh_show, | |
1228 | spacc_stat_irq_thresh_store); | |
1229 | ||
1230 | static struct spacc_alg ipsec_engine_algs[] = { | |
1231 | { | |
1232 | .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_CBC, | |
1233 | .key_offs = 0, | |
1234 | .iv_offs = AES_MAX_KEY_SIZE, | |
1235 | .alg = { | |
1236 | .cra_name = "cbc(aes)", | |
1237 | .cra_driver_name = "cbc-aes-picoxcell", | |
1238 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
1239 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
d912bb76 | 1240 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
ce921368 JI |
1241 | CRYPTO_ALG_ASYNC | |
1242 | CRYPTO_ALG_NEED_FALLBACK, | |
1243 | .cra_blocksize = AES_BLOCK_SIZE, | |
1244 | .cra_ctxsize = sizeof(struct spacc_ablk_ctx), | |
1245 | .cra_type = &crypto_ablkcipher_type, | |
1246 | .cra_module = THIS_MODULE, | |
1247 | .cra_ablkcipher = { | |
1248 | .setkey = spacc_aes_setkey, | |
1249 | .encrypt = spacc_ablk_encrypt, | |
1250 | .decrypt = spacc_ablk_decrypt, | |
1251 | .min_keysize = AES_MIN_KEY_SIZE, | |
1252 | .max_keysize = AES_MAX_KEY_SIZE, | |
1253 | .ivsize = AES_BLOCK_SIZE, | |
1254 | }, | |
1255 | .cra_init = spacc_ablk_cra_init, | |
1256 | .cra_exit = spacc_ablk_cra_exit, | |
1257 | }, | |
1258 | }, | |
1259 | { | |
1260 | .key_offs = 0, | |
1261 | .iv_offs = AES_MAX_KEY_SIZE, | |
1262 | .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_ECB, | |
1263 | .alg = { | |
1264 | .cra_name = "ecb(aes)", | |
1265 | .cra_driver_name = "ecb-aes-picoxcell", | |
1266 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
1267 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
d912bb76 | 1268 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
ce921368 JI |
1269 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, |
1270 | .cra_blocksize = AES_BLOCK_SIZE, | |
1271 | .cra_ctxsize = sizeof(struct spacc_ablk_ctx), | |
1272 | .cra_type = &crypto_ablkcipher_type, | |
1273 | .cra_module = THIS_MODULE, | |
1274 | .cra_ablkcipher = { | |
1275 | .setkey = spacc_aes_setkey, | |
1276 | .encrypt = spacc_ablk_encrypt, | |
1277 | .decrypt = spacc_ablk_decrypt, | |
1278 | .min_keysize = AES_MIN_KEY_SIZE, | |
1279 | .max_keysize = AES_MAX_KEY_SIZE, | |
1280 | }, | |
1281 | .cra_init = spacc_ablk_cra_init, | |
1282 | .cra_exit = spacc_ablk_cra_exit, | |
1283 | }, | |
1284 | }, | |
1285 | { | |
1286 | .key_offs = DES_BLOCK_SIZE, | |
1287 | .iv_offs = 0, | |
1288 | .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_CBC, | |
1289 | .alg = { | |
1290 | .cra_name = "cbc(des)", | |
1291 | .cra_driver_name = "cbc-des-picoxcell", | |
1292 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
d912bb76 NM |
1293 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
1294 | CRYPTO_ALG_ASYNC | | |
1295 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
ce921368 JI |
1296 | .cra_blocksize = DES_BLOCK_SIZE, |
1297 | .cra_ctxsize = sizeof(struct spacc_ablk_ctx), | |
1298 | .cra_type = &crypto_ablkcipher_type, | |
1299 | .cra_module = THIS_MODULE, | |
1300 | .cra_ablkcipher = { | |
1301 | .setkey = spacc_des_setkey, | |
1302 | .encrypt = spacc_ablk_encrypt, | |
1303 | .decrypt = spacc_ablk_decrypt, | |
1304 | .min_keysize = DES_KEY_SIZE, | |
1305 | .max_keysize = DES_KEY_SIZE, | |
1306 | .ivsize = DES_BLOCK_SIZE, | |
1307 | }, | |
1308 | .cra_init = spacc_ablk_cra_init, | |
1309 | .cra_exit = spacc_ablk_cra_exit, | |
1310 | }, | |
1311 | }, | |
1312 | { | |
1313 | .key_offs = DES_BLOCK_SIZE, | |
1314 | .iv_offs = 0, | |
1315 | .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_ECB, | |
1316 | .alg = { | |
1317 | .cra_name = "ecb(des)", | |
1318 | .cra_driver_name = "ecb-des-picoxcell", | |
1319 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
d912bb76 NM |
1320 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
1321 | CRYPTO_ALG_ASYNC | | |
1322 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
ce921368 JI |
1323 | .cra_blocksize = DES_BLOCK_SIZE, |
1324 | .cra_ctxsize = sizeof(struct spacc_ablk_ctx), | |
1325 | .cra_type = &crypto_ablkcipher_type, | |
1326 | .cra_module = THIS_MODULE, | |
1327 | .cra_ablkcipher = { | |
1328 | .setkey = spacc_des_setkey, | |
1329 | .encrypt = spacc_ablk_encrypt, | |
1330 | .decrypt = spacc_ablk_decrypt, | |
1331 | .min_keysize = DES_KEY_SIZE, | |
1332 | .max_keysize = DES_KEY_SIZE, | |
1333 | }, | |
1334 | .cra_init = spacc_ablk_cra_init, | |
1335 | .cra_exit = spacc_ablk_cra_exit, | |
1336 | }, | |
1337 | }, | |
1338 | { | |
1339 | .key_offs = DES_BLOCK_SIZE, | |
1340 | .iv_offs = 0, | |
1341 | .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_CBC, | |
1342 | .alg = { | |
1343 | .cra_name = "cbc(des3_ede)", | |
1344 | .cra_driver_name = "cbc-des3-ede-picoxcell", | |
1345 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
d912bb76 NM |
1346 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
1347 | CRYPTO_ALG_ASYNC | | |
1348 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
ce921368 JI |
1349 | .cra_blocksize = DES3_EDE_BLOCK_SIZE, |
1350 | .cra_ctxsize = sizeof(struct spacc_ablk_ctx), | |
1351 | .cra_type = &crypto_ablkcipher_type, | |
1352 | .cra_module = THIS_MODULE, | |
1353 | .cra_ablkcipher = { | |
1354 | .setkey = spacc_des_setkey, | |
1355 | .encrypt = spacc_ablk_encrypt, | |
1356 | .decrypt = spacc_ablk_decrypt, | |
1357 | .min_keysize = DES3_EDE_KEY_SIZE, | |
1358 | .max_keysize = DES3_EDE_KEY_SIZE, | |
1359 | .ivsize = DES3_EDE_BLOCK_SIZE, | |
1360 | }, | |
1361 | .cra_init = spacc_ablk_cra_init, | |
1362 | .cra_exit = spacc_ablk_cra_exit, | |
1363 | }, | |
1364 | }, | |
1365 | { | |
1366 | .key_offs = DES_BLOCK_SIZE, | |
1367 | .iv_offs = 0, | |
1368 | .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_ECB, | |
1369 | .alg = { | |
1370 | .cra_name = "ecb(des3_ede)", | |
1371 | .cra_driver_name = "ecb-des3-ede-picoxcell", | |
1372 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
d912bb76 NM |
1373 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
1374 | CRYPTO_ALG_ASYNC | | |
1375 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
ce921368 JI |
1376 | .cra_blocksize = DES3_EDE_BLOCK_SIZE, |
1377 | .cra_ctxsize = sizeof(struct spacc_ablk_ctx), | |
1378 | .cra_type = &crypto_ablkcipher_type, | |
1379 | .cra_module = THIS_MODULE, | |
1380 | .cra_ablkcipher = { | |
1381 | .setkey = spacc_des_setkey, | |
1382 | .encrypt = spacc_ablk_encrypt, | |
1383 | .decrypt = spacc_ablk_decrypt, | |
1384 | .min_keysize = DES3_EDE_KEY_SIZE, | |
1385 | .max_keysize = DES3_EDE_KEY_SIZE, | |
1386 | }, | |
1387 | .cra_init = spacc_ablk_cra_init, | |
1388 | .cra_exit = spacc_ablk_cra_exit, | |
1389 | }, | |
1390 | }, | |
c1359495 HX |
1391 | }; |
1392 | ||
1393 | static struct spacc_aead ipsec_engine_aeads[] = { | |
ce921368 | 1394 | { |
c1359495 HX |
1395 | .ctrl_default = SPA_CTRL_CIPH_ALG_AES | |
1396 | SPA_CTRL_CIPH_MODE_CBC | | |
1397 | SPA_CTRL_HASH_ALG_SHA | | |
1398 | SPA_CTRL_HASH_MODE_HMAC, | |
ce921368 JI |
1399 | .key_offs = 0, |
1400 | .iv_offs = AES_MAX_KEY_SIZE, | |
1401 | .alg = { | |
c1359495 HX |
1402 | .base = { |
1403 | .cra_name = "authenc(hmac(sha1),cbc(aes))", | |
1404 | .cra_driver_name = "authenc-hmac-sha1-" | |
1405 | "cbc-aes-picoxcell", | |
1406 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
1407 | .cra_flags = CRYPTO_ALG_ASYNC | | |
1408 | CRYPTO_ALG_NEED_FALLBACK | | |
1409 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
1410 | .cra_blocksize = AES_BLOCK_SIZE, | |
1411 | .cra_ctxsize = sizeof(struct spacc_aead_ctx), | |
1412 | .cra_module = THIS_MODULE, | |
ce921368 | 1413 | }, |
c1359495 HX |
1414 | .setkey = spacc_aead_setkey, |
1415 | .setauthsize = spacc_aead_setauthsize, | |
1416 | .encrypt = spacc_aead_encrypt, | |
1417 | .decrypt = spacc_aead_decrypt, | |
1418 | .ivsize = AES_BLOCK_SIZE, | |
1419 | .maxauthsize = SHA1_DIGEST_SIZE, | |
1420 | .init = spacc_aead_cra_init, | |
1421 | .exit = spacc_aead_cra_exit, | |
ce921368 JI |
1422 | }, |
1423 | }, | |
1424 | { | |
c1359495 HX |
1425 | .ctrl_default = SPA_CTRL_CIPH_ALG_AES | |
1426 | SPA_CTRL_CIPH_MODE_CBC | | |
ce921368 JI |
1427 | SPA_CTRL_HASH_ALG_SHA256 | |
1428 | SPA_CTRL_HASH_MODE_HMAC, | |
1429 | .key_offs = 0, | |
1430 | .iv_offs = AES_MAX_KEY_SIZE, | |
1431 | .alg = { | |
c1359495 HX |
1432 | .base = { |
1433 | .cra_name = "authenc(hmac(sha256),cbc(aes))", | |
1434 | .cra_driver_name = "authenc-hmac-sha256-" | |
1435 | "cbc-aes-picoxcell", | |
1436 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
1437 | .cra_flags = CRYPTO_ALG_ASYNC | | |
1438 | CRYPTO_ALG_NEED_FALLBACK | | |
1439 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
1440 | .cra_blocksize = AES_BLOCK_SIZE, | |
1441 | .cra_ctxsize = sizeof(struct spacc_aead_ctx), | |
1442 | .cra_module = THIS_MODULE, | |
ce921368 | 1443 | }, |
c1359495 HX |
1444 | .setkey = spacc_aead_setkey, |
1445 | .setauthsize = spacc_aead_setauthsize, | |
1446 | .encrypt = spacc_aead_encrypt, | |
1447 | .decrypt = spacc_aead_decrypt, | |
1448 | .ivsize = AES_BLOCK_SIZE, | |
1449 | .maxauthsize = SHA256_DIGEST_SIZE, | |
1450 | .init = spacc_aead_cra_init, | |
1451 | .exit = spacc_aead_cra_exit, | |
ce921368 JI |
1452 | }, |
1453 | }, | |
1454 | { | |
1455 | .key_offs = 0, | |
1456 | .iv_offs = AES_MAX_KEY_SIZE, | |
c1359495 HX |
1457 | .ctrl_default = SPA_CTRL_CIPH_ALG_AES | |
1458 | SPA_CTRL_CIPH_MODE_CBC | | |
1459 | SPA_CTRL_HASH_ALG_MD5 | | |
1460 | SPA_CTRL_HASH_MODE_HMAC, | |
ce921368 | 1461 | .alg = { |
c1359495 HX |
1462 | .base = { |
1463 | .cra_name = "authenc(hmac(md5),cbc(aes))", | |
1464 | .cra_driver_name = "authenc-hmac-md5-" | |
1465 | "cbc-aes-picoxcell", | |
1466 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
1467 | .cra_flags = CRYPTO_ALG_ASYNC | | |
1468 | CRYPTO_ALG_NEED_FALLBACK | | |
1469 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
1470 | .cra_blocksize = AES_BLOCK_SIZE, | |
1471 | .cra_ctxsize = sizeof(struct spacc_aead_ctx), | |
1472 | .cra_module = THIS_MODULE, | |
ce921368 | 1473 | }, |
c1359495 HX |
1474 | .setkey = spacc_aead_setkey, |
1475 | .setauthsize = spacc_aead_setauthsize, | |
1476 | .encrypt = spacc_aead_encrypt, | |
1477 | .decrypt = spacc_aead_decrypt, | |
1478 | .ivsize = AES_BLOCK_SIZE, | |
1479 | .maxauthsize = MD5_DIGEST_SIZE, | |
1480 | .init = spacc_aead_cra_init, | |
1481 | .exit = spacc_aead_cra_exit, | |
ce921368 JI |
1482 | }, |
1483 | }, | |
1484 | { | |
1485 | .key_offs = DES_BLOCK_SIZE, | |
1486 | .iv_offs = 0, | |
c1359495 HX |
1487 | .ctrl_default = SPA_CTRL_CIPH_ALG_DES | |
1488 | SPA_CTRL_CIPH_MODE_CBC | | |
1489 | SPA_CTRL_HASH_ALG_SHA | | |
1490 | SPA_CTRL_HASH_MODE_HMAC, | |
ce921368 | 1491 | .alg = { |
c1359495 HX |
1492 | .base = { |
1493 | .cra_name = "authenc(hmac(sha1),cbc(des3_ede))", | |
1494 | .cra_driver_name = "authenc-hmac-sha1-" | |
1495 | "cbc-3des-picoxcell", | |
1496 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
1497 | .cra_flags = CRYPTO_ALG_ASYNC | | |
1498 | CRYPTO_ALG_NEED_FALLBACK | | |
1499 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
1500 | .cra_blocksize = DES3_EDE_BLOCK_SIZE, | |
1501 | .cra_ctxsize = sizeof(struct spacc_aead_ctx), | |
1502 | .cra_module = THIS_MODULE, | |
ce921368 | 1503 | }, |
c1359495 HX |
1504 | .setkey = spacc_aead_setkey, |
1505 | .setauthsize = spacc_aead_setauthsize, | |
1506 | .encrypt = spacc_aead_encrypt, | |
1507 | .decrypt = spacc_aead_decrypt, | |
1508 | .ivsize = DES3_EDE_BLOCK_SIZE, | |
1509 | .maxauthsize = SHA1_DIGEST_SIZE, | |
1510 | .init = spacc_aead_cra_init, | |
1511 | .exit = spacc_aead_cra_exit, | |
ce921368 JI |
1512 | }, |
1513 | }, | |
1514 | { | |
1515 | .key_offs = DES_BLOCK_SIZE, | |
1516 | .iv_offs = 0, | |
c1359495 HX |
1517 | .ctrl_default = SPA_CTRL_CIPH_ALG_AES | |
1518 | SPA_CTRL_CIPH_MODE_CBC | | |
ce921368 JI |
1519 | SPA_CTRL_HASH_ALG_SHA256 | |
1520 | SPA_CTRL_HASH_MODE_HMAC, | |
1521 | .alg = { | |
c1359495 HX |
1522 | .base = { |
1523 | .cra_name = "authenc(hmac(sha256)," | |
1524 | "cbc(des3_ede))", | |
1525 | .cra_driver_name = "authenc-hmac-sha256-" | |
1526 | "cbc-3des-picoxcell", | |
1527 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
1528 | .cra_flags = CRYPTO_ALG_ASYNC | | |
1529 | CRYPTO_ALG_NEED_FALLBACK | | |
1530 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
1531 | .cra_blocksize = DES3_EDE_BLOCK_SIZE, | |
1532 | .cra_ctxsize = sizeof(struct spacc_aead_ctx), | |
1533 | .cra_module = THIS_MODULE, | |
ce921368 | 1534 | }, |
c1359495 HX |
1535 | .setkey = spacc_aead_setkey, |
1536 | .setauthsize = spacc_aead_setauthsize, | |
1537 | .encrypt = spacc_aead_encrypt, | |
1538 | .decrypt = spacc_aead_decrypt, | |
1539 | .ivsize = DES3_EDE_BLOCK_SIZE, | |
1540 | .maxauthsize = SHA256_DIGEST_SIZE, | |
1541 | .init = spacc_aead_cra_init, | |
1542 | .exit = spacc_aead_cra_exit, | |
ce921368 JI |
1543 | }, |
1544 | }, | |
1545 | { | |
1546 | .key_offs = DES_BLOCK_SIZE, | |
1547 | .iv_offs = 0, | |
c1359495 HX |
1548 | .ctrl_default = SPA_CTRL_CIPH_ALG_DES | |
1549 | SPA_CTRL_CIPH_MODE_CBC | | |
1550 | SPA_CTRL_HASH_ALG_MD5 | | |
1551 | SPA_CTRL_HASH_MODE_HMAC, | |
ce921368 | 1552 | .alg = { |
c1359495 HX |
1553 | .base = { |
1554 | .cra_name = "authenc(hmac(md5),cbc(des3_ede))", | |
1555 | .cra_driver_name = "authenc-hmac-md5-" | |
1556 | "cbc-3des-picoxcell", | |
1557 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
1558 | .cra_flags = CRYPTO_ALG_ASYNC | | |
1559 | CRYPTO_ALG_NEED_FALLBACK | | |
1560 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
1561 | .cra_blocksize = DES3_EDE_BLOCK_SIZE, | |
1562 | .cra_ctxsize = sizeof(struct spacc_aead_ctx), | |
1563 | .cra_module = THIS_MODULE, | |
ce921368 | 1564 | }, |
c1359495 HX |
1565 | .setkey = spacc_aead_setkey, |
1566 | .setauthsize = spacc_aead_setauthsize, | |
1567 | .encrypt = spacc_aead_encrypt, | |
1568 | .decrypt = spacc_aead_decrypt, | |
1569 | .ivsize = DES3_EDE_BLOCK_SIZE, | |
1570 | .maxauthsize = MD5_DIGEST_SIZE, | |
1571 | .init = spacc_aead_cra_init, | |
1572 | .exit = spacc_aead_cra_exit, | |
ce921368 JI |
1573 | }, |
1574 | }, | |
1575 | }; | |
1576 | ||
1577 | static struct spacc_alg l2_engine_algs[] = { | |
1578 | { | |
1579 | .key_offs = 0, | |
1580 | .iv_offs = SPACC_CRYPTO_KASUMI_F8_KEY_LEN, | |
1581 | .ctrl_default = SPA_CTRL_CIPH_ALG_KASUMI | | |
1582 | SPA_CTRL_CIPH_MODE_F8, | |
1583 | .alg = { | |
1584 | .cra_name = "f8(kasumi)", | |
1585 | .cra_driver_name = "f8-kasumi-picoxcell", | |
1586 | .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, | |
d912bb76 NM |
1587 | .cra_flags = CRYPTO_ALG_TYPE_GIVCIPHER | |
1588 | CRYPTO_ALG_ASYNC | | |
1589 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
ce921368 JI |
1590 | .cra_blocksize = 8, |
1591 | .cra_ctxsize = sizeof(struct spacc_ablk_ctx), | |
1592 | .cra_type = &crypto_ablkcipher_type, | |
1593 | .cra_module = THIS_MODULE, | |
1594 | .cra_ablkcipher = { | |
1595 | .setkey = spacc_kasumi_f8_setkey, | |
1596 | .encrypt = spacc_ablk_encrypt, | |
1597 | .decrypt = spacc_ablk_decrypt, | |
1598 | .min_keysize = 16, | |
1599 | .max_keysize = 16, | |
1600 | .ivsize = 8, | |
1601 | }, | |
1602 | .cra_init = spacc_ablk_cra_init, | |
1603 | .cra_exit = spacc_ablk_cra_exit, | |
1604 | }, | |
1605 | }, | |
1606 | }; | |
1607 | ||
30343ef1 JI |
1608 | #ifdef CONFIG_OF |
1609 | static const struct of_device_id spacc_of_id_table[] = { | |
1610 | { .compatible = "picochip,spacc-ipsec" }, | |
1611 | { .compatible = "picochip,spacc-l2" }, | |
1612 | {} | |
1613 | }; | |
c3abc0f3 | 1614 | MODULE_DEVICE_TABLE(of, spacc_of_id_table); |
30343ef1 JI |
1615 | #endif /* CONFIG_OF */ |
1616 | ||
1617 | static bool spacc_is_compatible(struct platform_device *pdev, | |
1618 | const char *spacc_type) | |
1619 | { | |
1620 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
1621 | ||
1622 | if (platid && !strcmp(platid->name, spacc_type)) | |
1623 | return true; | |
1624 | ||
1625 | #ifdef CONFIG_OF | |
1626 | if (of_device_is_compatible(pdev->dev.of_node, spacc_type)) | |
1627 | return true; | |
1628 | #endif /* CONFIG_OF */ | |
1629 | ||
1630 | return false; | |
1631 | } | |
1632 | ||
49cfe4db | 1633 | static int spacc_probe(struct platform_device *pdev) |
ce921368 JI |
1634 | { |
1635 | int i, err, ret = -EINVAL; | |
1636 | struct resource *mem, *irq; | |
1637 | struct spacc_engine *engine = devm_kzalloc(&pdev->dev, sizeof(*engine), | |
1638 | GFP_KERNEL); | |
1639 | if (!engine) | |
1640 | return -ENOMEM; | |
1641 | ||
30343ef1 | 1642 | if (spacc_is_compatible(pdev, "picochip,spacc-ipsec")) { |
c3f4200f JI |
1643 | engine->max_ctxs = SPACC_CRYPTO_IPSEC_MAX_CTXS; |
1644 | engine->cipher_pg_sz = SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ; | |
1645 | engine->hash_pg_sz = SPACC_CRYPTO_IPSEC_HASH_PG_SZ; | |
1646 | engine->fifo_sz = SPACC_CRYPTO_IPSEC_FIFO_SZ; | |
1647 | engine->algs = ipsec_engine_algs; | |
1648 | engine->num_algs = ARRAY_SIZE(ipsec_engine_algs); | |
c1359495 HX |
1649 | engine->aeads = ipsec_engine_aeads; |
1650 | engine->num_aeads = ARRAY_SIZE(ipsec_engine_aeads); | |
30343ef1 | 1651 | } else if (spacc_is_compatible(pdev, "picochip,spacc-l2")) { |
c3f4200f JI |
1652 | engine->max_ctxs = SPACC_CRYPTO_L2_MAX_CTXS; |
1653 | engine->cipher_pg_sz = SPACC_CRYPTO_L2_CIPHER_PG_SZ; | |
1654 | engine->hash_pg_sz = SPACC_CRYPTO_L2_HASH_PG_SZ; | |
1655 | engine->fifo_sz = SPACC_CRYPTO_L2_FIFO_SZ; | |
1656 | engine->algs = l2_engine_algs; | |
1657 | engine->num_algs = ARRAY_SIZE(l2_engine_algs); | |
1658 | } else { | |
1659 | return -EINVAL; | |
1660 | } | |
1661 | ||
1662 | engine->name = dev_name(&pdev->dev); | |
ce921368 JI |
1663 | |
1664 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
32af1e18 JH |
1665 | engine->regs = devm_ioremap_resource(&pdev->dev, mem); |
1666 | if (IS_ERR(engine->regs)) | |
1667 | return PTR_ERR(engine->regs); | |
1668 | ||
ce921368 | 1669 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
32af1e18 | 1670 | if (!irq) { |
ce921368 JI |
1671 | dev_err(&pdev->dev, "no memory/irq resource for engine\n"); |
1672 | return -ENXIO; | |
1673 | } | |
1674 | ||
ce921368 JI |
1675 | if (devm_request_irq(&pdev->dev, irq->start, spacc_spacc_irq, 0, |
1676 | engine->name, engine)) { | |
1677 | dev_err(engine->dev, "failed to request IRQ\n"); | |
1678 | return -EBUSY; | |
1679 | } | |
1680 | ||
1681 | engine->dev = &pdev->dev; | |
1682 | engine->cipher_ctx_base = engine->regs + SPA_CIPH_KEY_BASE_REG_OFFSET; | |
1683 | engine->hash_key_base = engine->regs + SPA_HASH_KEY_BASE_REG_OFFSET; | |
1684 | ||
1685 | engine->req_pool = dmam_pool_create(engine->name, engine->dev, | |
1686 | MAX_DDT_LEN * sizeof(struct spacc_ddt), 8, SZ_64K); | |
1687 | if (!engine->req_pool) | |
1688 | return -ENOMEM; | |
1689 | ||
1690 | spin_lock_init(&engine->hw_lock); | |
1691 | ||
4efae8c9 | 1692 | engine->clk = clk_get(&pdev->dev, "ref"); |
ce921368 JI |
1693 | if (IS_ERR(engine->clk)) { |
1694 | dev_info(&pdev->dev, "clk unavailable\n"); | |
1695 | device_remove_file(&pdev->dev, &dev_attr_stat_irq_thresh); | |
1696 | return PTR_ERR(engine->clk); | |
1697 | } | |
1698 | ||
1bd2cd6b MW |
1699 | if (clk_prepare_enable(engine->clk)) { |
1700 | dev_info(&pdev->dev, "unable to prepare/enable clk\n"); | |
ce921368 JI |
1701 | clk_put(engine->clk); |
1702 | return -EIO; | |
1703 | } | |
1704 | ||
1705 | err = device_create_file(&pdev->dev, &dev_attr_stat_irq_thresh); | |
1706 | if (err) { | |
1bd2cd6b | 1707 | clk_disable_unprepare(engine->clk); |
ce921368 JI |
1708 | clk_put(engine->clk); |
1709 | return err; | |
1710 | } | |
1711 | ||
1712 | ||
1713 | /* | |
1714 | * Use an IRQ threshold of 50% as a default. This seems to be a | |
1715 | * reasonable trade off of latency against throughput but can be | |
1716 | * changed at runtime. | |
1717 | */ | |
1718 | engine->stat_irq_thresh = (engine->fifo_sz / 2); | |
1719 | ||
1720 | /* | |
1721 | * Configure the interrupts. We only use the STAT_CNT interrupt as we | |
1722 | * only submit a new packet for processing when we complete another in | |
1723 | * the queue. This minimizes time spent in the interrupt handler. | |
1724 | */ | |
1725 | writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET, | |
1726 | engine->regs + SPA_IRQ_CTRL_REG_OFFSET); | |
1727 | writel(SPA_IRQ_EN_STAT_EN | SPA_IRQ_EN_GLBL_EN, | |
1728 | engine->regs + SPA_IRQ_EN_REG_OFFSET); | |
1729 | ||
1730 | setup_timer(&engine->packet_timeout, spacc_packet_timeout, | |
1731 | (unsigned long)engine); | |
1732 | ||
1733 | INIT_LIST_HEAD(&engine->pending); | |
1734 | INIT_LIST_HEAD(&engine->completed); | |
1735 | INIT_LIST_HEAD(&engine->in_progress); | |
1736 | engine->in_flight = 0; | |
1737 | tasklet_init(&engine->complete, spacc_spacc_complete, | |
1738 | (unsigned long)engine); | |
1739 | ||
1740 | platform_set_drvdata(pdev, engine); | |
1741 | ||
1742 | INIT_LIST_HEAD(&engine->registered_algs); | |
1743 | for (i = 0; i < engine->num_algs; ++i) { | |
1744 | engine->algs[i].engine = engine; | |
1745 | err = crypto_register_alg(&engine->algs[i].alg); | |
1746 | if (!err) { | |
1747 | list_add_tail(&engine->algs[i].entry, | |
1748 | &engine->registered_algs); | |
1749 | ret = 0; | |
1750 | } | |
1751 | if (err) | |
1752 | dev_err(engine->dev, "failed to register alg \"%s\"\n", | |
1753 | engine->algs[i].alg.cra_name); | |
1754 | else | |
1755 | dev_dbg(engine->dev, "registered alg \"%s\"\n", | |
1756 | engine->algs[i].alg.cra_name); | |
1757 | } | |
1758 | ||
c1359495 HX |
1759 | INIT_LIST_HEAD(&engine->registered_aeads); |
1760 | for (i = 0; i < engine->num_aeads; ++i) { | |
1761 | engine->aeads[i].engine = engine; | |
c1359495 HX |
1762 | err = crypto_register_aead(&engine->aeads[i].alg); |
1763 | if (!err) { | |
1764 | list_add_tail(&engine->aeads[i].entry, | |
1765 | &engine->registered_aeads); | |
1766 | ret = 0; | |
1767 | } | |
1768 | if (err) | |
1769 | dev_err(engine->dev, "failed to register alg \"%s\"\n", | |
1770 | engine->aeads[i].alg.base.cra_name); | |
1771 | else | |
1772 | dev_dbg(engine->dev, "registered alg \"%s\"\n", | |
1773 | engine->aeads[i].alg.base.cra_name); | |
1774 | } | |
1775 | ||
ce921368 JI |
1776 | return ret; |
1777 | } | |
1778 | ||
49cfe4db | 1779 | static int spacc_remove(struct platform_device *pdev) |
ce921368 | 1780 | { |
c1359495 | 1781 | struct spacc_aead *aead, *an; |
ce921368 JI |
1782 | struct spacc_alg *alg, *next; |
1783 | struct spacc_engine *engine = platform_get_drvdata(pdev); | |
1784 | ||
1785 | del_timer_sync(&engine->packet_timeout); | |
1786 | device_remove_file(&pdev->dev, &dev_attr_stat_irq_thresh); | |
1787 | ||
c1359495 HX |
1788 | list_for_each_entry_safe(aead, an, &engine->registered_aeads, entry) { |
1789 | list_del(&aead->entry); | |
1790 | crypto_unregister_aead(&aead->alg); | |
1791 | } | |
1792 | ||
ce921368 JI |
1793 | list_for_each_entry_safe(alg, next, &engine->registered_algs, entry) { |
1794 | list_del(&alg->entry); | |
1795 | crypto_unregister_alg(&alg->alg); | |
1796 | } | |
1797 | ||
1bd2cd6b | 1798 | clk_disable_unprepare(engine->clk); |
ce921368 JI |
1799 | clk_put(engine->clk); |
1800 | ||
1801 | return 0; | |
1802 | } | |
1803 | ||
c3f4200f JI |
1804 | static const struct platform_device_id spacc_id_table[] = { |
1805 | { "picochip,spacc-ipsec", }, | |
1806 | { "picochip,spacc-l2", }, | |
14198dd6 | 1807 | { } |
ce921368 JI |
1808 | }; |
1809 | ||
c3f4200f JI |
1810 | static struct platform_driver spacc_driver = { |
1811 | .probe = spacc_probe, | |
49cfe4db | 1812 | .remove = spacc_remove, |
ce921368 | 1813 | .driver = { |
c3f4200f | 1814 | .name = "picochip,spacc", |
ce921368 JI |
1815 | #ifdef CONFIG_PM |
1816 | .pm = &spacc_pm_ops, | |
1817 | #endif /* CONFIG_PM */ | |
5cec26e9 | 1818 | .of_match_table = of_match_ptr(spacc_of_id_table), |
ce921368 | 1819 | }, |
c3f4200f | 1820 | .id_table = spacc_id_table, |
ce921368 JI |
1821 | }; |
1822 | ||
741e8c2d | 1823 | module_platform_driver(spacc_driver); |
ce921368 JI |
1824 | |
1825 | MODULE_LICENSE("GPL"); | |
1826 | MODULE_AUTHOR("Jamie Iles"); |