]>
Commit | Line | Data |
---|---|---|
ceec5f5b VK |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2017-18 Linaro Limited | |
3 | // | |
4 | // Based on msm-rng.c and downstream driver | |
5 | ||
6 | #include <crypto/internal/rng.h> | |
d96542ac | 7 | #include <linux/acpi.h> |
ceec5f5b VK |
8 | #include <linux/clk.h> |
9 | #include <linux/crypto.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of.h> | |
12 | #include <linux/platform_device.h> | |
13 | ||
14 | /* Device specific register offsets */ | |
15 | #define PRNG_DATA_OUT 0x0000 | |
16 | #define PRNG_STATUS 0x0004 | |
17 | #define PRNG_LFSR_CFG 0x0100 | |
18 | #define PRNG_CONFIG 0x0104 | |
19 | ||
20 | /* Device specific register masks and config values */ | |
21 | #define PRNG_LFSR_CFG_MASK 0x0000ffff | |
22 | #define PRNG_LFSR_CFG_CLOCKS 0x0000dddd | |
23 | #define PRNG_CONFIG_HW_ENABLE BIT(1) | |
24 | #define PRNG_STATUS_DATA_AVAIL BIT(0) | |
25 | ||
26 | #define WORD_SZ 4 | |
27 | ||
28 | struct qcom_rng { | |
29 | struct mutex lock; | |
30 | void __iomem *base; | |
31 | struct clk *clk; | |
ba3ab637 | 32 | unsigned int skip_init; |
ceec5f5b VK |
33 | }; |
34 | ||
35 | struct qcom_rng_ctx { | |
36 | struct qcom_rng *rng; | |
37 | }; | |
38 | ||
39 | static struct qcom_rng *qcom_rng_dev; | |
40 | ||
41 | static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max) | |
42 | { | |
43 | unsigned int currsize = 0; | |
44 | u32 val; | |
45 | ||
46 | /* read random data from hardware */ | |
47 | do { | |
48 | val = readl_relaxed(rng->base + PRNG_STATUS); | |
49 | if (!(val & PRNG_STATUS_DATA_AVAIL)) | |
50 | break; | |
51 | ||
52 | val = readl_relaxed(rng->base + PRNG_DATA_OUT); | |
53 | if (!val) | |
54 | break; | |
55 | ||
56 | if ((max - currsize) >= WORD_SZ) { | |
57 | memcpy(data, &val, WORD_SZ); | |
58 | data += WORD_SZ; | |
59 | currsize += WORD_SZ; | |
60 | } else { | |
61 | /* copy only remaining bytes */ | |
62 | memcpy(data, &val, max - currsize); | |
63 | break; | |
64 | } | |
65 | } while (currsize < max); | |
66 | ||
67 | return currsize; | |
68 | } | |
69 | ||
70 | static int qcom_rng_generate(struct crypto_rng *tfm, | |
71 | const u8 *src, unsigned int slen, | |
72 | u8 *dstn, unsigned int dlen) | |
73 | { | |
74 | struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm); | |
75 | struct qcom_rng *rng = ctx->rng; | |
76 | int ret; | |
77 | ||
78 | ret = clk_prepare_enable(rng->clk); | |
79 | if (ret) | |
80 | return ret; | |
81 | ||
82 | mutex_lock(&rng->lock); | |
83 | ||
84 | ret = qcom_rng_read(rng, dstn, dlen); | |
85 | ||
86 | mutex_unlock(&rng->lock); | |
87 | clk_disable_unprepare(rng->clk); | |
88 | ||
89 | return 0; | |
90 | } | |
91 | ||
92 | static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed, | |
93 | unsigned int slen) | |
94 | { | |
95 | return 0; | |
96 | } | |
97 | ||
98 | static int qcom_rng_enable(struct qcom_rng *rng) | |
99 | { | |
100 | u32 val; | |
101 | int ret; | |
102 | ||
103 | ret = clk_prepare_enable(rng->clk); | |
104 | if (ret) | |
105 | return ret; | |
106 | ||
107 | /* Enable PRNG only if it is not already enabled */ | |
108 | val = readl_relaxed(rng->base + PRNG_CONFIG); | |
109 | if (val & PRNG_CONFIG_HW_ENABLE) | |
110 | goto already_enabled; | |
111 | ||
112 | val = readl_relaxed(rng->base + PRNG_LFSR_CFG); | |
113 | val &= ~PRNG_LFSR_CFG_MASK; | |
114 | val |= PRNG_LFSR_CFG_CLOCKS; | |
115 | writel(val, rng->base + PRNG_LFSR_CFG); | |
116 | ||
117 | val = readl_relaxed(rng->base + PRNG_CONFIG); | |
118 | val |= PRNG_CONFIG_HW_ENABLE; | |
119 | writel(val, rng->base + PRNG_CONFIG); | |
120 | ||
121 | already_enabled: | |
122 | clk_disable_unprepare(rng->clk); | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | static int qcom_rng_init(struct crypto_tfm *tfm) | |
128 | { | |
129 | struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm); | |
130 | ||
131 | ctx->rng = qcom_rng_dev; | |
132 | ||
ba3ab637 VK |
133 | if (!ctx->rng->skip_init) |
134 | return qcom_rng_enable(ctx->rng); | |
135 | ||
136 | return 0; | |
ceec5f5b VK |
137 | } |
138 | ||
139 | static struct rng_alg qcom_rng_alg = { | |
140 | .generate = qcom_rng_generate, | |
141 | .seed = qcom_rng_seed, | |
142 | .seedsize = 0, | |
143 | .base = { | |
144 | .cra_name = "stdrng", | |
145 | .cra_driver_name = "qcom-rng", | |
146 | .cra_flags = CRYPTO_ALG_TYPE_RNG, | |
147 | .cra_priority = 300, | |
148 | .cra_ctxsize = sizeof(struct qcom_rng_ctx), | |
149 | .cra_module = THIS_MODULE, | |
150 | .cra_init = qcom_rng_init, | |
151 | } | |
152 | }; | |
153 | ||
154 | static int qcom_rng_probe(struct platform_device *pdev) | |
155 | { | |
156 | struct resource *res; | |
157 | struct qcom_rng *rng; | |
158 | int ret; | |
159 | ||
160 | rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL); | |
161 | if (!rng) | |
162 | return -ENOMEM; | |
163 | ||
164 | platform_set_drvdata(pdev, rng); | |
165 | mutex_init(&rng->lock); | |
166 | ||
167 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
168 | rng->base = devm_ioremap_resource(&pdev->dev, res); | |
169 | if (IS_ERR(rng->base)) | |
170 | return PTR_ERR(rng->base); | |
171 | ||
d96542ac TT |
172 | /* ACPI systems have clk already on, so skip clk_get */ |
173 | if (!has_acpi_companion(&pdev->dev)) { | |
174 | rng->clk = devm_clk_get(&pdev->dev, "core"); | |
175 | if (IS_ERR(rng->clk)) | |
176 | return PTR_ERR(rng->clk); | |
177 | } | |
178 | ||
ceec5f5b | 179 | |
ba3ab637 VK |
180 | rng->skip_init = (unsigned long)device_get_match_data(&pdev->dev); |
181 | ||
ceec5f5b VK |
182 | qcom_rng_dev = rng; |
183 | ret = crypto_register_rng(&qcom_rng_alg); | |
184 | if (ret) { | |
185 | dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret); | |
186 | qcom_rng_dev = NULL; | |
187 | } | |
188 | ||
189 | return ret; | |
190 | } | |
191 | ||
192 | static int qcom_rng_remove(struct platform_device *pdev) | |
193 | { | |
194 | crypto_unregister_rng(&qcom_rng_alg); | |
195 | ||
196 | qcom_rng_dev = NULL; | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
d96542ac TT |
201 | #if IS_ENABLED(CONFIG_ACPI) |
202 | static const struct acpi_device_id qcom_rng_acpi_match[] = { | |
203 | { .id = "QCOM8160", .driver_data = 1 }, | |
204 | {} | |
205 | }; | |
206 | MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match); | |
207 | #endif | |
208 | ||
ceec5f5b | 209 | static const struct of_device_id qcom_rng_of_match[] = { |
ba3ab637 VK |
210 | { .compatible = "qcom,prng", .data = (void *)0}, |
211 | { .compatible = "qcom,prng-ee", .data = (void *)1}, | |
ceec5f5b VK |
212 | {} |
213 | }; | |
214 | MODULE_DEVICE_TABLE(of, qcom_rng_of_match); | |
215 | ||
216 | static struct platform_driver qcom_rng_driver = { | |
217 | .probe = qcom_rng_probe, | |
218 | .remove = qcom_rng_remove, | |
219 | .driver = { | |
220 | .name = KBUILD_MODNAME, | |
221 | .of_match_table = of_match_ptr(qcom_rng_of_match), | |
d96542ac | 222 | .acpi_match_table = ACPI_PTR(qcom_rng_acpi_match), |
ceec5f5b VK |
223 | } |
224 | }; | |
225 | module_platform_driver(qcom_rng_driver); | |
226 | ||
227 | MODULE_ALIAS("platform:" KBUILD_MODNAME); | |
228 | MODULE_DESCRIPTION("Qualcomm random number generator driver"); | |
229 | MODULE_LICENSE("GPL v2"); |