[mirror_ubuntu-focal-kernel.git] / drivers / crypto / qcom-rng.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2017-18 Linaro Limited
//
// Based on msm-rng.c and downstream driver

#include <crypto/internal/rng.h>
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/crypto.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>

/* Device specific register offsets */
#define PRNG_DATA_OUT		0x0000
#define PRNG_STATUS		0x0004
#define PRNG_LFSR_CFG		0x0100
#define PRNG_CONFIG		0x0104

/* Device specific register masks and config values */
#define PRNG_LFSR_CFG_MASK	0x0000ffff
#define PRNG_LFSR_CFG_CLOCKS	0x0000dddd
#define PRNG_CONFIG_HW_ENABLE	BIT(1)
#define PRNG_STATUS_DATA_AVAIL	BIT(0)

#define WORD_SZ			4

struct qcom_rng {
	struct mutex lock;
	void __iomem *base;
	struct clk *clk;
	unsigned int skip_init;
};

struct qcom_rng_ctx {
	struct qcom_rng *rng;
};

static struct qcom_rng *qcom_rng_dev;

static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max)
{
	unsigned int currsize = 0;
	u32 val;
	int ret;

	/* read random data from hardware */
	do {
		ret = readl_poll_timeout(rng->base + PRNG_STATUS, val,
					 val & PRNG_STATUS_DATA_AVAIL,
					 200, 10000);
		if (ret)
			return ret;

		val = readl_relaxed(rng->base + PRNG_DATA_OUT);
		if (!val)
			return -EINVAL;

		if ((max - currsize) >= WORD_SZ) {
			memcpy(data, &val, WORD_SZ);
			data += WORD_SZ;
			currsize += WORD_SZ;
		} else {
			/* copy only remaining bytes */
			memcpy(data, &val, max - currsize);
		}
	} while (currsize < max);

	return 0;
}

static int qcom_rng_generate(struct crypto_rng *tfm,
			     const u8 *src, unsigned int slen,
			     u8 *dstn, unsigned int dlen)
{
	struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm);
	struct qcom_rng *rng = ctx->rng;
	int ret;

	ret = clk_prepare_enable(rng->clk);
	if (ret)
		return ret;

	mutex_lock(&rng->lock);

	ret = qcom_rng_read(rng, dstn, dlen);

	mutex_unlock(&rng->lock);
	clk_disable_unprepare(rng->clk);

	return ret;
}

static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed,
			 unsigned int slen)
{
	return 0;
}

static int qcom_rng_enable(struct qcom_rng *rng)
{
	u32 val;
	int ret;

	ret = clk_prepare_enable(rng->clk);
	if (ret)
		return ret;

	/* Enable PRNG only if it is not already enabled */
	val = readl_relaxed(rng->base + PRNG_CONFIG);
	if (val & PRNG_CONFIG_HW_ENABLE)
		goto already_enabled;

	val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
	val &= ~PRNG_LFSR_CFG_MASK;
	val |= PRNG_LFSR_CFG_CLOCKS;
	writel(val, rng->base + PRNG_LFSR_CFG);

	val = readl_relaxed(rng->base + PRNG_CONFIG);
	val |= PRNG_CONFIG_HW_ENABLE;
	writel(val, rng->base + PRNG_CONFIG);

already_enabled:
	clk_disable_unprepare(rng->clk);

	return 0;
}

static int qcom_rng_init(struct crypto_tfm *tfm)
{
	struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm);

	ctx->rng = qcom_rng_dev;

	if (!ctx->rng->skip_init)
		return qcom_rng_enable(ctx->rng);

	return 0;
}

static struct rng_alg qcom_rng_alg = {
	.generate	= qcom_rng_generate,
	.seed		= qcom_rng_seed,
	.seedsize	= 0,
	.base		= {
		.cra_name		= "stdrng",
		.cra_driver_name	= "qcom-rng",
		.cra_flags		= CRYPTO_ALG_TYPE_RNG,
		.cra_priority		= 300,
		.cra_ctxsize		= sizeof(struct qcom_rng_ctx),
		.cra_module		= THIS_MODULE,
		.cra_init		= qcom_rng_init,
	}
};

static int qcom_rng_probe(struct platform_device *pdev)
{
	struct qcom_rng *rng;
	int ret;

	rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
	if (!rng)
		return -ENOMEM;

	platform_set_drvdata(pdev, rng);
	mutex_init(&rng->lock);

	rng->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(rng->base))
		return PTR_ERR(rng->base);

	/* ACPI systems have clk already on, so skip clk_get */
	if (!has_acpi_companion(&pdev->dev)) {
		rng->clk = devm_clk_get(&pdev->dev, "core");
		if (IS_ERR(rng->clk))
			return PTR_ERR(rng->clk);
	}


	rng->skip_init = (unsigned long)device_get_match_data(&pdev->dev);

	qcom_rng_dev = rng;
	ret = crypto_register_rng(&qcom_rng_alg);
	if (ret) {
		dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
		qcom_rng_dev = NULL;
	}

	return ret;
}

static int qcom_rng_remove(struct platform_device *pdev)
{
	crypto_unregister_rng(&qcom_rng_alg);

	qcom_rng_dev = NULL;

	return 0;
}

#if IS_ENABLED(CONFIG_ACPI)
static const struct acpi_device_id qcom_rng_acpi_match[] = {
	{ .id = "QCOM8160", .driver_data = 1 },
	{}
};
MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match);
#endif

static const struct of_device_id qcom_rng_of_match[] = {
	{ .compatible = "qcom,prng", .data = (void *)0},
	{ .compatible = "qcom,prng-ee", .data = (void *)1},
	{}
};
MODULE_DEVICE_TABLE(of, qcom_rng_of_match);

static struct platform_driver qcom_rng_driver = {
	.probe = qcom_rng_probe,
	.remove =  qcom_rng_remove,
	.driver = {
		.name = KBUILD_MODNAME,
		.of_match_table = of_match_ptr(qcom_rng_of_match),
		.acpi_match_table = ACPI_PTR(qcom_rng_acpi_match),
	}
};
module_platform_driver(qcom_rng_driver);

MODULE_ALIAS("platform:" KBUILD_MODNAME);
MODULE_DESCRIPTION("Qualcomm random number generator driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ceec5f5b VK	1	// SPDX-License-Identifier: GPL-2.0
	2	// Copyright (c) 2017-18 Linaro Limited
	3	//
	4	// Based on msm-rng.c and downstream driver
	5
	6	#include <crypto/internal/rng.h>
d96542ac	7	#include <linux/acpi.h>
ceec5f5b VK	8	#include <linux/clk.h>
ceec5f5b VK	9	#include <linux/crypto.h>
22422968	10	#include <linux/iopoll.h>
ceec5f5b VK	11	#include <linux/module.h>
	12	#include <linux/of.h>
	13	#include <linux/platform_device.h>
	14
	15	/* Device specific register offsets */
	16	#define PRNG_DATA_OUT 0x0000
	17	#define PRNG_STATUS 0x0004
	18	#define PRNG_LFSR_CFG 0x0100
	19	#define PRNG_CONFIG 0x0104
	20
	21	/* Device specific register masks and config values */
	22	#define PRNG_LFSR_CFG_MASK 0x0000ffff
	23	#define PRNG_LFSR_CFG_CLOCKS 0x0000dddd
	24	#define PRNG_CONFIG_HW_ENABLE BIT(1)
	25	#define PRNG_STATUS_DATA_AVAIL BIT(0)
	26
	27	#define WORD_SZ 4
	28
	29	struct qcom_rng {
	30	struct mutex lock;
	31	void __iomem *base;
	32	struct clk *clk;
ba3ab637	33	unsigned int skip_init;
ceec5f5b VK	34	};
	35
	36	struct qcom_rng_ctx {
	37	struct qcom_rng *rng;
	38	};
	39
	40	static struct qcom_rng *qcom_rng_dev;
	41
	42	static int qcom_rng_read(struct qcom_rng rng, u8 data, unsigned int max)
	43	{
	44	unsigned int currsize = 0;
	45	u32 val;
22422968	46	int ret;
ceec5f5b VK	47
	48	/* read random data from hardware */
	49	do {
22422968 BM	50	ret = readl_poll_timeout(rng->base + PRNG_STATUS, val,
	51	val & PRNG_STATUS_DATA_AVAIL,
	52	200, 10000);
	53	if (ret)
	54	return ret;
ceec5f5b VK	55
	56	val = readl_relaxed(rng->base + PRNG_DATA_OUT);
	57	if (!val)
22422968	58	return -EINVAL;
ceec5f5b VK	59
	60	if ((max - currsize) >= WORD_SZ) {
	61	memcpy(data, &val, WORD_SZ);
	62	data += WORD_SZ;
	63	currsize += WORD_SZ;
	64	} else {
	65	/* copy only remaining bytes */
	66	memcpy(data, &val, max - currsize);
ceec5f5b VK	67	}
	68	} while (currsize < max);
	69
22422968	70	return 0;
ceec5f5b VK	71	}
	72
	73	static int qcom_rng_generate(struct crypto_rng *tfm,
	74	const u8 *src, unsigned int slen,
	75	u8 *dstn, unsigned int dlen)
	76	{
	77	struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm);
	78	struct qcom_rng *rng = ctx->rng;
	79	int ret;
	80
	81	ret = clk_prepare_enable(rng->clk);
	82	if (ret)
	83	return ret;
	84
	85	mutex_lock(&rng->lock);
	86
	87	ret = qcom_rng_read(rng, dstn, dlen);
	88
	89	mutex_unlock(&rng->lock);
	90	clk_disable_unprepare(rng->clk);
	91
22422968	92	return ret;
ceec5f5b VK	93	}
	94
	95	static int qcom_rng_seed(struct crypto_rng tfm, const u8 seed,
	96	unsigned int slen)
	97	{
	98	return 0;
	99	}
	100
	101	static int qcom_rng_enable(struct qcom_rng *rng)
	102	{
	103	u32 val;
	104	int ret;
	105
	106	ret = clk_prepare_enable(rng->clk);
	107	if (ret)
	108	return ret;
	109
	110	/* Enable PRNG only if it is not already enabled */
	111	val = readl_relaxed(rng->base + PRNG_CONFIG);
	112	if (val & PRNG_CONFIG_HW_ENABLE)
	113	goto already_enabled;
	114
	115	val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
	116	val &= ~PRNG_LFSR_CFG_MASK;
	117	val \|= PRNG_LFSR_CFG_CLOCKS;
	118	writel(val, rng->base + PRNG_LFSR_CFG);
	119
	120	val = readl_relaxed(rng->base + PRNG_CONFIG);
	121	val \|= PRNG_CONFIG_HW_ENABLE;
	122	writel(val, rng->base + PRNG_CONFIG);
	123
	124	already_enabled:
	125	clk_disable_unprepare(rng->clk);
	126
	127	return 0;
	128	}
	129
	130	static int qcom_rng_init(struct crypto_tfm *tfm)
	131	{
	132	struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm);
	133
	134	ctx->rng = qcom_rng_dev;
	135
ba3ab637 VK	136	if (!ctx->rng->skip_init)
	137	return qcom_rng_enable(ctx->rng);
	138
	139	return 0;
ceec5f5b VK	140	}
	141
	142	static struct rng_alg qcom_rng_alg = {
	143	.generate = qcom_rng_generate,
	144	.seed = qcom_rng_seed,
	145	.seedsize = 0,
	146	.base = {
	147	.cra_name = "stdrng",
	148	.cra_driver_name = "qcom-rng",
	149	.cra_flags = CRYPTO_ALG_TYPE_RNG,
	150	.cra_priority = 300,
	151	.cra_ctxsize = sizeof(struct qcom_rng_ctx),
	152	.cra_module = THIS_MODULE,
	153	.cra_init = qcom_rng_init,
	154	}
	155	};
	156
	157	static int qcom_rng_probe(struct platform_device *pdev)
	158	{
ceec5f5b VK	159	struct qcom_rng *rng;
	160	int ret;
	161
	162	rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
	163	if (!rng)
	164	return -ENOMEM;
	165
	166	platform_set_drvdata(pdev, rng);
	167	mutex_init(&rng->lock);
	168
2229c740	169	rng->base = devm_platform_ioremap_resource(pdev, 0);
ceec5f5b VK	170	if (IS_ERR(rng->base))
	171	return PTR_ERR(rng->base);
	172
d96542ac TT	173	/* ACPI systems have clk already on, so skip clk_get */
	174	if (!has_acpi_companion(&pdev->dev)) {
	175	rng->clk = devm_clk_get(&pdev->dev, "core");
	176	if (IS_ERR(rng->clk))
	177	return PTR_ERR(rng->clk);
	178	}
	179
ceec5f5b	180
ba3ab637 VK	181	rng->skip_init = (unsigned long)device_get_match_data(&pdev->dev);
ba3ab637 VK	182
ceec5f5b VK	183	qcom_rng_dev = rng;
	184	ret = crypto_register_rng(&qcom_rng_alg);
	185	if (ret) {
	186	dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
	187	qcom_rng_dev = NULL;
	188	}
	189
	190	return ret;
	191	}
	192
	193	static int qcom_rng_remove(struct platform_device *pdev)
	194	{
	195	crypto_unregister_rng(&qcom_rng_alg);
	196
	197	qcom_rng_dev = NULL;
	198
	199	return 0;
	200	}
	201
d96542ac TT	202	#if IS_ENABLED(CONFIG_ACPI)
	203	static const struct acpi_device_id qcom_rng_acpi_match[] = {
	204	{ .id = "QCOM8160", .driver_data = 1 },
	205	{}
	206	};
	207	MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match);
	208	#endif
	209
ceec5f5b	210	static const struct of_device_id qcom_rng_of_match[] = {
ba3ab637 VK	211	{ .compatible = "qcom,prng", .data = (void *)0},
ba3ab637 VK	212	{ .compatible = "qcom,prng-ee", .data = (void *)1},
ceec5f5b VK	213	{}
	214	};
	215	MODULE_DEVICE_TABLE(of, qcom_rng_of_match);
	216
	217	static struct platform_driver qcom_rng_driver = {
	218	.probe = qcom_rng_probe,
	219	.remove = qcom_rng_remove,
	220	.driver = {
	221	.name = KBUILD_MODNAME,
	222	.of_match_table = of_match_ptr(qcom_rng_of_match),
d96542ac	223	.acpi_match_table = ACPI_PTR(qcom_rng_acpi_match),
ceec5f5b VK	224	}
	225	};
	226	module_platform_driver(qcom_rng_driver);
	227
	228	MODULE_ALIAS("platform:" KBUILD_MODNAME);
	229	MODULE_DESCRIPTION("Qualcomm random number generator driver");
	230	MODULE_LICENSE("GPL v2");