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Commit | Line | Data |
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a49e490c VZ |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for Samsung S5PV210 HW acceleration. | |
5 | * | |
6 | * Copyright (C) 2011 NetUP Inc. All rights reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as published | |
10 | * by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/delay.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/scatterlist.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/io.h> | |
6b9f16e6 | 25 | #include <linux/of.h> |
a49e490c VZ |
26 | #include <linux/crypto.h> |
27 | #include <linux/interrupt.h> | |
28 | ||
29 | #include <crypto/algapi.h> | |
30 | #include <crypto/aes.h> | |
31 | #include <crypto/ctr.h> | |
32 | ||
a49e490c VZ |
33 | #define _SBF(s, v) ((v) << (s)) |
34 | #define _BIT(b) _SBF(b, 1) | |
35 | ||
36 | /* Feed control registers */ | |
37 | #define SSS_REG_FCINTSTAT 0x0000 | |
38 | #define SSS_FCINTSTAT_BRDMAINT _BIT(3) | |
39 | #define SSS_FCINTSTAT_BTDMAINT _BIT(2) | |
40 | #define SSS_FCINTSTAT_HRDMAINT _BIT(1) | |
41 | #define SSS_FCINTSTAT_PKDMAINT _BIT(0) | |
42 | ||
43 | #define SSS_REG_FCINTENSET 0x0004 | |
44 | #define SSS_FCINTENSET_BRDMAINTENSET _BIT(3) | |
45 | #define SSS_FCINTENSET_BTDMAINTENSET _BIT(2) | |
46 | #define SSS_FCINTENSET_HRDMAINTENSET _BIT(1) | |
47 | #define SSS_FCINTENSET_PKDMAINTENSET _BIT(0) | |
48 | ||
49 | #define SSS_REG_FCINTENCLR 0x0008 | |
50 | #define SSS_FCINTENCLR_BRDMAINTENCLR _BIT(3) | |
51 | #define SSS_FCINTENCLR_BTDMAINTENCLR _BIT(2) | |
52 | #define SSS_FCINTENCLR_HRDMAINTENCLR _BIT(1) | |
53 | #define SSS_FCINTENCLR_PKDMAINTENCLR _BIT(0) | |
54 | ||
55 | #define SSS_REG_FCINTPEND 0x000C | |
56 | #define SSS_FCINTPEND_BRDMAINTP _BIT(3) | |
57 | #define SSS_FCINTPEND_BTDMAINTP _BIT(2) | |
58 | #define SSS_FCINTPEND_HRDMAINTP _BIT(1) | |
59 | #define SSS_FCINTPEND_PKDMAINTP _BIT(0) | |
60 | ||
61 | #define SSS_REG_FCFIFOSTAT 0x0010 | |
62 | #define SSS_FCFIFOSTAT_BRFIFOFUL _BIT(7) | |
63 | #define SSS_FCFIFOSTAT_BRFIFOEMP _BIT(6) | |
64 | #define SSS_FCFIFOSTAT_BTFIFOFUL _BIT(5) | |
65 | #define SSS_FCFIFOSTAT_BTFIFOEMP _BIT(4) | |
66 | #define SSS_FCFIFOSTAT_HRFIFOFUL _BIT(3) | |
67 | #define SSS_FCFIFOSTAT_HRFIFOEMP _BIT(2) | |
68 | #define SSS_FCFIFOSTAT_PKFIFOFUL _BIT(1) | |
69 | #define SSS_FCFIFOSTAT_PKFIFOEMP _BIT(0) | |
70 | ||
71 | #define SSS_REG_FCFIFOCTRL 0x0014 | |
72 | #define SSS_FCFIFOCTRL_DESSEL _BIT(2) | |
73 | #define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00) | |
74 | #define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01) | |
75 | #define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02) | |
76 | ||
77 | #define SSS_REG_FCBRDMAS 0x0020 | |
78 | #define SSS_REG_FCBRDMAL 0x0024 | |
79 | #define SSS_REG_FCBRDMAC 0x0028 | |
80 | #define SSS_FCBRDMAC_BYTESWAP _BIT(1) | |
81 | #define SSS_FCBRDMAC_FLUSH _BIT(0) | |
82 | ||
83 | #define SSS_REG_FCBTDMAS 0x0030 | |
84 | #define SSS_REG_FCBTDMAL 0x0034 | |
85 | #define SSS_REG_FCBTDMAC 0x0038 | |
86 | #define SSS_FCBTDMAC_BYTESWAP _BIT(1) | |
87 | #define SSS_FCBTDMAC_FLUSH _BIT(0) | |
88 | ||
89 | #define SSS_REG_FCHRDMAS 0x0040 | |
90 | #define SSS_REG_FCHRDMAL 0x0044 | |
91 | #define SSS_REG_FCHRDMAC 0x0048 | |
92 | #define SSS_FCHRDMAC_BYTESWAP _BIT(1) | |
93 | #define SSS_FCHRDMAC_FLUSH _BIT(0) | |
94 | ||
95 | #define SSS_REG_FCPKDMAS 0x0050 | |
96 | #define SSS_REG_FCPKDMAL 0x0054 | |
97 | #define SSS_REG_FCPKDMAC 0x0058 | |
98 | #define SSS_FCPKDMAC_BYTESWAP _BIT(3) | |
99 | #define SSS_FCPKDMAC_DESCEND _BIT(2) | |
100 | #define SSS_FCPKDMAC_TRANSMIT _BIT(1) | |
101 | #define SSS_FCPKDMAC_FLUSH _BIT(0) | |
102 | ||
103 | #define SSS_REG_FCPKDMAO 0x005C | |
104 | ||
105 | /* AES registers */ | |
89245107 | 106 | #define SSS_REG_AES_CONTROL 0x00 |
a49e490c VZ |
107 | #define SSS_AES_BYTESWAP_DI _BIT(11) |
108 | #define SSS_AES_BYTESWAP_DO _BIT(10) | |
109 | #define SSS_AES_BYTESWAP_IV _BIT(9) | |
110 | #define SSS_AES_BYTESWAP_CNT _BIT(8) | |
111 | #define SSS_AES_BYTESWAP_KEY _BIT(7) | |
112 | #define SSS_AES_KEY_CHANGE_MODE _BIT(6) | |
113 | #define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00) | |
114 | #define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01) | |
115 | #define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02) | |
116 | #define SSS_AES_FIFO_MODE _BIT(3) | |
117 | #define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00) | |
118 | #define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01) | |
119 | #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02) | |
120 | #define SSS_AES_MODE_DECRYPT _BIT(0) | |
121 | ||
89245107 | 122 | #define SSS_REG_AES_STATUS 0x04 |
a49e490c VZ |
123 | #define SSS_AES_BUSY _BIT(2) |
124 | #define SSS_AES_INPUT_READY _BIT(1) | |
125 | #define SSS_AES_OUTPUT_READY _BIT(0) | |
126 | ||
89245107 NKC |
127 | #define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2)) |
128 | #define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2)) | |
129 | #define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2)) | |
130 | #define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2)) | |
131 | #define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2)) | |
a49e490c VZ |
132 | |
133 | #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg)) | |
134 | #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) | |
135 | #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) | |
136 | ||
89245107 NKC |
137 | #define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg) |
138 | #define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \ | |
139 | SSS_AES_REG(dev, reg)) | |
140 | ||
a49e490c VZ |
141 | /* HW engine modes */ |
142 | #define FLAGS_AES_DECRYPT _BIT(0) | |
143 | #define FLAGS_AES_MODE_MASK _SBF(1, 0x03) | |
144 | #define FLAGS_AES_CBC _SBF(1, 0x01) | |
145 | #define FLAGS_AES_CTR _SBF(1, 0x02) | |
146 | ||
147 | #define AES_KEY_LEN 16 | |
148 | #define CRYPTO_QUEUE_LEN 1 | |
149 | ||
89245107 NKC |
150 | /** |
151 | * struct samsung_aes_variant - platform specific SSS driver data | |
152 | * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise | |
153 | * @aes_offset: AES register offset from SSS module's base. | |
154 | * | |
155 | * Specifies platform specific configuration of SSS module. | |
156 | * Note: A structure for driver specific platform data is used for future | |
157 | * expansion of its usage. | |
158 | */ | |
159 | struct samsung_aes_variant { | |
160 | bool has_hash_irq; | |
161 | unsigned int aes_offset; | |
162 | }; | |
163 | ||
a49e490c VZ |
164 | struct s5p_aes_reqctx { |
165 | unsigned long mode; | |
166 | }; | |
167 | ||
168 | struct s5p_aes_ctx { | |
169 | struct s5p_aes_dev *dev; | |
170 | ||
171 | uint8_t aes_key[AES_MAX_KEY_SIZE]; | |
172 | uint8_t nonce[CTR_RFC3686_NONCE_SIZE]; | |
173 | int keylen; | |
174 | }; | |
175 | ||
176 | struct s5p_aes_dev { | |
177 | struct device *dev; | |
178 | struct clk *clk; | |
179 | void __iomem *ioaddr; | |
89245107 | 180 | void __iomem *aes_ioaddr; |
a49e490c VZ |
181 | int irq_hash; |
182 | int irq_fc; | |
183 | ||
184 | struct ablkcipher_request *req; | |
185 | struct s5p_aes_ctx *ctx; | |
186 | struct scatterlist *sg_src; | |
187 | struct scatterlist *sg_dst; | |
188 | ||
189 | struct tasklet_struct tasklet; | |
190 | struct crypto_queue queue; | |
191 | bool busy; | |
192 | spinlock_t lock; | |
89245107 NKC |
193 | |
194 | struct samsung_aes_variant *variant; | |
a49e490c VZ |
195 | }; |
196 | ||
197 | static struct s5p_aes_dev *s5p_dev; | |
198 | ||
89245107 NKC |
199 | static const struct samsung_aes_variant s5p_aes_data = { |
200 | .has_hash_irq = true, | |
201 | .aes_offset = 0x4000, | |
202 | }; | |
203 | ||
204 | static const struct samsung_aes_variant exynos_aes_data = { | |
205 | .has_hash_irq = false, | |
206 | .aes_offset = 0x200, | |
207 | }; | |
208 | ||
6b9f16e6 | 209 | static const struct of_device_id s5p_sss_dt_match[] = { |
89245107 NKC |
210 | { |
211 | .compatible = "samsung,s5pv210-secss", | |
212 | .data = &s5p_aes_data, | |
213 | }, | |
214 | { | |
215 | .compatible = "samsung,exynos4210-secss", | |
216 | .data = &exynos_aes_data, | |
217 | }, | |
6b9f16e6 NKC |
218 | { }, |
219 | }; | |
220 | MODULE_DEVICE_TABLE(of, s5p_sss_dt_match); | |
221 | ||
89245107 NKC |
222 | static inline struct samsung_aes_variant *find_s5p_sss_version |
223 | (struct platform_device *pdev) | |
224 | { | |
225 | if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) { | |
226 | const struct of_device_id *match; | |
313becd1 | 227 | |
89245107 NKC |
228 | match = of_match_node(s5p_sss_dt_match, |
229 | pdev->dev.of_node); | |
230 | return (struct samsung_aes_variant *)match->data; | |
231 | } | |
232 | return (struct samsung_aes_variant *) | |
233 | platform_get_device_id(pdev)->driver_data; | |
234 | } | |
235 | ||
a49e490c VZ |
236 | static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg) |
237 | { | |
238 | SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg)); | |
239 | SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg)); | |
240 | } | |
241 | ||
242 | static void s5p_set_dma_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg) | |
243 | { | |
244 | SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg)); | |
245 | SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg)); | |
246 | } | |
247 | ||
248 | static void s5p_aes_complete(struct s5p_aes_dev *dev, int err) | |
249 | { | |
250 | /* holding a lock outside */ | |
251 | dev->req->base.complete(&dev->req->base, err); | |
252 | dev->busy = false; | |
253 | } | |
254 | ||
255 | static void s5p_unset_outdata(struct s5p_aes_dev *dev) | |
256 | { | |
257 | dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE); | |
258 | } | |
259 | ||
260 | static void s5p_unset_indata(struct s5p_aes_dev *dev) | |
261 | { | |
262 | dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE); | |
263 | } | |
264 | ||
265 | static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg) | |
266 | { | |
267 | int err; | |
268 | ||
269 | if (!IS_ALIGNED(sg_dma_len(sg), AES_BLOCK_SIZE)) { | |
270 | err = -EINVAL; | |
271 | goto exit; | |
272 | } | |
273 | if (!sg_dma_len(sg)) { | |
274 | err = -EINVAL; | |
275 | goto exit; | |
276 | } | |
277 | ||
278 | err = dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE); | |
279 | if (!err) { | |
280 | err = -ENOMEM; | |
281 | goto exit; | |
282 | } | |
283 | ||
284 | dev->sg_dst = sg; | |
285 | err = 0; | |
286 | ||
287 | exit: | |
288 | return err; | |
289 | } | |
290 | ||
291 | static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg) | |
292 | { | |
293 | int err; | |
294 | ||
295 | if (!IS_ALIGNED(sg_dma_len(sg), AES_BLOCK_SIZE)) { | |
296 | err = -EINVAL; | |
297 | goto exit; | |
298 | } | |
299 | if (!sg_dma_len(sg)) { | |
300 | err = -EINVAL; | |
301 | goto exit; | |
302 | } | |
303 | ||
304 | err = dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE); | |
305 | if (!err) { | |
306 | err = -ENOMEM; | |
307 | goto exit; | |
308 | } | |
309 | ||
310 | dev->sg_src = sg; | |
311 | err = 0; | |
312 | ||
313 | exit: | |
314 | return err; | |
315 | } | |
316 | ||
317 | static void s5p_aes_tx(struct s5p_aes_dev *dev) | |
318 | { | |
319 | int err = 0; | |
320 | ||
321 | s5p_unset_outdata(dev); | |
322 | ||
323 | if (!sg_is_last(dev->sg_dst)) { | |
324 | err = s5p_set_outdata(dev, sg_next(dev->sg_dst)); | |
325 | if (err) { | |
326 | s5p_aes_complete(dev, err); | |
327 | return; | |
328 | } | |
329 | ||
330 | s5p_set_dma_outdata(dev, dev->sg_dst); | |
dc5e3f19 | 331 | } else { |
a49e490c | 332 | s5p_aes_complete(dev, err); |
dc5e3f19 NKC |
333 | |
334 | dev->busy = true; | |
335 | tasklet_schedule(&dev->tasklet); | |
336 | } | |
a49e490c VZ |
337 | } |
338 | ||
339 | static void s5p_aes_rx(struct s5p_aes_dev *dev) | |
340 | { | |
341 | int err; | |
342 | ||
343 | s5p_unset_indata(dev); | |
344 | ||
345 | if (!sg_is_last(dev->sg_src)) { | |
346 | err = s5p_set_indata(dev, sg_next(dev->sg_src)); | |
347 | if (err) { | |
348 | s5p_aes_complete(dev, err); | |
349 | return; | |
350 | } | |
351 | ||
352 | s5p_set_dma_indata(dev, dev->sg_src); | |
353 | } | |
354 | } | |
355 | ||
356 | static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id) | |
357 | { | |
358 | struct platform_device *pdev = dev_id; | |
359 | struct s5p_aes_dev *dev = platform_get_drvdata(pdev); | |
360 | uint32_t status; | |
361 | unsigned long flags; | |
362 | ||
363 | spin_lock_irqsave(&dev->lock, flags); | |
364 | ||
365 | if (irq == dev->irq_fc) { | |
366 | status = SSS_READ(dev, FCINTSTAT); | |
367 | if (status & SSS_FCINTSTAT_BRDMAINT) | |
368 | s5p_aes_rx(dev); | |
369 | if (status & SSS_FCINTSTAT_BTDMAINT) | |
370 | s5p_aes_tx(dev); | |
371 | ||
372 | SSS_WRITE(dev, FCINTPEND, status); | |
373 | } | |
374 | ||
375 | spin_unlock_irqrestore(&dev->lock, flags); | |
376 | ||
377 | return IRQ_HANDLED; | |
378 | } | |
379 | ||
380 | static void s5p_set_aes(struct s5p_aes_dev *dev, | |
381 | uint8_t *key, uint8_t *iv, unsigned int keylen) | |
382 | { | |
383 | void __iomem *keystart; | |
384 | ||
8f9702aa | 385 | if (iv) |
1e3012d0 | 386 | memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10); |
a49e490c VZ |
387 | |
388 | if (keylen == AES_KEYSIZE_256) | |
89245107 | 389 | keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0); |
a49e490c | 390 | else if (keylen == AES_KEYSIZE_192) |
89245107 | 391 | keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2); |
a49e490c | 392 | else |
89245107 | 393 | keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4); |
a49e490c | 394 | |
1e3012d0 | 395 | memcpy_toio(keystart, key, keylen); |
a49e490c VZ |
396 | } |
397 | ||
398 | static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode) | |
399 | { | |
400 | struct ablkcipher_request *req = dev->req; | |
a49e490c VZ |
401 | uint32_t aes_control; |
402 | int err; | |
403 | unsigned long flags; | |
404 | ||
405 | aes_control = SSS_AES_KEY_CHANGE_MODE; | |
406 | if (mode & FLAGS_AES_DECRYPT) | |
407 | aes_control |= SSS_AES_MODE_DECRYPT; | |
408 | ||
409 | if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC) | |
410 | aes_control |= SSS_AES_CHAIN_MODE_CBC; | |
411 | else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR) | |
412 | aes_control |= SSS_AES_CHAIN_MODE_CTR; | |
413 | ||
414 | if (dev->ctx->keylen == AES_KEYSIZE_192) | |
415 | aes_control |= SSS_AES_KEY_SIZE_192; | |
416 | else if (dev->ctx->keylen == AES_KEYSIZE_256) | |
417 | aes_control |= SSS_AES_KEY_SIZE_256; | |
418 | ||
419 | aes_control |= SSS_AES_FIFO_MODE; | |
420 | ||
421 | /* as a variant it is possible to use byte swapping on DMA side */ | |
422 | aes_control |= SSS_AES_BYTESWAP_DI | |
423 | | SSS_AES_BYTESWAP_DO | |
424 | | SSS_AES_BYTESWAP_IV | |
425 | | SSS_AES_BYTESWAP_KEY | |
426 | | SSS_AES_BYTESWAP_CNT; | |
427 | ||
428 | spin_lock_irqsave(&dev->lock, flags); | |
429 | ||
430 | SSS_WRITE(dev, FCINTENCLR, | |
431 | SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR); | |
432 | SSS_WRITE(dev, FCFIFOCTRL, 0x00); | |
433 | ||
434 | err = s5p_set_indata(dev, req->src); | |
435 | if (err) | |
436 | goto indata_error; | |
437 | ||
438 | err = s5p_set_outdata(dev, req->dst); | |
439 | if (err) | |
440 | goto outdata_error; | |
441 | ||
89245107 | 442 | SSS_AES_WRITE(dev, AES_CONTROL, aes_control); |
a49e490c VZ |
443 | s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen); |
444 | ||
445 | s5p_set_dma_indata(dev, req->src); | |
446 | s5p_set_dma_outdata(dev, req->dst); | |
447 | ||
448 | SSS_WRITE(dev, FCINTENSET, | |
449 | SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET); | |
450 | ||
451 | spin_unlock_irqrestore(&dev->lock, flags); | |
452 | ||
453 | return; | |
454 | ||
455 | outdata_error: | |
456 | s5p_unset_indata(dev); | |
457 | ||
458 | indata_error: | |
459 | s5p_aes_complete(dev, err); | |
460 | spin_unlock_irqrestore(&dev->lock, flags); | |
461 | } | |
462 | ||
463 | static void s5p_tasklet_cb(unsigned long data) | |
464 | { | |
465 | struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data; | |
466 | struct crypto_async_request *async_req, *backlog; | |
467 | struct s5p_aes_reqctx *reqctx; | |
468 | unsigned long flags; | |
469 | ||
470 | spin_lock_irqsave(&dev->lock, flags); | |
471 | backlog = crypto_get_backlog(&dev->queue); | |
472 | async_req = crypto_dequeue_request(&dev->queue); | |
a49e490c | 473 | |
dc5e3f19 NKC |
474 | if (!async_req) { |
475 | dev->busy = false; | |
476 | spin_unlock_irqrestore(&dev->lock, flags); | |
a49e490c | 477 | return; |
dc5e3f19 NKC |
478 | } |
479 | spin_unlock_irqrestore(&dev->lock, flags); | |
a49e490c VZ |
480 | |
481 | if (backlog) | |
482 | backlog->complete(backlog, -EINPROGRESS); | |
483 | ||
484 | dev->req = ablkcipher_request_cast(async_req); | |
485 | dev->ctx = crypto_tfm_ctx(dev->req->base.tfm); | |
486 | reqctx = ablkcipher_request_ctx(dev->req); | |
487 | ||
488 | s5p_aes_crypt_start(dev, reqctx->mode); | |
489 | } | |
490 | ||
491 | static int s5p_aes_handle_req(struct s5p_aes_dev *dev, | |
492 | struct ablkcipher_request *req) | |
493 | { | |
494 | unsigned long flags; | |
495 | int err; | |
496 | ||
497 | spin_lock_irqsave(&dev->lock, flags); | |
dc5e3f19 | 498 | err = ablkcipher_enqueue_request(&dev->queue, req); |
a49e490c | 499 | if (dev->busy) { |
a49e490c VZ |
500 | spin_unlock_irqrestore(&dev->lock, flags); |
501 | goto exit; | |
502 | } | |
503 | dev->busy = true; | |
504 | ||
a49e490c VZ |
505 | spin_unlock_irqrestore(&dev->lock, flags); |
506 | ||
507 | tasklet_schedule(&dev->tasklet); | |
508 | ||
509 | exit: | |
510 | return err; | |
511 | } | |
512 | ||
513 | static int s5p_aes_crypt(struct ablkcipher_request *req, unsigned long mode) | |
514 | { | |
515 | struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); | |
516 | struct s5p_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); | |
517 | struct s5p_aes_reqctx *reqctx = ablkcipher_request_ctx(req); | |
518 | struct s5p_aes_dev *dev = ctx->dev; | |
519 | ||
520 | if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) { | |
313becd1 | 521 | dev_err(dev->dev, "request size is not exact amount of AES blocks\n"); |
a49e490c VZ |
522 | return -EINVAL; |
523 | } | |
524 | ||
525 | reqctx->mode = mode; | |
526 | ||
527 | return s5p_aes_handle_req(dev, req); | |
528 | } | |
529 | ||
530 | static int s5p_aes_setkey(struct crypto_ablkcipher *cipher, | |
531 | const uint8_t *key, unsigned int keylen) | |
532 | { | |
533 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
534 | struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm); | |
535 | ||
536 | if (keylen != AES_KEYSIZE_128 && | |
537 | keylen != AES_KEYSIZE_192 && | |
538 | keylen != AES_KEYSIZE_256) | |
539 | return -EINVAL; | |
540 | ||
541 | memcpy(ctx->aes_key, key, keylen); | |
542 | ctx->keylen = keylen; | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
547 | static int s5p_aes_ecb_encrypt(struct ablkcipher_request *req) | |
548 | { | |
549 | return s5p_aes_crypt(req, 0); | |
550 | } | |
551 | ||
552 | static int s5p_aes_ecb_decrypt(struct ablkcipher_request *req) | |
553 | { | |
554 | return s5p_aes_crypt(req, FLAGS_AES_DECRYPT); | |
555 | } | |
556 | ||
557 | static int s5p_aes_cbc_encrypt(struct ablkcipher_request *req) | |
558 | { | |
559 | return s5p_aes_crypt(req, FLAGS_AES_CBC); | |
560 | } | |
561 | ||
562 | static int s5p_aes_cbc_decrypt(struct ablkcipher_request *req) | |
563 | { | |
564 | return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC); | |
565 | } | |
566 | ||
567 | static int s5p_aes_cra_init(struct crypto_tfm *tfm) | |
568 | { | |
313becd1 | 569 | struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm); |
a49e490c VZ |
570 | |
571 | ctx->dev = s5p_dev; | |
572 | tfm->crt_ablkcipher.reqsize = sizeof(struct s5p_aes_reqctx); | |
573 | ||
574 | return 0; | |
575 | } | |
576 | ||
577 | static struct crypto_alg algs[] = { | |
578 | { | |
579 | .cra_name = "ecb(aes)", | |
580 | .cra_driver_name = "ecb-aes-s5p", | |
581 | .cra_priority = 100, | |
582 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
d912bb76 NM |
583 | CRYPTO_ALG_ASYNC | |
584 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
a49e490c VZ |
585 | .cra_blocksize = AES_BLOCK_SIZE, |
586 | .cra_ctxsize = sizeof(struct s5p_aes_ctx), | |
587 | .cra_alignmask = 0x0f, | |
588 | .cra_type = &crypto_ablkcipher_type, | |
589 | .cra_module = THIS_MODULE, | |
590 | .cra_init = s5p_aes_cra_init, | |
591 | .cra_u.ablkcipher = { | |
592 | .min_keysize = AES_MIN_KEY_SIZE, | |
593 | .max_keysize = AES_MAX_KEY_SIZE, | |
594 | .setkey = s5p_aes_setkey, | |
595 | .encrypt = s5p_aes_ecb_encrypt, | |
596 | .decrypt = s5p_aes_ecb_decrypt, | |
597 | } | |
598 | }, | |
599 | { | |
600 | .cra_name = "cbc(aes)", | |
601 | .cra_driver_name = "cbc-aes-s5p", | |
602 | .cra_priority = 100, | |
603 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
d912bb76 NM |
604 | CRYPTO_ALG_ASYNC | |
605 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
a49e490c VZ |
606 | .cra_blocksize = AES_BLOCK_SIZE, |
607 | .cra_ctxsize = sizeof(struct s5p_aes_ctx), | |
608 | .cra_alignmask = 0x0f, | |
609 | .cra_type = &crypto_ablkcipher_type, | |
610 | .cra_module = THIS_MODULE, | |
611 | .cra_init = s5p_aes_cra_init, | |
612 | .cra_u.ablkcipher = { | |
613 | .min_keysize = AES_MIN_KEY_SIZE, | |
614 | .max_keysize = AES_MAX_KEY_SIZE, | |
615 | .ivsize = AES_BLOCK_SIZE, | |
616 | .setkey = s5p_aes_setkey, | |
617 | .encrypt = s5p_aes_cbc_encrypt, | |
618 | .decrypt = s5p_aes_cbc_decrypt, | |
619 | } | |
620 | }, | |
621 | }; | |
622 | ||
623 | static int s5p_aes_probe(struct platform_device *pdev) | |
624 | { | |
625 | int i, j, err = -ENODEV; | |
626 | struct s5p_aes_dev *pdata; | |
627 | struct device *dev = &pdev->dev; | |
628 | struct resource *res; | |
89245107 | 629 | struct samsung_aes_variant *variant; |
a49e490c VZ |
630 | |
631 | if (s5p_dev) | |
632 | return -EEXIST; | |
633 | ||
a49e490c VZ |
634 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
635 | if (!pdata) | |
636 | return -ENOMEM; | |
637 | ||
0fdefe2c JH |
638 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
639 | pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res); | |
640 | if (IS_ERR(pdata->ioaddr)) | |
641 | return PTR_ERR(pdata->ioaddr); | |
a49e490c | 642 | |
89245107 NKC |
643 | variant = find_s5p_sss_version(pdev); |
644 | ||
5c22ba66 | 645 | pdata->clk = devm_clk_get(dev, "secss"); |
a49e490c VZ |
646 | if (IS_ERR(pdata->clk)) { |
647 | dev_err(dev, "failed to find secss clock source\n"); | |
648 | return -ENOENT; | |
649 | } | |
650 | ||
c1eb7ef2 NKC |
651 | err = clk_prepare_enable(pdata->clk); |
652 | if (err < 0) { | |
653 | dev_err(dev, "Enabling SSS clk failed, err %d\n", err); | |
654 | return err; | |
655 | } | |
a49e490c VZ |
656 | |
657 | spin_lock_init(&pdata->lock); | |
a49e490c | 658 | |
89245107 NKC |
659 | pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset; |
660 | ||
96fc70b6 NKC |
661 | pdata->irq_fc = platform_get_irq(pdev, 0); |
662 | if (pdata->irq_fc < 0) { | |
663 | err = pdata->irq_fc; | |
664 | dev_warn(dev, "feed control interrupt is not available.\n"); | |
a49e490c VZ |
665 | goto err_irq; |
666 | } | |
96fc70b6 | 667 | err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt, |
a49e490c VZ |
668 | IRQF_SHARED, pdev->name, pdev); |
669 | if (err < 0) { | |
96fc70b6 | 670 | dev_warn(dev, "feed control interrupt is not available.\n"); |
a49e490c VZ |
671 | goto err_irq; |
672 | } | |
673 | ||
89245107 NKC |
674 | if (variant->has_hash_irq) { |
675 | pdata->irq_hash = platform_get_irq(pdev, 1); | |
676 | if (pdata->irq_hash < 0) { | |
677 | err = pdata->irq_hash; | |
678 | dev_warn(dev, "hash interrupt is not available.\n"); | |
679 | goto err_irq; | |
680 | } | |
681 | err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt, | |
682 | IRQF_SHARED, pdev->name, pdev); | |
683 | if (err < 0) { | |
684 | dev_warn(dev, "hash interrupt is not available.\n"); | |
685 | goto err_irq; | |
686 | } | |
a49e490c VZ |
687 | } |
688 | ||
dc5e3f19 | 689 | pdata->busy = false; |
89245107 | 690 | pdata->variant = variant; |
a49e490c VZ |
691 | pdata->dev = dev; |
692 | platform_set_drvdata(pdev, pdata); | |
693 | s5p_dev = pdata; | |
694 | ||
695 | tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata); | |
696 | crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN); | |
697 | ||
698 | for (i = 0; i < ARRAY_SIZE(algs); i++) { | |
a49e490c VZ |
699 | err = crypto_register_alg(&algs[i]); |
700 | if (err) | |
701 | goto err_algs; | |
702 | } | |
703 | ||
313becd1 | 704 | dev_info(dev, "s5p-sss driver registered\n"); |
a49e490c VZ |
705 | |
706 | return 0; | |
707 | ||
708 | err_algs: | |
709 | dev_err(dev, "can't register '%s': %d\n", algs[i].cra_name, err); | |
710 | ||
711 | for (j = 0; j < i; j++) | |
712 | crypto_unregister_alg(&algs[j]); | |
713 | ||
714 | tasklet_kill(&pdata->tasklet); | |
715 | ||
716 | err_irq: | |
c1eb7ef2 | 717 | clk_disable_unprepare(pdata->clk); |
a49e490c VZ |
718 | |
719 | s5p_dev = NULL; | |
a49e490c VZ |
720 | |
721 | return err; | |
722 | } | |
723 | ||
724 | static int s5p_aes_remove(struct platform_device *pdev) | |
725 | { | |
726 | struct s5p_aes_dev *pdata = platform_get_drvdata(pdev); | |
727 | int i; | |
728 | ||
729 | if (!pdata) | |
730 | return -ENODEV; | |
731 | ||
732 | for (i = 0; i < ARRAY_SIZE(algs); i++) | |
733 | crypto_unregister_alg(&algs[i]); | |
734 | ||
735 | tasklet_kill(&pdata->tasklet); | |
736 | ||
c1eb7ef2 | 737 | clk_disable_unprepare(pdata->clk); |
a49e490c VZ |
738 | |
739 | s5p_dev = NULL; | |
a49e490c VZ |
740 | |
741 | return 0; | |
742 | } | |
743 | ||
744 | static struct platform_driver s5p_aes_crypto = { | |
745 | .probe = s5p_aes_probe, | |
746 | .remove = s5p_aes_remove, | |
747 | .driver = { | |
a49e490c | 748 | .name = "s5p-secss", |
6b9f16e6 | 749 | .of_match_table = s5p_sss_dt_match, |
a49e490c VZ |
750 | }, |
751 | }; | |
752 | ||
741e8c2d | 753 | module_platform_driver(s5p_aes_crypto); |
a49e490c VZ |
754 | |
755 | MODULE_DESCRIPTION("S5PV210 AES hw acceleration support."); | |
756 | MODULE_LICENSE("GPL v2"); | |
757 | MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>"); |