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a49e490c VZ |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for Samsung S5PV210 HW acceleration. | |
5 | * | |
6 | * Copyright (C) 2011 NetUP Inc. All rights reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as published | |
10 | * by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/delay.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/scatterlist.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/io.h> | |
6b9f16e6 | 25 | #include <linux/of.h> |
a49e490c VZ |
26 | #include <linux/crypto.h> |
27 | #include <linux/interrupt.h> | |
28 | ||
29 | #include <crypto/algapi.h> | |
30 | #include <crypto/aes.h> | |
31 | #include <crypto/ctr.h> | |
32 | ||
33 | #include <plat/cpu.h> | |
a465348f | 34 | #include <mach/dma.h> |
a49e490c VZ |
35 | |
36 | #define _SBF(s, v) ((v) << (s)) | |
37 | #define _BIT(b) _SBF(b, 1) | |
38 | ||
39 | /* Feed control registers */ | |
40 | #define SSS_REG_FCINTSTAT 0x0000 | |
41 | #define SSS_FCINTSTAT_BRDMAINT _BIT(3) | |
42 | #define SSS_FCINTSTAT_BTDMAINT _BIT(2) | |
43 | #define SSS_FCINTSTAT_HRDMAINT _BIT(1) | |
44 | #define SSS_FCINTSTAT_PKDMAINT _BIT(0) | |
45 | ||
46 | #define SSS_REG_FCINTENSET 0x0004 | |
47 | #define SSS_FCINTENSET_BRDMAINTENSET _BIT(3) | |
48 | #define SSS_FCINTENSET_BTDMAINTENSET _BIT(2) | |
49 | #define SSS_FCINTENSET_HRDMAINTENSET _BIT(1) | |
50 | #define SSS_FCINTENSET_PKDMAINTENSET _BIT(0) | |
51 | ||
52 | #define SSS_REG_FCINTENCLR 0x0008 | |
53 | #define SSS_FCINTENCLR_BRDMAINTENCLR _BIT(3) | |
54 | #define SSS_FCINTENCLR_BTDMAINTENCLR _BIT(2) | |
55 | #define SSS_FCINTENCLR_HRDMAINTENCLR _BIT(1) | |
56 | #define SSS_FCINTENCLR_PKDMAINTENCLR _BIT(0) | |
57 | ||
58 | #define SSS_REG_FCINTPEND 0x000C | |
59 | #define SSS_FCINTPEND_BRDMAINTP _BIT(3) | |
60 | #define SSS_FCINTPEND_BTDMAINTP _BIT(2) | |
61 | #define SSS_FCINTPEND_HRDMAINTP _BIT(1) | |
62 | #define SSS_FCINTPEND_PKDMAINTP _BIT(0) | |
63 | ||
64 | #define SSS_REG_FCFIFOSTAT 0x0010 | |
65 | #define SSS_FCFIFOSTAT_BRFIFOFUL _BIT(7) | |
66 | #define SSS_FCFIFOSTAT_BRFIFOEMP _BIT(6) | |
67 | #define SSS_FCFIFOSTAT_BTFIFOFUL _BIT(5) | |
68 | #define SSS_FCFIFOSTAT_BTFIFOEMP _BIT(4) | |
69 | #define SSS_FCFIFOSTAT_HRFIFOFUL _BIT(3) | |
70 | #define SSS_FCFIFOSTAT_HRFIFOEMP _BIT(2) | |
71 | #define SSS_FCFIFOSTAT_PKFIFOFUL _BIT(1) | |
72 | #define SSS_FCFIFOSTAT_PKFIFOEMP _BIT(0) | |
73 | ||
74 | #define SSS_REG_FCFIFOCTRL 0x0014 | |
75 | #define SSS_FCFIFOCTRL_DESSEL _BIT(2) | |
76 | #define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00) | |
77 | #define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01) | |
78 | #define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02) | |
79 | ||
80 | #define SSS_REG_FCBRDMAS 0x0020 | |
81 | #define SSS_REG_FCBRDMAL 0x0024 | |
82 | #define SSS_REG_FCBRDMAC 0x0028 | |
83 | #define SSS_FCBRDMAC_BYTESWAP _BIT(1) | |
84 | #define SSS_FCBRDMAC_FLUSH _BIT(0) | |
85 | ||
86 | #define SSS_REG_FCBTDMAS 0x0030 | |
87 | #define SSS_REG_FCBTDMAL 0x0034 | |
88 | #define SSS_REG_FCBTDMAC 0x0038 | |
89 | #define SSS_FCBTDMAC_BYTESWAP _BIT(1) | |
90 | #define SSS_FCBTDMAC_FLUSH _BIT(0) | |
91 | ||
92 | #define SSS_REG_FCHRDMAS 0x0040 | |
93 | #define SSS_REG_FCHRDMAL 0x0044 | |
94 | #define SSS_REG_FCHRDMAC 0x0048 | |
95 | #define SSS_FCHRDMAC_BYTESWAP _BIT(1) | |
96 | #define SSS_FCHRDMAC_FLUSH _BIT(0) | |
97 | ||
98 | #define SSS_REG_FCPKDMAS 0x0050 | |
99 | #define SSS_REG_FCPKDMAL 0x0054 | |
100 | #define SSS_REG_FCPKDMAC 0x0058 | |
101 | #define SSS_FCPKDMAC_BYTESWAP _BIT(3) | |
102 | #define SSS_FCPKDMAC_DESCEND _BIT(2) | |
103 | #define SSS_FCPKDMAC_TRANSMIT _BIT(1) | |
104 | #define SSS_FCPKDMAC_FLUSH _BIT(0) | |
105 | ||
106 | #define SSS_REG_FCPKDMAO 0x005C | |
107 | ||
108 | /* AES registers */ | |
109 | #define SSS_REG_AES_CONTROL 0x4000 | |
110 | #define SSS_AES_BYTESWAP_DI _BIT(11) | |
111 | #define SSS_AES_BYTESWAP_DO _BIT(10) | |
112 | #define SSS_AES_BYTESWAP_IV _BIT(9) | |
113 | #define SSS_AES_BYTESWAP_CNT _BIT(8) | |
114 | #define SSS_AES_BYTESWAP_KEY _BIT(7) | |
115 | #define SSS_AES_KEY_CHANGE_MODE _BIT(6) | |
116 | #define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00) | |
117 | #define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01) | |
118 | #define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02) | |
119 | #define SSS_AES_FIFO_MODE _BIT(3) | |
120 | #define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00) | |
121 | #define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01) | |
122 | #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02) | |
123 | #define SSS_AES_MODE_DECRYPT _BIT(0) | |
124 | ||
125 | #define SSS_REG_AES_STATUS 0x4004 | |
126 | #define SSS_AES_BUSY _BIT(2) | |
127 | #define SSS_AES_INPUT_READY _BIT(1) | |
128 | #define SSS_AES_OUTPUT_READY _BIT(0) | |
129 | ||
130 | #define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2)) | |
131 | #define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2)) | |
132 | #define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2)) | |
133 | #define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2)) | |
134 | #define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2)) | |
135 | ||
136 | #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg)) | |
137 | #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) | |
138 | #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) | |
139 | ||
140 | /* HW engine modes */ | |
141 | #define FLAGS_AES_DECRYPT _BIT(0) | |
142 | #define FLAGS_AES_MODE_MASK _SBF(1, 0x03) | |
143 | #define FLAGS_AES_CBC _SBF(1, 0x01) | |
144 | #define FLAGS_AES_CTR _SBF(1, 0x02) | |
145 | ||
146 | #define AES_KEY_LEN 16 | |
147 | #define CRYPTO_QUEUE_LEN 1 | |
148 | ||
149 | struct s5p_aes_reqctx { | |
150 | unsigned long mode; | |
151 | }; | |
152 | ||
153 | struct s5p_aes_ctx { | |
154 | struct s5p_aes_dev *dev; | |
155 | ||
156 | uint8_t aes_key[AES_MAX_KEY_SIZE]; | |
157 | uint8_t nonce[CTR_RFC3686_NONCE_SIZE]; | |
158 | int keylen; | |
159 | }; | |
160 | ||
161 | struct s5p_aes_dev { | |
162 | struct device *dev; | |
163 | struct clk *clk; | |
164 | void __iomem *ioaddr; | |
165 | int irq_hash; | |
166 | int irq_fc; | |
167 | ||
168 | struct ablkcipher_request *req; | |
169 | struct s5p_aes_ctx *ctx; | |
170 | struct scatterlist *sg_src; | |
171 | struct scatterlist *sg_dst; | |
172 | ||
173 | struct tasklet_struct tasklet; | |
174 | struct crypto_queue queue; | |
175 | bool busy; | |
176 | spinlock_t lock; | |
177 | }; | |
178 | ||
179 | static struct s5p_aes_dev *s5p_dev; | |
180 | ||
6b9f16e6 NKC |
181 | static const struct of_device_id s5p_sss_dt_match[] = { |
182 | { .compatible = "samsung,s5pv210-secss" }, | |
183 | { }, | |
184 | }; | |
185 | MODULE_DEVICE_TABLE(of, s5p_sss_dt_match); | |
186 | ||
a49e490c VZ |
187 | static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg) |
188 | { | |
189 | SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg)); | |
190 | SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg)); | |
191 | } | |
192 | ||
193 | static void s5p_set_dma_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg) | |
194 | { | |
195 | SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg)); | |
196 | SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg)); | |
197 | } | |
198 | ||
199 | static void s5p_aes_complete(struct s5p_aes_dev *dev, int err) | |
200 | { | |
201 | /* holding a lock outside */ | |
202 | dev->req->base.complete(&dev->req->base, err); | |
203 | dev->busy = false; | |
204 | } | |
205 | ||
206 | static void s5p_unset_outdata(struct s5p_aes_dev *dev) | |
207 | { | |
208 | dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE); | |
209 | } | |
210 | ||
211 | static void s5p_unset_indata(struct s5p_aes_dev *dev) | |
212 | { | |
213 | dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE); | |
214 | } | |
215 | ||
216 | static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg) | |
217 | { | |
218 | int err; | |
219 | ||
220 | if (!IS_ALIGNED(sg_dma_len(sg), AES_BLOCK_SIZE)) { | |
221 | err = -EINVAL; | |
222 | goto exit; | |
223 | } | |
224 | if (!sg_dma_len(sg)) { | |
225 | err = -EINVAL; | |
226 | goto exit; | |
227 | } | |
228 | ||
229 | err = dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE); | |
230 | if (!err) { | |
231 | err = -ENOMEM; | |
232 | goto exit; | |
233 | } | |
234 | ||
235 | dev->sg_dst = sg; | |
236 | err = 0; | |
237 | ||
238 | exit: | |
239 | return err; | |
240 | } | |
241 | ||
242 | static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg) | |
243 | { | |
244 | int err; | |
245 | ||
246 | if (!IS_ALIGNED(sg_dma_len(sg), AES_BLOCK_SIZE)) { | |
247 | err = -EINVAL; | |
248 | goto exit; | |
249 | } | |
250 | if (!sg_dma_len(sg)) { | |
251 | err = -EINVAL; | |
252 | goto exit; | |
253 | } | |
254 | ||
255 | err = dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE); | |
256 | if (!err) { | |
257 | err = -ENOMEM; | |
258 | goto exit; | |
259 | } | |
260 | ||
261 | dev->sg_src = sg; | |
262 | err = 0; | |
263 | ||
264 | exit: | |
265 | return err; | |
266 | } | |
267 | ||
268 | static void s5p_aes_tx(struct s5p_aes_dev *dev) | |
269 | { | |
270 | int err = 0; | |
271 | ||
272 | s5p_unset_outdata(dev); | |
273 | ||
274 | if (!sg_is_last(dev->sg_dst)) { | |
275 | err = s5p_set_outdata(dev, sg_next(dev->sg_dst)); | |
276 | if (err) { | |
277 | s5p_aes_complete(dev, err); | |
278 | return; | |
279 | } | |
280 | ||
281 | s5p_set_dma_outdata(dev, dev->sg_dst); | |
282 | } else | |
283 | s5p_aes_complete(dev, err); | |
284 | } | |
285 | ||
286 | static void s5p_aes_rx(struct s5p_aes_dev *dev) | |
287 | { | |
288 | int err; | |
289 | ||
290 | s5p_unset_indata(dev); | |
291 | ||
292 | if (!sg_is_last(dev->sg_src)) { | |
293 | err = s5p_set_indata(dev, sg_next(dev->sg_src)); | |
294 | if (err) { | |
295 | s5p_aes_complete(dev, err); | |
296 | return; | |
297 | } | |
298 | ||
299 | s5p_set_dma_indata(dev, dev->sg_src); | |
300 | } | |
301 | } | |
302 | ||
303 | static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id) | |
304 | { | |
305 | struct platform_device *pdev = dev_id; | |
306 | struct s5p_aes_dev *dev = platform_get_drvdata(pdev); | |
307 | uint32_t status; | |
308 | unsigned long flags; | |
309 | ||
310 | spin_lock_irqsave(&dev->lock, flags); | |
311 | ||
312 | if (irq == dev->irq_fc) { | |
313 | status = SSS_READ(dev, FCINTSTAT); | |
314 | if (status & SSS_FCINTSTAT_BRDMAINT) | |
315 | s5p_aes_rx(dev); | |
316 | if (status & SSS_FCINTSTAT_BTDMAINT) | |
317 | s5p_aes_tx(dev); | |
318 | ||
319 | SSS_WRITE(dev, FCINTPEND, status); | |
320 | } | |
321 | ||
322 | spin_unlock_irqrestore(&dev->lock, flags); | |
323 | ||
324 | return IRQ_HANDLED; | |
325 | } | |
326 | ||
327 | static void s5p_set_aes(struct s5p_aes_dev *dev, | |
328 | uint8_t *key, uint8_t *iv, unsigned int keylen) | |
329 | { | |
330 | void __iomem *keystart; | |
331 | ||
332 | memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10); | |
333 | ||
334 | if (keylen == AES_KEYSIZE_256) | |
335 | keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0); | |
336 | else if (keylen == AES_KEYSIZE_192) | |
337 | keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2); | |
338 | else | |
339 | keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4); | |
340 | ||
341 | memcpy(keystart, key, keylen); | |
342 | } | |
343 | ||
344 | static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode) | |
345 | { | |
346 | struct ablkcipher_request *req = dev->req; | |
347 | ||
348 | uint32_t aes_control; | |
349 | int err; | |
350 | unsigned long flags; | |
351 | ||
352 | aes_control = SSS_AES_KEY_CHANGE_MODE; | |
353 | if (mode & FLAGS_AES_DECRYPT) | |
354 | aes_control |= SSS_AES_MODE_DECRYPT; | |
355 | ||
356 | if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC) | |
357 | aes_control |= SSS_AES_CHAIN_MODE_CBC; | |
358 | else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR) | |
359 | aes_control |= SSS_AES_CHAIN_MODE_CTR; | |
360 | ||
361 | if (dev->ctx->keylen == AES_KEYSIZE_192) | |
362 | aes_control |= SSS_AES_KEY_SIZE_192; | |
363 | else if (dev->ctx->keylen == AES_KEYSIZE_256) | |
364 | aes_control |= SSS_AES_KEY_SIZE_256; | |
365 | ||
366 | aes_control |= SSS_AES_FIFO_MODE; | |
367 | ||
368 | /* as a variant it is possible to use byte swapping on DMA side */ | |
369 | aes_control |= SSS_AES_BYTESWAP_DI | |
370 | | SSS_AES_BYTESWAP_DO | |
371 | | SSS_AES_BYTESWAP_IV | |
372 | | SSS_AES_BYTESWAP_KEY | |
373 | | SSS_AES_BYTESWAP_CNT; | |
374 | ||
375 | spin_lock_irqsave(&dev->lock, flags); | |
376 | ||
377 | SSS_WRITE(dev, FCINTENCLR, | |
378 | SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR); | |
379 | SSS_WRITE(dev, FCFIFOCTRL, 0x00); | |
380 | ||
381 | err = s5p_set_indata(dev, req->src); | |
382 | if (err) | |
383 | goto indata_error; | |
384 | ||
385 | err = s5p_set_outdata(dev, req->dst); | |
386 | if (err) | |
387 | goto outdata_error; | |
388 | ||
389 | SSS_WRITE(dev, AES_CONTROL, aes_control); | |
390 | s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen); | |
391 | ||
392 | s5p_set_dma_indata(dev, req->src); | |
393 | s5p_set_dma_outdata(dev, req->dst); | |
394 | ||
395 | SSS_WRITE(dev, FCINTENSET, | |
396 | SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET); | |
397 | ||
398 | spin_unlock_irqrestore(&dev->lock, flags); | |
399 | ||
400 | return; | |
401 | ||
402 | outdata_error: | |
403 | s5p_unset_indata(dev); | |
404 | ||
405 | indata_error: | |
406 | s5p_aes_complete(dev, err); | |
407 | spin_unlock_irqrestore(&dev->lock, flags); | |
408 | } | |
409 | ||
410 | static void s5p_tasklet_cb(unsigned long data) | |
411 | { | |
412 | struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data; | |
413 | struct crypto_async_request *async_req, *backlog; | |
414 | struct s5p_aes_reqctx *reqctx; | |
415 | unsigned long flags; | |
416 | ||
417 | spin_lock_irqsave(&dev->lock, flags); | |
418 | backlog = crypto_get_backlog(&dev->queue); | |
419 | async_req = crypto_dequeue_request(&dev->queue); | |
420 | spin_unlock_irqrestore(&dev->lock, flags); | |
421 | ||
422 | if (!async_req) | |
423 | return; | |
424 | ||
425 | if (backlog) | |
426 | backlog->complete(backlog, -EINPROGRESS); | |
427 | ||
428 | dev->req = ablkcipher_request_cast(async_req); | |
429 | dev->ctx = crypto_tfm_ctx(dev->req->base.tfm); | |
430 | reqctx = ablkcipher_request_ctx(dev->req); | |
431 | ||
432 | s5p_aes_crypt_start(dev, reqctx->mode); | |
433 | } | |
434 | ||
435 | static int s5p_aes_handle_req(struct s5p_aes_dev *dev, | |
436 | struct ablkcipher_request *req) | |
437 | { | |
438 | unsigned long flags; | |
439 | int err; | |
440 | ||
441 | spin_lock_irqsave(&dev->lock, flags); | |
442 | if (dev->busy) { | |
443 | err = -EAGAIN; | |
444 | spin_unlock_irqrestore(&dev->lock, flags); | |
445 | goto exit; | |
446 | } | |
447 | dev->busy = true; | |
448 | ||
449 | err = ablkcipher_enqueue_request(&dev->queue, req); | |
450 | spin_unlock_irqrestore(&dev->lock, flags); | |
451 | ||
452 | tasklet_schedule(&dev->tasklet); | |
453 | ||
454 | exit: | |
455 | return err; | |
456 | } | |
457 | ||
458 | static int s5p_aes_crypt(struct ablkcipher_request *req, unsigned long mode) | |
459 | { | |
460 | struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); | |
461 | struct s5p_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); | |
462 | struct s5p_aes_reqctx *reqctx = ablkcipher_request_ctx(req); | |
463 | struct s5p_aes_dev *dev = ctx->dev; | |
464 | ||
465 | if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) { | |
466 | pr_err("request size is not exact amount of AES blocks\n"); | |
467 | return -EINVAL; | |
468 | } | |
469 | ||
470 | reqctx->mode = mode; | |
471 | ||
472 | return s5p_aes_handle_req(dev, req); | |
473 | } | |
474 | ||
475 | static int s5p_aes_setkey(struct crypto_ablkcipher *cipher, | |
476 | const uint8_t *key, unsigned int keylen) | |
477 | { | |
478 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
479 | struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm); | |
480 | ||
481 | if (keylen != AES_KEYSIZE_128 && | |
482 | keylen != AES_KEYSIZE_192 && | |
483 | keylen != AES_KEYSIZE_256) | |
484 | return -EINVAL; | |
485 | ||
486 | memcpy(ctx->aes_key, key, keylen); | |
487 | ctx->keylen = keylen; | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
492 | static int s5p_aes_ecb_encrypt(struct ablkcipher_request *req) | |
493 | { | |
494 | return s5p_aes_crypt(req, 0); | |
495 | } | |
496 | ||
497 | static int s5p_aes_ecb_decrypt(struct ablkcipher_request *req) | |
498 | { | |
499 | return s5p_aes_crypt(req, FLAGS_AES_DECRYPT); | |
500 | } | |
501 | ||
502 | static int s5p_aes_cbc_encrypt(struct ablkcipher_request *req) | |
503 | { | |
504 | return s5p_aes_crypt(req, FLAGS_AES_CBC); | |
505 | } | |
506 | ||
507 | static int s5p_aes_cbc_decrypt(struct ablkcipher_request *req) | |
508 | { | |
509 | return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC); | |
510 | } | |
511 | ||
512 | static int s5p_aes_cra_init(struct crypto_tfm *tfm) | |
513 | { | |
514 | struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm); | |
515 | ||
516 | ctx->dev = s5p_dev; | |
517 | tfm->crt_ablkcipher.reqsize = sizeof(struct s5p_aes_reqctx); | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
522 | static struct crypto_alg algs[] = { | |
523 | { | |
524 | .cra_name = "ecb(aes)", | |
525 | .cra_driver_name = "ecb-aes-s5p", | |
526 | .cra_priority = 100, | |
527 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
d912bb76 NM |
528 | CRYPTO_ALG_ASYNC | |
529 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
a49e490c VZ |
530 | .cra_blocksize = AES_BLOCK_SIZE, |
531 | .cra_ctxsize = sizeof(struct s5p_aes_ctx), | |
532 | .cra_alignmask = 0x0f, | |
533 | .cra_type = &crypto_ablkcipher_type, | |
534 | .cra_module = THIS_MODULE, | |
535 | .cra_init = s5p_aes_cra_init, | |
536 | .cra_u.ablkcipher = { | |
537 | .min_keysize = AES_MIN_KEY_SIZE, | |
538 | .max_keysize = AES_MAX_KEY_SIZE, | |
539 | .setkey = s5p_aes_setkey, | |
540 | .encrypt = s5p_aes_ecb_encrypt, | |
541 | .decrypt = s5p_aes_ecb_decrypt, | |
542 | } | |
543 | }, | |
544 | { | |
545 | .cra_name = "cbc(aes)", | |
546 | .cra_driver_name = "cbc-aes-s5p", | |
547 | .cra_priority = 100, | |
548 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
d912bb76 NM |
549 | CRYPTO_ALG_ASYNC | |
550 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
a49e490c VZ |
551 | .cra_blocksize = AES_BLOCK_SIZE, |
552 | .cra_ctxsize = sizeof(struct s5p_aes_ctx), | |
553 | .cra_alignmask = 0x0f, | |
554 | .cra_type = &crypto_ablkcipher_type, | |
555 | .cra_module = THIS_MODULE, | |
556 | .cra_init = s5p_aes_cra_init, | |
557 | .cra_u.ablkcipher = { | |
558 | .min_keysize = AES_MIN_KEY_SIZE, | |
559 | .max_keysize = AES_MAX_KEY_SIZE, | |
560 | .ivsize = AES_BLOCK_SIZE, | |
561 | .setkey = s5p_aes_setkey, | |
562 | .encrypt = s5p_aes_cbc_encrypt, | |
563 | .decrypt = s5p_aes_cbc_decrypt, | |
564 | } | |
565 | }, | |
566 | }; | |
567 | ||
568 | static int s5p_aes_probe(struct platform_device *pdev) | |
569 | { | |
570 | int i, j, err = -ENODEV; | |
571 | struct s5p_aes_dev *pdata; | |
572 | struct device *dev = &pdev->dev; | |
573 | struct resource *res; | |
574 | ||
575 | if (s5p_dev) | |
576 | return -EEXIST; | |
577 | ||
a49e490c VZ |
578 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
579 | if (!pdata) | |
580 | return -ENOMEM; | |
581 | ||
0fdefe2c JH |
582 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
583 | pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res); | |
584 | if (IS_ERR(pdata->ioaddr)) | |
585 | return PTR_ERR(pdata->ioaddr); | |
a49e490c | 586 | |
5c22ba66 | 587 | pdata->clk = devm_clk_get(dev, "secss"); |
a49e490c VZ |
588 | if (IS_ERR(pdata->clk)) { |
589 | dev_err(dev, "failed to find secss clock source\n"); | |
590 | return -ENOENT; | |
591 | } | |
592 | ||
593 | clk_enable(pdata->clk); | |
594 | ||
595 | spin_lock_init(&pdata->lock); | |
a49e490c | 596 | |
96fc70b6 NKC |
597 | pdata->irq_fc = platform_get_irq(pdev, 0); |
598 | if (pdata->irq_fc < 0) { | |
599 | err = pdata->irq_fc; | |
600 | dev_warn(dev, "feed control interrupt is not available.\n"); | |
a49e490c VZ |
601 | goto err_irq; |
602 | } | |
96fc70b6 | 603 | err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt, |
a49e490c VZ |
604 | IRQF_SHARED, pdev->name, pdev); |
605 | if (err < 0) { | |
96fc70b6 | 606 | dev_warn(dev, "feed control interrupt is not available.\n"); |
a49e490c VZ |
607 | goto err_irq; |
608 | } | |
609 | ||
96fc70b6 NKC |
610 | pdata->irq_hash = platform_get_irq(pdev, 1); |
611 | if (pdata->irq_hash < 0) { | |
612 | err = pdata->irq_hash; | |
613 | dev_warn(dev, "hash interrupt is not available.\n"); | |
a49e490c VZ |
614 | goto err_irq; |
615 | } | |
96fc70b6 | 616 | err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt, |
a49e490c VZ |
617 | IRQF_SHARED, pdev->name, pdev); |
618 | if (err < 0) { | |
96fc70b6 | 619 | dev_warn(dev, "hash interrupt is not available.\n"); |
a49e490c VZ |
620 | goto err_irq; |
621 | } | |
622 | ||
623 | pdata->dev = dev; | |
624 | platform_set_drvdata(pdev, pdata); | |
625 | s5p_dev = pdata; | |
626 | ||
627 | tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata); | |
628 | crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN); | |
629 | ||
630 | for (i = 0; i < ARRAY_SIZE(algs); i++) { | |
a49e490c VZ |
631 | err = crypto_register_alg(&algs[i]); |
632 | if (err) | |
633 | goto err_algs; | |
634 | } | |
635 | ||
636 | pr_info("s5p-sss driver registered\n"); | |
637 | ||
638 | return 0; | |
639 | ||
640 | err_algs: | |
641 | dev_err(dev, "can't register '%s': %d\n", algs[i].cra_name, err); | |
642 | ||
643 | for (j = 0; j < i; j++) | |
644 | crypto_unregister_alg(&algs[j]); | |
645 | ||
646 | tasklet_kill(&pdata->tasklet); | |
647 | ||
648 | err_irq: | |
649 | clk_disable(pdata->clk); | |
a49e490c VZ |
650 | |
651 | s5p_dev = NULL; | |
a49e490c VZ |
652 | |
653 | return err; | |
654 | } | |
655 | ||
656 | static int s5p_aes_remove(struct platform_device *pdev) | |
657 | { | |
658 | struct s5p_aes_dev *pdata = platform_get_drvdata(pdev); | |
659 | int i; | |
660 | ||
661 | if (!pdata) | |
662 | return -ENODEV; | |
663 | ||
664 | for (i = 0; i < ARRAY_SIZE(algs); i++) | |
665 | crypto_unregister_alg(&algs[i]); | |
666 | ||
667 | tasklet_kill(&pdata->tasklet); | |
668 | ||
669 | clk_disable(pdata->clk); | |
a49e490c VZ |
670 | |
671 | s5p_dev = NULL; | |
a49e490c VZ |
672 | |
673 | return 0; | |
674 | } | |
675 | ||
676 | static struct platform_driver s5p_aes_crypto = { | |
677 | .probe = s5p_aes_probe, | |
678 | .remove = s5p_aes_remove, | |
679 | .driver = { | |
680 | .owner = THIS_MODULE, | |
681 | .name = "s5p-secss", | |
6b9f16e6 | 682 | .of_match_table = s5p_sss_dt_match, |
a49e490c VZ |
683 | }, |
684 | }; | |
685 | ||
741e8c2d | 686 | module_platform_driver(s5p_aes_crypto); |
a49e490c VZ |
687 | |
688 | MODULE_DESCRIPTION("S5PV210 AES hw acceleration support."); | |
689 | MODULE_LICENSE("GPL v2"); | |
690 | MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>"); |