[mirror_ubuntu-hirsute-kernel.git] / drivers / crypto / sunxi-ss / sun4i-ss-core.c

/*
 * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
 *
 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
 *
 * Core file which registers crypto algorithms supported by the SS.
 *
 * You could find a link for the datasheet in Documentation/arm/sunxi/README
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */
#include <linux/clk.h>
#include <linux/crypto.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <crypto/scatterwalk.h>
#include <linux/scatterlist.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/reset.h>

#include "sun4i-ss.h"

static struct sun4i_ss_alg_template ss_algs[] = {
{       .type = CRYPTO_ALG_TYPE_AHASH,
	.mode = SS_OP_MD5,
	.alg.hash = {
		.init = sun4i_hash_init,
		.update = sun4i_hash_update,
		.final = sun4i_hash_final,
		.finup = sun4i_hash_finup,
		.digest = sun4i_hash_digest,
		.export = sun4i_hash_export_md5,
		.import = sun4i_hash_import_md5,
		.halg = {
			.digestsize = MD5_DIGEST_SIZE,
			.statesize = sizeof(struct md5_state),
			.base = {
				.cra_name = "md5",
				.cra_driver_name = "md5-sun4i-ss",
				.cra_priority = 300,
				.cra_alignmask = 3,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH,
				.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
				.cra_ctxsize = sizeof(struct sun4i_req_ctx),
				.cra_module = THIS_MODULE,
				.cra_type = &crypto_ahash_type,
				.cra_init = sun4i_hash_crainit
			}
		}
	}
},
{       .type = CRYPTO_ALG_TYPE_AHASH,
	.mode = SS_OP_SHA1,
	.alg.hash = {
		.init = sun4i_hash_init,
		.update = sun4i_hash_update,
		.final = sun4i_hash_final,
		.finup = sun4i_hash_finup,
		.digest = sun4i_hash_digest,
		.export = sun4i_hash_export_sha1,
		.import = sun4i_hash_import_sha1,
		.halg = {
			.digestsize = SHA1_DIGEST_SIZE,
			.statesize = sizeof(struct sha1_state),
			.base = {
				.cra_name = "sha1",
				.cra_driver_name = "sha1-sun4i-ss",
				.cra_priority = 300,
				.cra_alignmask = 3,
				.cra_flags = CRYPTO_ALG_TYPE_AHASH,
				.cra_blocksize = SHA1_BLOCK_SIZE,
				.cra_ctxsize = sizeof(struct sun4i_req_ctx),
				.cra_module = THIS_MODULE,
				.cra_type = &crypto_ahash_type,
				.cra_init = sun4i_hash_crainit
			}
		}
	}
},
{       .type = CRYPTO_ALG_TYPE_SKCIPHER,
	.alg.crypto = {
		.setkey         = sun4i_ss_aes_setkey,
		.encrypt        = sun4i_ss_cbc_aes_encrypt,
		.decrypt        = sun4i_ss_cbc_aes_decrypt,
		.min_keysize	= AES_MIN_KEY_SIZE,
		.max_keysize	= AES_MAX_KEY_SIZE,
		.ivsize		= AES_BLOCK_SIZE,
		.base = {
			.cra_name = "cbc(aes)",
			.cra_driver_name = "cbc-aes-sun4i-ss",
			.cra_priority = 300,
			.cra_blocksize = AES_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
				     CRYPTO_ALG_KERN_DRIVER_ONLY,
			.cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
			.cra_module = THIS_MODULE,
			.cra_alignmask = 3,
			.cra_init = sun4i_ss_cipher_init,
		}
	}
},
{       .type = CRYPTO_ALG_TYPE_SKCIPHER,
	.alg.crypto = {
		.setkey         = sun4i_ss_aes_setkey,
		.encrypt        = sun4i_ss_ecb_aes_encrypt,
		.decrypt        = sun4i_ss_ecb_aes_decrypt,
		.min_keysize	= AES_MIN_KEY_SIZE,
		.max_keysize	= AES_MAX_KEY_SIZE,
		.ivsize		= AES_BLOCK_SIZE,
		.base = {
			.cra_name = "ecb(aes)",
			.cra_driver_name = "ecb-aes-sun4i-ss",
			.cra_priority = 300,
			.cra_blocksize = AES_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
				     CRYPTO_ALG_KERN_DRIVER_ONLY,
			.cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
			.cra_module = THIS_MODULE,
			.cra_alignmask = 3,
			.cra_init = sun4i_ss_cipher_init,
		}
	}
},
{       .type = CRYPTO_ALG_TYPE_SKCIPHER,
	.alg.crypto = {
		.setkey         = sun4i_ss_des_setkey,
		.encrypt        = sun4i_ss_cbc_des_encrypt,
		.decrypt        = sun4i_ss_cbc_des_decrypt,
		.min_keysize    = DES_KEY_SIZE,
		.max_keysize    = DES_KEY_SIZE,
		.ivsize         = DES_BLOCK_SIZE,
		.base = {
			.cra_name = "cbc(des)",
			.cra_driver_name = "cbc-des-sun4i-ss",
			.cra_priority = 300,
			.cra_blocksize = DES_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
				     CRYPTO_ALG_KERN_DRIVER_ONLY,
			.cra_ctxsize = sizeof(struct sun4i_req_ctx),
			.cra_module = THIS_MODULE,
			.cra_alignmask = 3,
			.cra_init = sun4i_ss_cipher_init,
		}
	}
},
{       .type = CRYPTO_ALG_TYPE_SKCIPHER,
	.alg.crypto = {
		.setkey         = sun4i_ss_des_setkey,
		.encrypt        = sun4i_ss_ecb_des_encrypt,
		.decrypt        = sun4i_ss_ecb_des_decrypt,
		.min_keysize    = DES_KEY_SIZE,
		.max_keysize    = DES_KEY_SIZE,
		.base = {
			.cra_name = "ecb(des)",
			.cra_driver_name = "ecb-des-sun4i-ss",
			.cra_priority = 300,
			.cra_blocksize = DES_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
				     CRYPTO_ALG_KERN_DRIVER_ONLY,
			.cra_ctxsize = sizeof(struct sun4i_req_ctx),
			.cra_module = THIS_MODULE,
			.cra_alignmask = 3,
			.cra_init = sun4i_ss_cipher_init,
		}
	}
},
{       .type = CRYPTO_ALG_TYPE_SKCIPHER,
	.alg.crypto = {
		.setkey         = sun4i_ss_des3_setkey,
		.encrypt        = sun4i_ss_cbc_des3_encrypt,
		.decrypt        = sun4i_ss_cbc_des3_decrypt,
		.min_keysize    = DES3_EDE_KEY_SIZE,
		.max_keysize    = DES3_EDE_KEY_SIZE,
		.ivsize         = DES3_EDE_BLOCK_SIZE,
		.base = {
			.cra_name = "cbc(des3_ede)",
			.cra_driver_name = "cbc-des3-sun4i-ss",
			.cra_priority = 300,
			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
				     CRYPTO_ALG_KERN_DRIVER_ONLY,
			.cra_ctxsize = sizeof(struct sun4i_req_ctx),
			.cra_module = THIS_MODULE,
			.cra_alignmask = 3,
			.cra_init = sun4i_ss_cipher_init,
		}
	}
},
{       .type = CRYPTO_ALG_TYPE_SKCIPHER,
	.alg.crypto = {
		.setkey         = sun4i_ss_des3_setkey,
		.encrypt        = sun4i_ss_ecb_des3_encrypt,
		.decrypt        = sun4i_ss_ecb_des3_decrypt,
		.min_keysize    = DES3_EDE_KEY_SIZE,
		.max_keysize    = DES3_EDE_KEY_SIZE,
		.ivsize         = DES3_EDE_BLOCK_SIZE,
		.base = {
			.cra_name = "ecb(des3_ede)",
			.cra_driver_name = "ecb-des3-sun4i-ss",
			.cra_priority = 300,
			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
			.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER,
			.cra_ctxsize = sizeof(struct sun4i_req_ctx),
			.cra_module = THIS_MODULE,
			.cra_alignmask = 3,
			.cra_init = sun4i_ss_cipher_init,
		}
	}
},
#ifdef CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG
{
	.type = CRYPTO_ALG_TYPE_RNG,
	.alg.rng = {
		.base = {
			.cra_name		= "stdrng",
			.cra_driver_name	= "sun4i_ss_rng",
			.cra_priority		= 300,
			.cra_ctxsize		= 0,
			.cra_module		= THIS_MODULE,
		},
		.generate               = sun4i_ss_prng_generate,
		.seed                   = sun4i_ss_prng_seed,
		.seedsize               = SS_SEED_LEN / BITS_PER_BYTE,
	}
},
#endif
};

static int sun4i_ss_probe(struct platform_device *pdev)
{
	struct resource *res;
	u32 v;
	int err, i;
	unsigned long cr;
	const unsigned long cr_ahb = 24 * 1000 * 1000;
	const unsigned long cr_mod = 150 * 1000 * 1000;
	struct sun4i_ss_ctx *ss;

	if (!pdev->dev.of_node)
		return -ENODEV;

	ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
	if (!ss)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ss->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ss->base)) {
		dev_err(&pdev->dev, "Cannot request MMIO\n");
		return PTR_ERR(ss->base);
	}

	ss->ssclk = devm_clk_get(&pdev->dev, "mod");
	if (IS_ERR(ss->ssclk)) {
		err = PTR_ERR(ss->ssclk);
		dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
		return err;
	}
	dev_dbg(&pdev->dev, "clock ss acquired\n");

	ss->busclk = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(ss->busclk)) {
		err = PTR_ERR(ss->busclk);
		dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
		return err;
	}
	dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");

	ss->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
	if (IS_ERR(ss->reset)) {
		if (PTR_ERR(ss->reset) == -EPROBE_DEFER)
			return PTR_ERR(ss->reset);
		dev_info(&pdev->dev, "no reset control found\n");
		ss->reset = NULL;
	}

	/* Enable both clocks */
	err = clk_prepare_enable(ss->busclk);
	if (err) {
		dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
		return err;
	}
	err = clk_prepare_enable(ss->ssclk);
	if (err) {
		dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
		goto error_ssclk;
	}

	/*
	 * Check that clock have the correct rates given in the datasheet
	 * Try to set the clock to the maximum allowed
	 */
	err = clk_set_rate(ss->ssclk, cr_mod);
	if (err) {
		dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
		goto error_clk;
	}

	/* Deassert reset if we have a reset control */
	if (ss->reset) {
		err = reset_control_deassert(ss->reset);
		if (err) {
			dev_err(&pdev->dev, "Cannot deassert reset control\n");
			goto error_clk;
		}
	}

	/*
	 * The only impact on clocks below requirement are bad performance,
	 * so do not print "errors"
	 * warn on Overclocked clocks
	 */
	cr = clk_get_rate(ss->busclk);
	if (cr >= cr_ahb)
		dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
			cr, cr / 1000000, cr_ahb);
	else
		dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
			 cr, cr / 1000000, cr_ahb);

	cr = clk_get_rate(ss->ssclk);
	if (cr <= cr_mod)
		if (cr < cr_mod)
			dev_warn(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
				 cr, cr / 1000000, cr_mod);
		else
			dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
				cr, cr / 1000000, cr_mod);
	else
		dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
			 cr, cr / 1000000, cr_mod);

	/*
	 * Datasheet named it "Die Bonding ID"
	 * I expect to be a sort of Security System Revision number.
	 * Since the A80 seems to have an other version of SS
	 * this info could be useful
	 */
	writel(SS_ENABLED, ss->base + SS_CTL);
	v = readl(ss->base + SS_CTL);
	v >>= 16;
	v &= 0x07;
	dev_info(&pdev->dev, "Die ID %d\n", v);
	writel(0, ss->base + SS_CTL);

	ss->dev = &pdev->dev;

	spin_lock_init(&ss->slock);

	for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
		ss_algs[i].ss = ss;
		switch (ss_algs[i].type) {
		case CRYPTO_ALG_TYPE_SKCIPHER:
			err = crypto_register_skcipher(&ss_algs[i].alg.crypto);
			if (err) {
				dev_err(ss->dev, "Fail to register %s\n",
					ss_algs[i].alg.crypto.base.cra_name);
				goto error_alg;
			}
			break;
		case CRYPTO_ALG_TYPE_AHASH:
			err = crypto_register_ahash(&ss_algs[i].alg.hash);
			if (err) {
				dev_err(ss->dev, "Fail to register %s\n",
					ss_algs[i].alg.hash.halg.base.cra_name);
				goto error_alg;
			}
			break;
		case CRYPTO_ALG_TYPE_RNG:
			err = crypto_register_rng(&ss_algs[i].alg.rng);
			if (err) {
				dev_err(ss->dev, "Fail to register %s\n",
					ss_algs[i].alg.rng.base.cra_name);
			}
			break;
		}
	}
	platform_set_drvdata(pdev, ss);
	return 0;
error_alg:
	i--;
	for (; i >= 0; i--) {
		switch (ss_algs[i].type) {
		case CRYPTO_ALG_TYPE_SKCIPHER:
			crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
			break;
		case CRYPTO_ALG_TYPE_AHASH:
			crypto_unregister_ahash(&ss_algs[i].alg.hash);
			break;
		case CRYPTO_ALG_TYPE_RNG:
			crypto_unregister_rng(&ss_algs[i].alg.rng);
			break;
		}
	}
	if (ss->reset)
		reset_control_assert(ss->reset);
error_clk:
	clk_disable_unprepare(ss->ssclk);
error_ssclk:
	clk_disable_unprepare(ss->busclk);
	return err;
}

static int sun4i_ss_remove(struct platform_device *pdev)
{
	int i;
	struct sun4i_ss_ctx *ss = platform_get_drvdata(pdev);

	for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
		switch (ss_algs[i].type) {
		case CRYPTO_ALG_TYPE_SKCIPHER:
			crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
			break;
		case CRYPTO_ALG_TYPE_AHASH:
			crypto_unregister_ahash(&ss_algs[i].alg.hash);
			break;
		case CRYPTO_ALG_TYPE_RNG:
			crypto_unregister_rng(&ss_algs[i].alg.rng);
			break;
		}
	}

	writel(0, ss->base + SS_CTL);
	if (ss->reset)
		reset_control_assert(ss->reset);
	clk_disable_unprepare(ss->busclk);
	clk_disable_unprepare(ss->ssclk);
	return 0;
}

static const struct of_device_id a20ss_crypto_of_match_table[] = {
	{ .compatible = "allwinner,sun4i-a10-crypto" },
	{}
};
MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);

static struct platform_driver sun4i_ss_driver = {
	.probe          = sun4i_ss_probe,
	.remove         = sun4i_ss_remove,
	.driver         = {
		.name           = "sun4i-ss",
		.of_match_table	= a20ss_crypto_of_match_table,
	},
};

module_platform_driver(sun4i_ss_driver);

MODULE_ALIAS("platform:sun4i-ss");
MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");
Commit	Line	Data
6298e948 LC	1	/*
	2	* sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
	3	*
	4	* Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
	5	*
	6	* Core file which registers crypto algorithms supported by the SS.
	7	*
	8	* You could find a link for the datasheet in Documentation/arm/sunxi/README
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*/
	15	#include <linux/clk.h>
	16	#include <linux/crypto.h>
	17	#include <linux/io.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/platform_device.h>
	21	#include <crypto/scatterwalk.h>
	22	#include <linux/scatterlist.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/delay.h>
7ab64628	25	#include <linux/reset.h>
6298e948 LC	26
	27	#include "sun4i-ss.h"
	28
	29	static struct sun4i_ss_alg_template ss_algs[] = {
	30	{ .type = CRYPTO_ALG_TYPE_AHASH,
	31	.mode = SS_OP_MD5,
	32	.alg.hash = {
	33	.init = sun4i_hash_init,
	34	.update = sun4i_hash_update,
	35	.final = sun4i_hash_final,
	36	.finup = sun4i_hash_finup,
	37	.digest = sun4i_hash_digest,
	38	.export = sun4i_hash_export_md5,
	39	.import = sun4i_hash_import_md5,
	40	.halg = {
	41	.digestsize = MD5_DIGEST_SIZE,
4f9ea866	42	.statesize = sizeof(struct md5_state),
6298e948 LC	43	.base = {
	44	.cra_name = "md5",
	45	.cra_driver_name = "md5-sun4i-ss",
	46	.cra_priority = 300,
	47	.cra_alignmask = 3,
	48	.cra_flags = CRYPTO_ALG_TYPE_AHASH,
	49	.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
	50	.cra_ctxsize = sizeof(struct sun4i_req_ctx),
	51	.cra_module = THIS_MODULE,
	52	.cra_type = &crypto_ahash_type,
	53	.cra_init = sun4i_hash_crainit
	54	}
	55	}
	56	}
	57	},
	58	{ .type = CRYPTO_ALG_TYPE_AHASH,
	59	.mode = SS_OP_SHA1,
	60	.alg.hash = {
	61	.init = sun4i_hash_init,
	62	.update = sun4i_hash_update,
	63	.final = sun4i_hash_final,
	64	.finup = sun4i_hash_finup,
	65	.digest = sun4i_hash_digest,
	66	.export = sun4i_hash_export_sha1,
	67	.import = sun4i_hash_import_sha1,
	68	.halg = {
	69	.digestsize = SHA1_DIGEST_SIZE,
4f9ea866	70	.statesize = sizeof(struct sha1_state),
6298e948 LC	71	.base = {
	72	.cra_name = "sha1",
	73	.cra_driver_name = "sha1-sun4i-ss",
	74	.cra_priority = 300,
	75	.cra_alignmask = 3,
	76	.cra_flags = CRYPTO_ALG_TYPE_AHASH,
	77	.cra_blocksize = SHA1_BLOCK_SIZE,
	78	.cra_ctxsize = sizeof(struct sun4i_req_ctx),
	79	.cra_module = THIS_MODULE,
	80	.cra_type = &crypto_ahash_type,
	81	.cra_init = sun4i_hash_crainit
	82	}
	83	}
	84	}
	85	},
317cbacf	86	{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
6298e948	87	.alg.crypto = {
317cbacf AT	88	.setkey = sun4i_ss_aes_setkey,
	89	.encrypt = sun4i_ss_cbc_aes_encrypt,
	90	.decrypt = sun4i_ss_cbc_aes_decrypt,
	91	.min_keysize = AES_MIN_KEY_SIZE,
	92	.max_keysize = AES_MAX_KEY_SIZE,
	93	.ivsize = AES_BLOCK_SIZE,
	94	.base = {
	95	.cra_name = "cbc(aes)",
	96	.cra_driver_name = "cbc-aes-sun4i-ss",
	97	.cra_priority = 300,
	98	.cra_blocksize = AES_BLOCK_SIZE,
0d9c68a9 AT	99	.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER \|
0d9c68a9 AT	100	CRYPTO_ALG_KERN_DRIVER_ONLY,
317cbacf AT	101	.cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
	102	.cra_module = THIS_MODULE,
	103	.cra_alignmask = 3,
	104	.cra_init = sun4i_ss_cipher_init,
6298e948 LC	105	}
	106	}
	107	},
317cbacf	108	{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
6298e948	109	.alg.crypto = {
317cbacf AT	110	.setkey = sun4i_ss_aes_setkey,
	111	.encrypt = sun4i_ss_ecb_aes_encrypt,
	112	.decrypt = sun4i_ss_ecb_aes_decrypt,
	113	.min_keysize = AES_MIN_KEY_SIZE,
	114	.max_keysize = AES_MAX_KEY_SIZE,
	115	.ivsize = AES_BLOCK_SIZE,
	116	.base = {
	117	.cra_name = "ecb(aes)",
	118	.cra_driver_name = "ecb-aes-sun4i-ss",
	119	.cra_priority = 300,
	120	.cra_blocksize = AES_BLOCK_SIZE,
0d9c68a9 AT	121	.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER \|
0d9c68a9 AT	122	CRYPTO_ALG_KERN_DRIVER_ONLY,
317cbacf AT	123	.cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
	124	.cra_module = THIS_MODULE,
	125	.cra_alignmask = 3,
	126	.cra_init = sun4i_ss_cipher_init,
6298e948 LC	127	}
	128	}
	129	},
317cbacf	130	{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
6298e948	131	.alg.crypto = {
317cbacf AT	132	.setkey = sun4i_ss_des_setkey,
	133	.encrypt = sun4i_ss_cbc_des_encrypt,
	134	.decrypt = sun4i_ss_cbc_des_decrypt,
	135	.min_keysize = DES_KEY_SIZE,
	136	.max_keysize = DES_KEY_SIZE,
	137	.ivsize = DES_BLOCK_SIZE,
	138	.base = {
	139	.cra_name = "cbc(des)",
	140	.cra_driver_name = "cbc-des-sun4i-ss",
	141	.cra_priority = 300,
	142	.cra_blocksize = DES_BLOCK_SIZE,
0d9c68a9 AT	143	.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER \|
0d9c68a9 AT	144	CRYPTO_ALG_KERN_DRIVER_ONLY,
317cbacf AT	145	.cra_ctxsize = sizeof(struct sun4i_req_ctx),
	146	.cra_module = THIS_MODULE,
	147	.cra_alignmask = 3,
	148	.cra_init = sun4i_ss_cipher_init,
6298e948 LC	149	}
	150	}
	151	},
317cbacf	152	{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
6298e948	153	.alg.crypto = {
317cbacf AT	154	.setkey = sun4i_ss_des_setkey,
	155	.encrypt = sun4i_ss_ecb_des_encrypt,
	156	.decrypt = sun4i_ss_ecb_des_decrypt,
	157	.min_keysize = DES_KEY_SIZE,
	158	.max_keysize = DES_KEY_SIZE,
	159	.base = {
	160	.cra_name = "ecb(des)",
	161	.cra_driver_name = "ecb-des-sun4i-ss",
	162	.cra_priority = 300,
	163	.cra_blocksize = DES_BLOCK_SIZE,
0d9c68a9 AT	164	.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER \|
0d9c68a9 AT	165	CRYPTO_ALG_KERN_DRIVER_ONLY,
317cbacf AT	166	.cra_ctxsize = sizeof(struct sun4i_req_ctx),
	167	.cra_module = THIS_MODULE,
	168	.cra_alignmask = 3,
	169	.cra_init = sun4i_ss_cipher_init,
6298e948 LC	170	}
	171	}
	172	},
317cbacf	173	{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
6298e948	174	.alg.crypto = {
317cbacf AT	175	.setkey = sun4i_ss_des3_setkey,
	176	.encrypt = sun4i_ss_cbc_des3_encrypt,
	177	.decrypt = sun4i_ss_cbc_des3_decrypt,
	178	.min_keysize = DES3_EDE_KEY_SIZE,
	179	.max_keysize = DES3_EDE_KEY_SIZE,
	180	.ivsize = DES3_EDE_BLOCK_SIZE,
	181	.base = {
	182	.cra_name = "cbc(des3_ede)",
	183	.cra_driver_name = "cbc-des3-sun4i-ss",
	184	.cra_priority = 300,
	185	.cra_blocksize = DES3_EDE_BLOCK_SIZE,
0d9c68a9 AT	186	.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER \|
0d9c68a9 AT	187	CRYPTO_ALG_KERN_DRIVER_ONLY,
317cbacf AT	188	.cra_ctxsize = sizeof(struct sun4i_req_ctx),
	189	.cra_module = THIS_MODULE,
	190	.cra_alignmask = 3,
	191	.cra_init = sun4i_ss_cipher_init,
6298e948 LC	192	}
	193	}
	194	},
317cbacf	195	{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
6298e948	196	.alg.crypto = {
317cbacf AT	197	.setkey = sun4i_ss_des3_setkey,
	198	.encrypt = sun4i_ss_ecb_des3_encrypt,
	199	.decrypt = sun4i_ss_ecb_des3_decrypt,
	200	.min_keysize = DES3_EDE_KEY_SIZE,
	201	.max_keysize = DES3_EDE_KEY_SIZE,
	202	.ivsize = DES3_EDE_BLOCK_SIZE,
	203	.base = {
	204	.cra_name = "ecb(des3_ede)",
	205	.cra_driver_name = "ecb-des3-sun4i-ss",
	206	.cra_priority = 300,
	207	.cra_blocksize = DES3_EDE_BLOCK_SIZE,
	208	.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER,
	209	.cra_ctxsize = sizeof(struct sun4i_req_ctx),
	210	.cra_module = THIS_MODULE,
	211	.cra_alignmask = 3,
	212	.cra_init = sun4i_ss_cipher_init,
6298e948 LC	213	}
	214	}
	215	},
b8ae5c73 CL	216	#ifdef CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG
	217	{
	218	.type = CRYPTO_ALG_TYPE_RNG,
	219	.alg.rng = {
	220	.base = {
	221	.cra_name = "stdrng",
	222	.cra_driver_name = "sun4i_ss_rng",
	223	.cra_priority = 300,
	224	.cra_ctxsize = 0,
	225	.cra_module = THIS_MODULE,
	226	},
	227	.generate = sun4i_ss_prng_generate,
	228	.seed = sun4i_ss_prng_seed,
	229	.seedsize = SS_SEED_LEN / BITS_PER_BYTE,
	230	}
	231	},
	232	#endif
6298e948 LC	233	};
	234
	235	static int sun4i_ss_probe(struct platform_device *pdev)
	236	{
	237	struct resource *res;
	238	u32 v;
	239	int err, i;
	240	unsigned long cr;
	241	const unsigned long cr_ahb = 24 * 1000 * 1000;
	242	const unsigned long cr_mod = 150 * 1000 * 1000;
	243	struct sun4i_ss_ctx *ss;
	244
	245	if (!pdev->dev.of_node)
	246	return -ENODEV;
	247
	248	ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
	249	if (!ss)
	250	return -ENOMEM;
	251
	252	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	253	ss->base = devm_ioremap_resource(&pdev->dev, res);
	254	if (IS_ERR(ss->base)) {
	255	dev_err(&pdev->dev, "Cannot request MMIO\n");
	256	return PTR_ERR(ss->base);
	257	}
	258
	259	ss->ssclk = devm_clk_get(&pdev->dev, "mod");
	260	if (IS_ERR(ss->ssclk)) {
	261	err = PTR_ERR(ss->ssclk);
	262	dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
	263	return err;
	264	}
	265	dev_dbg(&pdev->dev, "clock ss acquired\n");
	266
	267	ss->busclk = devm_clk_get(&pdev->dev, "ahb");
	268	if (IS_ERR(ss->busclk)) {
	269	err = PTR_ERR(ss->busclk);
	270	dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
	271	return err;
	272	}
	273	dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
	274
7ab64628 CYT	275	ss->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
	276	if (IS_ERR(ss->reset)) {
	277	if (PTR_ERR(ss->reset) == -EPROBE_DEFER)
	278	return PTR_ERR(ss->reset);
	279	dev_info(&pdev->dev, "no reset control found\n");
	280	ss->reset = NULL;
	281	}
	282
6298e948 LC	283	/* Enable both clocks */
6298e948 LC	284	err = clk_prepare_enable(ss->busclk);
a595e60a	285	if (err) {
6298e948 LC	286	dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
	287	return err;
	288	}
	289	err = clk_prepare_enable(ss->ssclk);
a595e60a	290	if (err) {
6298e948 LC	291	dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
	292	goto error_ssclk;
	293	}
	294
	295	/*
	296	* Check that clock have the correct rates given in the datasheet
	297	* Try to set the clock to the maximum allowed
	298	*/
	299	err = clk_set_rate(ss->ssclk, cr_mod);
a595e60a	300	if (err) {
6298e948 LC	301	dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
	302	goto error_clk;
	303	}
	304
7ab64628 CYT	305	/* Deassert reset if we have a reset control */
	306	if (ss->reset) {
	307	err = reset_control_deassert(ss->reset);
	308	if (err) {
	309	dev_err(&pdev->dev, "Cannot deassert reset control\n");
	310	goto error_clk;
	311	}
	312	}
	313
6298e948 LC	314	/*
	315	* The only impact on clocks below requirement are bad performance,
	316	* so do not print "errors"
	317	* warn on Overclocked clocks
	318	*/
	319	cr = clk_get_rate(ss->busclk);
	320	if (cr >= cr_ahb)
	321	dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
	322	cr, cr / 1000000, cr_ahb);
	323	else
	324	dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
	325	cr, cr / 1000000, cr_ahb);
	326
	327	cr = clk_get_rate(ss->ssclk);
	328	if (cr <= cr_mod)
	329	if (cr < cr_mod)
	330	dev_warn(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
	331	cr, cr / 1000000, cr_mod);
	332	else
	333	dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
	334	cr, cr / 1000000, cr_mod);
	335	else
	336	dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
	337	cr, cr / 1000000, cr_mod);
	338
	339	/*
	340	* Datasheet named it "Die Bonding ID"
	341	* I expect to be a sort of Security System Revision number.
	342	* Since the A80 seems to have an other version of SS
	343	* this info could be useful
	344	*/
	345	writel(SS_ENABLED, ss->base + SS_CTL);
	346	v = readl(ss->base + SS_CTL);
	347	v >>= 16;
	348	v &= 0x07;
	349	dev_info(&pdev->dev, "Die ID %d\n", v);
	350	writel(0, ss->base + SS_CTL);
	351
	352	ss->dev = &pdev->dev;
	353
	354	spin_lock_init(&ss->slock);
	355
	356	for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
	357	ss_algs[i].ss = ss;
	358	switch (ss_algs[i].type) {
317cbacf AT	359	case CRYPTO_ALG_TYPE_SKCIPHER:
317cbacf AT	360	err = crypto_register_skcipher(&ss_algs[i].alg.crypto);
a595e60a	361	if (err) {
6298e948	362	dev_err(ss->dev, "Fail to register %s\n",
317cbacf	363	ss_algs[i].alg.crypto.base.cra_name);
6298e948 LC	364	goto error_alg;
	365	}
	366	break;
	367	case CRYPTO_ALG_TYPE_AHASH:
	368	err = crypto_register_ahash(&ss_algs[i].alg.hash);
a595e60a	369	if (err) {
6298e948 LC	370	dev_err(ss->dev, "Fail to register %s\n",
	371	ss_algs[i].alg.hash.halg.base.cra_name);
	372	goto error_alg;
	373	}
	374	break;
b8ae5c73 CL	375	case CRYPTO_ALG_TYPE_RNG:
	376	err = crypto_register_rng(&ss_algs[i].alg.rng);
	377	if (err) {
	378	dev_err(ss->dev, "Fail to register %s\n",
	379	ss_algs[i].alg.rng.base.cra_name);
	380	}
	381	break;
6298e948 LC	382	}
	383	}
	384	platform_set_drvdata(pdev, ss);
	385	return 0;
	386	error_alg:
	387	i--;
	388	for (; i >= 0; i--) {
	389	switch (ss_algs[i].type) {
317cbacf AT	390	case CRYPTO_ALG_TYPE_SKCIPHER:
317cbacf AT	391	crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
6298e948 LC	392	break;
	393	case CRYPTO_ALG_TYPE_AHASH:
	394	crypto_unregister_ahash(&ss_algs[i].alg.hash);
	395	break;
b8ae5c73 CL	396	case CRYPTO_ALG_TYPE_RNG:
	397	crypto_unregister_rng(&ss_algs[i].alg.rng);
	398	break;
6298e948 LC	399	}
6298e948 LC	400	}
7ab64628 CYT	401	if (ss->reset)
7ab64628 CYT	402	reset_control_assert(ss->reset);
6298e948 LC	403	error_clk:
	404	clk_disable_unprepare(ss->ssclk);
	405	error_ssclk:
	406	clk_disable_unprepare(ss->busclk);
	407	return err;
	408	}
	409
	410	static int sun4i_ss_remove(struct platform_device *pdev)
	411	{
	412	int i;
	413	struct sun4i_ss_ctx *ss = platform_get_drvdata(pdev);
	414
	415	for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
	416	switch (ss_algs[i].type) {
317cbacf AT	417	case CRYPTO_ALG_TYPE_SKCIPHER:
317cbacf AT	418	crypto_unregister_skcipher(&ss_algs[i].alg.crypto);
6298e948 LC	419	break;
	420	case CRYPTO_ALG_TYPE_AHASH:
	421	crypto_unregister_ahash(&ss_algs[i].alg.hash);
	422	break;
b8ae5c73 CL	423	case CRYPTO_ALG_TYPE_RNG:
	424	crypto_unregister_rng(&ss_algs[i].alg.rng);
	425	break;
6298e948 LC	426	}
	427	}
	428
	429	writel(0, ss->base + SS_CTL);
7ab64628 CYT	430	if (ss->reset)
7ab64628 CYT	431	reset_control_assert(ss->reset);
6298e948 LC	432	clk_disable_unprepare(ss->busclk);
	433	clk_disable_unprepare(ss->ssclk);
	434	return 0;
	435	}
	436
	437	static const struct of_device_id a20ss_crypto_of_match_table[] = {
	438	{ .compatible = "allwinner,sun4i-a10-crypto" },
	439	{}
	440	};
	441	MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
	442
	443	static struct platform_driver sun4i_ss_driver = {
	444	.probe = sun4i_ss_probe,
	445	.remove = sun4i_ss_remove,
	446	.driver = {
	447	.name = "sun4i-ss",
	448	.of_match_table = a20ss_crypto_of_match_table,
	449	},
	450	};
	451
	452	module_platform_driver(sun4i_ss_driver);
	453
7c73cf4c	454	MODULE_ALIAS("platform:sun4i-ss");
6298e948 LC	455	MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
	456	MODULE_LICENSE("GPL");
	457	MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");