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6298e948 LC |
1 | /* |
2 | * sun4i-ss.h - hardware cryptographic accelerator for Allwinner A20 SoC | |
3 | * | |
4 | * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com> | |
5 | * | |
6 | * Support AES cipher with 128,192,256 bits keysize. | |
7 | * Support MD5 and SHA1 hash algorithms. | |
8 | * Support DES and 3DES | |
9 | * | |
10 | * You could find the datasheet in Documentation/arm/sunxi/README | |
11 | * | |
12 | * Licensed under the GPL-2. | |
13 | */ | |
14 | ||
15 | #include <linux/clk.h> | |
16 | #include <linux/crypto.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/platform_device.h> | |
7ab64628 | 21 | #include <linux/reset.h> |
6298e948 LC |
22 | #include <crypto/scatterwalk.h> |
23 | #include <linux/scatterlist.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/delay.h> | |
26 | #include <crypto/md5.h> | |
317cbacf | 27 | #include <crypto/skcipher.h> |
6298e948 LC |
28 | #include <crypto/sha.h> |
29 | #include <crypto/hash.h> | |
30 | #include <crypto/internal/hash.h> | |
317cbacf | 31 | #include <crypto/internal/skcipher.h> |
6298e948 LC |
32 | #include <crypto/aes.h> |
33 | #include <crypto/des.h> | |
34 | #include <crypto/internal/rng.h> | |
b8ae5c73 | 35 | #include <crypto/rng.h> |
6298e948 LC |
36 | |
37 | #define SS_CTL 0x00 | |
38 | #define SS_KEY0 0x04 | |
39 | #define SS_KEY1 0x08 | |
40 | #define SS_KEY2 0x0C | |
41 | #define SS_KEY3 0x10 | |
42 | #define SS_KEY4 0x14 | |
43 | #define SS_KEY5 0x18 | |
44 | #define SS_KEY6 0x1C | |
45 | #define SS_KEY7 0x20 | |
46 | ||
47 | #define SS_IV0 0x24 | |
48 | #define SS_IV1 0x28 | |
49 | #define SS_IV2 0x2C | |
50 | #define SS_IV3 0x30 | |
51 | ||
52 | #define SS_FCSR 0x44 | |
53 | ||
54 | #define SS_MD0 0x4C | |
55 | #define SS_MD1 0x50 | |
56 | #define SS_MD2 0x54 | |
57 | #define SS_MD3 0x58 | |
58 | #define SS_MD4 0x5C | |
59 | ||
60 | #define SS_RXFIFO 0x200 | |
61 | #define SS_TXFIFO 0x204 | |
62 | ||
63 | /* SS_CTL configuration values */ | |
64 | ||
65 | /* PRNG generator mode - bit 15 */ | |
66 | #define SS_PRNG_ONESHOT (0 << 15) | |
67 | #define SS_PRNG_CONTINUE (1 << 15) | |
68 | ||
69 | /* IV mode for hash */ | |
70 | #define SS_IV_ARBITRARY (1 << 14) | |
71 | ||
72 | /* SS operation mode - bits 12-13 */ | |
73 | #define SS_ECB (0 << 12) | |
74 | #define SS_CBC (1 << 12) | |
75 | #define SS_CTS (3 << 12) | |
76 | ||
77 | /* Counter width for CNT mode - bits 10-11 */ | |
78 | #define SS_CNT_16BITS (0 << 10) | |
79 | #define SS_CNT_32BITS (1 << 10) | |
80 | #define SS_CNT_64BITS (2 << 10) | |
81 | ||
82 | /* Key size for AES - bits 8-9 */ | |
83 | #define SS_AES_128BITS (0 << 8) | |
84 | #define SS_AES_192BITS (1 << 8) | |
85 | #define SS_AES_256BITS (2 << 8) | |
86 | ||
87 | /* Operation direction - bit 7 */ | |
88 | #define SS_ENCRYPTION (0 << 7) | |
89 | #define SS_DECRYPTION (1 << 7) | |
90 | ||
91 | /* SS Method - bits 4-6 */ | |
92 | #define SS_OP_AES (0 << 4) | |
93 | #define SS_OP_DES (1 << 4) | |
94 | #define SS_OP_3DES (2 << 4) | |
95 | #define SS_OP_SHA1 (3 << 4) | |
96 | #define SS_OP_MD5 (4 << 4) | |
97 | #define SS_OP_PRNG (5 << 4) | |
98 | ||
99 | /* Data end bit - bit 2 */ | |
100 | #define SS_DATA_END (1 << 2) | |
101 | ||
102 | /* PRNG start bit - bit 1 */ | |
103 | #define SS_PRNG_START (1 << 1) | |
104 | ||
105 | /* SS Enable bit - bit 0 */ | |
106 | #define SS_DISABLED (0 << 0) | |
107 | #define SS_ENABLED (1 << 0) | |
108 | ||
109 | /* SS_FCSR configuration values */ | |
110 | /* RX FIFO status - bit 30 */ | |
111 | #define SS_RXFIFO_FREE (1 << 30) | |
112 | ||
113 | /* RX FIFO empty spaces - bits 24-29 */ | |
114 | #define SS_RXFIFO_SPACES(val) (((val) >> 24) & 0x3f) | |
115 | ||
116 | /* TX FIFO status - bit 22 */ | |
117 | #define SS_TXFIFO_AVAILABLE (1 << 22) | |
118 | ||
119 | /* TX FIFO available spaces - bits 16-21 */ | |
120 | #define SS_TXFIFO_SPACES(val) (((val) >> 16) & 0x3f) | |
121 | ||
122 | #define SS_RX_MAX 32 | |
123 | #define SS_RX_DEFAULT SS_RX_MAX | |
124 | #define SS_TX_MAX 33 | |
125 | ||
126 | #define SS_RXFIFO_EMP_INT_PENDING (1 << 10) | |
127 | #define SS_TXFIFO_AVA_INT_PENDING (1 << 8) | |
128 | #define SS_RXFIFO_EMP_INT_ENABLE (1 << 2) | |
129 | #define SS_TXFIFO_AVA_INT_ENABLE (1 << 0) | |
130 | ||
b8ae5c73 CL |
131 | #define SS_SEED_LEN 192 |
132 | #define SS_DATA_LEN 160 | |
133 | ||
6298e948 LC |
134 | struct sun4i_ss_ctx { |
135 | void __iomem *base; | |
136 | int irq; | |
137 | struct clk *busclk; | |
138 | struct clk *ssclk; | |
7ab64628 | 139 | struct reset_control *reset; |
6298e948 LC |
140 | struct device *dev; |
141 | struct resource *res; | |
142 | spinlock_t slock; /* control the use of the device */ | |
b8ae5c73 CL |
143 | #ifdef CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG |
144 | u32 seed[SS_SEED_LEN / BITS_PER_LONG]; | |
145 | #endif | |
6298e948 LC |
146 | }; |
147 | ||
148 | struct sun4i_ss_alg_template { | |
149 | u32 type; | |
150 | u32 mode; | |
151 | union { | |
317cbacf | 152 | struct skcipher_alg crypto; |
6298e948 | 153 | struct ahash_alg hash; |
b8ae5c73 | 154 | struct rng_alg rng; |
6298e948 LC |
155 | } alg; |
156 | struct sun4i_ss_ctx *ss; | |
157 | }; | |
158 | ||
159 | struct sun4i_tfm_ctx { | |
160 | u32 key[AES_MAX_KEY_SIZE / 4];/* divided by sizeof(u32) */ | |
161 | u32 keylen; | |
162 | u32 keymode; | |
163 | struct sun4i_ss_ctx *ss; | |
164 | }; | |
165 | ||
166 | struct sun4i_cipher_req_ctx { | |
167 | u32 mode; | |
168 | }; | |
169 | ||
170 | struct sun4i_req_ctx { | |
171 | u32 mode; | |
172 | u64 byte_count; /* number of bytes "uploaded" to the device */ | |
173 | u32 hash[5]; /* for storing SS_IVx register */ | |
174 | char buf[64]; | |
175 | unsigned int len; | |
477d9b2e | 176 | int flags; |
6298e948 LC |
177 | }; |
178 | ||
179 | int sun4i_hash_crainit(struct crypto_tfm *tfm); | |
180 | int sun4i_hash_init(struct ahash_request *areq); | |
181 | int sun4i_hash_update(struct ahash_request *areq); | |
182 | int sun4i_hash_final(struct ahash_request *areq); | |
183 | int sun4i_hash_finup(struct ahash_request *areq); | |
184 | int sun4i_hash_digest(struct ahash_request *areq); | |
185 | int sun4i_hash_export_md5(struct ahash_request *areq, void *out); | |
186 | int sun4i_hash_import_md5(struct ahash_request *areq, const void *in); | |
187 | int sun4i_hash_export_sha1(struct ahash_request *areq, void *out); | |
188 | int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in); | |
189 | ||
317cbacf AT |
190 | int sun4i_ss_cbc_aes_encrypt(struct skcipher_request *areq); |
191 | int sun4i_ss_cbc_aes_decrypt(struct skcipher_request *areq); | |
192 | int sun4i_ss_ecb_aes_encrypt(struct skcipher_request *areq); | |
193 | int sun4i_ss_ecb_aes_decrypt(struct skcipher_request *areq); | |
6298e948 | 194 | |
317cbacf AT |
195 | int sun4i_ss_cbc_des_encrypt(struct skcipher_request *areq); |
196 | int sun4i_ss_cbc_des_decrypt(struct skcipher_request *areq); | |
197 | int sun4i_ss_ecb_des_encrypt(struct skcipher_request *areq); | |
198 | int sun4i_ss_ecb_des_decrypt(struct skcipher_request *areq); | |
6298e948 | 199 | |
317cbacf AT |
200 | int sun4i_ss_cbc_des3_encrypt(struct skcipher_request *areq); |
201 | int sun4i_ss_cbc_des3_decrypt(struct skcipher_request *areq); | |
202 | int sun4i_ss_ecb_des3_encrypt(struct skcipher_request *areq); | |
203 | int sun4i_ss_ecb_des3_decrypt(struct skcipher_request *areq); | |
6298e948 LC |
204 | |
205 | int sun4i_ss_cipher_init(struct crypto_tfm *tfm); | |
317cbacf | 206 | int sun4i_ss_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, |
6298e948 | 207 | unsigned int keylen); |
317cbacf | 208 | int sun4i_ss_des_setkey(struct crypto_skcipher *tfm, const u8 *key, |
6298e948 | 209 | unsigned int keylen); |
317cbacf | 210 | int sun4i_ss_des3_setkey(struct crypto_skcipher *tfm, const u8 *key, |
6298e948 | 211 | unsigned int keylen); |
b8ae5c73 CL |
212 | int sun4i_ss_prng_generate(struct crypto_rng *tfm, const u8 *src, |
213 | unsigned int slen, u8 *dst, unsigned int dlen); | |
214 | int sun4i_ss_prng_seed(struct crypto_rng *tfm, const u8 *seed, unsigned int slen); |