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9c4a7965 KP |
1 | /* |
2 | * talitos - Freescale Integrated Security Engine (SEC) device driver | |
3 | * | |
5228f0f7 | 4 | * Copyright (c) 2008-2011 Freescale Semiconductor, Inc. |
9c4a7965 KP |
5 | * |
6 | * Scatterlist Crypto API glue code copied from files with the following: | |
7 | * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au> | |
8 | * | |
9 | * Crypto algorithm registration code copied from hifn driver: | |
10 | * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru> | |
11 | * All rights reserved. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/mod_devicetable.h> | |
31 | #include <linux/device.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/crypto.h> | |
34 | #include <linux/hw_random.h> | |
35 | #include <linux/of_platform.h> | |
36 | #include <linux/dma-mapping.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/rtnetlink.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
9c4a7965 KP |
41 | |
42 | #include <crypto/algapi.h> | |
43 | #include <crypto/aes.h> | |
3952f17e | 44 | #include <crypto/des.h> |
9c4a7965 | 45 | #include <crypto/sha.h> |
497f2e6b | 46 | #include <crypto/md5.h> |
9c4a7965 KP |
47 | #include <crypto/aead.h> |
48 | #include <crypto/authenc.h> | |
4de9d0b5 | 49 | #include <crypto/skcipher.h> |
acbf7c62 LN |
50 | #include <crypto/hash.h> |
51 | #include <crypto/internal/hash.h> | |
4de9d0b5 | 52 | #include <crypto/scatterwalk.h> |
9c4a7965 KP |
53 | |
54 | #include "talitos.h" | |
55 | ||
56 | #define TALITOS_TIMEOUT 100000 | |
57 | #define TALITOS_MAX_DATA_LEN 65535 | |
58 | ||
59 | #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f) | |
60 | #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf) | |
61 | #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf) | |
62 | ||
63 | /* descriptor pointer entry */ | |
64 | struct talitos_ptr { | |
65 | __be16 len; /* length */ | |
66 | u8 j_extent; /* jump to sg link table and/or extent */ | |
67 | u8 eptr; /* extended address */ | |
68 | __be32 ptr; /* address */ | |
69 | }; | |
70 | ||
497f2e6b LN |
71 | static const struct talitos_ptr zero_entry = { |
72 | .len = 0, | |
73 | .j_extent = 0, | |
74 | .eptr = 0, | |
75 | .ptr = 0 | |
76 | }; | |
77 | ||
9c4a7965 KP |
78 | /* descriptor */ |
79 | struct talitos_desc { | |
80 | __be32 hdr; /* header high bits */ | |
81 | __be32 hdr_lo; /* header low bits */ | |
82 | struct talitos_ptr ptr[7]; /* ptr/len pair array */ | |
83 | }; | |
84 | ||
85 | /** | |
86 | * talitos_request - descriptor submission request | |
87 | * @desc: descriptor pointer (kernel virtual) | |
88 | * @dma_desc: descriptor's physical bus address | |
89 | * @callback: whom to call when descriptor processing is done | |
90 | * @context: caller context (optional) | |
91 | */ | |
92 | struct talitos_request { | |
93 | struct talitos_desc *desc; | |
94 | dma_addr_t dma_desc; | |
95 | void (*callback) (struct device *dev, struct talitos_desc *desc, | |
96 | void *context, int error); | |
97 | void *context; | |
98 | }; | |
99 | ||
4b992628 KP |
100 | /* per-channel fifo management */ |
101 | struct talitos_channel { | |
ad42d5fc KP |
102 | void __iomem *reg; |
103 | ||
4b992628 KP |
104 | /* request fifo */ |
105 | struct talitos_request *fifo; | |
106 | ||
107 | /* number of requests pending in channel h/w fifo */ | |
108 | atomic_t submit_count ____cacheline_aligned; | |
109 | ||
110 | /* request submission (head) lock */ | |
111 | spinlock_t head_lock ____cacheline_aligned; | |
112 | /* index to next free descriptor request */ | |
113 | int head; | |
114 | ||
115 | /* request release (tail) lock */ | |
116 | spinlock_t tail_lock ____cacheline_aligned; | |
117 | /* index to next in-progress/done descriptor request */ | |
118 | int tail; | |
119 | }; | |
120 | ||
9c4a7965 KP |
121 | struct talitos_private { |
122 | struct device *dev; | |
2dc11581 | 123 | struct platform_device *ofdev; |
9c4a7965 KP |
124 | void __iomem *reg; |
125 | int irq; | |
126 | ||
127 | /* SEC version geometry (from device tree node) */ | |
128 | unsigned int num_channels; | |
129 | unsigned int chfifo_len; | |
130 | unsigned int exec_units; | |
131 | unsigned int desc_types; | |
132 | ||
f3c85bc1 LN |
133 | /* SEC Compatibility info */ |
134 | unsigned long features; | |
135 | ||
9c4a7965 KP |
136 | /* |
137 | * length of the request fifo | |
138 | * fifo_len is chfifo_len rounded up to next power of 2 | |
139 | * so we can use bitwise ops to wrap | |
140 | */ | |
141 | unsigned int fifo_len; | |
142 | ||
4b992628 | 143 | struct talitos_channel *chan; |
9c4a7965 | 144 | |
4b992628 KP |
145 | /* next channel to be assigned next incoming descriptor */ |
146 | atomic_t last_chan ____cacheline_aligned; | |
9c4a7965 KP |
147 | |
148 | /* request callback tasklet */ | |
149 | struct tasklet_struct done_task; | |
9c4a7965 KP |
150 | |
151 | /* list of registered algorithms */ | |
152 | struct list_head alg_list; | |
153 | ||
154 | /* hwrng device */ | |
155 | struct hwrng rng; | |
156 | }; | |
157 | ||
f3c85bc1 LN |
158 | /* .features flag */ |
159 | #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001 | |
fe5720e2 | 160 | #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002 |
60f208d7 | 161 | #define TALITOS_FTR_SHA224_HWINIT 0x00000004 |
79b3a418 | 162 | #define TALITOS_FTR_HMAC_OK 0x00000008 |
f3c85bc1 | 163 | |
81eb024c KP |
164 | static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr) |
165 | { | |
166 | talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr)); | |
a752447a | 167 | talitos_ptr->eptr = upper_32_bits(dma_addr); |
81eb024c KP |
168 | } |
169 | ||
9c4a7965 KP |
170 | /* |
171 | * map virtual single (contiguous) pointer to h/w descriptor pointer | |
172 | */ | |
173 | static void map_single_talitos_ptr(struct device *dev, | |
174 | struct talitos_ptr *talitos_ptr, | |
175 | unsigned short len, void *data, | |
176 | unsigned char extent, | |
177 | enum dma_data_direction dir) | |
178 | { | |
81eb024c KP |
179 | dma_addr_t dma_addr = dma_map_single(dev, data, len, dir); |
180 | ||
9c4a7965 | 181 | talitos_ptr->len = cpu_to_be16(len); |
81eb024c | 182 | to_talitos_ptr(talitos_ptr, dma_addr); |
9c4a7965 KP |
183 | talitos_ptr->j_extent = extent; |
184 | } | |
185 | ||
186 | /* | |
187 | * unmap bus single (contiguous) h/w descriptor pointer | |
188 | */ | |
189 | static void unmap_single_talitos_ptr(struct device *dev, | |
190 | struct talitos_ptr *talitos_ptr, | |
191 | enum dma_data_direction dir) | |
192 | { | |
193 | dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr), | |
194 | be16_to_cpu(talitos_ptr->len), dir); | |
195 | } | |
196 | ||
197 | static int reset_channel(struct device *dev, int ch) | |
198 | { | |
199 | struct talitos_private *priv = dev_get_drvdata(dev); | |
200 | unsigned int timeout = TALITOS_TIMEOUT; | |
201 | ||
ad42d5fc | 202 | setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET); |
9c4a7965 | 203 | |
ad42d5fc | 204 | while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET) |
9c4a7965 KP |
205 | && --timeout) |
206 | cpu_relax(); | |
207 | ||
208 | if (timeout == 0) { | |
209 | dev_err(dev, "failed to reset channel %d\n", ch); | |
210 | return -EIO; | |
211 | } | |
212 | ||
81eb024c | 213 | /* set 36-bit addressing, done writeback enable and done IRQ enable */ |
ad42d5fc | 214 | setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE | |
81eb024c | 215 | TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE); |
9c4a7965 | 216 | |
fe5720e2 KP |
217 | /* and ICCR writeback, if available */ |
218 | if (priv->features & TALITOS_FTR_HW_AUTH_CHECK) | |
ad42d5fc | 219 | setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, |
fe5720e2 KP |
220 | TALITOS_CCCR_LO_IWSE); |
221 | ||
9c4a7965 KP |
222 | return 0; |
223 | } | |
224 | ||
225 | static int reset_device(struct device *dev) | |
226 | { | |
227 | struct talitos_private *priv = dev_get_drvdata(dev); | |
228 | unsigned int timeout = TALITOS_TIMEOUT; | |
229 | ||
230 | setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR); | |
231 | ||
232 | while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR) | |
233 | && --timeout) | |
234 | cpu_relax(); | |
235 | ||
236 | if (timeout == 0) { | |
237 | dev_err(dev, "failed to reset device\n"); | |
238 | return -EIO; | |
239 | } | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
244 | /* | |
245 | * Reset and initialize the device | |
246 | */ | |
247 | static int init_device(struct device *dev) | |
248 | { | |
249 | struct talitos_private *priv = dev_get_drvdata(dev); | |
250 | int ch, err; | |
251 | ||
252 | /* | |
253 | * Master reset | |
254 | * errata documentation: warning: certain SEC interrupts | |
255 | * are not fully cleared by writing the MCR:SWR bit, | |
256 | * set bit twice to completely reset | |
257 | */ | |
258 | err = reset_device(dev); | |
259 | if (err) | |
260 | return err; | |
261 | ||
262 | err = reset_device(dev); | |
263 | if (err) | |
264 | return err; | |
265 | ||
266 | /* reset channels */ | |
267 | for (ch = 0; ch < priv->num_channels; ch++) { | |
268 | err = reset_channel(dev, ch); | |
269 | if (err) | |
270 | return err; | |
271 | } | |
272 | ||
273 | /* enable channel done and error interrupts */ | |
274 | setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT); | |
275 | setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT); | |
276 | ||
fe5720e2 KP |
277 | /* disable integrity check error interrupts (use writeback instead) */ |
278 | if (priv->features & TALITOS_FTR_HW_AUTH_CHECK) | |
279 | setbits32(priv->reg + TALITOS_MDEUICR_LO, | |
280 | TALITOS_MDEUICR_LO_ICE); | |
281 | ||
9c4a7965 KP |
282 | return 0; |
283 | } | |
284 | ||
285 | /** | |
286 | * talitos_submit - submits a descriptor to the device for processing | |
287 | * @dev: the SEC device to be used | |
5228f0f7 | 288 | * @ch: the SEC device channel to be used |
9c4a7965 KP |
289 | * @desc: the descriptor to be processed by the device |
290 | * @callback: whom to call when processing is complete | |
291 | * @context: a handle for use by caller (optional) | |
292 | * | |
293 | * desc must contain valid dma-mapped (bus physical) address pointers. | |
294 | * callback must check err and feedback in descriptor header | |
295 | * for device processing status. | |
296 | */ | |
5228f0f7 | 297 | static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc, |
9c4a7965 KP |
298 | void (*callback)(struct device *dev, |
299 | struct talitos_desc *desc, | |
300 | void *context, int error), | |
301 | void *context) | |
302 | { | |
303 | struct talitos_private *priv = dev_get_drvdata(dev); | |
304 | struct talitos_request *request; | |
5228f0f7 | 305 | unsigned long flags; |
9c4a7965 KP |
306 | int head; |
307 | ||
4b992628 | 308 | spin_lock_irqsave(&priv->chan[ch].head_lock, flags); |
9c4a7965 | 309 | |
4b992628 | 310 | if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) { |
ec6644d6 | 311 | /* h/w fifo is full */ |
4b992628 | 312 | spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags); |
9c4a7965 KP |
313 | return -EAGAIN; |
314 | } | |
315 | ||
4b992628 KP |
316 | head = priv->chan[ch].head; |
317 | request = &priv->chan[ch].fifo[head]; | |
ec6644d6 | 318 | |
9c4a7965 KP |
319 | /* map descriptor and save caller data */ |
320 | request->dma_desc = dma_map_single(dev, desc, sizeof(*desc), | |
321 | DMA_BIDIRECTIONAL); | |
322 | request->callback = callback; | |
323 | request->context = context; | |
324 | ||
325 | /* increment fifo head */ | |
4b992628 | 326 | priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1); |
9c4a7965 KP |
327 | |
328 | smp_wmb(); | |
329 | request->desc = desc; | |
330 | ||
331 | /* GO! */ | |
332 | wmb(); | |
ad42d5fc KP |
333 | out_be32(priv->chan[ch].reg + TALITOS_FF, |
334 | upper_32_bits(request->dma_desc)); | |
335 | out_be32(priv->chan[ch].reg + TALITOS_FF_LO, | |
a752447a | 336 | lower_32_bits(request->dma_desc)); |
9c4a7965 | 337 | |
4b992628 | 338 | spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags); |
9c4a7965 KP |
339 | |
340 | return -EINPROGRESS; | |
341 | } | |
342 | ||
343 | /* | |
344 | * process what was done, notify callback of error if not | |
345 | */ | |
346 | static void flush_channel(struct device *dev, int ch, int error, int reset_ch) | |
347 | { | |
348 | struct talitos_private *priv = dev_get_drvdata(dev); | |
349 | struct talitos_request *request, saved_req; | |
350 | unsigned long flags; | |
351 | int tail, status; | |
352 | ||
4b992628 | 353 | spin_lock_irqsave(&priv->chan[ch].tail_lock, flags); |
9c4a7965 | 354 | |
4b992628 KP |
355 | tail = priv->chan[ch].tail; |
356 | while (priv->chan[ch].fifo[tail].desc) { | |
357 | request = &priv->chan[ch].fifo[tail]; | |
9c4a7965 KP |
358 | |
359 | /* descriptors with their done bits set don't get the error */ | |
360 | rmb(); | |
ca38a814 | 361 | if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE) |
9c4a7965 | 362 | status = 0; |
ca38a814 | 363 | else |
9c4a7965 KP |
364 | if (!error) |
365 | break; | |
366 | else | |
367 | status = error; | |
368 | ||
369 | dma_unmap_single(dev, request->dma_desc, | |
e938e465 KP |
370 | sizeof(struct talitos_desc), |
371 | DMA_BIDIRECTIONAL); | |
9c4a7965 KP |
372 | |
373 | /* copy entries so we can call callback outside lock */ | |
374 | saved_req.desc = request->desc; | |
375 | saved_req.callback = request->callback; | |
376 | saved_req.context = request->context; | |
377 | ||
378 | /* release request entry in fifo */ | |
379 | smp_wmb(); | |
380 | request->desc = NULL; | |
381 | ||
382 | /* increment fifo tail */ | |
4b992628 | 383 | priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1); |
9c4a7965 | 384 | |
4b992628 | 385 | spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags); |
ec6644d6 | 386 | |
4b992628 | 387 | atomic_dec(&priv->chan[ch].submit_count); |
ec6644d6 | 388 | |
9c4a7965 KP |
389 | saved_req.callback(dev, saved_req.desc, saved_req.context, |
390 | status); | |
391 | /* channel may resume processing in single desc error case */ | |
392 | if (error && !reset_ch && status == error) | |
393 | return; | |
4b992628 KP |
394 | spin_lock_irqsave(&priv->chan[ch].tail_lock, flags); |
395 | tail = priv->chan[ch].tail; | |
9c4a7965 KP |
396 | } |
397 | ||
4b992628 | 398 | spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags); |
9c4a7965 KP |
399 | } |
400 | ||
401 | /* | |
402 | * process completed requests for channels that have done status | |
403 | */ | |
404 | static void talitos_done(unsigned long data) | |
405 | { | |
406 | struct device *dev = (struct device *)data; | |
407 | struct talitos_private *priv = dev_get_drvdata(dev); | |
408 | int ch; | |
409 | ||
410 | for (ch = 0; ch < priv->num_channels; ch++) | |
411 | flush_channel(dev, ch, 0, 0); | |
1c2e8811 LN |
412 | |
413 | /* At this point, all completed channels have been processed. | |
414 | * Unmask done interrupts for channels completed later on. | |
415 | */ | |
fe5720e2 KP |
416 | setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT); |
417 | setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT); | |
9c4a7965 KP |
418 | } |
419 | ||
420 | /* | |
421 | * locate current (offending) descriptor | |
422 | */ | |
3e721aeb | 423 | static u32 current_desc_hdr(struct device *dev, int ch) |
9c4a7965 KP |
424 | { |
425 | struct talitos_private *priv = dev_get_drvdata(dev); | |
4b992628 | 426 | int tail = priv->chan[ch].tail; |
9c4a7965 KP |
427 | dma_addr_t cur_desc; |
428 | ||
ad42d5fc | 429 | cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO); |
9c4a7965 | 430 | |
4b992628 | 431 | while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) { |
9c4a7965 | 432 | tail = (tail + 1) & (priv->fifo_len - 1); |
4b992628 | 433 | if (tail == priv->chan[ch].tail) { |
9c4a7965 | 434 | dev_err(dev, "couldn't locate current descriptor\n"); |
3e721aeb | 435 | return 0; |
9c4a7965 KP |
436 | } |
437 | } | |
438 | ||
3e721aeb | 439 | return priv->chan[ch].fifo[tail].desc->hdr; |
9c4a7965 KP |
440 | } |
441 | ||
442 | /* | |
443 | * user diagnostics; report root cause of error based on execution unit status | |
444 | */ | |
3e721aeb | 445 | static void report_eu_error(struct device *dev, int ch, u32 desc_hdr) |
9c4a7965 KP |
446 | { |
447 | struct talitos_private *priv = dev_get_drvdata(dev); | |
448 | int i; | |
449 | ||
3e721aeb | 450 | if (!desc_hdr) |
ad42d5fc | 451 | desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF); |
3e721aeb KP |
452 | |
453 | switch (desc_hdr & DESC_HDR_SEL0_MASK) { | |
9c4a7965 KP |
454 | case DESC_HDR_SEL0_AFEU: |
455 | dev_err(dev, "AFEUISR 0x%08x_%08x\n", | |
456 | in_be32(priv->reg + TALITOS_AFEUISR), | |
457 | in_be32(priv->reg + TALITOS_AFEUISR_LO)); | |
458 | break; | |
459 | case DESC_HDR_SEL0_DEU: | |
460 | dev_err(dev, "DEUISR 0x%08x_%08x\n", | |
461 | in_be32(priv->reg + TALITOS_DEUISR), | |
462 | in_be32(priv->reg + TALITOS_DEUISR_LO)); | |
463 | break; | |
464 | case DESC_HDR_SEL0_MDEUA: | |
465 | case DESC_HDR_SEL0_MDEUB: | |
466 | dev_err(dev, "MDEUISR 0x%08x_%08x\n", | |
467 | in_be32(priv->reg + TALITOS_MDEUISR), | |
468 | in_be32(priv->reg + TALITOS_MDEUISR_LO)); | |
469 | break; | |
470 | case DESC_HDR_SEL0_RNG: | |
471 | dev_err(dev, "RNGUISR 0x%08x_%08x\n", | |
472 | in_be32(priv->reg + TALITOS_RNGUISR), | |
473 | in_be32(priv->reg + TALITOS_RNGUISR_LO)); | |
474 | break; | |
475 | case DESC_HDR_SEL0_PKEU: | |
476 | dev_err(dev, "PKEUISR 0x%08x_%08x\n", | |
477 | in_be32(priv->reg + TALITOS_PKEUISR), | |
478 | in_be32(priv->reg + TALITOS_PKEUISR_LO)); | |
479 | break; | |
480 | case DESC_HDR_SEL0_AESU: | |
481 | dev_err(dev, "AESUISR 0x%08x_%08x\n", | |
482 | in_be32(priv->reg + TALITOS_AESUISR), | |
483 | in_be32(priv->reg + TALITOS_AESUISR_LO)); | |
484 | break; | |
485 | case DESC_HDR_SEL0_CRCU: | |
486 | dev_err(dev, "CRCUISR 0x%08x_%08x\n", | |
487 | in_be32(priv->reg + TALITOS_CRCUISR), | |
488 | in_be32(priv->reg + TALITOS_CRCUISR_LO)); | |
489 | break; | |
490 | case DESC_HDR_SEL0_KEU: | |
491 | dev_err(dev, "KEUISR 0x%08x_%08x\n", | |
492 | in_be32(priv->reg + TALITOS_KEUISR), | |
493 | in_be32(priv->reg + TALITOS_KEUISR_LO)); | |
494 | break; | |
495 | } | |
496 | ||
3e721aeb | 497 | switch (desc_hdr & DESC_HDR_SEL1_MASK) { |
9c4a7965 KP |
498 | case DESC_HDR_SEL1_MDEUA: |
499 | case DESC_HDR_SEL1_MDEUB: | |
500 | dev_err(dev, "MDEUISR 0x%08x_%08x\n", | |
501 | in_be32(priv->reg + TALITOS_MDEUISR), | |
502 | in_be32(priv->reg + TALITOS_MDEUISR_LO)); | |
503 | break; | |
504 | case DESC_HDR_SEL1_CRCU: | |
505 | dev_err(dev, "CRCUISR 0x%08x_%08x\n", | |
506 | in_be32(priv->reg + TALITOS_CRCUISR), | |
507 | in_be32(priv->reg + TALITOS_CRCUISR_LO)); | |
508 | break; | |
509 | } | |
510 | ||
511 | for (i = 0; i < 8; i++) | |
512 | dev_err(dev, "DESCBUF 0x%08x_%08x\n", | |
ad42d5fc KP |
513 | in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i), |
514 | in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i)); | |
9c4a7965 KP |
515 | } |
516 | ||
517 | /* | |
518 | * recover from error interrupts | |
519 | */ | |
40405f10 | 520 | static void talitos_error(unsigned long data, u32 isr, u32 isr_lo) |
9c4a7965 KP |
521 | { |
522 | struct device *dev = (struct device *)data; | |
523 | struct talitos_private *priv = dev_get_drvdata(dev); | |
524 | unsigned int timeout = TALITOS_TIMEOUT; | |
525 | int ch, error, reset_dev = 0, reset_ch = 0; | |
40405f10 | 526 | u32 v, v_lo; |
9c4a7965 KP |
527 | |
528 | for (ch = 0; ch < priv->num_channels; ch++) { | |
529 | /* skip channels without errors */ | |
530 | if (!(isr & (1 << (ch * 2 + 1)))) | |
531 | continue; | |
532 | ||
533 | error = -EINVAL; | |
534 | ||
ad42d5fc KP |
535 | v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR); |
536 | v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO); | |
9c4a7965 KP |
537 | |
538 | if (v_lo & TALITOS_CCPSR_LO_DOF) { | |
539 | dev_err(dev, "double fetch fifo overflow error\n"); | |
540 | error = -EAGAIN; | |
541 | reset_ch = 1; | |
542 | } | |
543 | if (v_lo & TALITOS_CCPSR_LO_SOF) { | |
544 | /* h/w dropped descriptor */ | |
545 | dev_err(dev, "single fetch fifo overflow error\n"); | |
546 | error = -EAGAIN; | |
547 | } | |
548 | if (v_lo & TALITOS_CCPSR_LO_MDTE) | |
549 | dev_err(dev, "master data transfer error\n"); | |
550 | if (v_lo & TALITOS_CCPSR_LO_SGDLZ) | |
551 | dev_err(dev, "s/g data length zero error\n"); | |
552 | if (v_lo & TALITOS_CCPSR_LO_FPZ) | |
553 | dev_err(dev, "fetch pointer zero error\n"); | |
554 | if (v_lo & TALITOS_CCPSR_LO_IDH) | |
555 | dev_err(dev, "illegal descriptor header error\n"); | |
556 | if (v_lo & TALITOS_CCPSR_LO_IEU) | |
557 | dev_err(dev, "invalid execution unit error\n"); | |
558 | if (v_lo & TALITOS_CCPSR_LO_EU) | |
3e721aeb | 559 | report_eu_error(dev, ch, current_desc_hdr(dev, ch)); |
9c4a7965 KP |
560 | if (v_lo & TALITOS_CCPSR_LO_GB) |
561 | dev_err(dev, "gather boundary error\n"); | |
562 | if (v_lo & TALITOS_CCPSR_LO_GRL) | |
563 | dev_err(dev, "gather return/length error\n"); | |
564 | if (v_lo & TALITOS_CCPSR_LO_SB) | |
565 | dev_err(dev, "scatter boundary error\n"); | |
566 | if (v_lo & TALITOS_CCPSR_LO_SRL) | |
567 | dev_err(dev, "scatter return/length error\n"); | |
568 | ||
569 | flush_channel(dev, ch, error, reset_ch); | |
570 | ||
571 | if (reset_ch) { | |
572 | reset_channel(dev, ch); | |
573 | } else { | |
ad42d5fc | 574 | setbits32(priv->chan[ch].reg + TALITOS_CCCR, |
9c4a7965 | 575 | TALITOS_CCCR_CONT); |
ad42d5fc KP |
576 | setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0); |
577 | while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & | |
9c4a7965 KP |
578 | TALITOS_CCCR_CONT) && --timeout) |
579 | cpu_relax(); | |
580 | if (timeout == 0) { | |
581 | dev_err(dev, "failed to restart channel %d\n", | |
582 | ch); | |
583 | reset_dev = 1; | |
584 | } | |
585 | } | |
586 | } | |
587 | if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) { | |
588 | dev_err(dev, "done overflow, internal time out, or rngu error: " | |
589 | "ISR 0x%08x_%08x\n", isr, isr_lo); | |
590 | ||
591 | /* purge request queues */ | |
592 | for (ch = 0; ch < priv->num_channels; ch++) | |
593 | flush_channel(dev, ch, -EIO, 1); | |
594 | ||
595 | /* reset and reinitialize the device */ | |
596 | init_device(dev); | |
597 | } | |
598 | } | |
599 | ||
600 | static irqreturn_t talitos_interrupt(int irq, void *data) | |
601 | { | |
602 | struct device *dev = data; | |
603 | struct talitos_private *priv = dev_get_drvdata(dev); | |
604 | u32 isr, isr_lo; | |
605 | ||
606 | isr = in_be32(priv->reg + TALITOS_ISR); | |
607 | isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); | |
ca38a814 LN |
608 | /* Acknowledge interrupt */ |
609 | out_be32(priv->reg + TALITOS_ICR, isr); | |
610 | out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); | |
9c4a7965 | 611 | |
ca38a814 | 612 | if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo)) |
40405f10 | 613 | talitos_error((unsigned long)data, isr, isr_lo); |
ca38a814 | 614 | else |
1c2e8811 LN |
615 | if (likely(isr & TALITOS_ISR_CHDONE)) { |
616 | /* mask further done interrupts. */ | |
617 | clrbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE); | |
618 | /* done_task will unmask done interrupts at exit */ | |
9c4a7965 | 619 | tasklet_schedule(&priv->done_task); |
1c2e8811 | 620 | } |
9c4a7965 KP |
621 | |
622 | return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE; | |
623 | } | |
624 | ||
625 | /* | |
626 | * hwrng | |
627 | */ | |
628 | static int talitos_rng_data_present(struct hwrng *rng, int wait) | |
629 | { | |
630 | struct device *dev = (struct device *)rng->priv; | |
631 | struct talitos_private *priv = dev_get_drvdata(dev); | |
632 | u32 ofl; | |
633 | int i; | |
634 | ||
635 | for (i = 0; i < 20; i++) { | |
636 | ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) & | |
637 | TALITOS_RNGUSR_LO_OFL; | |
638 | if (ofl || !wait) | |
639 | break; | |
640 | udelay(10); | |
641 | } | |
642 | ||
643 | return !!ofl; | |
644 | } | |
645 | ||
646 | static int talitos_rng_data_read(struct hwrng *rng, u32 *data) | |
647 | { | |
648 | struct device *dev = (struct device *)rng->priv; | |
649 | struct talitos_private *priv = dev_get_drvdata(dev); | |
650 | ||
651 | /* rng fifo requires 64-bit accesses */ | |
652 | *data = in_be32(priv->reg + TALITOS_RNGU_FIFO); | |
653 | *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO); | |
654 | ||
655 | return sizeof(u32); | |
656 | } | |
657 | ||
658 | static int talitos_rng_init(struct hwrng *rng) | |
659 | { | |
660 | struct device *dev = (struct device *)rng->priv; | |
661 | struct talitos_private *priv = dev_get_drvdata(dev); | |
662 | unsigned int timeout = TALITOS_TIMEOUT; | |
663 | ||
664 | setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR); | |
665 | while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD) | |
666 | && --timeout) | |
667 | cpu_relax(); | |
668 | if (timeout == 0) { | |
669 | dev_err(dev, "failed to reset rng hw\n"); | |
670 | return -ENODEV; | |
671 | } | |
672 | ||
673 | /* start generating */ | |
674 | setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0); | |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
679 | static int talitos_register_rng(struct device *dev) | |
680 | { | |
681 | struct talitos_private *priv = dev_get_drvdata(dev); | |
682 | ||
683 | priv->rng.name = dev_driver_string(dev), | |
684 | priv->rng.init = talitos_rng_init, | |
685 | priv->rng.data_present = talitos_rng_data_present, | |
686 | priv->rng.data_read = talitos_rng_data_read, | |
687 | priv->rng.priv = (unsigned long)dev; | |
688 | ||
689 | return hwrng_register(&priv->rng); | |
690 | } | |
691 | ||
692 | static void talitos_unregister_rng(struct device *dev) | |
693 | { | |
694 | struct talitos_private *priv = dev_get_drvdata(dev); | |
695 | ||
696 | hwrng_unregister(&priv->rng); | |
697 | } | |
698 | ||
699 | /* | |
700 | * crypto alg | |
701 | */ | |
702 | #define TALITOS_CRA_PRIORITY 3000 | |
703 | #define TALITOS_MAX_KEY_SIZE 64 | |
3952f17e | 704 | #define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */ |
70bcaca7 | 705 | |
497f2e6b | 706 | #define MD5_BLOCK_SIZE 64 |
9c4a7965 KP |
707 | |
708 | struct talitos_ctx { | |
709 | struct device *dev; | |
5228f0f7 | 710 | int ch; |
9c4a7965 KP |
711 | __be32 desc_hdr_template; |
712 | u8 key[TALITOS_MAX_KEY_SIZE]; | |
70bcaca7 | 713 | u8 iv[TALITOS_MAX_IV_LENGTH]; |
9c4a7965 KP |
714 | unsigned int keylen; |
715 | unsigned int enckeylen; | |
716 | unsigned int authkeylen; | |
717 | unsigned int authsize; | |
718 | }; | |
719 | ||
497f2e6b LN |
720 | #define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE |
721 | #define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 | |
722 | ||
723 | struct talitos_ahash_req_ctx { | |
60f208d7 | 724 | u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)]; |
497f2e6b LN |
725 | unsigned int hw_context_size; |
726 | u8 buf[HASH_MAX_BLOCK_SIZE]; | |
727 | u8 bufnext[HASH_MAX_BLOCK_SIZE]; | |
60f208d7 | 728 | unsigned int swinit; |
497f2e6b LN |
729 | unsigned int first; |
730 | unsigned int last; | |
731 | unsigned int to_hash_later; | |
5e833bc4 | 732 | u64 nbuf; |
497f2e6b LN |
733 | struct scatterlist bufsl[2]; |
734 | struct scatterlist *psrc; | |
735 | }; | |
736 | ||
56af8cd4 LN |
737 | static int aead_setauthsize(struct crypto_aead *authenc, |
738 | unsigned int authsize) | |
9c4a7965 KP |
739 | { |
740 | struct talitos_ctx *ctx = crypto_aead_ctx(authenc); | |
741 | ||
742 | ctx->authsize = authsize; | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
56af8cd4 LN |
747 | static int aead_setkey(struct crypto_aead *authenc, |
748 | const u8 *key, unsigned int keylen) | |
9c4a7965 KP |
749 | { |
750 | struct talitos_ctx *ctx = crypto_aead_ctx(authenc); | |
751 | struct rtattr *rta = (void *)key; | |
752 | struct crypto_authenc_key_param *param; | |
753 | unsigned int authkeylen; | |
754 | unsigned int enckeylen; | |
755 | ||
756 | if (!RTA_OK(rta, keylen)) | |
757 | goto badkey; | |
758 | ||
759 | if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM) | |
760 | goto badkey; | |
761 | ||
762 | if (RTA_PAYLOAD(rta) < sizeof(*param)) | |
763 | goto badkey; | |
764 | ||
765 | param = RTA_DATA(rta); | |
766 | enckeylen = be32_to_cpu(param->enckeylen); | |
767 | ||
768 | key += RTA_ALIGN(rta->rta_len); | |
769 | keylen -= RTA_ALIGN(rta->rta_len); | |
770 | ||
771 | if (keylen < enckeylen) | |
772 | goto badkey; | |
773 | ||
774 | authkeylen = keylen - enckeylen; | |
775 | ||
776 | if (keylen > TALITOS_MAX_KEY_SIZE) | |
777 | goto badkey; | |
778 | ||
779 | memcpy(&ctx->key, key, keylen); | |
780 | ||
781 | ctx->keylen = keylen; | |
782 | ctx->enckeylen = enckeylen; | |
783 | ctx->authkeylen = authkeylen; | |
784 | ||
785 | return 0; | |
786 | ||
787 | badkey: | |
788 | crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
789 | return -EINVAL; | |
790 | } | |
791 | ||
792 | /* | |
56af8cd4 | 793 | * talitos_edesc - s/w-extended descriptor |
9c4a7965 KP |
794 | * @src_nents: number of segments in input scatterlist |
795 | * @dst_nents: number of segments in output scatterlist | |
796 | * @dma_len: length of dma mapped link_tbl space | |
797 | * @dma_link_tbl: bus physical address of link_tbl | |
798 | * @desc: h/w descriptor | |
799 | * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1) | |
800 | * | |
801 | * if decrypting (with authcheck), or either one of src_nents or dst_nents | |
802 | * is greater than 1, an integrity check value is concatenated to the end | |
803 | * of link_tbl data | |
804 | */ | |
56af8cd4 | 805 | struct talitos_edesc { |
9c4a7965 KP |
806 | int src_nents; |
807 | int dst_nents; | |
4de9d0b5 LN |
808 | int src_is_chained; |
809 | int dst_is_chained; | |
9c4a7965 KP |
810 | int dma_len; |
811 | dma_addr_t dma_link_tbl; | |
812 | struct talitos_desc desc; | |
813 | struct talitos_ptr link_tbl[0]; | |
814 | }; | |
815 | ||
4de9d0b5 LN |
816 | static int talitos_map_sg(struct device *dev, struct scatterlist *sg, |
817 | unsigned int nents, enum dma_data_direction dir, | |
818 | int chained) | |
819 | { | |
820 | if (unlikely(chained)) | |
821 | while (sg) { | |
822 | dma_map_sg(dev, sg, 1, dir); | |
823 | sg = scatterwalk_sg_next(sg); | |
824 | } | |
825 | else | |
826 | dma_map_sg(dev, sg, nents, dir); | |
827 | return nents; | |
828 | } | |
829 | ||
830 | static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg, | |
831 | enum dma_data_direction dir) | |
832 | { | |
833 | while (sg) { | |
834 | dma_unmap_sg(dev, sg, 1, dir); | |
835 | sg = scatterwalk_sg_next(sg); | |
836 | } | |
837 | } | |
838 | ||
839 | static void talitos_sg_unmap(struct device *dev, | |
840 | struct talitos_edesc *edesc, | |
841 | struct scatterlist *src, | |
842 | struct scatterlist *dst) | |
843 | { | |
844 | unsigned int src_nents = edesc->src_nents ? : 1; | |
845 | unsigned int dst_nents = edesc->dst_nents ? : 1; | |
846 | ||
847 | if (src != dst) { | |
848 | if (edesc->src_is_chained) | |
849 | talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE); | |
850 | else | |
851 | dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE); | |
852 | ||
497f2e6b LN |
853 | if (dst) { |
854 | if (edesc->dst_is_chained) | |
855 | talitos_unmap_sg_chain(dev, dst, | |
856 | DMA_FROM_DEVICE); | |
857 | else | |
858 | dma_unmap_sg(dev, dst, dst_nents, | |
859 | DMA_FROM_DEVICE); | |
860 | } | |
4de9d0b5 LN |
861 | } else |
862 | if (edesc->src_is_chained) | |
863 | talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL); | |
864 | else | |
865 | dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL); | |
866 | } | |
867 | ||
9c4a7965 | 868 | static void ipsec_esp_unmap(struct device *dev, |
56af8cd4 | 869 | struct talitos_edesc *edesc, |
9c4a7965 KP |
870 | struct aead_request *areq) |
871 | { | |
872 | unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE); | |
873 | unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE); | |
874 | unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE); | |
875 | unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE); | |
876 | ||
877 | dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE); | |
878 | ||
4de9d0b5 | 879 | talitos_sg_unmap(dev, edesc, areq->src, areq->dst); |
9c4a7965 KP |
880 | |
881 | if (edesc->dma_len) | |
882 | dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len, | |
883 | DMA_BIDIRECTIONAL); | |
884 | } | |
885 | ||
886 | /* | |
887 | * ipsec_esp descriptor callbacks | |
888 | */ | |
889 | static void ipsec_esp_encrypt_done(struct device *dev, | |
890 | struct talitos_desc *desc, void *context, | |
891 | int err) | |
892 | { | |
893 | struct aead_request *areq = context; | |
9c4a7965 KP |
894 | struct crypto_aead *authenc = crypto_aead_reqtfm(areq); |
895 | struct talitos_ctx *ctx = crypto_aead_ctx(authenc); | |
19bbbc63 | 896 | struct talitos_edesc *edesc; |
9c4a7965 KP |
897 | struct scatterlist *sg; |
898 | void *icvdata; | |
899 | ||
19bbbc63 KP |
900 | edesc = container_of(desc, struct talitos_edesc, desc); |
901 | ||
9c4a7965 KP |
902 | ipsec_esp_unmap(dev, edesc, areq); |
903 | ||
904 | /* copy the generated ICV to dst */ | |
905 | if (edesc->dma_len) { | |
906 | icvdata = &edesc->link_tbl[edesc->src_nents + | |
f3c85bc1 | 907 | edesc->dst_nents + 2]; |
9c4a7965 KP |
908 | sg = sg_last(areq->dst, edesc->dst_nents); |
909 | memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize, | |
910 | icvdata, ctx->authsize); | |
911 | } | |
912 | ||
913 | kfree(edesc); | |
914 | ||
915 | aead_request_complete(areq, err); | |
916 | } | |
917 | ||
fe5720e2 | 918 | static void ipsec_esp_decrypt_swauth_done(struct device *dev, |
e938e465 KP |
919 | struct talitos_desc *desc, |
920 | void *context, int err) | |
9c4a7965 KP |
921 | { |
922 | struct aead_request *req = context; | |
9c4a7965 KP |
923 | struct crypto_aead *authenc = crypto_aead_reqtfm(req); |
924 | struct talitos_ctx *ctx = crypto_aead_ctx(authenc); | |
19bbbc63 | 925 | struct talitos_edesc *edesc; |
9c4a7965 KP |
926 | struct scatterlist *sg; |
927 | void *icvdata; | |
928 | ||
19bbbc63 KP |
929 | edesc = container_of(desc, struct talitos_edesc, desc); |
930 | ||
9c4a7965 KP |
931 | ipsec_esp_unmap(dev, edesc, req); |
932 | ||
933 | if (!err) { | |
934 | /* auth check */ | |
935 | if (edesc->dma_len) | |
936 | icvdata = &edesc->link_tbl[edesc->src_nents + | |
f3c85bc1 | 937 | edesc->dst_nents + 2]; |
9c4a7965 KP |
938 | else |
939 | icvdata = &edesc->link_tbl[0]; | |
940 | ||
941 | sg = sg_last(req->dst, edesc->dst_nents ? : 1); | |
942 | err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length - | |
943 | ctx->authsize, ctx->authsize) ? -EBADMSG : 0; | |
944 | } | |
945 | ||
946 | kfree(edesc); | |
947 | ||
948 | aead_request_complete(req, err); | |
949 | } | |
950 | ||
fe5720e2 | 951 | static void ipsec_esp_decrypt_hwauth_done(struct device *dev, |
e938e465 KP |
952 | struct talitos_desc *desc, |
953 | void *context, int err) | |
fe5720e2 KP |
954 | { |
955 | struct aead_request *req = context; | |
19bbbc63 KP |
956 | struct talitos_edesc *edesc; |
957 | ||
958 | edesc = container_of(desc, struct talitos_edesc, desc); | |
fe5720e2 KP |
959 | |
960 | ipsec_esp_unmap(dev, edesc, req); | |
961 | ||
962 | /* check ICV auth status */ | |
e938e465 KP |
963 | if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) != |
964 | DESC_HDR_LO_ICCR1_PASS)) | |
965 | err = -EBADMSG; | |
fe5720e2 KP |
966 | |
967 | kfree(edesc); | |
968 | ||
969 | aead_request_complete(req, err); | |
970 | } | |
971 | ||
9c4a7965 KP |
972 | /* |
973 | * convert scatterlist to SEC h/w link table format | |
974 | * stop at cryptlen bytes | |
975 | */ | |
70bcaca7 | 976 | static int sg_to_link_tbl(struct scatterlist *sg, int sg_count, |
9c4a7965 KP |
977 | int cryptlen, struct talitos_ptr *link_tbl_ptr) |
978 | { | |
70bcaca7 LN |
979 | int n_sg = sg_count; |
980 | ||
981 | while (n_sg--) { | |
81eb024c | 982 | to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg)); |
9c4a7965 KP |
983 | link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg)); |
984 | link_tbl_ptr->j_extent = 0; | |
985 | link_tbl_ptr++; | |
986 | cryptlen -= sg_dma_len(sg); | |
4de9d0b5 | 987 | sg = scatterwalk_sg_next(sg); |
9c4a7965 KP |
988 | } |
989 | ||
70bcaca7 | 990 | /* adjust (decrease) last one (or two) entry's len to cryptlen */ |
9c4a7965 | 991 | link_tbl_ptr--; |
c0e741d4 | 992 | while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) { |
70bcaca7 LN |
993 | /* Empty this entry, and move to previous one */ |
994 | cryptlen += be16_to_cpu(link_tbl_ptr->len); | |
995 | link_tbl_ptr->len = 0; | |
996 | sg_count--; | |
997 | link_tbl_ptr--; | |
998 | } | |
9c4a7965 KP |
999 | link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len) |
1000 | + cryptlen); | |
1001 | ||
1002 | /* tag end of link table */ | |
1003 | link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN; | |
70bcaca7 LN |
1004 | |
1005 | return sg_count; | |
9c4a7965 KP |
1006 | } |
1007 | ||
1008 | /* | |
1009 | * fill in and submit ipsec_esp descriptor | |
1010 | */ | |
56af8cd4 | 1011 | static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq, |
9c4a7965 KP |
1012 | u8 *giv, u64 seq, |
1013 | void (*callback) (struct device *dev, | |
1014 | struct talitos_desc *desc, | |
1015 | void *context, int error)) | |
1016 | { | |
1017 | struct crypto_aead *aead = crypto_aead_reqtfm(areq); | |
1018 | struct talitos_ctx *ctx = crypto_aead_ctx(aead); | |
1019 | struct device *dev = ctx->dev; | |
1020 | struct talitos_desc *desc = &edesc->desc; | |
1021 | unsigned int cryptlen = areq->cryptlen; | |
1022 | unsigned int authsize = ctx->authsize; | |
e41256f1 | 1023 | unsigned int ivsize = crypto_aead_ivsize(aead); |
fa86a267 | 1024 | int sg_count, ret; |
fe5720e2 | 1025 | int sg_link_tbl_len; |
9c4a7965 KP |
1026 | |
1027 | /* hmac key */ | |
1028 | map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key, | |
1029 | 0, DMA_TO_DEVICE); | |
1030 | /* hmac data */ | |
e41256f1 KP |
1031 | map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize, |
1032 | sg_virt(areq->assoc), 0, DMA_TO_DEVICE); | |
9c4a7965 | 1033 | /* cipher iv */ |
9c4a7965 KP |
1034 | map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0, |
1035 | DMA_TO_DEVICE); | |
1036 | ||
1037 | /* cipher key */ | |
1038 | map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen, | |
1039 | (char *)&ctx->key + ctx->authkeylen, 0, | |
1040 | DMA_TO_DEVICE); | |
1041 | ||
1042 | /* | |
1043 | * cipher in | |
1044 | * map and adjust cipher len to aead request cryptlen. | |
1045 | * extent is bytes of HMAC postpended to ciphertext, | |
1046 | * typically 12 for ipsec | |
1047 | */ | |
1048 | desc->ptr[4].len = cpu_to_be16(cryptlen); | |
1049 | desc->ptr[4].j_extent = authsize; | |
1050 | ||
e938e465 KP |
1051 | sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1, |
1052 | (areq->src == areq->dst) ? DMA_BIDIRECTIONAL | |
1053 | : DMA_TO_DEVICE, | |
4de9d0b5 | 1054 | edesc->src_is_chained); |
9c4a7965 KP |
1055 | |
1056 | if (sg_count == 1) { | |
81eb024c | 1057 | to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src)); |
9c4a7965 | 1058 | } else { |
fe5720e2 KP |
1059 | sg_link_tbl_len = cryptlen; |
1060 | ||
962a9c99 | 1061 | if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV) |
fe5720e2 | 1062 | sg_link_tbl_len = cryptlen + authsize; |
e938e465 | 1063 | |
fe5720e2 | 1064 | sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len, |
70bcaca7 LN |
1065 | &edesc->link_tbl[0]); |
1066 | if (sg_count > 1) { | |
1067 | desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP; | |
81eb024c | 1068 | to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl); |
e938e465 KP |
1069 | dma_sync_single_for_device(dev, edesc->dma_link_tbl, |
1070 | edesc->dma_len, | |
1071 | DMA_BIDIRECTIONAL); | |
70bcaca7 LN |
1072 | } else { |
1073 | /* Only one segment now, so no link tbl needed */ | |
81eb024c KP |
1074 | to_talitos_ptr(&desc->ptr[4], |
1075 | sg_dma_address(areq->src)); | |
70bcaca7 | 1076 | } |
9c4a7965 KP |
1077 | } |
1078 | ||
1079 | /* cipher out */ | |
1080 | desc->ptr[5].len = cpu_to_be16(cryptlen); | |
1081 | desc->ptr[5].j_extent = authsize; | |
1082 | ||
e938e465 | 1083 | if (areq->src != areq->dst) |
4de9d0b5 LN |
1084 | sg_count = talitos_map_sg(dev, areq->dst, |
1085 | edesc->dst_nents ? : 1, | |
1086 | DMA_FROM_DEVICE, | |
1087 | edesc->dst_is_chained); | |
9c4a7965 KP |
1088 | |
1089 | if (sg_count == 1) { | |
81eb024c | 1090 | to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst)); |
9c4a7965 KP |
1091 | } else { |
1092 | struct talitos_ptr *link_tbl_ptr = | |
f3c85bc1 | 1093 | &edesc->link_tbl[edesc->src_nents + 1]; |
9c4a7965 | 1094 | |
81eb024c KP |
1095 | to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl + |
1096 | (edesc->src_nents + 1) * | |
1097 | sizeof(struct talitos_ptr)); | |
fe5720e2 KP |
1098 | sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen, |
1099 | link_tbl_ptr); | |
1100 | ||
f3c85bc1 | 1101 | /* Add an entry to the link table for ICV data */ |
9c4a7965 | 1102 | link_tbl_ptr += sg_count - 1; |
9c4a7965 | 1103 | link_tbl_ptr->j_extent = 0; |
f3c85bc1 | 1104 | sg_count++; |
9c4a7965 KP |
1105 | link_tbl_ptr++; |
1106 | link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN; | |
1107 | link_tbl_ptr->len = cpu_to_be16(authsize); | |
1108 | ||
1109 | /* icv data follows link tables */ | |
81eb024c KP |
1110 | to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl + |
1111 | (edesc->src_nents + edesc->dst_nents + 2) * | |
1112 | sizeof(struct talitos_ptr)); | |
9c4a7965 KP |
1113 | desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP; |
1114 | dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl, | |
1115 | edesc->dma_len, DMA_BIDIRECTIONAL); | |
1116 | } | |
1117 | ||
1118 | /* iv out */ | |
1119 | map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0, | |
1120 | DMA_FROM_DEVICE); | |
1121 | ||
5228f0f7 | 1122 | ret = talitos_submit(dev, ctx->ch, desc, callback, areq); |
fa86a267 KP |
1123 | if (ret != -EINPROGRESS) { |
1124 | ipsec_esp_unmap(dev, edesc, areq); | |
1125 | kfree(edesc); | |
1126 | } | |
1127 | return ret; | |
9c4a7965 KP |
1128 | } |
1129 | ||
9c4a7965 KP |
1130 | /* |
1131 | * derive number of elements in scatterlist | |
1132 | */ | |
4de9d0b5 | 1133 | static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained) |
9c4a7965 KP |
1134 | { |
1135 | struct scatterlist *sg = sg_list; | |
1136 | int sg_nents = 0; | |
1137 | ||
4de9d0b5 LN |
1138 | *chained = 0; |
1139 | while (nbytes > 0) { | |
9c4a7965 KP |
1140 | sg_nents++; |
1141 | nbytes -= sg->length; | |
4de9d0b5 LN |
1142 | if (!sg_is_last(sg) && (sg + 1)->length == 0) |
1143 | *chained = 1; | |
1144 | sg = scatterwalk_sg_next(sg); | |
9c4a7965 KP |
1145 | } |
1146 | ||
1147 | return sg_nents; | |
1148 | } | |
1149 | ||
497f2e6b LN |
1150 | /** |
1151 | * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer | |
1152 | * @sgl: The SG list | |
1153 | * @nents: Number of SG entries | |
1154 | * @buf: Where to copy to | |
1155 | * @buflen: The number of bytes to copy | |
1156 | * @skip: The number of bytes to skip before copying. | |
1157 | * Note: skip + buflen should equal SG total size. | |
1158 | * | |
1159 | * Returns the number of copied bytes. | |
1160 | * | |
1161 | **/ | |
1162 | static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents, | |
1163 | void *buf, size_t buflen, unsigned int skip) | |
1164 | { | |
1165 | unsigned int offset = 0; | |
1166 | unsigned int boffset = 0; | |
1167 | struct sg_mapping_iter miter; | |
1168 | unsigned long flags; | |
1169 | unsigned int sg_flags = SG_MITER_ATOMIC; | |
1170 | size_t total_buffer = buflen + skip; | |
1171 | ||
1172 | sg_flags |= SG_MITER_FROM_SG; | |
1173 | ||
1174 | sg_miter_start(&miter, sgl, nents, sg_flags); | |
1175 | ||
1176 | local_irq_save(flags); | |
1177 | ||
1178 | while (sg_miter_next(&miter) && offset < total_buffer) { | |
1179 | unsigned int len; | |
1180 | unsigned int ignore; | |
1181 | ||
1182 | if ((offset + miter.length) > skip) { | |
1183 | if (offset < skip) { | |
1184 | /* Copy part of this segment */ | |
1185 | ignore = skip - offset; | |
1186 | len = miter.length - ignore; | |
7260042b LN |
1187 | if (boffset + len > buflen) |
1188 | len = buflen - boffset; | |
497f2e6b LN |
1189 | memcpy(buf + boffset, miter.addr + ignore, len); |
1190 | } else { | |
7260042b | 1191 | /* Copy all of this segment (up to buflen) */ |
497f2e6b | 1192 | len = miter.length; |
7260042b LN |
1193 | if (boffset + len > buflen) |
1194 | len = buflen - boffset; | |
497f2e6b LN |
1195 | memcpy(buf + boffset, miter.addr, len); |
1196 | } | |
1197 | boffset += len; | |
1198 | } | |
1199 | offset += miter.length; | |
1200 | } | |
1201 | ||
1202 | sg_miter_stop(&miter); | |
1203 | ||
1204 | local_irq_restore(flags); | |
1205 | return boffset; | |
1206 | } | |
1207 | ||
9c4a7965 | 1208 | /* |
56af8cd4 | 1209 | * allocate and map the extended descriptor |
9c4a7965 | 1210 | */ |
4de9d0b5 LN |
1211 | static struct talitos_edesc *talitos_edesc_alloc(struct device *dev, |
1212 | struct scatterlist *src, | |
1213 | struct scatterlist *dst, | |
497f2e6b | 1214 | int hash_result, |
4de9d0b5 LN |
1215 | unsigned int cryptlen, |
1216 | unsigned int authsize, | |
1217 | int icv_stashing, | |
1218 | u32 cryptoflags) | |
9c4a7965 | 1219 | { |
56af8cd4 | 1220 | struct talitos_edesc *edesc; |
9c4a7965 | 1221 | int src_nents, dst_nents, alloc_len, dma_len; |
4de9d0b5 LN |
1222 | int src_chained, dst_chained = 0; |
1223 | gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : | |
586725f8 | 1224 | GFP_ATOMIC; |
9c4a7965 | 1225 | |
4de9d0b5 LN |
1226 | if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) { |
1227 | dev_err(dev, "length exceeds h/w max limit\n"); | |
9c4a7965 KP |
1228 | return ERR_PTR(-EINVAL); |
1229 | } | |
1230 | ||
4de9d0b5 | 1231 | src_nents = sg_count(src, cryptlen + authsize, &src_chained); |
9c4a7965 KP |
1232 | src_nents = (src_nents == 1) ? 0 : src_nents; |
1233 | ||
497f2e6b LN |
1234 | if (hash_result) { |
1235 | dst_nents = 0; | |
9c4a7965 | 1236 | } else { |
497f2e6b LN |
1237 | if (dst == src) { |
1238 | dst_nents = src_nents; | |
1239 | } else { | |
1240 | dst_nents = sg_count(dst, cryptlen + authsize, | |
1241 | &dst_chained); | |
1242 | dst_nents = (dst_nents == 1) ? 0 : dst_nents; | |
1243 | } | |
9c4a7965 KP |
1244 | } |
1245 | ||
1246 | /* | |
1247 | * allocate space for base edesc plus the link tables, | |
f3c85bc1 | 1248 | * allowing for two separate entries for ICV and generated ICV (+ 2), |
9c4a7965 KP |
1249 | * and the ICV data itself |
1250 | */ | |
56af8cd4 | 1251 | alloc_len = sizeof(struct talitos_edesc); |
9c4a7965 | 1252 | if (src_nents || dst_nents) { |
f3c85bc1 | 1253 | dma_len = (src_nents + dst_nents + 2) * |
4de9d0b5 | 1254 | sizeof(struct talitos_ptr) + authsize; |
9c4a7965 KP |
1255 | alloc_len += dma_len; |
1256 | } else { | |
1257 | dma_len = 0; | |
4de9d0b5 | 1258 | alloc_len += icv_stashing ? authsize : 0; |
9c4a7965 KP |
1259 | } |
1260 | ||
586725f8 | 1261 | edesc = kmalloc(alloc_len, GFP_DMA | flags); |
9c4a7965 | 1262 | if (!edesc) { |
4de9d0b5 | 1263 | dev_err(dev, "could not allocate edescriptor\n"); |
9c4a7965 KP |
1264 | return ERR_PTR(-ENOMEM); |
1265 | } | |
1266 | ||
1267 | edesc->src_nents = src_nents; | |
1268 | edesc->dst_nents = dst_nents; | |
4de9d0b5 LN |
1269 | edesc->src_is_chained = src_chained; |
1270 | edesc->dst_is_chained = dst_chained; | |
9c4a7965 | 1271 | edesc->dma_len = dma_len; |
497f2e6b LN |
1272 | if (dma_len) |
1273 | edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0], | |
1274 | edesc->dma_len, | |
1275 | DMA_BIDIRECTIONAL); | |
9c4a7965 KP |
1276 | |
1277 | return edesc; | |
1278 | } | |
1279 | ||
4de9d0b5 LN |
1280 | static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, |
1281 | int icv_stashing) | |
1282 | { | |
1283 | struct crypto_aead *authenc = crypto_aead_reqtfm(areq); | |
1284 | struct talitos_ctx *ctx = crypto_aead_ctx(authenc); | |
1285 | ||
497f2e6b | 1286 | return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0, |
4de9d0b5 LN |
1287 | areq->cryptlen, ctx->authsize, icv_stashing, |
1288 | areq->base.flags); | |
1289 | } | |
1290 | ||
56af8cd4 | 1291 | static int aead_encrypt(struct aead_request *req) |
9c4a7965 KP |
1292 | { |
1293 | struct crypto_aead *authenc = crypto_aead_reqtfm(req); | |
1294 | struct talitos_ctx *ctx = crypto_aead_ctx(authenc); | |
56af8cd4 | 1295 | struct talitos_edesc *edesc; |
9c4a7965 KP |
1296 | |
1297 | /* allocate extended descriptor */ | |
4de9d0b5 | 1298 | edesc = aead_edesc_alloc(req, 0); |
9c4a7965 KP |
1299 | if (IS_ERR(edesc)) |
1300 | return PTR_ERR(edesc); | |
1301 | ||
1302 | /* set encrypt */ | |
70bcaca7 | 1303 | edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT; |
9c4a7965 KP |
1304 | |
1305 | return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done); | |
1306 | } | |
1307 | ||
56af8cd4 | 1308 | static int aead_decrypt(struct aead_request *req) |
9c4a7965 KP |
1309 | { |
1310 | struct crypto_aead *authenc = crypto_aead_reqtfm(req); | |
1311 | struct talitos_ctx *ctx = crypto_aead_ctx(authenc); | |
1312 | unsigned int authsize = ctx->authsize; | |
fe5720e2 | 1313 | struct talitos_private *priv = dev_get_drvdata(ctx->dev); |
56af8cd4 | 1314 | struct talitos_edesc *edesc; |
9c4a7965 KP |
1315 | struct scatterlist *sg; |
1316 | void *icvdata; | |
1317 | ||
1318 | req->cryptlen -= authsize; | |
1319 | ||
1320 | /* allocate extended descriptor */ | |
4de9d0b5 | 1321 | edesc = aead_edesc_alloc(req, 1); |
9c4a7965 KP |
1322 | if (IS_ERR(edesc)) |
1323 | return PTR_ERR(edesc); | |
1324 | ||
fe5720e2 | 1325 | if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) && |
e938e465 KP |
1326 | ((!edesc->src_nents && !edesc->dst_nents) || |
1327 | priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) { | |
9c4a7965 | 1328 | |
fe5720e2 | 1329 | /* decrypt and check the ICV */ |
e938e465 KP |
1330 | edesc->desc.hdr = ctx->desc_hdr_template | |
1331 | DESC_HDR_DIR_INBOUND | | |
fe5720e2 | 1332 | DESC_HDR_MODE1_MDEU_CICV; |
9c4a7965 | 1333 | |
fe5720e2 KP |
1334 | /* reset integrity check result bits */ |
1335 | edesc->desc.hdr_lo = 0; | |
9c4a7965 | 1336 | |
e938e465 KP |
1337 | return ipsec_esp(edesc, req, NULL, 0, |
1338 | ipsec_esp_decrypt_hwauth_done); | |
fe5720e2 | 1339 | |
e938e465 | 1340 | } |
fe5720e2 | 1341 | |
e938e465 KP |
1342 | /* Have to check the ICV with software */ |
1343 | edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND; | |
fe5720e2 | 1344 | |
e938e465 KP |
1345 | /* stash incoming ICV for later cmp with ICV generated by the h/w */ |
1346 | if (edesc->dma_len) | |
1347 | icvdata = &edesc->link_tbl[edesc->src_nents + | |
1348 | edesc->dst_nents + 2]; | |
1349 | else | |
1350 | icvdata = &edesc->link_tbl[0]; | |
fe5720e2 | 1351 | |
e938e465 | 1352 | sg = sg_last(req->src, edesc->src_nents ? : 1); |
fe5720e2 | 1353 | |
e938e465 KP |
1354 | memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize, |
1355 | ctx->authsize); | |
fe5720e2 | 1356 | |
e938e465 | 1357 | return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done); |
9c4a7965 KP |
1358 | } |
1359 | ||
56af8cd4 | 1360 | static int aead_givencrypt(struct aead_givcrypt_request *req) |
9c4a7965 KP |
1361 | { |
1362 | struct aead_request *areq = &req->areq; | |
1363 | struct crypto_aead *authenc = crypto_aead_reqtfm(areq); | |
1364 | struct talitos_ctx *ctx = crypto_aead_ctx(authenc); | |
56af8cd4 | 1365 | struct talitos_edesc *edesc; |
9c4a7965 KP |
1366 | |
1367 | /* allocate extended descriptor */ | |
4de9d0b5 | 1368 | edesc = aead_edesc_alloc(areq, 0); |
9c4a7965 KP |
1369 | if (IS_ERR(edesc)) |
1370 | return PTR_ERR(edesc); | |
1371 | ||
1372 | /* set encrypt */ | |
70bcaca7 | 1373 | edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT; |
9c4a7965 KP |
1374 | |
1375 | memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc)); | |
ba95487d KP |
1376 | /* avoid consecutive packets going out with same IV */ |
1377 | *(__be64 *)req->giv ^= cpu_to_be64(req->seq); | |
9c4a7965 KP |
1378 | |
1379 | return ipsec_esp(edesc, areq, req->giv, req->seq, | |
1380 | ipsec_esp_encrypt_done); | |
1381 | } | |
1382 | ||
4de9d0b5 LN |
1383 | static int ablkcipher_setkey(struct crypto_ablkcipher *cipher, |
1384 | const u8 *key, unsigned int keylen) | |
1385 | { | |
1386 | struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher); | |
4de9d0b5 LN |
1387 | |
1388 | memcpy(&ctx->key, key, keylen); | |
1389 | ctx->keylen = keylen; | |
1390 | ||
1391 | return 0; | |
4de9d0b5 LN |
1392 | } |
1393 | ||
1394 | static void common_nonsnoop_unmap(struct device *dev, | |
1395 | struct talitos_edesc *edesc, | |
1396 | struct ablkcipher_request *areq) | |
1397 | { | |
1398 | unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE); | |
1399 | unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE); | |
1400 | unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE); | |
1401 | ||
1402 | talitos_sg_unmap(dev, edesc, areq->src, areq->dst); | |
1403 | ||
1404 | if (edesc->dma_len) | |
1405 | dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len, | |
1406 | DMA_BIDIRECTIONAL); | |
1407 | } | |
1408 | ||
1409 | static void ablkcipher_done(struct device *dev, | |
1410 | struct talitos_desc *desc, void *context, | |
1411 | int err) | |
1412 | { | |
1413 | struct ablkcipher_request *areq = context; | |
19bbbc63 KP |
1414 | struct talitos_edesc *edesc; |
1415 | ||
1416 | edesc = container_of(desc, struct talitos_edesc, desc); | |
4de9d0b5 LN |
1417 | |
1418 | common_nonsnoop_unmap(dev, edesc, areq); | |
1419 | ||
1420 | kfree(edesc); | |
1421 | ||
1422 | areq->base.complete(&areq->base, err); | |
1423 | } | |
1424 | ||
1425 | static int common_nonsnoop(struct talitos_edesc *edesc, | |
1426 | struct ablkcipher_request *areq, | |
4de9d0b5 LN |
1427 | void (*callback) (struct device *dev, |
1428 | struct talitos_desc *desc, | |
1429 | void *context, int error)) | |
1430 | { | |
1431 | struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq); | |
1432 | struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher); | |
1433 | struct device *dev = ctx->dev; | |
1434 | struct talitos_desc *desc = &edesc->desc; | |
1435 | unsigned int cryptlen = areq->nbytes; | |
1436 | unsigned int ivsize; | |
1437 | int sg_count, ret; | |
1438 | ||
1439 | /* first DWORD empty */ | |
1440 | desc->ptr[0].len = 0; | |
81eb024c | 1441 | to_talitos_ptr(&desc->ptr[0], 0); |
4de9d0b5 LN |
1442 | desc->ptr[0].j_extent = 0; |
1443 | ||
1444 | /* cipher iv */ | |
1445 | ivsize = crypto_ablkcipher_ivsize(cipher); | |
febec542 | 1446 | map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, areq->info, 0, |
4de9d0b5 LN |
1447 | DMA_TO_DEVICE); |
1448 | ||
1449 | /* cipher key */ | |
1450 | map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen, | |
1451 | (char *)&ctx->key, 0, DMA_TO_DEVICE); | |
1452 | ||
1453 | /* | |
1454 | * cipher in | |
1455 | */ | |
1456 | desc->ptr[3].len = cpu_to_be16(cryptlen); | |
1457 | desc->ptr[3].j_extent = 0; | |
1458 | ||
1459 | sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1, | |
1460 | (areq->src == areq->dst) ? DMA_BIDIRECTIONAL | |
1461 | : DMA_TO_DEVICE, | |
1462 | edesc->src_is_chained); | |
1463 | ||
1464 | if (sg_count == 1) { | |
81eb024c | 1465 | to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src)); |
4de9d0b5 LN |
1466 | } else { |
1467 | sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen, | |
1468 | &edesc->link_tbl[0]); | |
1469 | if (sg_count > 1) { | |
81eb024c | 1470 | to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl); |
4de9d0b5 | 1471 | desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP; |
e938e465 KP |
1472 | dma_sync_single_for_device(dev, edesc->dma_link_tbl, |
1473 | edesc->dma_len, | |
1474 | DMA_BIDIRECTIONAL); | |
4de9d0b5 LN |
1475 | } else { |
1476 | /* Only one segment now, so no link tbl needed */ | |
81eb024c KP |
1477 | to_talitos_ptr(&desc->ptr[3], |
1478 | sg_dma_address(areq->src)); | |
4de9d0b5 LN |
1479 | } |
1480 | } | |
1481 | ||
1482 | /* cipher out */ | |
1483 | desc->ptr[4].len = cpu_to_be16(cryptlen); | |
1484 | desc->ptr[4].j_extent = 0; | |
1485 | ||
1486 | if (areq->src != areq->dst) | |
1487 | sg_count = talitos_map_sg(dev, areq->dst, | |
1488 | edesc->dst_nents ? : 1, | |
1489 | DMA_FROM_DEVICE, | |
1490 | edesc->dst_is_chained); | |
1491 | ||
1492 | if (sg_count == 1) { | |
81eb024c | 1493 | to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst)); |
4de9d0b5 LN |
1494 | } else { |
1495 | struct talitos_ptr *link_tbl_ptr = | |
1496 | &edesc->link_tbl[edesc->src_nents + 1]; | |
1497 | ||
81eb024c KP |
1498 | to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl + |
1499 | (edesc->src_nents + 1) * | |
1500 | sizeof(struct talitos_ptr)); | |
4de9d0b5 | 1501 | desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP; |
4de9d0b5 LN |
1502 | sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen, |
1503 | link_tbl_ptr); | |
1504 | dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl, | |
1505 | edesc->dma_len, DMA_BIDIRECTIONAL); | |
1506 | } | |
1507 | ||
1508 | /* iv out */ | |
1509 | map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0, | |
1510 | DMA_FROM_DEVICE); | |
1511 | ||
1512 | /* last DWORD empty */ | |
1513 | desc->ptr[6].len = 0; | |
81eb024c | 1514 | to_talitos_ptr(&desc->ptr[6], 0); |
4de9d0b5 LN |
1515 | desc->ptr[6].j_extent = 0; |
1516 | ||
5228f0f7 | 1517 | ret = talitos_submit(dev, ctx->ch, desc, callback, areq); |
4de9d0b5 LN |
1518 | if (ret != -EINPROGRESS) { |
1519 | common_nonsnoop_unmap(dev, edesc, areq); | |
1520 | kfree(edesc); | |
1521 | } | |
1522 | return ret; | |
1523 | } | |
1524 | ||
e938e465 KP |
1525 | static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request * |
1526 | areq) | |
4de9d0b5 LN |
1527 | { |
1528 | struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq); | |
1529 | struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher); | |
1530 | ||
497f2e6b LN |
1531 | return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0, |
1532 | areq->nbytes, 0, 0, areq->base.flags); | |
4de9d0b5 LN |
1533 | } |
1534 | ||
1535 | static int ablkcipher_encrypt(struct ablkcipher_request *areq) | |
1536 | { | |
1537 | struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq); | |
1538 | struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher); | |
1539 | struct talitos_edesc *edesc; | |
1540 | ||
1541 | /* allocate extended descriptor */ | |
1542 | edesc = ablkcipher_edesc_alloc(areq); | |
1543 | if (IS_ERR(edesc)) | |
1544 | return PTR_ERR(edesc); | |
1545 | ||
1546 | /* set encrypt */ | |
1547 | edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT; | |
1548 | ||
febec542 | 1549 | return common_nonsnoop(edesc, areq, ablkcipher_done); |
4de9d0b5 LN |
1550 | } |
1551 | ||
1552 | static int ablkcipher_decrypt(struct ablkcipher_request *areq) | |
1553 | { | |
1554 | struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq); | |
1555 | struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher); | |
1556 | struct talitos_edesc *edesc; | |
1557 | ||
1558 | /* allocate extended descriptor */ | |
1559 | edesc = ablkcipher_edesc_alloc(areq); | |
1560 | if (IS_ERR(edesc)) | |
1561 | return PTR_ERR(edesc); | |
1562 | ||
1563 | edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND; | |
1564 | ||
febec542 | 1565 | return common_nonsnoop(edesc, areq, ablkcipher_done); |
4de9d0b5 LN |
1566 | } |
1567 | ||
497f2e6b LN |
1568 | static void common_nonsnoop_hash_unmap(struct device *dev, |
1569 | struct talitos_edesc *edesc, | |
1570 | struct ahash_request *areq) | |
1571 | { | |
1572 | struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); | |
1573 | ||
1574 | unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE); | |
1575 | ||
1576 | /* When using hashctx-in, must unmap it. */ | |
1577 | if (edesc->desc.ptr[1].len) | |
1578 | unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], | |
1579 | DMA_TO_DEVICE); | |
1580 | ||
1581 | if (edesc->desc.ptr[2].len) | |
1582 | unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], | |
1583 | DMA_TO_DEVICE); | |
1584 | ||
1585 | talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL); | |
1586 | ||
1587 | if (edesc->dma_len) | |
1588 | dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len, | |
1589 | DMA_BIDIRECTIONAL); | |
1590 | ||
1591 | } | |
1592 | ||
1593 | static void ahash_done(struct device *dev, | |
1594 | struct talitos_desc *desc, void *context, | |
1595 | int err) | |
1596 | { | |
1597 | struct ahash_request *areq = context; | |
1598 | struct talitos_edesc *edesc = | |
1599 | container_of(desc, struct talitos_edesc, desc); | |
1600 | struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); | |
1601 | ||
1602 | if (!req_ctx->last && req_ctx->to_hash_later) { | |
1603 | /* Position any partial block for next update/final/finup */ | |
1604 | memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later); | |
5e833bc4 | 1605 | req_ctx->nbuf = req_ctx->to_hash_later; |
497f2e6b LN |
1606 | } |
1607 | common_nonsnoop_hash_unmap(dev, edesc, areq); | |
1608 | ||
1609 | kfree(edesc); | |
1610 | ||
1611 | areq->base.complete(&areq->base, err); | |
1612 | } | |
1613 | ||
1614 | static int common_nonsnoop_hash(struct talitos_edesc *edesc, | |
1615 | struct ahash_request *areq, unsigned int length, | |
1616 | void (*callback) (struct device *dev, | |
1617 | struct talitos_desc *desc, | |
1618 | void *context, int error)) | |
1619 | { | |
1620 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); | |
1621 | struct talitos_ctx *ctx = crypto_ahash_ctx(tfm); | |
1622 | struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); | |
1623 | struct device *dev = ctx->dev; | |
1624 | struct talitos_desc *desc = &edesc->desc; | |
1625 | int sg_count, ret; | |
1626 | ||
1627 | /* first DWORD empty */ | |
1628 | desc->ptr[0] = zero_entry; | |
1629 | ||
60f208d7 KP |
1630 | /* hash context in */ |
1631 | if (!req_ctx->first || req_ctx->swinit) { | |
497f2e6b LN |
1632 | map_single_talitos_ptr(dev, &desc->ptr[1], |
1633 | req_ctx->hw_context_size, | |
1634 | (char *)req_ctx->hw_context, 0, | |
1635 | DMA_TO_DEVICE); | |
60f208d7 | 1636 | req_ctx->swinit = 0; |
497f2e6b LN |
1637 | } else { |
1638 | desc->ptr[1] = zero_entry; | |
1639 | /* Indicate next op is not the first. */ | |
1640 | req_ctx->first = 0; | |
1641 | } | |
1642 | ||
1643 | /* HMAC key */ | |
1644 | if (ctx->keylen) | |
1645 | map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen, | |
1646 | (char *)&ctx->key, 0, DMA_TO_DEVICE); | |
1647 | else | |
1648 | desc->ptr[2] = zero_entry; | |
1649 | ||
1650 | /* | |
1651 | * data in | |
1652 | */ | |
1653 | desc->ptr[3].len = cpu_to_be16(length); | |
1654 | desc->ptr[3].j_extent = 0; | |
1655 | ||
1656 | sg_count = talitos_map_sg(dev, req_ctx->psrc, | |
1657 | edesc->src_nents ? : 1, | |
1658 | DMA_TO_DEVICE, | |
1659 | edesc->src_is_chained); | |
1660 | ||
1661 | if (sg_count == 1) { | |
1662 | to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc)); | |
1663 | } else { | |
1664 | sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length, | |
1665 | &edesc->link_tbl[0]); | |
1666 | if (sg_count > 1) { | |
1667 | desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP; | |
1668 | to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl); | |
1669 | dma_sync_single_for_device(ctx->dev, | |
1670 | edesc->dma_link_tbl, | |
1671 | edesc->dma_len, | |
1672 | DMA_BIDIRECTIONAL); | |
1673 | } else { | |
1674 | /* Only one segment now, so no link tbl needed */ | |
1675 | to_talitos_ptr(&desc->ptr[3], | |
1676 | sg_dma_address(req_ctx->psrc)); | |
1677 | } | |
1678 | } | |
1679 | ||
1680 | /* fifth DWORD empty */ | |
1681 | desc->ptr[4] = zero_entry; | |
1682 | ||
1683 | /* hash/HMAC out -or- hash context out */ | |
1684 | if (req_ctx->last) | |
1685 | map_single_talitos_ptr(dev, &desc->ptr[5], | |
1686 | crypto_ahash_digestsize(tfm), | |
1687 | areq->result, 0, DMA_FROM_DEVICE); | |
1688 | else | |
1689 | map_single_talitos_ptr(dev, &desc->ptr[5], | |
1690 | req_ctx->hw_context_size, | |
1691 | req_ctx->hw_context, 0, DMA_FROM_DEVICE); | |
1692 | ||
1693 | /* last DWORD empty */ | |
1694 | desc->ptr[6] = zero_entry; | |
1695 | ||
5228f0f7 | 1696 | ret = talitos_submit(dev, ctx->ch, desc, callback, areq); |
497f2e6b LN |
1697 | if (ret != -EINPROGRESS) { |
1698 | common_nonsnoop_hash_unmap(dev, edesc, areq); | |
1699 | kfree(edesc); | |
1700 | } | |
1701 | return ret; | |
1702 | } | |
1703 | ||
1704 | static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq, | |
1705 | unsigned int nbytes) | |
1706 | { | |
1707 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); | |
1708 | struct talitos_ctx *ctx = crypto_ahash_ctx(tfm); | |
1709 | struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); | |
1710 | ||
1711 | return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, 1, | |
1712 | nbytes, 0, 0, areq->base.flags); | |
1713 | } | |
1714 | ||
1715 | static int ahash_init(struct ahash_request *areq) | |
1716 | { | |
1717 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); | |
1718 | struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); | |
1719 | ||
1720 | /* Initialize the context */ | |
5e833bc4 | 1721 | req_ctx->nbuf = 0; |
60f208d7 KP |
1722 | req_ctx->first = 1; /* first indicates h/w must init its context */ |
1723 | req_ctx->swinit = 0; /* assume h/w init of context */ | |
497f2e6b LN |
1724 | req_ctx->hw_context_size = |
1725 | (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE) | |
1726 | ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 | |
1727 | : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512; | |
1728 | ||
1729 | return 0; | |
1730 | } | |
1731 | ||
60f208d7 KP |
1732 | /* |
1733 | * on h/w without explicit sha224 support, we initialize h/w context | |
1734 | * manually with sha224 constants, and tell it to run sha256. | |
1735 | */ | |
1736 | static int ahash_init_sha224_swinit(struct ahash_request *areq) | |
1737 | { | |
1738 | struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); | |
1739 | ||
1740 | ahash_init(areq); | |
1741 | req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/ | |
1742 | ||
a752447a KP |
1743 | req_ctx->hw_context[0] = SHA224_H0; |
1744 | req_ctx->hw_context[1] = SHA224_H1; | |
1745 | req_ctx->hw_context[2] = SHA224_H2; | |
1746 | req_ctx->hw_context[3] = SHA224_H3; | |
1747 | req_ctx->hw_context[4] = SHA224_H4; | |
1748 | req_ctx->hw_context[5] = SHA224_H5; | |
1749 | req_ctx->hw_context[6] = SHA224_H6; | |
1750 | req_ctx->hw_context[7] = SHA224_H7; | |
60f208d7 KP |
1751 | |
1752 | /* init 64-bit count */ | |
1753 | req_ctx->hw_context[8] = 0; | |
1754 | req_ctx->hw_context[9] = 0; | |
1755 | ||
1756 | return 0; | |
1757 | } | |
1758 | ||
497f2e6b LN |
1759 | static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes) |
1760 | { | |
1761 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); | |
1762 | struct talitos_ctx *ctx = crypto_ahash_ctx(tfm); | |
1763 | struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); | |
1764 | struct talitos_edesc *edesc; | |
1765 | unsigned int blocksize = | |
1766 | crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); | |
1767 | unsigned int nbytes_to_hash; | |
1768 | unsigned int to_hash_later; | |
5e833bc4 | 1769 | unsigned int nsg; |
497f2e6b LN |
1770 | int chained; |
1771 | ||
5e833bc4 LN |
1772 | if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) { |
1773 | /* Buffer up to one whole block */ | |
497f2e6b LN |
1774 | sg_copy_to_buffer(areq->src, |
1775 | sg_count(areq->src, nbytes, &chained), | |
5e833bc4 LN |
1776 | req_ctx->buf + req_ctx->nbuf, nbytes); |
1777 | req_ctx->nbuf += nbytes; | |
497f2e6b LN |
1778 | return 0; |
1779 | } | |
1780 | ||
5e833bc4 LN |
1781 | /* At least (blocksize + 1) bytes are available to hash */ |
1782 | nbytes_to_hash = nbytes + req_ctx->nbuf; | |
1783 | to_hash_later = nbytes_to_hash & (blocksize - 1); | |
1784 | ||
1785 | if (req_ctx->last) | |
1786 | to_hash_later = 0; | |
1787 | else if (to_hash_later) | |
1788 | /* There is a partial block. Hash the full block(s) now */ | |
1789 | nbytes_to_hash -= to_hash_later; | |
1790 | else { | |
1791 | /* Keep one block buffered */ | |
1792 | nbytes_to_hash -= blocksize; | |
1793 | to_hash_later = blocksize; | |
1794 | } | |
1795 | ||
1796 | /* Chain in any previously buffered data */ | |
1797 | if (req_ctx->nbuf) { | |
1798 | nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1; | |
1799 | sg_init_table(req_ctx->bufsl, nsg); | |
1800 | sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf); | |
1801 | if (nsg > 1) | |
1802 | scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src); | |
497f2e6b | 1803 | req_ctx->psrc = req_ctx->bufsl; |
5e833bc4 | 1804 | } else |
497f2e6b | 1805 | req_ctx->psrc = areq->src; |
5e833bc4 LN |
1806 | |
1807 | if (to_hash_later) { | |
1808 | int nents = sg_count(areq->src, nbytes, &chained); | |
1809 | sg_copy_end_to_buffer(areq->src, nents, | |
1810 | req_ctx->bufnext, | |
1811 | to_hash_later, | |
1812 | nbytes - to_hash_later); | |
497f2e6b | 1813 | } |
5e833bc4 | 1814 | req_ctx->to_hash_later = to_hash_later; |
497f2e6b | 1815 | |
5e833bc4 | 1816 | /* Allocate extended descriptor */ |
497f2e6b LN |
1817 | edesc = ahash_edesc_alloc(areq, nbytes_to_hash); |
1818 | if (IS_ERR(edesc)) | |
1819 | return PTR_ERR(edesc); | |
1820 | ||
1821 | edesc->desc.hdr = ctx->desc_hdr_template; | |
1822 | ||
1823 | /* On last one, request SEC to pad; otherwise continue */ | |
1824 | if (req_ctx->last) | |
1825 | edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD; | |
1826 | else | |
1827 | edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT; | |
1828 | ||
60f208d7 KP |
1829 | /* request SEC to INIT hash. */ |
1830 | if (req_ctx->first && !req_ctx->swinit) | |
497f2e6b LN |
1831 | edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT; |
1832 | ||
1833 | /* When the tfm context has a keylen, it's an HMAC. | |
1834 | * A first or last (ie. not middle) descriptor must request HMAC. | |
1835 | */ | |
1836 | if (ctx->keylen && (req_ctx->first || req_ctx->last)) | |
1837 | edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC; | |
1838 | ||
1839 | return common_nonsnoop_hash(edesc, areq, nbytes_to_hash, | |
1840 | ahash_done); | |
1841 | } | |
1842 | ||
1843 | static int ahash_update(struct ahash_request *areq) | |
1844 | { | |
1845 | struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); | |
1846 | ||
1847 | req_ctx->last = 0; | |
1848 | ||
1849 | return ahash_process_req(areq, areq->nbytes); | |
1850 | } | |
1851 | ||
1852 | static int ahash_final(struct ahash_request *areq) | |
1853 | { | |
1854 | struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); | |
1855 | ||
1856 | req_ctx->last = 1; | |
1857 | ||
1858 | return ahash_process_req(areq, 0); | |
1859 | } | |
1860 | ||
1861 | static int ahash_finup(struct ahash_request *areq) | |
1862 | { | |
1863 | struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); | |
1864 | ||
1865 | req_ctx->last = 1; | |
1866 | ||
1867 | return ahash_process_req(areq, areq->nbytes); | |
1868 | } | |
1869 | ||
1870 | static int ahash_digest(struct ahash_request *areq) | |
1871 | { | |
1872 | struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); | |
60f208d7 | 1873 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq); |
497f2e6b | 1874 | |
60f208d7 | 1875 | ahash->init(areq); |
497f2e6b LN |
1876 | req_ctx->last = 1; |
1877 | ||
1878 | return ahash_process_req(areq, areq->nbytes); | |
1879 | } | |
1880 | ||
79b3a418 LN |
1881 | struct keyhash_result { |
1882 | struct completion completion; | |
1883 | int err; | |
1884 | }; | |
1885 | ||
1886 | static void keyhash_complete(struct crypto_async_request *req, int err) | |
1887 | { | |
1888 | struct keyhash_result *res = req->data; | |
1889 | ||
1890 | if (err == -EINPROGRESS) | |
1891 | return; | |
1892 | ||
1893 | res->err = err; | |
1894 | complete(&res->completion); | |
1895 | } | |
1896 | ||
1897 | static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen, | |
1898 | u8 *hash) | |
1899 | { | |
1900 | struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm)); | |
1901 | ||
1902 | struct scatterlist sg[1]; | |
1903 | struct ahash_request *req; | |
1904 | struct keyhash_result hresult; | |
1905 | int ret; | |
1906 | ||
1907 | init_completion(&hresult.completion); | |
1908 | ||
1909 | req = ahash_request_alloc(tfm, GFP_KERNEL); | |
1910 | if (!req) | |
1911 | return -ENOMEM; | |
1912 | ||
1913 | /* Keep tfm keylen == 0 during hash of the long key */ | |
1914 | ctx->keylen = 0; | |
1915 | ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, | |
1916 | keyhash_complete, &hresult); | |
1917 | ||
1918 | sg_init_one(&sg[0], key, keylen); | |
1919 | ||
1920 | ahash_request_set_crypt(req, sg, hash, keylen); | |
1921 | ret = crypto_ahash_digest(req); | |
1922 | switch (ret) { | |
1923 | case 0: | |
1924 | break; | |
1925 | case -EINPROGRESS: | |
1926 | case -EBUSY: | |
1927 | ret = wait_for_completion_interruptible( | |
1928 | &hresult.completion); | |
1929 | if (!ret) | |
1930 | ret = hresult.err; | |
1931 | break; | |
1932 | default: | |
1933 | break; | |
1934 | } | |
1935 | ahash_request_free(req); | |
1936 | ||
1937 | return ret; | |
1938 | } | |
1939 | ||
1940 | static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key, | |
1941 | unsigned int keylen) | |
1942 | { | |
1943 | struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm)); | |
1944 | unsigned int blocksize = | |
1945 | crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); | |
1946 | unsigned int digestsize = crypto_ahash_digestsize(tfm); | |
1947 | unsigned int keysize = keylen; | |
1948 | u8 hash[SHA512_DIGEST_SIZE]; | |
1949 | int ret; | |
1950 | ||
1951 | if (keylen <= blocksize) | |
1952 | memcpy(ctx->key, key, keysize); | |
1953 | else { | |
1954 | /* Must get the hash of the long key */ | |
1955 | ret = keyhash(tfm, key, keylen, hash); | |
1956 | ||
1957 | if (ret) { | |
1958 | crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
1959 | return -EINVAL; | |
1960 | } | |
1961 | ||
1962 | keysize = digestsize; | |
1963 | memcpy(ctx->key, hash, digestsize); | |
1964 | } | |
1965 | ||
1966 | ctx->keylen = keysize; | |
1967 | ||
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | ||
9c4a7965 | 1972 | struct talitos_alg_template { |
d5e4aaef LN |
1973 | u32 type; |
1974 | union { | |
1975 | struct crypto_alg crypto; | |
acbf7c62 | 1976 | struct ahash_alg hash; |
d5e4aaef | 1977 | } alg; |
9c4a7965 KP |
1978 | __be32 desc_hdr_template; |
1979 | }; | |
1980 | ||
1981 | static struct talitos_alg_template driver_algs[] = { | |
56af8cd4 | 1982 | /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */ |
d5e4aaef LN |
1983 | { .type = CRYPTO_ALG_TYPE_AEAD, |
1984 | .alg.crypto = { | |
56af8cd4 LN |
1985 | .cra_name = "authenc(hmac(sha1),cbc(aes))", |
1986 | .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos", | |
1987 | .cra_blocksize = AES_BLOCK_SIZE, | |
1988 | .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, | |
1989 | .cra_type = &crypto_aead_type, | |
1990 | .cra_aead = { | |
1991 | .setkey = aead_setkey, | |
1992 | .setauthsize = aead_setauthsize, | |
1993 | .encrypt = aead_encrypt, | |
1994 | .decrypt = aead_decrypt, | |
1995 | .givencrypt = aead_givencrypt, | |
1996 | .geniv = "<built-in>", | |
1997 | .ivsize = AES_BLOCK_SIZE, | |
1998 | .maxauthsize = SHA1_DIGEST_SIZE, | |
1999 | } | |
2000 | }, | |
9c4a7965 KP |
2001 | .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP | |
2002 | DESC_HDR_SEL0_AESU | | |
2003 | DESC_HDR_MODE0_AESU_CBC | | |
2004 | DESC_HDR_SEL1_MDEUA | | |
2005 | DESC_HDR_MODE1_MDEU_INIT | | |
2006 | DESC_HDR_MODE1_MDEU_PAD | | |
2007 | DESC_HDR_MODE1_MDEU_SHA1_HMAC, | |
70bcaca7 | 2008 | }, |
d5e4aaef LN |
2009 | { .type = CRYPTO_ALG_TYPE_AEAD, |
2010 | .alg.crypto = { | |
56af8cd4 LN |
2011 | .cra_name = "authenc(hmac(sha1),cbc(des3_ede))", |
2012 | .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos", | |
2013 | .cra_blocksize = DES3_EDE_BLOCK_SIZE, | |
2014 | .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, | |
2015 | .cra_type = &crypto_aead_type, | |
2016 | .cra_aead = { | |
2017 | .setkey = aead_setkey, | |
2018 | .setauthsize = aead_setauthsize, | |
2019 | .encrypt = aead_encrypt, | |
2020 | .decrypt = aead_decrypt, | |
2021 | .givencrypt = aead_givencrypt, | |
2022 | .geniv = "<built-in>", | |
2023 | .ivsize = DES3_EDE_BLOCK_SIZE, | |
2024 | .maxauthsize = SHA1_DIGEST_SIZE, | |
2025 | } | |
2026 | }, | |
70bcaca7 LN |
2027 | .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP | |
2028 | DESC_HDR_SEL0_DEU | | |
2029 | DESC_HDR_MODE0_DEU_CBC | | |
2030 | DESC_HDR_MODE0_DEU_3DES | | |
2031 | DESC_HDR_SEL1_MDEUA | | |
2032 | DESC_HDR_MODE1_MDEU_INIT | | |
2033 | DESC_HDR_MODE1_MDEU_PAD | | |
2034 | DESC_HDR_MODE1_MDEU_SHA1_HMAC, | |
3952f17e | 2035 | }, |
d5e4aaef LN |
2036 | { .type = CRYPTO_ALG_TYPE_AEAD, |
2037 | .alg.crypto = { | |
56af8cd4 LN |
2038 | .cra_name = "authenc(hmac(sha256),cbc(aes))", |
2039 | .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos", | |
2040 | .cra_blocksize = AES_BLOCK_SIZE, | |
2041 | .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, | |
2042 | .cra_type = &crypto_aead_type, | |
2043 | .cra_aead = { | |
2044 | .setkey = aead_setkey, | |
2045 | .setauthsize = aead_setauthsize, | |
2046 | .encrypt = aead_encrypt, | |
2047 | .decrypt = aead_decrypt, | |
2048 | .givencrypt = aead_givencrypt, | |
2049 | .geniv = "<built-in>", | |
2050 | .ivsize = AES_BLOCK_SIZE, | |
2051 | .maxauthsize = SHA256_DIGEST_SIZE, | |
2052 | } | |
2053 | }, | |
3952f17e LN |
2054 | .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP | |
2055 | DESC_HDR_SEL0_AESU | | |
2056 | DESC_HDR_MODE0_AESU_CBC | | |
2057 | DESC_HDR_SEL1_MDEUA | | |
2058 | DESC_HDR_MODE1_MDEU_INIT | | |
2059 | DESC_HDR_MODE1_MDEU_PAD | | |
2060 | DESC_HDR_MODE1_MDEU_SHA256_HMAC, | |
2061 | }, | |
d5e4aaef LN |
2062 | { .type = CRYPTO_ALG_TYPE_AEAD, |
2063 | .alg.crypto = { | |
56af8cd4 LN |
2064 | .cra_name = "authenc(hmac(sha256),cbc(des3_ede))", |
2065 | .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos", | |
2066 | .cra_blocksize = DES3_EDE_BLOCK_SIZE, | |
2067 | .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, | |
2068 | .cra_type = &crypto_aead_type, | |
2069 | .cra_aead = { | |
2070 | .setkey = aead_setkey, | |
2071 | .setauthsize = aead_setauthsize, | |
2072 | .encrypt = aead_encrypt, | |
2073 | .decrypt = aead_decrypt, | |
2074 | .givencrypt = aead_givencrypt, | |
2075 | .geniv = "<built-in>", | |
2076 | .ivsize = DES3_EDE_BLOCK_SIZE, | |
2077 | .maxauthsize = SHA256_DIGEST_SIZE, | |
2078 | } | |
2079 | }, | |
3952f17e LN |
2080 | .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP | |
2081 | DESC_HDR_SEL0_DEU | | |
2082 | DESC_HDR_MODE0_DEU_CBC | | |
2083 | DESC_HDR_MODE0_DEU_3DES | | |
2084 | DESC_HDR_SEL1_MDEUA | | |
2085 | DESC_HDR_MODE1_MDEU_INIT | | |
2086 | DESC_HDR_MODE1_MDEU_PAD | | |
2087 | DESC_HDR_MODE1_MDEU_SHA256_HMAC, | |
2088 | }, | |
d5e4aaef LN |
2089 | { .type = CRYPTO_ALG_TYPE_AEAD, |
2090 | .alg.crypto = { | |
56af8cd4 LN |
2091 | .cra_name = "authenc(hmac(md5),cbc(aes))", |
2092 | .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos", | |
2093 | .cra_blocksize = AES_BLOCK_SIZE, | |
2094 | .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, | |
2095 | .cra_type = &crypto_aead_type, | |
2096 | .cra_aead = { | |
2097 | .setkey = aead_setkey, | |
2098 | .setauthsize = aead_setauthsize, | |
2099 | .encrypt = aead_encrypt, | |
2100 | .decrypt = aead_decrypt, | |
2101 | .givencrypt = aead_givencrypt, | |
2102 | .geniv = "<built-in>", | |
2103 | .ivsize = AES_BLOCK_SIZE, | |
2104 | .maxauthsize = MD5_DIGEST_SIZE, | |
2105 | } | |
2106 | }, | |
3952f17e LN |
2107 | .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP | |
2108 | DESC_HDR_SEL0_AESU | | |
2109 | DESC_HDR_MODE0_AESU_CBC | | |
2110 | DESC_HDR_SEL1_MDEUA | | |
2111 | DESC_HDR_MODE1_MDEU_INIT | | |
2112 | DESC_HDR_MODE1_MDEU_PAD | | |
2113 | DESC_HDR_MODE1_MDEU_MD5_HMAC, | |
2114 | }, | |
d5e4aaef LN |
2115 | { .type = CRYPTO_ALG_TYPE_AEAD, |
2116 | .alg.crypto = { | |
56af8cd4 LN |
2117 | .cra_name = "authenc(hmac(md5),cbc(des3_ede))", |
2118 | .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos", | |
2119 | .cra_blocksize = DES3_EDE_BLOCK_SIZE, | |
2120 | .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, | |
2121 | .cra_type = &crypto_aead_type, | |
2122 | .cra_aead = { | |
2123 | .setkey = aead_setkey, | |
2124 | .setauthsize = aead_setauthsize, | |
2125 | .encrypt = aead_encrypt, | |
2126 | .decrypt = aead_decrypt, | |
2127 | .givencrypt = aead_givencrypt, | |
2128 | .geniv = "<built-in>", | |
2129 | .ivsize = DES3_EDE_BLOCK_SIZE, | |
2130 | .maxauthsize = MD5_DIGEST_SIZE, | |
2131 | } | |
2132 | }, | |
3952f17e LN |
2133 | .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP | |
2134 | DESC_HDR_SEL0_DEU | | |
2135 | DESC_HDR_MODE0_DEU_CBC | | |
2136 | DESC_HDR_MODE0_DEU_3DES | | |
2137 | DESC_HDR_SEL1_MDEUA | | |
2138 | DESC_HDR_MODE1_MDEU_INIT | | |
2139 | DESC_HDR_MODE1_MDEU_PAD | | |
2140 | DESC_HDR_MODE1_MDEU_MD5_HMAC, | |
4de9d0b5 LN |
2141 | }, |
2142 | /* ABLKCIPHER algorithms. */ | |
d5e4aaef LN |
2143 | { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, |
2144 | .alg.crypto = { | |
4de9d0b5 LN |
2145 | .cra_name = "cbc(aes)", |
2146 | .cra_driver_name = "cbc-aes-talitos", | |
2147 | .cra_blocksize = AES_BLOCK_SIZE, | |
2148 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
2149 | CRYPTO_ALG_ASYNC, | |
2150 | .cra_type = &crypto_ablkcipher_type, | |
2151 | .cra_ablkcipher = { | |
2152 | .setkey = ablkcipher_setkey, | |
2153 | .encrypt = ablkcipher_encrypt, | |
2154 | .decrypt = ablkcipher_decrypt, | |
2155 | .geniv = "eseqiv", | |
2156 | .min_keysize = AES_MIN_KEY_SIZE, | |
2157 | .max_keysize = AES_MAX_KEY_SIZE, | |
2158 | .ivsize = AES_BLOCK_SIZE, | |
2159 | } | |
2160 | }, | |
2161 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2162 | DESC_HDR_SEL0_AESU | | |
2163 | DESC_HDR_MODE0_AESU_CBC, | |
2164 | }, | |
d5e4aaef LN |
2165 | { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, |
2166 | .alg.crypto = { | |
4de9d0b5 LN |
2167 | .cra_name = "cbc(des3_ede)", |
2168 | .cra_driver_name = "cbc-3des-talitos", | |
2169 | .cra_blocksize = DES3_EDE_BLOCK_SIZE, | |
2170 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
2171 | CRYPTO_ALG_ASYNC, | |
2172 | .cra_type = &crypto_ablkcipher_type, | |
2173 | .cra_ablkcipher = { | |
2174 | .setkey = ablkcipher_setkey, | |
2175 | .encrypt = ablkcipher_encrypt, | |
2176 | .decrypt = ablkcipher_decrypt, | |
2177 | .geniv = "eseqiv", | |
2178 | .min_keysize = DES3_EDE_KEY_SIZE, | |
2179 | .max_keysize = DES3_EDE_KEY_SIZE, | |
2180 | .ivsize = DES3_EDE_BLOCK_SIZE, | |
2181 | } | |
2182 | }, | |
2183 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2184 | DESC_HDR_SEL0_DEU | | |
2185 | DESC_HDR_MODE0_DEU_CBC | | |
2186 | DESC_HDR_MODE0_DEU_3DES, | |
497f2e6b LN |
2187 | }, |
2188 | /* AHASH algorithms. */ | |
2189 | { .type = CRYPTO_ALG_TYPE_AHASH, | |
2190 | .alg.hash = { | |
2191 | .init = ahash_init, | |
2192 | .update = ahash_update, | |
2193 | .final = ahash_final, | |
2194 | .finup = ahash_finup, | |
2195 | .digest = ahash_digest, | |
2196 | .halg.digestsize = MD5_DIGEST_SIZE, | |
2197 | .halg.base = { | |
2198 | .cra_name = "md5", | |
2199 | .cra_driver_name = "md5-talitos", | |
2200 | .cra_blocksize = MD5_BLOCK_SIZE, | |
2201 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2202 | CRYPTO_ALG_ASYNC, | |
2203 | .cra_type = &crypto_ahash_type | |
2204 | } | |
2205 | }, | |
2206 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2207 | DESC_HDR_SEL0_MDEUA | | |
2208 | DESC_HDR_MODE0_MDEU_MD5, | |
2209 | }, | |
2210 | { .type = CRYPTO_ALG_TYPE_AHASH, | |
2211 | .alg.hash = { | |
2212 | .init = ahash_init, | |
2213 | .update = ahash_update, | |
2214 | .final = ahash_final, | |
2215 | .finup = ahash_finup, | |
2216 | .digest = ahash_digest, | |
2217 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
2218 | .halg.base = { | |
2219 | .cra_name = "sha1", | |
2220 | .cra_driver_name = "sha1-talitos", | |
2221 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
2222 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2223 | CRYPTO_ALG_ASYNC, | |
2224 | .cra_type = &crypto_ahash_type | |
2225 | } | |
2226 | }, | |
2227 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2228 | DESC_HDR_SEL0_MDEUA | | |
2229 | DESC_HDR_MODE0_MDEU_SHA1, | |
2230 | }, | |
60f208d7 KP |
2231 | { .type = CRYPTO_ALG_TYPE_AHASH, |
2232 | .alg.hash = { | |
2233 | .init = ahash_init, | |
2234 | .update = ahash_update, | |
2235 | .final = ahash_final, | |
2236 | .finup = ahash_finup, | |
2237 | .digest = ahash_digest, | |
2238 | .halg.digestsize = SHA224_DIGEST_SIZE, | |
2239 | .halg.base = { | |
2240 | .cra_name = "sha224", | |
2241 | .cra_driver_name = "sha224-talitos", | |
2242 | .cra_blocksize = SHA224_BLOCK_SIZE, | |
2243 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2244 | CRYPTO_ALG_ASYNC, | |
2245 | .cra_type = &crypto_ahash_type | |
2246 | } | |
2247 | }, | |
2248 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2249 | DESC_HDR_SEL0_MDEUA | | |
2250 | DESC_HDR_MODE0_MDEU_SHA224, | |
2251 | }, | |
497f2e6b LN |
2252 | { .type = CRYPTO_ALG_TYPE_AHASH, |
2253 | .alg.hash = { | |
2254 | .init = ahash_init, | |
2255 | .update = ahash_update, | |
2256 | .final = ahash_final, | |
2257 | .finup = ahash_finup, | |
2258 | .digest = ahash_digest, | |
2259 | .halg.digestsize = SHA256_DIGEST_SIZE, | |
2260 | .halg.base = { | |
2261 | .cra_name = "sha256", | |
2262 | .cra_driver_name = "sha256-talitos", | |
2263 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
2264 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2265 | CRYPTO_ALG_ASYNC, | |
2266 | .cra_type = &crypto_ahash_type | |
2267 | } | |
2268 | }, | |
2269 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2270 | DESC_HDR_SEL0_MDEUA | | |
2271 | DESC_HDR_MODE0_MDEU_SHA256, | |
2272 | }, | |
2273 | { .type = CRYPTO_ALG_TYPE_AHASH, | |
2274 | .alg.hash = { | |
2275 | .init = ahash_init, | |
2276 | .update = ahash_update, | |
2277 | .final = ahash_final, | |
2278 | .finup = ahash_finup, | |
2279 | .digest = ahash_digest, | |
2280 | .halg.digestsize = SHA384_DIGEST_SIZE, | |
2281 | .halg.base = { | |
2282 | .cra_name = "sha384", | |
2283 | .cra_driver_name = "sha384-talitos", | |
2284 | .cra_blocksize = SHA384_BLOCK_SIZE, | |
2285 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2286 | CRYPTO_ALG_ASYNC, | |
2287 | .cra_type = &crypto_ahash_type | |
2288 | } | |
2289 | }, | |
2290 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2291 | DESC_HDR_SEL0_MDEUB | | |
2292 | DESC_HDR_MODE0_MDEUB_SHA384, | |
2293 | }, | |
2294 | { .type = CRYPTO_ALG_TYPE_AHASH, | |
2295 | .alg.hash = { | |
2296 | .init = ahash_init, | |
2297 | .update = ahash_update, | |
2298 | .final = ahash_final, | |
2299 | .finup = ahash_finup, | |
2300 | .digest = ahash_digest, | |
2301 | .halg.digestsize = SHA512_DIGEST_SIZE, | |
2302 | .halg.base = { | |
2303 | .cra_name = "sha512", | |
2304 | .cra_driver_name = "sha512-talitos", | |
2305 | .cra_blocksize = SHA512_BLOCK_SIZE, | |
2306 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2307 | CRYPTO_ALG_ASYNC, | |
2308 | .cra_type = &crypto_ahash_type | |
2309 | } | |
2310 | }, | |
2311 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2312 | DESC_HDR_SEL0_MDEUB | | |
2313 | DESC_HDR_MODE0_MDEUB_SHA512, | |
2314 | }, | |
79b3a418 LN |
2315 | { .type = CRYPTO_ALG_TYPE_AHASH, |
2316 | .alg.hash = { | |
2317 | .init = ahash_init, | |
2318 | .update = ahash_update, | |
2319 | .final = ahash_final, | |
2320 | .finup = ahash_finup, | |
2321 | .digest = ahash_digest, | |
2322 | .setkey = ahash_setkey, | |
2323 | .halg.digestsize = MD5_DIGEST_SIZE, | |
2324 | .halg.base = { | |
2325 | .cra_name = "hmac(md5)", | |
2326 | .cra_driver_name = "hmac-md5-talitos", | |
2327 | .cra_blocksize = MD5_BLOCK_SIZE, | |
2328 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2329 | CRYPTO_ALG_ASYNC, | |
2330 | .cra_type = &crypto_ahash_type | |
2331 | } | |
2332 | }, | |
2333 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2334 | DESC_HDR_SEL0_MDEUA | | |
2335 | DESC_HDR_MODE0_MDEU_MD5, | |
2336 | }, | |
2337 | { .type = CRYPTO_ALG_TYPE_AHASH, | |
2338 | .alg.hash = { | |
2339 | .init = ahash_init, | |
2340 | .update = ahash_update, | |
2341 | .final = ahash_final, | |
2342 | .finup = ahash_finup, | |
2343 | .digest = ahash_digest, | |
2344 | .setkey = ahash_setkey, | |
2345 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
2346 | .halg.base = { | |
2347 | .cra_name = "hmac(sha1)", | |
2348 | .cra_driver_name = "hmac-sha1-talitos", | |
2349 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
2350 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2351 | CRYPTO_ALG_ASYNC, | |
2352 | .cra_type = &crypto_ahash_type | |
2353 | } | |
2354 | }, | |
2355 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2356 | DESC_HDR_SEL0_MDEUA | | |
2357 | DESC_HDR_MODE0_MDEU_SHA1, | |
2358 | }, | |
2359 | { .type = CRYPTO_ALG_TYPE_AHASH, | |
2360 | .alg.hash = { | |
2361 | .init = ahash_init, | |
2362 | .update = ahash_update, | |
2363 | .final = ahash_final, | |
2364 | .finup = ahash_finup, | |
2365 | .digest = ahash_digest, | |
2366 | .setkey = ahash_setkey, | |
2367 | .halg.digestsize = SHA224_DIGEST_SIZE, | |
2368 | .halg.base = { | |
2369 | .cra_name = "hmac(sha224)", | |
2370 | .cra_driver_name = "hmac-sha224-talitos", | |
2371 | .cra_blocksize = SHA224_BLOCK_SIZE, | |
2372 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2373 | CRYPTO_ALG_ASYNC, | |
2374 | .cra_type = &crypto_ahash_type | |
2375 | } | |
2376 | }, | |
2377 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2378 | DESC_HDR_SEL0_MDEUA | | |
2379 | DESC_HDR_MODE0_MDEU_SHA224, | |
2380 | }, | |
2381 | { .type = CRYPTO_ALG_TYPE_AHASH, | |
2382 | .alg.hash = { | |
2383 | .init = ahash_init, | |
2384 | .update = ahash_update, | |
2385 | .final = ahash_final, | |
2386 | .finup = ahash_finup, | |
2387 | .digest = ahash_digest, | |
2388 | .setkey = ahash_setkey, | |
2389 | .halg.digestsize = SHA256_DIGEST_SIZE, | |
2390 | .halg.base = { | |
2391 | .cra_name = "hmac(sha256)", | |
2392 | .cra_driver_name = "hmac-sha256-talitos", | |
2393 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
2394 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2395 | CRYPTO_ALG_ASYNC, | |
2396 | .cra_type = &crypto_ahash_type | |
2397 | } | |
2398 | }, | |
2399 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2400 | DESC_HDR_SEL0_MDEUA | | |
2401 | DESC_HDR_MODE0_MDEU_SHA256, | |
2402 | }, | |
2403 | { .type = CRYPTO_ALG_TYPE_AHASH, | |
2404 | .alg.hash = { | |
2405 | .init = ahash_init, | |
2406 | .update = ahash_update, | |
2407 | .final = ahash_final, | |
2408 | .finup = ahash_finup, | |
2409 | .digest = ahash_digest, | |
2410 | .setkey = ahash_setkey, | |
2411 | .halg.digestsize = SHA384_DIGEST_SIZE, | |
2412 | .halg.base = { | |
2413 | .cra_name = "hmac(sha384)", | |
2414 | .cra_driver_name = "hmac-sha384-talitos", | |
2415 | .cra_blocksize = SHA384_BLOCK_SIZE, | |
2416 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2417 | CRYPTO_ALG_ASYNC, | |
2418 | .cra_type = &crypto_ahash_type | |
2419 | } | |
2420 | }, | |
2421 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2422 | DESC_HDR_SEL0_MDEUB | | |
2423 | DESC_HDR_MODE0_MDEUB_SHA384, | |
2424 | }, | |
2425 | { .type = CRYPTO_ALG_TYPE_AHASH, | |
2426 | .alg.hash = { | |
2427 | .init = ahash_init, | |
2428 | .update = ahash_update, | |
2429 | .final = ahash_final, | |
2430 | .finup = ahash_finup, | |
2431 | .digest = ahash_digest, | |
2432 | .setkey = ahash_setkey, | |
2433 | .halg.digestsize = SHA512_DIGEST_SIZE, | |
2434 | .halg.base = { | |
2435 | .cra_name = "hmac(sha512)", | |
2436 | .cra_driver_name = "hmac-sha512-talitos", | |
2437 | .cra_blocksize = SHA512_BLOCK_SIZE, | |
2438 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
2439 | CRYPTO_ALG_ASYNC, | |
2440 | .cra_type = &crypto_ahash_type | |
2441 | } | |
2442 | }, | |
2443 | .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2444 | DESC_HDR_SEL0_MDEUB | | |
2445 | DESC_HDR_MODE0_MDEUB_SHA512, | |
2446 | } | |
9c4a7965 KP |
2447 | }; |
2448 | ||
2449 | struct talitos_crypto_alg { | |
2450 | struct list_head entry; | |
2451 | struct device *dev; | |
acbf7c62 | 2452 | struct talitos_alg_template algt; |
9c4a7965 KP |
2453 | }; |
2454 | ||
2455 | static int talitos_cra_init(struct crypto_tfm *tfm) | |
2456 | { | |
2457 | struct crypto_alg *alg = tfm->__crt_alg; | |
19bbbc63 | 2458 | struct talitos_crypto_alg *talitos_alg; |
9c4a7965 | 2459 | struct talitos_ctx *ctx = crypto_tfm_ctx(tfm); |
5228f0f7 | 2460 | struct talitos_private *priv; |
9c4a7965 | 2461 | |
497f2e6b LN |
2462 | if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH) |
2463 | talitos_alg = container_of(__crypto_ahash_alg(alg), | |
2464 | struct talitos_crypto_alg, | |
2465 | algt.alg.hash); | |
2466 | else | |
2467 | talitos_alg = container_of(alg, struct talitos_crypto_alg, | |
2468 | algt.alg.crypto); | |
19bbbc63 | 2469 | |
9c4a7965 KP |
2470 | /* update context with ptr to dev */ |
2471 | ctx->dev = talitos_alg->dev; | |
19bbbc63 | 2472 | |
5228f0f7 KP |
2473 | /* assign SEC channel to tfm in round-robin fashion */ |
2474 | priv = dev_get_drvdata(ctx->dev); | |
2475 | ctx->ch = atomic_inc_return(&priv->last_chan) & | |
2476 | (priv->num_channels - 1); | |
2477 | ||
9c4a7965 | 2478 | /* copy descriptor header template value */ |
acbf7c62 | 2479 | ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template; |
9c4a7965 | 2480 | |
602dba5a KP |
2481 | /* select done notification */ |
2482 | ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY; | |
2483 | ||
497f2e6b LN |
2484 | return 0; |
2485 | } | |
2486 | ||
2487 | static int talitos_cra_init_aead(struct crypto_tfm *tfm) | |
2488 | { | |
2489 | struct talitos_ctx *ctx = crypto_tfm_ctx(tfm); | |
2490 | ||
2491 | talitos_cra_init(tfm); | |
9c4a7965 KP |
2492 | |
2493 | /* random first IV */ | |
70bcaca7 | 2494 | get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH); |
9c4a7965 KP |
2495 | |
2496 | return 0; | |
2497 | } | |
2498 | ||
497f2e6b LN |
2499 | static int talitos_cra_init_ahash(struct crypto_tfm *tfm) |
2500 | { | |
2501 | struct talitos_ctx *ctx = crypto_tfm_ctx(tfm); | |
2502 | ||
2503 | talitos_cra_init(tfm); | |
2504 | ||
2505 | ctx->keylen = 0; | |
2506 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
2507 | sizeof(struct talitos_ahash_req_ctx)); | |
2508 | ||
2509 | return 0; | |
2510 | } | |
2511 | ||
9c4a7965 KP |
2512 | /* |
2513 | * given the alg's descriptor header template, determine whether descriptor | |
2514 | * type and primary/secondary execution units required match the hw | |
2515 | * capabilities description provided in the device tree node. | |
2516 | */ | |
2517 | static int hw_supports(struct device *dev, __be32 desc_hdr_template) | |
2518 | { | |
2519 | struct talitos_private *priv = dev_get_drvdata(dev); | |
2520 | int ret; | |
2521 | ||
2522 | ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) && | |
2523 | (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units); | |
2524 | ||
2525 | if (SECONDARY_EU(desc_hdr_template)) | |
2526 | ret = ret && (1 << SECONDARY_EU(desc_hdr_template) | |
2527 | & priv->exec_units); | |
2528 | ||
2529 | return ret; | |
2530 | } | |
2531 | ||
2dc11581 | 2532 | static int talitos_remove(struct platform_device *ofdev) |
9c4a7965 KP |
2533 | { |
2534 | struct device *dev = &ofdev->dev; | |
2535 | struct talitos_private *priv = dev_get_drvdata(dev); | |
2536 | struct talitos_crypto_alg *t_alg, *n; | |
2537 | int i; | |
2538 | ||
2539 | list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) { | |
acbf7c62 LN |
2540 | switch (t_alg->algt.type) { |
2541 | case CRYPTO_ALG_TYPE_ABLKCIPHER: | |
2542 | case CRYPTO_ALG_TYPE_AEAD: | |
2543 | crypto_unregister_alg(&t_alg->algt.alg.crypto); | |
2544 | break; | |
2545 | case CRYPTO_ALG_TYPE_AHASH: | |
2546 | crypto_unregister_ahash(&t_alg->algt.alg.hash); | |
2547 | break; | |
2548 | } | |
9c4a7965 KP |
2549 | list_del(&t_alg->entry); |
2550 | kfree(t_alg); | |
2551 | } | |
2552 | ||
2553 | if (hw_supports(dev, DESC_HDR_SEL0_RNG)) | |
2554 | talitos_unregister_rng(dev); | |
2555 | ||
4b992628 | 2556 | for (i = 0; i < priv->num_channels; i++) |
0b798247 | 2557 | kfree(priv->chan[i].fifo); |
9c4a7965 | 2558 | |
4b992628 | 2559 | kfree(priv->chan); |
9c4a7965 KP |
2560 | |
2561 | if (priv->irq != NO_IRQ) { | |
2562 | free_irq(priv->irq, dev); | |
2563 | irq_dispose_mapping(priv->irq); | |
2564 | } | |
2565 | ||
2566 | tasklet_kill(&priv->done_task); | |
9c4a7965 KP |
2567 | |
2568 | iounmap(priv->reg); | |
2569 | ||
2570 | dev_set_drvdata(dev, NULL); | |
2571 | ||
2572 | kfree(priv); | |
2573 | ||
2574 | return 0; | |
2575 | } | |
2576 | ||
2577 | static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev, | |
2578 | struct talitos_alg_template | |
2579 | *template) | |
2580 | { | |
60f208d7 | 2581 | struct talitos_private *priv = dev_get_drvdata(dev); |
9c4a7965 KP |
2582 | struct talitos_crypto_alg *t_alg; |
2583 | struct crypto_alg *alg; | |
2584 | ||
2585 | t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL); | |
2586 | if (!t_alg) | |
2587 | return ERR_PTR(-ENOMEM); | |
2588 | ||
acbf7c62 LN |
2589 | t_alg->algt = *template; |
2590 | ||
2591 | switch (t_alg->algt.type) { | |
2592 | case CRYPTO_ALG_TYPE_ABLKCIPHER: | |
497f2e6b LN |
2593 | alg = &t_alg->algt.alg.crypto; |
2594 | alg->cra_init = talitos_cra_init; | |
2595 | break; | |
acbf7c62 LN |
2596 | case CRYPTO_ALG_TYPE_AEAD: |
2597 | alg = &t_alg->algt.alg.crypto; | |
497f2e6b | 2598 | alg->cra_init = talitos_cra_init_aead; |
acbf7c62 LN |
2599 | break; |
2600 | case CRYPTO_ALG_TYPE_AHASH: | |
2601 | alg = &t_alg->algt.alg.hash.halg.base; | |
497f2e6b | 2602 | alg->cra_init = talitos_cra_init_ahash; |
79b3a418 LN |
2603 | if (!(priv->features & TALITOS_FTR_HMAC_OK) && |
2604 | !strncmp(alg->cra_name, "hmac", 4)) | |
2605 | return ERR_PTR(-ENOTSUPP); | |
60f208d7 | 2606 | if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) && |
79b3a418 LN |
2607 | (!strcmp(alg->cra_name, "sha224") || |
2608 | !strcmp(alg->cra_name, "hmac(sha224)"))) { | |
60f208d7 KP |
2609 | t_alg->algt.alg.hash.init = ahash_init_sha224_swinit; |
2610 | t_alg->algt.desc_hdr_template = | |
2611 | DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | | |
2612 | DESC_HDR_SEL0_MDEUA | | |
2613 | DESC_HDR_MODE0_MDEU_SHA256; | |
2614 | } | |
497f2e6b | 2615 | break; |
1d11911a KP |
2616 | default: |
2617 | dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type); | |
2618 | return ERR_PTR(-EINVAL); | |
acbf7c62 | 2619 | } |
9c4a7965 | 2620 | |
9c4a7965 | 2621 | alg->cra_module = THIS_MODULE; |
9c4a7965 | 2622 | alg->cra_priority = TALITOS_CRA_PRIORITY; |
9c4a7965 | 2623 | alg->cra_alignmask = 0; |
9c4a7965 | 2624 | alg->cra_ctxsize = sizeof(struct talitos_ctx); |
9c4a7965 | 2625 | |
9c4a7965 KP |
2626 | t_alg->dev = dev; |
2627 | ||
2628 | return t_alg; | |
2629 | } | |
2630 | ||
1c48a5c9 | 2631 | static int talitos_probe(struct platform_device *ofdev) |
9c4a7965 KP |
2632 | { |
2633 | struct device *dev = &ofdev->dev; | |
61c7a080 | 2634 | struct device_node *np = ofdev->dev.of_node; |
9c4a7965 KP |
2635 | struct talitos_private *priv; |
2636 | const unsigned int *prop; | |
2637 | int i, err; | |
2638 | ||
2639 | priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL); | |
2640 | if (!priv) | |
2641 | return -ENOMEM; | |
2642 | ||
2643 | dev_set_drvdata(dev, priv); | |
2644 | ||
2645 | priv->ofdev = ofdev; | |
2646 | ||
2647 | tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev); | |
9c4a7965 | 2648 | |
fe5720e2 KP |
2649 | INIT_LIST_HEAD(&priv->alg_list); |
2650 | ||
9c4a7965 KP |
2651 | priv->irq = irq_of_parse_and_map(np, 0); |
2652 | ||
2653 | if (priv->irq == NO_IRQ) { | |
2654 | dev_err(dev, "failed to map irq\n"); | |
2655 | err = -EINVAL; | |
2656 | goto err_out; | |
2657 | } | |
2658 | ||
2659 | /* get the irq line */ | |
2660 | err = request_irq(priv->irq, talitos_interrupt, 0, | |
2661 | dev_driver_string(dev), dev); | |
2662 | if (err) { | |
2663 | dev_err(dev, "failed to request irq %d\n", priv->irq); | |
2664 | irq_dispose_mapping(priv->irq); | |
2665 | priv->irq = NO_IRQ; | |
2666 | goto err_out; | |
2667 | } | |
2668 | ||
2669 | priv->reg = of_iomap(np, 0); | |
2670 | if (!priv->reg) { | |
2671 | dev_err(dev, "failed to of_iomap\n"); | |
2672 | err = -ENOMEM; | |
2673 | goto err_out; | |
2674 | } | |
2675 | ||
2676 | /* get SEC version capabilities from device tree */ | |
2677 | prop = of_get_property(np, "fsl,num-channels", NULL); | |
2678 | if (prop) | |
2679 | priv->num_channels = *prop; | |
2680 | ||
2681 | prop = of_get_property(np, "fsl,channel-fifo-len", NULL); | |
2682 | if (prop) | |
2683 | priv->chfifo_len = *prop; | |
2684 | ||
2685 | prop = of_get_property(np, "fsl,exec-units-mask", NULL); | |
2686 | if (prop) | |
2687 | priv->exec_units = *prop; | |
2688 | ||
2689 | prop = of_get_property(np, "fsl,descriptor-types-mask", NULL); | |
2690 | if (prop) | |
2691 | priv->desc_types = *prop; | |
2692 | ||
2693 | if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len || | |
2694 | !priv->exec_units || !priv->desc_types) { | |
2695 | dev_err(dev, "invalid property data in device tree node\n"); | |
2696 | err = -EINVAL; | |
2697 | goto err_out; | |
2698 | } | |
2699 | ||
f3c85bc1 LN |
2700 | if (of_device_is_compatible(np, "fsl,sec3.0")) |
2701 | priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT; | |
2702 | ||
fe5720e2 | 2703 | if (of_device_is_compatible(np, "fsl,sec2.1")) |
60f208d7 | 2704 | priv->features |= TALITOS_FTR_HW_AUTH_CHECK | |
79b3a418 LN |
2705 | TALITOS_FTR_SHA224_HWINIT | |
2706 | TALITOS_FTR_HMAC_OK; | |
fe5720e2 | 2707 | |
4b992628 KP |
2708 | priv->chan = kzalloc(sizeof(struct talitos_channel) * |
2709 | priv->num_channels, GFP_KERNEL); | |
2710 | if (!priv->chan) { | |
2711 | dev_err(dev, "failed to allocate channel management space\n"); | |
9c4a7965 KP |
2712 | err = -ENOMEM; |
2713 | goto err_out; | |
2714 | } | |
2715 | ||
ad42d5fc KP |
2716 | for (i = 0; i < priv->num_channels; i++) |
2717 | priv->chan[i].reg = priv->reg + TALITOS_CH_BASE_OFFSET + | |
2718 | TALITOS_CH_STRIDE * (i + 1); | |
2719 | ||
9c4a7965 | 2720 | for (i = 0; i < priv->num_channels; i++) { |
4b992628 KP |
2721 | spin_lock_init(&priv->chan[i].head_lock); |
2722 | spin_lock_init(&priv->chan[i].tail_lock); | |
9c4a7965 KP |
2723 | } |
2724 | ||
2725 | priv->fifo_len = roundup_pow_of_two(priv->chfifo_len); | |
2726 | ||
2727 | for (i = 0; i < priv->num_channels; i++) { | |
4b992628 KP |
2728 | priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) * |
2729 | priv->fifo_len, GFP_KERNEL); | |
2730 | if (!priv->chan[i].fifo) { | |
9c4a7965 KP |
2731 | dev_err(dev, "failed to allocate request fifo %d\n", i); |
2732 | err = -ENOMEM; | |
2733 | goto err_out; | |
2734 | } | |
2735 | } | |
2736 | ||
ec6644d6 | 2737 | for (i = 0; i < priv->num_channels; i++) |
4b992628 KP |
2738 | atomic_set(&priv->chan[i].submit_count, |
2739 | -(priv->chfifo_len - 1)); | |
9c4a7965 | 2740 | |
81eb024c KP |
2741 | dma_set_mask(dev, DMA_BIT_MASK(36)); |
2742 | ||
9c4a7965 KP |
2743 | /* reset and initialize the h/w */ |
2744 | err = init_device(dev); | |
2745 | if (err) { | |
2746 | dev_err(dev, "failed to initialize device\n"); | |
2747 | goto err_out; | |
2748 | } | |
2749 | ||
2750 | /* register the RNG, if available */ | |
2751 | if (hw_supports(dev, DESC_HDR_SEL0_RNG)) { | |
2752 | err = talitos_register_rng(dev); | |
2753 | if (err) { | |
2754 | dev_err(dev, "failed to register hwrng: %d\n", err); | |
2755 | goto err_out; | |
2756 | } else | |
2757 | dev_info(dev, "hwrng\n"); | |
2758 | } | |
2759 | ||
2760 | /* register crypto algorithms the device supports */ | |
9c4a7965 KP |
2761 | for (i = 0; i < ARRAY_SIZE(driver_algs); i++) { |
2762 | if (hw_supports(dev, driver_algs[i].desc_hdr_template)) { | |
2763 | struct talitos_crypto_alg *t_alg; | |
acbf7c62 | 2764 | char *name = NULL; |
9c4a7965 KP |
2765 | |
2766 | t_alg = talitos_alg_alloc(dev, &driver_algs[i]); | |
2767 | if (IS_ERR(t_alg)) { | |
2768 | err = PTR_ERR(t_alg); | |
79b3a418 LN |
2769 | if (err == -ENOTSUPP) { |
2770 | kfree(t_alg); | |
2771 | continue; | |
2772 | } | |
9c4a7965 KP |
2773 | goto err_out; |
2774 | } | |
2775 | ||
acbf7c62 LN |
2776 | switch (t_alg->algt.type) { |
2777 | case CRYPTO_ALG_TYPE_ABLKCIPHER: | |
2778 | case CRYPTO_ALG_TYPE_AEAD: | |
2779 | err = crypto_register_alg( | |
2780 | &t_alg->algt.alg.crypto); | |
2781 | name = t_alg->algt.alg.crypto.cra_driver_name; | |
2782 | break; | |
2783 | case CRYPTO_ALG_TYPE_AHASH: | |
2784 | err = crypto_register_ahash( | |
2785 | &t_alg->algt.alg.hash); | |
2786 | name = | |
2787 | t_alg->algt.alg.hash.halg.base.cra_driver_name; | |
2788 | break; | |
2789 | } | |
9c4a7965 KP |
2790 | if (err) { |
2791 | dev_err(dev, "%s alg registration failed\n", | |
acbf7c62 | 2792 | name); |
9c4a7965 | 2793 | kfree(t_alg); |
5b859b6e | 2794 | } else |
9c4a7965 | 2795 | list_add_tail(&t_alg->entry, &priv->alg_list); |
9c4a7965 KP |
2796 | } |
2797 | } | |
5b859b6e KP |
2798 | if (!list_empty(&priv->alg_list)) |
2799 | dev_info(dev, "%s algorithms registered in /proc/crypto\n", | |
2800 | (char *)of_get_property(np, "compatible", NULL)); | |
9c4a7965 KP |
2801 | |
2802 | return 0; | |
2803 | ||
2804 | err_out: | |
2805 | talitos_remove(ofdev); | |
9c4a7965 KP |
2806 | |
2807 | return err; | |
2808 | } | |
2809 | ||
6c3f975a | 2810 | static const struct of_device_id talitos_match[] = { |
9c4a7965 KP |
2811 | { |
2812 | .compatible = "fsl,sec2.0", | |
2813 | }, | |
2814 | {}, | |
2815 | }; | |
2816 | MODULE_DEVICE_TABLE(of, talitos_match); | |
2817 | ||
1c48a5c9 | 2818 | static struct platform_driver talitos_driver = { |
4018294b GL |
2819 | .driver = { |
2820 | .name = "talitos", | |
2821 | .owner = THIS_MODULE, | |
2822 | .of_match_table = talitos_match, | |
2823 | }, | |
9c4a7965 | 2824 | .probe = talitos_probe, |
596f1034 | 2825 | .remove = talitos_remove, |
9c4a7965 KP |
2826 | }; |
2827 | ||
2828 | static int __init talitos_init(void) | |
2829 | { | |
1c48a5c9 | 2830 | return platform_driver_register(&talitos_driver); |
9c4a7965 KP |
2831 | } |
2832 | module_init(talitos_init); | |
2833 | ||
2834 | static void __exit talitos_exit(void) | |
2835 | { | |
1c48a5c9 | 2836 | platform_driver_unregister(&talitos_driver); |
9c4a7965 KP |
2837 | } |
2838 | module_exit(talitos_exit); | |
2839 | ||
2840 | MODULE_LICENSE("GPL"); | |
2841 | MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>"); | |
2842 | MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver"); |