[mirror_ubuntu-kernels.git] / drivers / cxl / cxlpci.h

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
#ifndef __CXL_PCI_H__
#define __CXL_PCI_H__
#include <linux/pci.h>
#include "cxl.h"

#define CXL_MEMORY_PROGIF	0x10

/*
 * See section 8.1 Configuration Space Registers in the CXL 2.0
 * Specification. Names are taken straight from the specification with "CXL" and
 * "DVSEC" redundancies removed. When obvious, abbreviations may be used.
 */
#define PCI_DVSEC_HEADER1_LENGTH_MASK	GENMASK(31, 20)
#define PCI_DVSEC_VENDOR_ID_CXL		0x1E98

/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
#define CXL_DVSEC_PCIE_DEVICE					0
#define   CXL_DVSEC_CAP_OFFSET		0xA
#define     CXL_DVSEC_MEM_CAPABLE	BIT(2)
#define     CXL_DVSEC_HDM_COUNT_MASK	GENMASK(5, 4)
#define   CXL_DVSEC_CTRL_OFFSET		0xC
#define     CXL_DVSEC_MEM_ENABLE	BIT(2)
#define   CXL_DVSEC_RANGE_SIZE_HIGH(i)	(0x18 + (i * 0x10))
#define   CXL_DVSEC_RANGE_SIZE_LOW(i)	(0x1C + (i * 0x10))
#define     CXL_DVSEC_MEM_INFO_VALID	BIT(0)
#define     CXL_DVSEC_MEM_ACTIVE	BIT(1)
#define     CXL_DVSEC_MEM_SIZE_LOW_MASK	GENMASK(31, 28)
#define   CXL_DVSEC_RANGE_BASE_HIGH(i)	(0x20 + (i * 0x10))
#define   CXL_DVSEC_RANGE_BASE_LOW(i)	(0x24 + (i * 0x10))
#define     CXL_DVSEC_MEM_BASE_LOW_MASK	GENMASK(31, 28)

/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
#define CXL_DVSEC_FUNCTION_MAP					2

/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
#define CXL_DVSEC_PORT_EXTENSIONS				3

/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
#define CXL_DVSEC_PORT_GPF					4

/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
#define CXL_DVSEC_DEVICE_GPF					5

/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
#define CXL_DVSEC_PCIE_FLEXBUS_PORT				7

/* CXL 2.0 8.1.9: Register Locator DVSEC */
#define CXL_DVSEC_REG_LOCATOR					8
#define   CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET			0xC
#define     CXL_DVSEC_REG_LOCATOR_BIR_MASK			GENMASK(2, 0)
#define	    CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK			GENMASK(15, 8)
#define     CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK		GENMASK(31, 16)

/* Register Block Identifier (RBI) */
enum cxl_regloc_type {
	CXL_REGLOC_RBI_EMPTY = 0,
	CXL_REGLOC_RBI_COMPONENT,
	CXL_REGLOC_RBI_VIRT,
	CXL_REGLOC_RBI_MEMDEV,
	CXL_REGLOC_RBI_TYPES
};

static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
						 struct cxl_register_map *map)
{
	if (map->block_offset == U64_MAX)
		return CXL_RESOURCE_NONE;

	return pci_resource_start(pdev, map->barno) + map->block_offset;
}

int devm_cxl_port_enumerate_dports(struct cxl_port *port);
struct cxl_dev_state;
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
#endif /* __CXL_PCI_H__ */
Commit	Line	Data
4cdadfd5 DW	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
	3	#ifndef __CXL_PCI_H__
	4	#define __CXL_PCI_H__
54cdbf84	5	#include <linux/pci.h>
af9cae9f	6	#include "cxl.h"
4cdadfd5 DW	7
	8	#define CXL_MEMORY_PROGIF 0x10
	9
	10	/*
	11	* See section 8.1 Configuration Space Registers in the CXL 2.0
46c6ad27 BW	12	* Specification. Names are taken straight from the specification with "CXL" and
46c6ad27 BW	13	* "DVSEC" redundancies removed. When obvious, abbreviations may be used.
4cdadfd5	14	*/
8adaf747	15	#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20)
4cdadfd5	16	#define PCI_DVSEC_VENDOR_ID_CXL 0x1E98
4cdadfd5	17
46c6ad27 BW	18	/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
46c6ad27 BW	19	#define CXL_DVSEC_PCIE_DEVICE 0
560f7855 BW	20	#define CXL_DVSEC_CAP_OFFSET 0xA
	21	#define CXL_DVSEC_MEM_CAPABLE BIT(2)
	22	#define CXL_DVSEC_HDM_COUNT_MASK GENMASK(5, 4)
	23	#define CXL_DVSEC_CTRL_OFFSET 0xC
	24	#define CXL_DVSEC_MEM_ENABLE BIT(2)
	25	#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
	26	#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))
	27	#define CXL_DVSEC_MEM_INFO_VALID BIT(0)
	28	#define CXL_DVSEC_MEM_ACTIVE BIT(1)
	29	#define CXL_DVSEC_MEM_SIZE_LOW_MASK GENMASK(31, 28)
	30	#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
	31	#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10))
	32	#define CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28)
8adaf747	33
8baa787b BW	34	/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
	35	#define CXL_DVSEC_FUNCTION_MAP 2
	36
	37	/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
	38	#define CXL_DVSEC_PORT_EXTENSIONS 3
	39
	40	/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
	41	#define CXL_DVSEC_PORT_GPF 4
	42
	43	/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
	44	#define CXL_DVSEC_DEVICE_GPF 5
	45
	46	/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
	47	#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7
	48
46c6ad27 BW	49	/* CXL 2.0 8.1.9: Register Locator DVSEC */
	50	#define CXL_DVSEC_REG_LOCATOR 8
	51	#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC
	52	#define CXL_DVSEC_REG_LOCATOR_BIR_MASK GENMASK(2, 0)
	53	#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8)
	54	#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16)
8adaf747 BW	55
8adaf747 BW	56	/* Register Block Identifier (RBI) */
cdcce47c BW	57	enum cxl_regloc_type {
	58	CXL_REGLOC_RBI_EMPTY = 0,
	59	CXL_REGLOC_RBI_COMPONENT,
	60	CXL_REGLOC_RBI_VIRT,
	61	CXL_REGLOC_RBI_MEMDEV,
	62	CXL_REGLOC_RBI_TYPES
	63	};
8adaf747	64
303ebc1b BW	65	static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
	66	struct cxl_register_map *map)
	67	{
	68	if (map->block_offset == U64_MAX)
	69	return CXL_RESOURCE_NONE;
	70
	71	return pci_resource_start(pdev, map->barno) + map->block_offset;
	72	}
	73
664bf115	74	int devm_cxl_port_enumerate_dports(struct cxl_port *port);
14d78874	75	struct cxl_dev_state;
fcfbc93c	76	int cxl_hdm_decode_init(struct cxl_dev_state cxlds, struct cxl_hdm cxlhdm);
4cdadfd5	77	#endif /* __CXL_PCI_H__ */