[mirror_ubuntu-jammy-kernel.git] / drivers / devfreq / rk3399_dmc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
 * Author: Lin Huang <hl@rock-chips.com>
 */

#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/devfreq.h>
#include <linux/devfreq-event.h>
#include <linux/interrupt.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/rwsem.h>
#include <linux/suspend.h>

#include <soc/rockchip/rk3399_grf.h>
#include <soc/rockchip/rockchip_sip.h>

struct dram_timing {
	unsigned int ddr3_speed_bin;
	unsigned int pd_idle;
	unsigned int sr_idle;
	unsigned int sr_mc_gate_idle;
	unsigned int srpd_lite_idle;
	unsigned int standby_idle;
	unsigned int auto_pd_dis_freq;
	unsigned int dram_dll_dis_freq;
	unsigned int phy_dll_dis_freq;
	unsigned int ddr3_odt_dis_freq;
	unsigned int ddr3_drv;
	unsigned int ddr3_odt;
	unsigned int phy_ddr3_ca_drv;
	unsigned int phy_ddr3_dq_drv;
	unsigned int phy_ddr3_odt;
	unsigned int lpddr3_odt_dis_freq;
	unsigned int lpddr3_drv;
	unsigned int lpddr3_odt;
	unsigned int phy_lpddr3_ca_drv;
	unsigned int phy_lpddr3_dq_drv;
	unsigned int phy_lpddr3_odt;
	unsigned int lpddr4_odt_dis_freq;
	unsigned int lpddr4_drv;
	unsigned int lpddr4_dq_odt;
	unsigned int lpddr4_ca_odt;
	unsigned int phy_lpddr4_ca_drv;
	unsigned int phy_lpddr4_ck_cs_drv;
	unsigned int phy_lpddr4_dq_drv;
	unsigned int phy_lpddr4_odt;
};

struct rk3399_dmcfreq {
	struct device *dev;
	struct devfreq *devfreq;
	struct devfreq_simple_ondemand_data ondemand_data;
	struct clk *dmc_clk;
	struct devfreq_event_dev *edev;
	struct mutex lock;
	struct dram_timing timing;
	struct regulator *vdd_center;
	struct regmap *regmap_pmu;
	unsigned long rate, target_rate;
	unsigned long volt, target_volt;
	unsigned int odt_dis_freq;
	int odt_pd_arg0, odt_pd_arg1;
};

static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
				 u32 flags)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	struct dev_pm_opp *opp;
	unsigned long old_clk_rate = dmcfreq->rate;
	unsigned long target_volt, target_rate;
	struct arm_smccc_res res;
	bool odt_enable = false;
	int err;

	opp = devfreq_recommended_opp(dev, freq, flags);
	if (IS_ERR(opp))
		return PTR_ERR(opp);

	target_rate = dev_pm_opp_get_freq(opp);
	target_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	if (dmcfreq->rate == target_rate)
		return 0;

	mutex_lock(&dmcfreq->lock);

	if (target_rate >= dmcfreq->odt_dis_freq)
		odt_enable = true;

	/*
	 * This makes a SMC call to the TF-A to set the DDR PD (power-down)
	 * timings and to enable or disable the ODT (on-die termination)
	 * resistors.
	 */
	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
		      dmcfreq->odt_pd_arg1,
		      ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
		      odt_enable, 0, 0, 0, &res);

	/*
	 * If frequency scaling from low to high, adjust voltage first.
	 * If frequency scaling from high to low, adjust frequency first.
	 */
	if (old_clk_rate < target_rate) {
		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
					    target_volt);
		if (err) {
			dev_err(dev, "Cannot set voltage %lu uV\n",
				target_volt);
			goto out;
		}
	}

	err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
	if (err) {
		dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
			err);
		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
				      dmcfreq->volt);
		goto out;
	}

	/*
	 * Check the dpll rate,
	 * There only two result we will get,
	 * 1. Ddr frequency scaling fail, we still get the old rate.
	 * 2. Ddr frequency scaling sucessful, we get the rate we set.
	 */
	dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);

	/* If get the incorrect rate, set voltage to old value. */
	if (dmcfreq->rate != target_rate) {
		dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
			target_rate, dmcfreq->rate);
		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
				      dmcfreq->volt);
		goto out;
	} else if (old_clk_rate > target_rate)
		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
					    target_volt);
	if (err)
		dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);

	dmcfreq->rate = target_rate;
	dmcfreq->volt = target_volt;

out:
	mutex_unlock(&dmcfreq->lock);
	return err;
}

static int rk3399_dmcfreq_get_dev_status(struct device *dev,
					 struct devfreq_dev_status *stat)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	struct devfreq_event_data edata;
	int ret = 0;

	ret = devfreq_event_get_event(dmcfreq->edev, &edata);
	if (ret < 0)
		return ret;

	stat->current_frequency = dmcfreq->rate;
	stat->busy_time = edata.load_count;
	stat->total_time = edata.total_count;

	return ret;
}

static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);

	*freq = dmcfreq->rate;

	return 0;
}

static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
	.polling_ms	= 200,
	.target		= rk3399_dmcfreq_target,
	.get_dev_status	= rk3399_dmcfreq_get_dev_status,
	.get_cur_freq	= rk3399_dmcfreq_get_cur_freq,
};

static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	int ret = 0;

	ret = devfreq_event_disable_edev(dmcfreq->edev);
	if (ret < 0) {
		dev_err(dev, "failed to disable the devfreq-event devices\n");
		return ret;
	}

	ret = devfreq_suspend_device(dmcfreq->devfreq);
	if (ret < 0) {
		dev_err(dev, "failed to suspend the devfreq devices\n");
		return ret;
	}

	return 0;
}

static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	int ret = 0;

	ret = devfreq_event_enable_edev(dmcfreq->edev);
	if (ret < 0) {
		dev_err(dev, "failed to enable the devfreq-event devices\n");
		return ret;
	}

	ret = devfreq_resume_device(dmcfreq->devfreq);
	if (ret < 0) {
		dev_err(dev, "failed to resume the devfreq devices\n");
		return ret;
	}
	return ret;
}

static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
			 rk3399_dmcfreq_resume);

static int of_get_ddr_timings(struct dram_timing *timing,
			      struct device_node *np)
{
	int ret = 0;

	ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
				   &timing->ddr3_speed_bin);
	ret |= of_property_read_u32(np, "rockchip,pd_idle",
				    &timing->pd_idle);
	ret |= of_property_read_u32(np, "rockchip,sr_idle",
				    &timing->sr_idle);
	ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
				    &timing->sr_mc_gate_idle);
	ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
				    &timing->srpd_lite_idle);
	ret |= of_property_read_u32(np, "rockchip,standby_idle",
				    &timing->standby_idle);
	ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
				    &timing->auto_pd_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
				    &timing->dram_dll_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
				    &timing->phy_dll_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
				    &timing->ddr3_odt_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
				    &timing->ddr3_drv);
	ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
				    &timing->ddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
				    &timing->phy_ddr3_ca_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
				    &timing->phy_ddr3_dq_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
				    &timing->phy_ddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
				    &timing->lpddr3_odt_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
				    &timing->lpddr3_drv);
	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
				    &timing->lpddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
				    &timing->phy_lpddr3_ca_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
				    &timing->phy_lpddr3_dq_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
				    &timing->phy_lpddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
				    &timing->lpddr4_odt_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
				    &timing->lpddr4_drv);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
				    &timing->lpddr4_dq_odt);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
				    &timing->lpddr4_ca_odt);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
				    &timing->phy_lpddr4_ca_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
				    &timing->phy_lpddr4_ck_cs_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
				    &timing->phy_lpddr4_dq_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
				    &timing->phy_lpddr4_odt);

	return ret;
}

static int rk3399_dmcfreq_probe(struct platform_device *pdev)
{
	struct arm_smccc_res res;
	struct device *dev = &pdev->dev;
	struct device_node *np = pdev->dev.of_node, *node;
	struct rk3399_dmcfreq *data;
	int ret, index, size;
	uint32_t *timing;
	struct dev_pm_opp *opp;
	u32 ddr_type;
	u32 val;

	data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	mutex_init(&data->lock);

	data->vdd_center = devm_regulator_get(dev, "center");
	if (IS_ERR(data->vdd_center)) {
		if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)
			return -EPROBE_DEFER;

		dev_err(dev, "Cannot get the regulator \"center\"\n");
		return PTR_ERR(data->vdd_center);
	}

	data->dmc_clk = devm_clk_get(dev, "dmc_clk");
	if (IS_ERR(data->dmc_clk)) {
		if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
			return -EPROBE_DEFER;

		dev_err(dev, "Cannot get the clk dmc_clk\n");
		return PTR_ERR(data->dmc_clk);
	}

	data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
	if (IS_ERR(data->edev))
		return -EPROBE_DEFER;

	ret = devfreq_event_enable_edev(data->edev);
	if (ret < 0) {
		dev_err(dev, "failed to enable devfreq-event devices\n");
		return ret;
	}

	/*
	 * Get dram timing and pass it to arm trust firmware,
	 * the dram driver in arm trust firmware will get these
	 * timing and to do dram initial.
	 */
	if (!of_get_ddr_timings(&data->timing, np)) {
		timing = &data->timing.ddr3_speed_bin;
		size = sizeof(struct dram_timing) / 4;
		for (index = 0; index < size; index++) {
			arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
				      ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
				      0, 0, 0, 0, &res);
			if (res.a0) {
				dev_err(dev, "Failed to set dram param: %ld\n",
					res.a0);
				ret = -EINVAL;
				goto err_edev;
			}
		}
	}

	node = of_parse_phandle(np, "rockchip,pmu", 0);
	if (node) {
		data->regmap_pmu = syscon_node_to_regmap(node);
		of_node_put(node);
		if (IS_ERR(data->regmap_pmu)) {
			ret = PTR_ERR(data->regmap_pmu);
			goto err_edev;
		}
	}

	regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
	ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
		    RK3399_PMUGRF_DDRTYPE_MASK;

	switch (ddr_type) {
	case RK3399_PMUGRF_DDRTYPE_DDR3:
		data->odt_dis_freq = data->timing.ddr3_odt_dis_freq;
		break;
	case RK3399_PMUGRF_DDRTYPE_LPDDR3:
		data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq;
		break;
	case RK3399_PMUGRF_DDRTYPE_LPDDR4:
		data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq;
		break;
	default:
		ret = -EINVAL;
		goto err_edev;
	};

	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
		      ROCKCHIP_SIP_CONFIG_DRAM_INIT,
		      0, 0, 0, 0, &res);

	/*
	 * In TF-A there is a platform SIP call to set the PD (power-down)
	 * timings and to enable or disable the ODT (on-die termination).
	 * This call needs three arguments as follows:
	 *
	 * arg0:
	 *     bit[0-7]   : sr_idle
	 *     bit[8-15]  : sr_mc_gate_idle
	 *     bit[16-31] : standby idle
	 * arg1:
	 *     bit[0-11]  : pd_idle
	 *     bit[16-27] : srpd_lite_idle
	 * arg2:
	 *     bit[0]     : odt enable
	 */
	data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) |
			    ((data->timing.sr_mc_gate_idle & 0xff) << 8) |
			    ((data->timing.standby_idle & 0xffff) << 16);
	data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) |
			    ((data->timing.srpd_lite_idle & 0xfff) << 16);

	/*
	 * We add a devfreq driver to our parent since it has a device tree node
	 * with operating points.
	 */
	if (dev_pm_opp_of_add_table(dev)) {
		dev_err(dev, "Invalid operating-points in device tree.\n");
		ret = -EINVAL;
		goto err_edev;
	}

	of_property_read_u32(np, "upthreshold",
			     &data->ondemand_data.upthreshold);
	of_property_read_u32(np, "downdifferential",
			     &data->ondemand_data.downdifferential);

	data->rate = clk_get_rate(data->dmc_clk);

	opp = devfreq_recommended_opp(dev, &data->rate, 0);
	if (IS_ERR(opp)) {
		ret = PTR_ERR(opp);
		goto err_free_opp;
	}

	data->rate = dev_pm_opp_get_freq(opp);
	data->volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	rk3399_devfreq_dmc_profile.initial_freq = data->rate;

	data->devfreq = devm_devfreq_add_device(dev,
					   &rk3399_devfreq_dmc_profile,
					   DEVFREQ_GOV_SIMPLE_ONDEMAND,
					   &data->ondemand_data);
	if (IS_ERR(data->devfreq)) {
		ret = PTR_ERR(data->devfreq);
		goto err_free_opp;
	}

	devm_devfreq_register_opp_notifier(dev, data->devfreq);

	data->dev = dev;
	platform_set_drvdata(pdev, data);

	return 0;

err_free_opp:
	dev_pm_opp_of_remove_table(&pdev->dev);
err_edev:
	devfreq_event_disable_edev(data->edev);

	return ret;
}

static int rk3399_dmcfreq_remove(struct platform_device *pdev)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);

	/*
	 * Before remove the opp table we need to unregister the opp notifier.
	 */
	devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);
	dev_pm_opp_of_remove_table(dmcfreq->dev);

	return 0;
}

static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
	{ .compatible = "rockchip,rk3399-dmc" },
	{ },
};
MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);

static struct platform_driver rk3399_dmcfreq_driver = {
	.probe	= rk3399_dmcfreq_probe,
	.remove = rk3399_dmcfreq_remove,
	.driver = {
		.name	= "rk3399-dmc-freq",
		.pm	= &rk3399_dmcfreq_pm,
		.of_match_table = rk3399dmc_devfreq_of_match,
	},
};
module_platform_driver(rk3399_dmcfreq_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");
Commit	Line	Data
2025cf9e	1	// SPDX-License-Identifier: GPL-2.0-only
5a893e31 LH	2	/*
	3	* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
	4	* Author: Lin Huang <hl@rock-chips.com>
5a893e31 LH	5	*/
	6
	7	#include <linux/arm-smccc.h>
	8	#include <linux/clk.h>
	9	#include <linux/delay.h>
	10	#include <linux/devfreq.h>
	11	#include <linux/devfreq-event.h>
	12	#include <linux/interrupt.h>
9173c5ce	13	#include <linux/mfd/syscon.h>
5a893e31 LH	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/pm_opp.h>
9173c5ce	18	#include <linux/regmap.h>
5a893e31 LH	19	#include <linux/regulator/consumer.h>
	20	#include <linux/rwsem.h>
	21	#include <linux/suspend.h>
	22
9173c5ce	23	#include <soc/rockchip/rk3399_grf.h>
5a893e31 LH	24	#include <soc/rockchip/rockchip_sip.h>
	25
	26	struct dram_timing {
	27	unsigned int ddr3_speed_bin;
	28	unsigned int pd_idle;
	29	unsigned int sr_idle;
	30	unsigned int sr_mc_gate_idle;
	31	unsigned int srpd_lite_idle;
	32	unsigned int standby_idle;
	33	unsigned int auto_pd_dis_freq;
	34	unsigned int dram_dll_dis_freq;
	35	unsigned int phy_dll_dis_freq;
	36	unsigned int ddr3_odt_dis_freq;
	37	unsigned int ddr3_drv;
	38	unsigned int ddr3_odt;
	39	unsigned int phy_ddr3_ca_drv;
	40	unsigned int phy_ddr3_dq_drv;
	41	unsigned int phy_ddr3_odt;
	42	unsigned int lpddr3_odt_dis_freq;
	43	unsigned int lpddr3_drv;
	44	unsigned int lpddr3_odt;
	45	unsigned int phy_lpddr3_ca_drv;
	46	unsigned int phy_lpddr3_dq_drv;
	47	unsigned int phy_lpddr3_odt;
	48	unsigned int lpddr4_odt_dis_freq;
	49	unsigned int lpddr4_drv;
	50	unsigned int lpddr4_dq_odt;
	51	unsigned int lpddr4_ca_odt;
	52	unsigned int phy_lpddr4_ca_drv;
	53	unsigned int phy_lpddr4_ck_cs_drv;
	54	unsigned int phy_lpddr4_dq_drv;
	55	unsigned int phy_lpddr4_odt;
	56	};
	57
	58	struct rk3399_dmcfreq {
	59	struct device *dev;
	60	struct devfreq *devfreq;
	61	struct devfreq_simple_ondemand_data ondemand_data;
	62	struct clk *dmc_clk;
	63	struct devfreq_event_dev *edev;
	64	struct mutex lock;
	65	struct dram_timing timing;
5a893e31	66	struct regulator *vdd_center;
9173c5ce	67	struct regmap *regmap_pmu;
5a893e31 LH	68	unsigned long rate, target_rate;
5a893e31 LH	69	unsigned long volt, target_volt;
9173c5ce EBS	70	unsigned int odt_dis_freq;
9173c5ce EBS	71	int odt_pd_arg0, odt_pd_arg1;
5a893e31 LH	72	};
	73
	74	static int rk3399_dmcfreq_target(struct device dev, unsigned long freq,
	75	u32 flags)
	76	{
	77	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	78	struct dev_pm_opp *opp;
	79	unsigned long old_clk_rate = dmcfreq->rate;
	80	unsigned long target_volt, target_rate;
9173c5ce EBS	81	struct arm_smccc_res res;
9173c5ce EBS	82	bool odt_enable = false;
5a893e31 LH	83	int err;
5a893e31 LH	84
5a893e31	85	opp = devfreq_recommended_opp(dev, freq, flags);
8a31d9d9	86	if (IS_ERR(opp))
5a893e31	87	return PTR_ERR(opp);
5a893e31 LH	88
	89	target_rate = dev_pm_opp_get_freq(opp);
	90	target_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9	91	dev_pm_opp_put(opp);
5a893e31 LH	92
	93	if (dmcfreq->rate == target_rate)
	94	return 0;
	95
	96	mutex_lock(&dmcfreq->lock);
	97
9173c5ce EBS	98	if (target_rate >= dmcfreq->odt_dis_freq)
	99	odt_enable = true;
	100
	101	/*
	102	* This makes a SMC call to the TF-A to set the DDR PD (power-down)
	103	* timings and to enable or disable the ODT (on-die termination)
	104	* resistors.
	105	*/
	106	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
	107	dmcfreq->odt_pd_arg1,
	108	ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
	109	odt_enable, 0, 0, 0, &res);
	110
5a893e31 LH	111	/*
	112	* If frequency scaling from low to high, adjust voltage first.
	113	* If frequency scaling from high to low, adjust frequency first.
	114	*/
	115	if (old_clk_rate < target_rate) {
	116	err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
	117	target_volt);
	118	if (err) {
dfa7d764	119	dev_err(dev, "Cannot set voltage %lu uV\n",
5a893e31 LH	120	target_volt);
	121	goto out;
	122	}
	123	}
5a893e31 LH	124
	125	err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
	126	if (err) {
dfa7d764 EBS	127	dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
dfa7d764 EBS	128	err);
5a893e31 LH	129	regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
	130	dmcfreq->volt);
	131	goto out;
	132	}
	133
5a893e31 LH	134	/*
	135	* Check the dpll rate,
	136	* There only two result we will get,
	137	* 1. Ddr frequency scaling fail, we still get the old rate.
	138	* 2. Ddr frequency scaling sucessful, we get the rate we set.
	139	*/
	140	dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
	141
	142	/* If get the incorrect rate, set voltage to old value. */
	143	if (dmcfreq->rate != target_rate) {
dfa7d764 EBS	144	dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
dfa7d764 EBS	145	target_rate, dmcfreq->rate);
5a893e31 LH	146	regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
	147	dmcfreq->volt);
	148	goto out;
	149	} else if (old_clk_rate > target_rate)
	150	err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
	151	target_volt);
	152	if (err)
dfa7d764	153	dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
5a893e31	154
e37d3508 VK	155	dmcfreq->rate = target_rate;
	156	dmcfreq->volt = target_volt;
	157
5a893e31 LH	158	out:
	159	mutex_unlock(&dmcfreq->lock);
	160	return err;
	161	}
	162
	163	static int rk3399_dmcfreq_get_dev_status(struct device *dev,
	164	struct devfreq_dev_status *stat)
	165	{
	166	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	167	struct devfreq_event_data edata;
	168	int ret = 0;
	169
	170	ret = devfreq_event_get_event(dmcfreq->edev, &edata);
	171	if (ret < 0)
	172	return ret;
	173
	174	stat->current_frequency = dmcfreq->rate;
	175	stat->busy_time = edata.load_count;
	176	stat->total_time = edata.total_count;
	177
	178	return ret;
	179	}
	180
	181	static int rk3399_dmcfreq_get_cur_freq(struct device dev, unsigned long freq)
	182	{
	183	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	184
	185	*freq = dmcfreq->rate;
	186
	187	return 0;
	188	}
	189
	190	static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
	191	.polling_ms = 200,
	192	.target = rk3399_dmcfreq_target,
	193	.get_dev_status = rk3399_dmcfreq_get_dev_status,
	194	.get_cur_freq = rk3399_dmcfreq_get_cur_freq,
	195	};
	196
	197	static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
	198	{
	199	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	200	int ret = 0;
	201
	202	ret = devfreq_event_disable_edev(dmcfreq->edev);
	203	if (ret < 0) {
	204	dev_err(dev, "failed to disable the devfreq-event devices\n");
	205	return ret;
	206	}
	207
	208	ret = devfreq_suspend_device(dmcfreq->devfreq);
	209	if (ret < 0) {
	210	dev_err(dev, "failed to suspend the devfreq devices\n");
	211	return ret;
	212	}
	213
	214	return 0;
	215	}
	216
	217	static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
	218	{
	219	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	220	int ret = 0;
	221
222	ret = devfreq_event_enable_edev(dmcfreq->edev);
223	if (ret < 0) {
224	dev_err(dev, "failed to enable the devfreq-event devices\n");
225	return ret;
226	}
227
228	ret = devfreq_resume_device(dmcfreq->devfreq);
229	if (ret < 0) {
230	dev_err(dev, "failed to resume the devfreq devices\n");
231	return ret;
232	}
233	return ret;
234	}
235
236	static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
237	rk3399_dmcfreq_resume);
238
5a893e31 LH	239	static int of_get_ddr_timings(struct dram_timing *timing,
	240	struct device_node *np)
	241	{
	242	int ret = 0;
	243
	244	ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
	245	&timing->ddr3_speed_bin);
	246	ret \|= of_property_read_u32(np, "rockchip,pd_idle",
	247	&timing->pd_idle);
	248	ret \|= of_property_read_u32(np, "rockchip,sr_idle",
	249	&timing->sr_idle);
	250	ret \|= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
	251	&timing->sr_mc_gate_idle);
	252	ret \|= of_property_read_u32(np, "rockchip,srpd_lite_idle",
	253	&timing->srpd_lite_idle);
	254	ret \|= of_property_read_u32(np, "rockchip,standby_idle",
	255	&timing->standby_idle);
	256	ret \|= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
	257	&timing->auto_pd_dis_freq);
	258	ret \|= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
	259	&timing->dram_dll_dis_freq);
	260	ret \|= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
	261	&timing->phy_dll_dis_freq);
	262	ret \|= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
	263	&timing->ddr3_odt_dis_freq);
	264	ret \|= of_property_read_u32(np, "rockchip,ddr3_drv",
	265	&timing->ddr3_drv);
	266	ret \|= of_property_read_u32(np, "rockchip,ddr3_odt",
	267	&timing->ddr3_odt);
	268	ret \|= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
	269	&timing->phy_ddr3_ca_drv);
	270	ret \|= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
	271	&timing->phy_ddr3_dq_drv);
	272	ret \|= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
	273	&timing->phy_ddr3_odt);
	274	ret \|= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
	275	&timing->lpddr3_odt_dis_freq);
	276	ret \|= of_property_read_u32(np, "rockchip,lpddr3_drv",
	277	&timing->lpddr3_drv);
	278	ret \|= of_property_read_u32(np, "rockchip,lpddr3_odt",
	279	&timing->lpddr3_odt);
	280	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
	281	&timing->phy_lpddr3_ca_drv);
	282	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
	283	&timing->phy_lpddr3_dq_drv);
	284	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
	285	&timing->phy_lpddr3_odt);
	286	ret \|= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
	287	&timing->lpddr4_odt_dis_freq);
	288	ret \|= of_property_read_u32(np, "rockchip,lpddr4_drv",
	289	&timing->lpddr4_drv);
	290	ret \|= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
	291	&timing->lpddr4_dq_odt);
	292	ret \|= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
	293	&timing->lpddr4_ca_odt);
	294	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
	295	&timing->phy_lpddr4_ca_drv);
	296	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
	297	&timing->phy_lpddr4_ck_cs_drv);
	298	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
	299	&timing->phy_lpddr4_dq_drv);
	300	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
	301	&timing->phy_lpddr4_odt);
	302
303	return ret;
304	}
305
306	static int rk3399_dmcfreq_probe(struct platform_device *pdev)
307	{
308	struct arm_smccc_res res;
309	struct device *dev = &pdev->dev;
9173c5ce	310	struct device_node np = pdev->dev.of_node, node;
5a893e31	311	struct rk3399_dmcfreq *data;
90dd72e1	312	int ret, index, size;
5a893e31 LH	313	uint32_t *timing;
5a893e31 LH	314	struct dev_pm_opp *opp;
9173c5ce EBS	315	u32 ddr_type;
9173c5ce EBS	316	u32 val;
5a893e31	317
5a893e31 LH	318	data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
	319	if (!data)
	320	return -ENOMEM;
	321
	322	mutex_init(&data->lock);
	323
	324	data->vdd_center = devm_regulator_get(dev, "center");
	325	if (IS_ERR(data->vdd_center)) {
49edc523 LH	326	if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)
	327	return -EPROBE_DEFER;
	328
5a893e31 LH	329	dev_err(dev, "Cannot get the regulator \"center\"\n");
	330	return PTR_ERR(data->vdd_center);
	331	}
	332
	333	data->dmc_clk = devm_clk_get(dev, "dmc_clk");
	334	if (IS_ERR(data->dmc_clk)) {
49edc523 LH	335	if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
	336	return -EPROBE_DEFER;
	337
5a893e31 LH	338	dev_err(dev, "Cannot get the clk dmc_clk\n");
5a893e31 LH	339	return PTR_ERR(data->dmc_clk);
e2794d74	340	}
5a893e31	341
5a893e31 LH	342	data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
	343	if (IS_ERR(data->edev))
	344	return -EPROBE_DEFER;
	345
	346	ret = devfreq_event_enable_edev(data->edev);
	347	if (ret < 0) {
	348	dev_err(dev, "failed to enable devfreq-event devices\n");
	349	return ret;
	350	}
	351
	352	/*
	353	* Get dram timing and pass it to arm trust firmware,
0a453aca	354	* the dram driver in arm trust firmware will get these
5a893e31 LH	355	* timing and to do dram initial.
	356	*/
	357	if (!of_get_ddr_timings(&data->timing, np)) {
	358	timing = &data->timing.ddr3_speed_bin;
	359	size = sizeof(struct dram_timing) / 4;
	360	for (index = 0; index < size; index++) {
	361	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
	362	ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
	363	0, 0, 0, 0, &res);
	364	if (res.a0) {
	365	dev_err(dev, "Failed to set dram param: %ld\n",
	366	res.a0);
39a6e473 YL	367	ret = -EINVAL;
39a6e473 YL	368	goto err_edev;
5a893e31 LH	369	}
	370	}
	371	}
	372
9173c5ce EBS	373	node = of_parse_phandle(np, "rockchip,pmu", 0);
	374	if (node) {
	375	data->regmap_pmu = syscon_node_to_regmap(node);
29d867e9	376	of_node_put(node);
39a6e473 YL	377	if (IS_ERR(data->regmap_pmu)) {
	378	ret = PTR_ERR(data->regmap_pmu);
	379	goto err_edev;
	380	}
9173c5ce EBS	381	}
	382
	383	regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
	384	ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
	385	RK3399_PMUGRF_DDRTYPE_MASK;
	386
	387	switch (ddr_type) {
	388	case RK3399_PMUGRF_DDRTYPE_DDR3:
	389	data->odt_dis_freq = data->timing.ddr3_odt_dis_freq;
	390	break;
	391	case RK3399_PMUGRF_DDRTYPE_LPDDR3:
	392	data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq;
	393	break;
	394	case RK3399_PMUGRF_DDRTYPE_LPDDR4:
	395	data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq;
	396	break;
	397	default:
39a6e473 YL	398	ret = -EINVAL;
39a6e473 YL	399	goto err_edev;
9173c5ce EBS	400	};
9173c5ce EBS	401
5a893e31 LH	402	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
	403	ROCKCHIP_SIP_CONFIG_DRAM_INIT,
	404	0, 0, 0, 0, &res);
	405
9173c5ce EBS	406	/*
	407	* In TF-A there is a platform SIP call to set the PD (power-down)
	408	* timings and to enable or disable the ODT (on-die termination).
	409	* This call needs three arguments as follows:
	410	*
	411	* arg0:
	412	* bit[0-7] : sr_idle
	413	* bit[8-15] : sr_mc_gate_idle
	414	* bit[16-31] : standby idle
	415	* arg1:
	416	* bit[0-11] : pd_idle
	417	* bit[16-27] : srpd_lite_idle
	418	* arg2:
	419	* bit[0] : odt enable
	420	*/
	421	data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) \|
	422	((data->timing.sr_mc_gate_idle & 0xff) << 8) \|
	423	((data->timing.standby_idle & 0xffff) << 16);
	424	data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) \|
	425	((data->timing.srpd_lite_idle & 0xfff) << 16);
	426
5a893e31 LH	427	/*
	428	* We add a devfreq driver to our parent since it has a device tree node
	429	* with operating points.
	430	*/
	431	if (dev_pm_opp_of_add_table(dev)) {
	432	dev_err(dev, "Invalid operating-points in device tree.\n");
39a6e473 YL	433	ret = -EINVAL;
39a6e473 YL	434	goto err_edev;
5a893e31 LH	435	}
	436
	437	of_property_read_u32(np, "upthreshold",
	438	&data->ondemand_data.upthreshold);
	439	of_property_read_u32(np, "downdifferential",
	440	&data->ondemand_data.downdifferential);
	441
	442	data->rate = clk_get_rate(data->dmc_clk);
	443
5a893e31	444	opp = devfreq_recommended_opp(dev, &data->rate, 0);
d6e98f3e EBS	445	if (IS_ERR(opp)) {
	446	ret = PTR_ERR(opp);
	447	goto err_free_opp;
	448	}
8a31d9d9	449
e37d3508 VK	450	data->rate = dev_pm_opp_get_freq(opp);
e37d3508 VK	451	data->volt = dev_pm_opp_get_voltage(opp);
8a31d9d9	452	dev_pm_opp_put(opp);
5a893e31 LH	453
	454	rk3399_devfreq_dmc_profile.initial_freq = data->rate;
	455
927b75a6	456	data->devfreq = devm_devfreq_add_device(dev,
5a893e31	457	&rk3399_devfreq_dmc_profile,
aa7c352f	458	DEVFREQ_GOV_SIMPLE_ONDEMAND,
5a893e31	459	&data->ondemand_data);
d6e98f3e EBS	460	if (IS_ERR(data->devfreq)) {
	461	ret = PTR_ERR(data->devfreq);
	462	goto err_free_opp;
	463	}
	464
5a893e31 LH	465	devm_devfreq_register_opp_notifier(dev, data->devfreq);
	466
	467	data->dev = dev;
	468	platform_set_drvdata(pdev, data);
	469
d6e98f3e EBS	470	return 0;
	471
	472	err_free_opp:
	473	dev_pm_opp_of_remove_table(&pdev->dev);
39a6e473 YL	474	err_edev:
	475	devfreq_event_disable_edev(data->edev);
	476
d6e98f3e EBS	477	return ret;
	478	}
	479
	480	static int rk3399_dmcfreq_remove(struct platform_device *pdev)
	481	{
	482	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);
	483
	484	/*
	485	* Before remove the opp table we need to unregister the opp notifier.
	486	*/
	487	devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);
	488	dev_pm_opp_of_remove_table(dmcfreq->dev);
	489
5a893e31 LH	490	return 0;
	491	}
	492
5a893e31 LH	493	static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
	494	{ .compatible = "rockchip,rk3399-dmc" },
	495	{ },
	496	};
2f3f1a26	497	MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
5a893e31 LH	498
	499	static struct platform_driver rk3399_dmcfreq_driver = {
	500	.probe = rk3399_dmcfreq_probe,
d6e98f3e	501	.remove = rk3399_dmcfreq_remove,
5a893e31 LH	502	.driver = {
	503	.name = "rk3399-dmc-freq",
	504	.pm = &rk3399_dmcfreq_pm,
	505	.of_match_table = rk3399dmc_devfreq_of_match,
	506	},
	507	};
	508	module_platform_driver(rk3399_dmcfreq_driver);
	509
	510	MODULE_LICENSE("GPL v2");
	511	MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
	512	MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");