[mirror_ubuntu-artful-kernel.git] / drivers / devfreq / rk3399_dmc.c

/*
 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
 * Author: Lin Huang <hl@rock-chips.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/devfreq.h>
#include <linux/devfreq-event.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/regulator/consumer.h>
#include <linux/rwsem.h>
#include <linux/suspend.h>

#include <soc/rockchip/rockchip_sip.h>

struct dram_timing {
	unsigned int ddr3_speed_bin;
	unsigned int pd_idle;
	unsigned int sr_idle;
	unsigned int sr_mc_gate_idle;
	unsigned int srpd_lite_idle;
	unsigned int standby_idle;
	unsigned int auto_pd_dis_freq;
	unsigned int dram_dll_dis_freq;
	unsigned int phy_dll_dis_freq;
	unsigned int ddr3_odt_dis_freq;
	unsigned int ddr3_drv;
	unsigned int ddr3_odt;
	unsigned int phy_ddr3_ca_drv;
	unsigned int phy_ddr3_dq_drv;
	unsigned int phy_ddr3_odt;
	unsigned int lpddr3_odt_dis_freq;
	unsigned int lpddr3_drv;
	unsigned int lpddr3_odt;
	unsigned int phy_lpddr3_ca_drv;
	unsigned int phy_lpddr3_dq_drv;
	unsigned int phy_lpddr3_odt;
	unsigned int lpddr4_odt_dis_freq;
	unsigned int lpddr4_drv;
	unsigned int lpddr4_dq_odt;
	unsigned int lpddr4_ca_odt;
	unsigned int phy_lpddr4_ca_drv;
	unsigned int phy_lpddr4_ck_cs_drv;
	unsigned int phy_lpddr4_dq_drv;
	unsigned int phy_lpddr4_odt;
};

struct rk3399_dmcfreq {
	struct device *dev;
	struct devfreq *devfreq;
	struct devfreq_simple_ondemand_data ondemand_data;
	struct clk *dmc_clk;
	struct devfreq_event_dev *edev;
	struct mutex lock;
	struct dram_timing timing;

	/*
	 * DDR Converser of Frequency (DCF) is used to implement DDR frequency
	 * conversion without the participation of CPU, we will implement and
	 * control it in arm trust firmware.
	 */
	wait_queue_head_t	wait_dcf_queue;
	int irq;
	int wait_dcf_flag;
	struct regulator *vdd_center;
	unsigned long rate, target_rate;
	unsigned long volt, target_volt;
};

static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
				 u32 flags)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	struct dev_pm_opp *opp;
	unsigned long old_clk_rate = dmcfreq->rate;
	unsigned long target_volt, target_rate;
	int err;

	opp = devfreq_recommended_opp(dev, freq, flags);
	if (IS_ERR(opp))
		return PTR_ERR(opp);

	target_rate = dev_pm_opp_get_freq(opp);
	target_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	if (dmcfreq->rate == target_rate)
		return 0;

	mutex_lock(&dmcfreq->lock);

	/*
	 * If frequency scaling from low to high, adjust voltage first.
	 * If frequency scaling from high to low, adjust frequency first.
	 */
	if (old_clk_rate < target_rate) {
		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
					    target_volt);
		if (err) {
			dev_err(dev, "Cannot to set voltage %lu uV\n",
				target_volt);
			goto out;
		}
	}
	dmcfreq->wait_dcf_flag = 1;

	err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
	if (err) {
		dev_err(dev, "Cannot to set frequency %lu (%d)\n",
			target_rate, err);
		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
				      dmcfreq->volt);
		goto out;
	}

	/*
	 * Wait until bcf irq happen, it means freq scaling finish in
	 * arm trust firmware, use 100ms as timeout time.
	 */
	if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
				!dmcfreq->wait_dcf_flag, HZ / 10))
		dev_warn(dev, "Timeout waiting for dcf interrupt\n");

	/*
	 * Check the dpll rate,
	 * There only two result we will get,
	 * 1. Ddr frequency scaling fail, we still get the old rate.
	 * 2. Ddr frequency scaling sucessful, we get the rate we set.
	 */
	dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);

	/* If get the incorrect rate, set voltage to old value. */
	if (dmcfreq->rate != target_rate) {
		dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
			Current frequency %lu\n", target_rate, dmcfreq->rate);
		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
				      dmcfreq->volt);
		goto out;
	} else if (old_clk_rate > target_rate)
		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
					    target_volt);
	if (err)
		dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);

	dmcfreq->rate = target_rate;
	dmcfreq->volt = target_volt;

out:
	mutex_unlock(&dmcfreq->lock);
	return err;
}

static int rk3399_dmcfreq_get_dev_status(struct device *dev,
					 struct devfreq_dev_status *stat)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	struct devfreq_event_data edata;
	int ret = 0;

	ret = devfreq_event_get_event(dmcfreq->edev, &edata);
	if (ret < 0)
		return ret;

	stat->current_frequency = dmcfreq->rate;
	stat->busy_time = edata.load_count;
	stat->total_time = edata.total_count;

	return ret;
}

static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);

	*freq = dmcfreq->rate;

	return 0;
}

static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
	.polling_ms	= 200,
	.target		= rk3399_dmcfreq_target,
	.get_dev_status	= rk3399_dmcfreq_get_dev_status,
	.get_cur_freq	= rk3399_dmcfreq_get_cur_freq,
};

static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	int ret = 0;

	ret = devfreq_event_disable_edev(dmcfreq->edev);
	if (ret < 0) {
		dev_err(dev, "failed to disable the devfreq-event devices\n");
		return ret;
	}

	ret = devfreq_suspend_device(dmcfreq->devfreq);
	if (ret < 0) {
		dev_err(dev, "failed to suspend the devfreq devices\n");
		return ret;
	}

	return 0;
}

static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	int ret = 0;

	ret = devfreq_event_enable_edev(dmcfreq->edev);
	if (ret < 0) {
		dev_err(dev, "failed to enable the devfreq-event devices\n");
		return ret;
	}

	ret = devfreq_resume_device(dmcfreq->devfreq);
	if (ret < 0) {
		dev_err(dev, "failed to resume the devfreq devices\n");
		return ret;
	}
	return ret;
}

static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
			 rk3399_dmcfreq_resume);

static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
{
	struct rk3399_dmcfreq *dmcfreq = dev_id;
	struct arm_smccc_res res;

	dmcfreq->wait_dcf_flag = 0;
	wake_up(&dmcfreq->wait_dcf_queue);

	/* Clear the DCF interrupt */
	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
		      ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
		      0, 0, 0, 0, &res);

	return IRQ_HANDLED;
}

static int of_get_ddr_timings(struct dram_timing *timing,
			      struct device_node *np)
{
	int ret = 0;

	ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
				   &timing->ddr3_speed_bin);
	ret |= of_property_read_u32(np, "rockchip,pd_idle",
				    &timing->pd_idle);
	ret |= of_property_read_u32(np, "rockchip,sr_idle",
				    &timing->sr_idle);
	ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
				    &timing->sr_mc_gate_idle);
	ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
				    &timing->srpd_lite_idle);
	ret |= of_property_read_u32(np, "rockchip,standby_idle",
				    &timing->standby_idle);
	ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
				    &timing->auto_pd_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
				    &timing->dram_dll_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
				    &timing->phy_dll_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
				    &timing->ddr3_odt_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
				    &timing->ddr3_drv);
	ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
				    &timing->ddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
				    &timing->phy_ddr3_ca_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
				    &timing->phy_ddr3_dq_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
				    &timing->phy_ddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
				    &timing->lpddr3_odt_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
				    &timing->lpddr3_drv);
	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
				    &timing->lpddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
				    &timing->phy_lpddr3_ca_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
				    &timing->phy_lpddr3_dq_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
				    &timing->phy_lpddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
				    &timing->lpddr4_odt_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
				    &timing->lpddr4_drv);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
				    &timing->lpddr4_dq_odt);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
				    &timing->lpddr4_ca_odt);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
				    &timing->phy_lpddr4_ca_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
				    &timing->phy_lpddr4_ck_cs_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
				    &timing->phy_lpddr4_dq_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
				    &timing->phy_lpddr4_odt);

	return ret;
}

static int rk3399_dmcfreq_probe(struct platform_device *pdev)
{
	struct arm_smccc_res res;
	struct device *dev = &pdev->dev;
	struct device_node *np = pdev->dev.of_node;
	struct rk3399_dmcfreq *data;
	int ret, irq, index, size;
	uint32_t *timing;
	struct dev_pm_opp *opp;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "Cannot get the dmc interrupt resource\n");
		return -EINVAL;
	}
	data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	mutex_init(&data->lock);

	data->vdd_center = devm_regulator_get(dev, "center");
	if (IS_ERR(data->vdd_center)) {
		dev_err(dev, "Cannot get the regulator \"center\"\n");
		return PTR_ERR(data->vdd_center);
	}

	data->dmc_clk = devm_clk_get(dev, "dmc_clk");
	if (IS_ERR(data->dmc_clk)) {
		dev_err(dev, "Cannot get the clk dmc_clk\n");
		return PTR_ERR(data->dmc_clk);
	};

	data->irq = irq;
	ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
			       dev_name(dev), data);
	if (ret) {
		dev_err(dev, "Failed to request dmc irq: %d\n", ret);
		return ret;
	}

	init_waitqueue_head(&data->wait_dcf_queue);
	data->wait_dcf_flag = 0;

	data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
	if (IS_ERR(data->edev))
		return -EPROBE_DEFER;

	ret = devfreq_event_enable_edev(data->edev);
	if (ret < 0) {
		dev_err(dev, "failed to enable devfreq-event devices\n");
		return ret;
	}

	/*
	 * Get dram timing and pass it to arm trust firmware,
	 * the dram drvier in arm trust firmware will get these
	 * timing and to do dram initial.
	 */
	if (!of_get_ddr_timings(&data->timing, np)) {
		timing = &data->timing.ddr3_speed_bin;
		size = sizeof(struct dram_timing) / 4;
		for (index = 0; index < size; index++) {
			arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
				      ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
				      0, 0, 0, 0, &res);
			if (res.a0) {
				dev_err(dev, "Failed to set dram param: %ld\n",
					res.a0);
				return -EINVAL;
			}
		}
	}

	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
		      ROCKCHIP_SIP_CONFIG_DRAM_INIT,
		      0, 0, 0, 0, &res);

	/*
	 * We add a devfreq driver to our parent since it has a device tree node
	 * with operating points.
	 */
	if (dev_pm_opp_of_add_table(dev)) {
		dev_err(dev, "Invalid operating-points in device tree.\n");
		return -EINVAL;
	}

	of_property_read_u32(np, "upthreshold",
			     &data->ondemand_data.upthreshold);
	of_property_read_u32(np, "downdifferential",
			     &data->ondemand_data.downdifferential);

	data->rate = clk_get_rate(data->dmc_clk);

	opp = devfreq_recommended_opp(dev, &data->rate, 0);
	if (IS_ERR(opp))
		return PTR_ERR(opp);

	data->rate = dev_pm_opp_get_freq(opp);
	data->volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	rk3399_devfreq_dmc_profile.initial_freq = data->rate;

	data->devfreq = devm_devfreq_add_device(dev,
					   &rk3399_devfreq_dmc_profile,
					   "simple_ondemand",
					   &data->ondemand_data);
	if (IS_ERR(data->devfreq))
		return PTR_ERR(data->devfreq);
	devm_devfreq_register_opp_notifier(dev, data->devfreq);

	data->dev = dev;
	platform_set_drvdata(pdev, data);

	return 0;
}

static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
	{ .compatible = "rockchip,rk3399-dmc" },
	{ },
};
MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);

static struct platform_driver rk3399_dmcfreq_driver = {
	.probe	= rk3399_dmcfreq_probe,
	.driver = {
		.name	= "rk3399-dmc-freq",
		.pm	= &rk3399_dmcfreq_pm,
		.of_match_table = rk3399dmc_devfreq_of_match,
	},
};
module_platform_driver(rk3399_dmcfreq_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");
Commit	Line	Data
5a893e31 LH	1	/*
	2	* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
	3	* Author: Lin Huang <hl@rock-chips.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	#include <linux/arm-smccc.h>
	16	#include <linux/clk.h>
	17	#include <linux/delay.h>
	18	#include <linux/devfreq.h>
	19	#include <linux/devfreq-event.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/module.h>
	22	#include <linux/of.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/pm_opp.h>
	25	#include <linux/regulator/consumer.h>
	26	#include <linux/rwsem.h>
	27	#include <linux/suspend.h>
	28
	29	#include <soc/rockchip/rockchip_sip.h>
	30
	31	struct dram_timing {
	32	unsigned int ddr3_speed_bin;
	33	unsigned int pd_idle;
	34	unsigned int sr_idle;
	35	unsigned int sr_mc_gate_idle;
	36	unsigned int srpd_lite_idle;
	37	unsigned int standby_idle;
	38	unsigned int auto_pd_dis_freq;
	39	unsigned int dram_dll_dis_freq;
	40	unsigned int phy_dll_dis_freq;
	41	unsigned int ddr3_odt_dis_freq;
	42	unsigned int ddr3_drv;
	43	unsigned int ddr3_odt;
	44	unsigned int phy_ddr3_ca_drv;
	45	unsigned int phy_ddr3_dq_drv;
	46	unsigned int phy_ddr3_odt;
	47	unsigned int lpddr3_odt_dis_freq;
	48	unsigned int lpddr3_drv;
	49	unsigned int lpddr3_odt;
	50	unsigned int phy_lpddr3_ca_drv;
	51	unsigned int phy_lpddr3_dq_drv;
	52	unsigned int phy_lpddr3_odt;
	53	unsigned int lpddr4_odt_dis_freq;
	54	unsigned int lpddr4_drv;
	55	unsigned int lpddr4_dq_odt;
	56	unsigned int lpddr4_ca_odt;
	57	unsigned int phy_lpddr4_ca_drv;
	58	unsigned int phy_lpddr4_ck_cs_drv;
	59	unsigned int phy_lpddr4_dq_drv;
	60	unsigned int phy_lpddr4_odt;
	61	};
	62
	63	struct rk3399_dmcfreq {
	64	struct device *dev;
65	struct devfreq *devfreq;
66	struct devfreq_simple_ondemand_data ondemand_data;
67	struct clk *dmc_clk;
68	struct devfreq_event_dev *edev;
69	struct mutex lock;
70	struct dram_timing timing;
71
72	/*
73	* DDR Converser of Frequency (DCF) is used to implement DDR frequency
74	* conversion without the participation of CPU, we will implement and
75	* control it in arm trust firmware.
76	*/
77	wait_queue_head_t wait_dcf_queue;
78	int irq;
79	int wait_dcf_flag;
80	struct regulator *vdd_center;
81	unsigned long rate, target_rate;
82	unsigned long volt, target_volt;
5a893e31 LH	83	};
	84
	85	static int rk3399_dmcfreq_target(struct device dev, unsigned long freq,
	86	u32 flags)
	87	{
	88	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	89	struct dev_pm_opp *opp;
	90	unsigned long old_clk_rate = dmcfreq->rate;
	91	unsigned long target_volt, target_rate;
	92	int err;
	93
5a893e31	94	opp = devfreq_recommended_opp(dev, freq, flags);
8a31d9d9	95	if (IS_ERR(opp))
5a893e31	96	return PTR_ERR(opp);
5a893e31 LH	97
	98	target_rate = dev_pm_opp_get_freq(opp);
	99	target_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9	100	dev_pm_opp_put(opp);
5a893e31 LH	101
	102	if (dmcfreq->rate == target_rate)
	103	return 0;
	104
	105	mutex_lock(&dmcfreq->lock);
	106
	107	/*
	108	* If frequency scaling from low to high, adjust voltage first.
	109	* If frequency scaling from high to low, adjust frequency first.
	110	*/
	111	if (old_clk_rate < target_rate) {
	112	err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
	113	target_volt);
	114	if (err) {
	115	dev_err(dev, "Cannot to set voltage %lu uV\n",
	116	target_volt);
	117	goto out;
	118	}
	119	}
	120	dmcfreq->wait_dcf_flag = 1;
	121
	122	err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
	123	if (err) {
	124	dev_err(dev, "Cannot to set frequency %lu (%d)\n",
	125	target_rate, err);
	126	regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
	127	dmcfreq->volt);
	128	goto out;
	129	}
	130
	131	/*
	132	* Wait until bcf irq happen, it means freq scaling finish in
	133	* arm trust firmware, use 100ms as timeout time.
	134	*/
	135	if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
	136	!dmcfreq->wait_dcf_flag, HZ / 10))
	137	dev_warn(dev, "Timeout waiting for dcf interrupt\n");
	138
	139	/*
	140	* Check the dpll rate,
	141	* There only two result we will get,
	142	* 1. Ddr frequency scaling fail, we still get the old rate.
	143	* 2. Ddr frequency scaling sucessful, we get the rate we set.
	144	*/
	145	dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
	146
	147	/* If get the incorrect rate, set voltage to old value. */
	148	if (dmcfreq->rate != target_rate) {
	149	dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
	150	Current frequency %lu\n", target_rate, dmcfreq->rate);
	151	regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
	152	dmcfreq->volt);
	153	goto out;
	154	} else if (old_clk_rate > target_rate)
	155	err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
	156	target_volt);
	157	if (err)
	158	dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
	159
e37d3508 VK	160	dmcfreq->rate = target_rate;
	161	dmcfreq->volt = target_volt;
	162
5a893e31 LH	163	out:
	164	mutex_unlock(&dmcfreq->lock);
	165	return err;
	166	}
	167
	168	static int rk3399_dmcfreq_get_dev_status(struct device *dev,
	169	struct devfreq_dev_status *stat)
	170	{
	171	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	172	struct devfreq_event_data edata;
	173	int ret = 0;
	174
	175	ret = devfreq_event_get_event(dmcfreq->edev, &edata);
	176	if (ret < 0)
	177	return ret;
	178
	179	stat->current_frequency = dmcfreq->rate;
	180	stat->busy_time = edata.load_count;
	181	stat->total_time = edata.total_count;
	182
	183	return ret;
	184	}
	185
	186	static int rk3399_dmcfreq_get_cur_freq(struct device dev, unsigned long freq)
	187	{
	188	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	189
	190	*freq = dmcfreq->rate;
	191
	192	return 0;
	193	}
	194
	195	static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
	196	.polling_ms = 200,
	197	.target = rk3399_dmcfreq_target,
	198	.get_dev_status = rk3399_dmcfreq_get_dev_status,
	199	.get_cur_freq = rk3399_dmcfreq_get_cur_freq,
	200	};
	201
	202	static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
	203	{
	204	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	205	int ret = 0;
	206
	207	ret = devfreq_event_disable_edev(dmcfreq->edev);
	208	if (ret < 0) {
	209	dev_err(dev, "failed to disable the devfreq-event devices\n");
	210	return ret;
	211	}
	212
	213	ret = devfreq_suspend_device(dmcfreq->devfreq);
	214	if (ret < 0) {
	215	dev_err(dev, "failed to suspend the devfreq devices\n");
	216	return ret;
	217	}
	218
	219	return 0;
	220	}
	221
	222	static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
	223	{
	224	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	225	int ret = 0;
	226
227	ret = devfreq_event_enable_edev(dmcfreq->edev);
228	if (ret < 0) {
229	dev_err(dev, "failed to enable the devfreq-event devices\n");
230	return ret;
231	}
232
233	ret = devfreq_resume_device(dmcfreq->devfreq);
234	if (ret < 0) {
235	dev_err(dev, "failed to resume the devfreq devices\n");
236	return ret;
237	}
238	return ret;
239	}
240
241	static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
242	rk3399_dmcfreq_resume);
243
244	static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
245	{
246	struct rk3399_dmcfreq *dmcfreq = dev_id;
247	struct arm_smccc_res res;
248
249	dmcfreq->wait_dcf_flag = 0;
250	wake_up(&dmcfreq->wait_dcf_queue);
251
252	/* Clear the DCF interrupt */
253	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
254	ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
255	0, 0, 0, 0, &res);
256
257	return IRQ_HANDLED;
258	}
259
260	static int of_get_ddr_timings(struct dram_timing *timing,
261	struct device_node *np)
262	{
263	int ret = 0;
264
265	ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
266	&timing->ddr3_speed_bin);
267	ret \|= of_property_read_u32(np, "rockchip,pd_idle",
268	&timing->pd_idle);
269	ret \|= of_property_read_u32(np, "rockchip,sr_idle",
270	&timing->sr_idle);
271	ret \|= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
272	&timing->sr_mc_gate_idle);
273	ret \|= of_property_read_u32(np, "rockchip,srpd_lite_idle",
274	&timing->srpd_lite_idle);
275	ret \|= of_property_read_u32(np, "rockchip,standby_idle",
276	&timing->standby_idle);
277	ret \|= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
278	&timing->auto_pd_dis_freq);
279	ret \|= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
280	&timing->dram_dll_dis_freq);
281	ret \|= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
282	&timing->phy_dll_dis_freq);
283	ret \|= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
284	&timing->ddr3_odt_dis_freq);
285	ret \|= of_property_read_u32(np, "rockchip,ddr3_drv",
286	&timing->ddr3_drv);
287	ret \|= of_property_read_u32(np, "rockchip,ddr3_odt",
288	&timing->ddr3_odt);
289	ret \|= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
290	&timing->phy_ddr3_ca_drv);
291	ret \|= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
292	&timing->phy_ddr3_dq_drv);
293	ret \|= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
294	&timing->phy_ddr3_odt);
295	ret \|= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
296	&timing->lpddr3_odt_dis_freq);
297	ret \|= of_property_read_u32(np, "rockchip,lpddr3_drv",
298	&timing->lpddr3_drv);
299	ret \|= of_property_read_u32(np, "rockchip,lpddr3_odt",
300	&timing->lpddr3_odt);
301	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
302	&timing->phy_lpddr3_ca_drv);
303	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
304	&timing->phy_lpddr3_dq_drv);
305	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
306	&timing->phy_lpddr3_odt);
307	ret \|= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
308	&timing->lpddr4_odt_dis_freq);
309	ret \|= of_property_read_u32(np, "rockchip,lpddr4_drv",
310	&timing->lpddr4_drv);
311	ret \|= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
312	&timing->lpddr4_dq_odt);
313	ret \|= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
314	&timing->lpddr4_ca_odt);
315	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
316	&timing->phy_lpddr4_ca_drv);
317	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
318	&timing->phy_lpddr4_ck_cs_drv);
319	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
320	&timing->phy_lpddr4_dq_drv);
321	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
322	&timing->phy_lpddr4_odt);
323
324	return ret;
325	}
326
327	static int rk3399_dmcfreq_probe(struct platform_device *pdev)
328	{
329	struct arm_smccc_res res;
330	struct device *dev = &pdev->dev;
331	struct device_node *np = pdev->dev.of_node;
332	struct rk3399_dmcfreq *data;
333	int ret, irq, index, size;
334	uint32_t *timing;
335	struct dev_pm_opp *opp;
336
337	irq = platform_get_irq(pdev, 0);
338	if (irq < 0) {
339	dev_err(&pdev->dev, "Cannot get the dmc interrupt resource\n");
340	return -EINVAL;
341	}
342	data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
343	if (!data)
344	return -ENOMEM;
345
346	mutex_init(&data->lock);
347
348	data->vdd_center = devm_regulator_get(dev, "center");
349	if (IS_ERR(data->vdd_center)) {
350	dev_err(dev, "Cannot get the regulator \"center\"\n");
351	return PTR_ERR(data->vdd_center);
352	}
353
354	data->dmc_clk = devm_clk_get(dev, "dmc_clk");
355	if (IS_ERR(data->dmc_clk)) {
356	dev_err(dev, "Cannot get the clk dmc_clk\n");
357	return PTR_ERR(data->dmc_clk);
358	};
359
360	data->irq = irq;
361	ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
362	dev_name(dev), data);
363	if (ret) {
364	dev_err(dev, "Failed to request dmc irq: %d\n", ret);
365	return ret;
366	}
367
368	init_waitqueue_head(&data->wait_dcf_queue);
369	data->wait_dcf_flag = 0;
370
371	data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
372	if (IS_ERR(data->edev))
373	return -EPROBE_DEFER;
374
375	ret = devfreq_event_enable_edev(data->edev);
376	if (ret < 0) {
377	dev_err(dev, "failed to enable devfreq-event devices\n");
378	return ret;
379	}
380
381	/*
382	* Get dram timing and pass it to arm trust firmware,
383	* the dram drvier in arm trust firmware will get these
384	* timing and to do dram initial.
385	*/
386	if (!of_get_ddr_timings(&data->timing, np)) {
387	timing = &data->timing.ddr3_speed_bin;
388	size = sizeof(struct dram_timing) / 4;
389	for (index = 0; index < size; index++) {
390	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
391	ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
392	0, 0, 0, 0, &res);
393	if (res.a0) {
394	dev_err(dev, "Failed to set dram param: %ld\n",
395	res.a0);
396	return -EINVAL;
397	}
398	}
399	}
400
401	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
402	ROCKCHIP_SIP_CONFIG_DRAM_INIT,
403	0, 0, 0, 0, &res);
404
405	/*
406	* We add a devfreq driver to our parent since it has a device tree node
407	* with operating points.
408	*/
409	if (dev_pm_opp_of_add_table(dev)) {
410	dev_err(dev, "Invalid operating-points in device tree.\n");
5a893e31 LH	411	return -EINVAL;
	412	}
	413
	414	of_property_read_u32(np, "upthreshold",
	415	&data->ondemand_data.upthreshold);
	416	of_property_read_u32(np, "downdifferential",
	417	&data->ondemand_data.downdifferential);
	418
	419	data->rate = clk_get_rate(data->dmc_clk);
	420
5a893e31	421	opp = devfreq_recommended_opp(dev, &data->rate, 0);
8a31d9d9	422	if (IS_ERR(opp))
5a893e31	423	return PTR_ERR(opp);
8a31d9d9	424
e37d3508 VK	425	data->rate = dev_pm_opp_get_freq(opp);
e37d3508 VK	426	data->volt = dev_pm_opp_get_voltage(opp);
8a31d9d9	427	dev_pm_opp_put(opp);
5a893e31 LH	428
	429	rk3399_devfreq_dmc_profile.initial_freq = data->rate;
	430
927b75a6	431	data->devfreq = devm_devfreq_add_device(dev,
5a893e31 LH	432	&rk3399_devfreq_dmc_profile,
	433	"simple_ondemand",
	434	&data->ondemand_data);
	435	if (IS_ERR(data->devfreq))
	436	return PTR_ERR(data->devfreq);
	437	devm_devfreq_register_opp_notifier(dev, data->devfreq);
	438
	439	data->dev = dev;
	440	platform_set_drvdata(pdev, data);
	441
	442	return 0;
	443	}
	444
5a893e31 LH	445	static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
	446	{ .compatible = "rockchip,rk3399-dmc" },
	447	{ },
	448	};
2f3f1a26	449	MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
5a893e31 LH	450
	451	static struct platform_driver rk3399_dmcfreq_driver = {
	452	.probe = rk3399_dmcfreq_probe,
5a893e31 LH	453	.driver = {
	454	.name = "rk3399-dmc-freq",
	455	.pm = &rk3399_dmcfreq_pm,
	456	.of_match_table = rk3399dmc_devfreq_of_match,
	457	},
	458	};
	459	module_platform_driver(rk3399_dmcfreq_driver);
	460
	461	MODULE_LICENSE("GPL v2");
	462	MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
	463	MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");