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ioatdma: fix race between updating ioat->head and IOAT_COMPLETION_PENDING
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c13c8260
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1#
2# DMA engine configuration
3#
4
2ed6dc34 5menuconfig DMADEVICES
6d4f5879 6 bool "DMA Engine support"
04ce9ab3 7 depends on HAS_DMA
2ed6dc34 8 help
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HS
9 DMA engines can do asynchronous data transfers without
10 involving the host CPU. Currently, this framework can be
11 used to offload memory copies in the network stack and
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12 RAID operations in the MD driver. This menu only presents
13 DMA Device drivers supported by the configured arch, it may
14 be empty in some cases.
2ed6dc34 15
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16config DMADEVICES_DEBUG
17 bool "DMA Engine debugging"
18 depends on DMADEVICES != n
19 help
20 This is an option for use by developers; most people should
21 say N here. This enables DMA engine core and driver debugging.
22
23config DMADEVICES_VDEBUG
24 bool "DMA Engine verbose debugging"
25 depends on DMADEVICES_DEBUG != n
26 help
27 This is an option for use by developers; most people should
28 say N here. This enables deeper (more verbose) debugging of
29 the DMA engine core and drivers.
30
31
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SN
32if DMADEVICES
33
34comment "DMA Devices"
35
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36config INTEL_MID_DMAC
37 tristate "Intel MID DMA support for Peripheral DMA controllers"
38 depends on PCI && X86
39 select DMA_ENGINE
40 default n
41 help
42 Enable support for the Intel(R) MID DMA engine present
43 in Intel MID chipsets.
44
45 Say Y here if you have such a chipset.
46
47 If unsure, say N.
48
5fc6d897 49config ASYNC_TX_ENABLE_CHANNEL_SWITCH
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50 bool
51
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52config AMBA_PL08X
53 bool "ARM PrimeCell PL080 or PL081 support"
c6a0aec9 54 depends on ARM_AMBA
e8689e63 55 select DMA_ENGINE
083be28a 56 select DMA_VIRTUAL_CHANNELS
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57 help
58 Platform has a PL08x DMAC device
59 which can provide DMA engine support
60
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61config INTEL_IOATDMA
62 tristate "Intel I/OAT DMA support"
63 depends on PCI && X86
64 select DMA_ENGINE
65 select DCA
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66 select ASYNC_TX_DISABLE_PQ_VAL_DMA
67 select ASYNC_TX_DISABLE_XOR_VAL_DMA
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68 help
69 Enable support for the Intel(R) I/OAT DMA engine present
70 in recent Intel Xeon chipsets.
71
72 Say Y here if you have such a chipset.
73
74 If unsure, say N.
75
76config INTEL_IOP_ADMA
77 tristate "Intel IOP ADMA support"
78 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
2ed6dc34 79 select DMA_ENGINE
5fc6d897 80 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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81 help
82 Enable support for the Intel(R) IOP Series RAID engines.
c13c8260 83
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84config DW_DMAC
85 tristate "Synopsys DesignWare AHB DMA support"
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86 select DMA_ENGINE
87 default y if CPU_AT32AP7000
88 help
89 Support the Synopsys DesignWare AHB DMA controller. This
90 can be integrated in chips such as the Atmel AT32ap7000.
91
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92config DW_DMAC_BIG_ENDIAN_IO
93 bool "Use big endian I/O register access"
94 default y if AVR32
95 depends on DW_DMAC
96 help
97 Say yes here to use big endian I/O access when reading and writing
98 to the DMA controller registers. This is needed on some platforms,
99 like the Atmel AVR32 architecture.
100
101 If unsure, use the default setting.
102
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103config AT_HDMAC
104 tristate "Atmel AHB DMA support"
f898fed0 105 depends on ARCH_AT91
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106 select DMA_ENGINE
107 help
f898fed0 108 Support the Atmel AHB DMA controller.
dc78baa2 109
173acc7c 110config FSL_DMA
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111 tristate "Freescale Elo and Elo Plus DMA support"
112 depends on FSL_SOC
173acc7c 113 select DMA_ENGINE
5fc6d897 114 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
173acc7c 115 ---help---
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116 Enable support for the Freescale Elo and Elo Plus DMA controllers.
117 The Elo is the DMA controller on some 82xx and 83xx parts, and the
118 Elo Plus is the DMA controller on 85xx and 86xx parts.
173acc7c 119
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120config MPC512X_DMA
121 tristate "Freescale MPC512x built-in DMA engine support"
ba2eea25 122 depends on PPC_MPC512x || PPC_MPC831x
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123 select DMA_ENGINE
124 ---help---
125 Enable support for the Freescale MPC512x built-in DMA engine.
126
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127config MV_XOR
128 bool "Marvell XOR engine support"
129 depends on PLAT_ORION
ff7b0479 130 select DMA_ENGINE
5fc6d897 131 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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132 ---help---
133 Enable support for the Marvell XOR engine.
134
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135config MX3_IPU
136 bool "MX3x Image Processing Unit support"
8e2d41f8 137 depends on ARCH_MXC
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138 select DMA_ENGINE
139 default y
140 help
141 If you plan to use the Image Processing unit in the i.MX3x, say
142 Y here. If unsure, select Y.
143
144config MX3_IPU_IRQS
145 int "Number of dynamically mapped interrupts for IPU"
146 depends on MX3_IPU
147 range 2 137
148 default 4
149 help
150 Out of 137 interrupt sources on i.MX31 IPU only very few are used.
151 To avoid bloating the irq_desc[] array we allocate a sufficient
152 number of IRQ slots and map them dynamically to specific sources.
153
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154config TXX9_DMAC
155 tristate "Toshiba TXx9 SoC DMA support"
156 depends on MACH_TX49XX || MACH_TX39XX
157 select DMA_ENGINE
158 help
159 Support the TXx9 SoC internal DMA controller. This can be
160 integrated in chips such as the Toshiba TX4927/38/39.
161
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162config TEGRA20_APB_DMA
163 bool "NVIDIA Tegra20 APB DMA support"
164 depends on ARCH_TEGRA
165 select DMA_ENGINE
166 help
167 Support for the NVIDIA Tegra20 APB DMA controller driver. The
168 DMA controller is having multiple DMA channel which can be
169 configured for different peripherals like audio, UART, SPI,
170 I2C etc which is in APB bus.
171 This DMA controller transfers data from memory to peripheral fifo
172 or vice versa. It does not support memory to memory data transfer.
173
174
175
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NI
176config SH_DMAE
177 tristate "Renesas SuperH DMAC support"
927a7c9c 178 depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
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NI
179 depends on !SH_DMA_API
180 select DMA_ENGINE
181 help
182 Enable support for the Renesas SuperH DMA controllers.
183
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184config COH901318
185 bool "ST-Ericsson COH901318 DMA support"
186 select DMA_ENGINE
187 depends on ARCH_U300
188 help
189 Enable support for ST-Ericsson COH 901 318 DMA.
190
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191config STE_DMA40
192 bool "ST-Ericsson DMA40 support"
193 depends on ARCH_U8500
194 select DMA_ENGINE
195 help
196 Support for ST-Ericsson DMA40 controller
197
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198config AMCC_PPC440SPE_ADMA
199 tristate "AMCC PPC440SPe ADMA support"
200 depends on 440SPe || 440SP
201 select DMA_ENGINE
202 select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
5fc6d897 203 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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204 help
205 Enable support for the AMCC PPC440SPe RAID engines.
206
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207config TIMB_DMA
208 tristate "Timberdale FPGA DMA support"
209 depends on MFD_TIMBERDALE || HAS_IOMEM
210 select DMA_ENGINE
211 help
212 Enable support for the Timberdale FPGA DMA engine.
213
ca21a146 214config SIRF_DMA
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215 tristate "CSR SiRFprimaII/SiRFmarco DMA support"
216 depends on ARCH_SIRF
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217 select DMA_ENGINE
218 help
219 Enable support for the CSR SiRFprimaII DMA engine.
220
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221config TI_EDMA
222 tristate "TI EDMA support"
223 depends on ARCH_DAVINCI
224 select DMA_ENGINE
225 select DMA_VIRTUAL_CHANNELS
226 default n
227 help
228 Enable support for the TI EDMA controller. This DMA
229 engine is found on TI DaVinci and AM33xx parts.
230
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231config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
232 bool
233
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234config PL330_DMA
235 tristate "DMA API Driver for PL330"
236 select DMA_ENGINE
1b9bb715 237 depends on ARM_AMBA
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238 help
239 Select if your platform has one or more PL330 DMACs.
240 You need to provide platform specific settings via
241 platform_data for a dma-pl330 device.
242
0c42bd0e 243config PCH_DMA
ca7fe2db 244 tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
0c42bd0e
YW
245 depends on PCI && X86
246 select DMA_ENGINE
247 help
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248 Enable support for Intel EG20T PCH DMA engine.
249
e79e72be 250 This driver also can be used for LAPIS Semiconductor IOH(Input/
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251 Output Hub), ML7213, ML7223 and ML7831.
252 ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
253 for MP(Media Phone) use and ML7831 IOH is for general purpose use.
254 ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
255 ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
0c42bd0e 256
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257config IMX_SDMA
258 tristate "i.MX SDMA support"
8e2d41f8 259 depends on ARCH_MXC
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260 select DMA_ENGINE
261 help
262 Support the i.MX SDMA engine. This engine is integrated into
8e2d41f8 263 Freescale i.MX25/31/35/51/53 chips.
1ec1e82f 264
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265config IMX_DMA
266 tristate "i.MX DMA support"
5b2e02e4 267 depends on ARCH_MXC
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268 select DMA_ENGINE
269 help
270 Support the i.MX DMA engine. This engine is integrated into
271 Freescale i.MX1/21/27 chips.
272
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273config MXS_DMA
274 bool "MXS DMA support"
f5c55847 275 depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q
f5b7efcc 276 select STMP_DEVICE
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277 select DMA_ENGINE
278 help
279 Support the MXS DMA engine. This engine including APBH-DMA
280 and APBX-DMA is integrated into Freescale i.MX23/28 chips.
281
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282config EP93XX_DMA
283 bool "Cirrus Logic EP93xx DMA support"
284 depends on ARCH_EP93XX
285 select DMA_ENGINE
286 help
287 Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
288
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289config DMA_SA11X0
290 tristate "SA-11x0 DMA support"
291 depends on ARCH_SA1100
292 select DMA_ENGINE
50437bff 293 select DMA_VIRTUAL_CHANNELS
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294 help
295 Support the DMA engine found on Intel StrongARM SA-1100 and
296 SA-1110 SoCs. This DMA engine can only be used with on-chip
297 devices.
298
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299config MMP_TDMA
300 bool "MMP Two-Channel DMA support"
49d57b5e 301 depends on ARCH_MMP
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302 select DMA_ENGINE
303 help
304 Support the MMP Two-Channel DMA engine.
305 This engine used for MMP Audio DMA and pxa910 SQU.
306
307 Say Y here if you enabled MMP ADMA, otherwise say N.
308
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309config DMA_OMAP
310 tristate "OMAP DMA support"
311 depends on ARCH_OMAP
312 select DMA_ENGINE
313 select DMA_VIRTUAL_CHANNELS
314
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315config MMP_PDMA
316 bool "MMP PDMA support"
317 depends on (ARCH_MMP || ARCH_PXA)
318 select DMA_ENGINE
319 help
320 Support the MMP PDMA engine for PXA and MMP platfrom.
321
c13c8260 322config DMA_ENGINE
2ed6dc34 323 bool
c13c8260 324
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325config DMA_VIRTUAL_CHANNELS
326 tristate
327
db217334 328comment "DMA Clients"
2ed6dc34 329 depends on DMA_ENGINE
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330
331config NET_DMA
332 bool "Network: TCP receive copy offload"
333 depends on DMA_ENGINE && NET
9c402f4e 334 default (INTEL_IOATDMA || FSL_DMA)
2ed6dc34 335 help
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336 This enables the use of DMA engines in the network stack to
337 offload receive copy-to-user operations, freeing CPU cycles.
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338
339 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
340 say N.
db217334 341
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342config ASYNC_TX_DMA
343 bool "Async_tx: Offload support for the async_tx api"
9a8de639 344 depends on DMA_ENGINE
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345 help
346 This allows the async_tx api to take advantage of offload engines for
347 memcpy, memset, xor, and raid6 p+q operations. If your platform has
348 a dma engine that can perform raid operations and you have enabled
349 MD_RAID456 say Y.
350
351 If unsure, say N.
352
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353config DMATEST
354 tristate "DMA Test client"
355 depends on DMA_ENGINE
356 help
357 Simple DMA test client. Say N unless you're debugging a
358 DMA Device driver.
359
2ed6dc34 360endif