]>
Commit | Line | Data |
---|---|---|
c13c8260 CL |
1 | # |
2 | # DMA engine configuration | |
3 | # | |
4 | ||
2ed6dc34 | 5 | menuconfig DMADEVICES |
6d4f5879 | 6 | bool "DMA Engine support" |
04ce9ab3 | 7 | depends on HAS_DMA |
2ed6dc34 | 8 | help |
6d4f5879 HS |
9 | DMA engines can do asynchronous data transfers without |
10 | involving the host CPU. Currently, this framework can be | |
11 | used to offload memory copies in the network stack and | |
9c402f4e DW |
12 | RAID operations in the MD driver. This menu only presents |
13 | DMA Device drivers supported by the configured arch, it may | |
14 | be empty in some cases. | |
2ed6dc34 | 15 | |
6c664a89 LW |
16 | config DMADEVICES_DEBUG |
17 | bool "DMA Engine debugging" | |
18 | depends on DMADEVICES != n | |
19 | help | |
20 | This is an option for use by developers; most people should | |
21 | say N here. This enables DMA engine core and driver debugging. | |
22 | ||
23 | config DMADEVICES_VDEBUG | |
24 | bool "DMA Engine verbose debugging" | |
25 | depends on DMADEVICES_DEBUG != n | |
26 | help | |
27 | This is an option for use by developers; most people should | |
28 | say N here. This enables deeper (more verbose) debugging of | |
29 | the DMA engine core and drivers. | |
30 | ||
31 | ||
2ed6dc34 SN |
32 | if DMADEVICES |
33 | ||
34 | comment "DMA Devices" | |
35 | ||
138f4c35 DW |
36 | config ASYNC_TX_DISABLE_CHANNEL_SWITCH |
37 | bool | |
38 | ||
2ed6dc34 SN |
39 | config INTEL_IOATDMA |
40 | tristate "Intel I/OAT DMA support" | |
41 | depends on PCI && X86 | |
42 | select DMA_ENGINE | |
43 | select DCA | |
138f4c35 | 44 | select ASYNC_TX_DISABLE_CHANNEL_SWITCH |
7b3cc2b1 DW |
45 | select ASYNC_TX_DISABLE_PQ_VAL_DMA |
46 | select ASYNC_TX_DISABLE_XOR_VAL_DMA | |
2ed6dc34 SN |
47 | help |
48 | Enable support for the Intel(R) I/OAT DMA engine present | |
49 | in recent Intel Xeon chipsets. | |
50 | ||
51 | Say Y here if you have such a chipset. | |
52 | ||
53 | If unsure, say N. | |
54 | ||
55 | config INTEL_IOP_ADMA | |
56 | tristate "Intel IOP ADMA support" | |
57 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX | |
2ed6dc34 SN |
58 | select DMA_ENGINE |
59 | help | |
60 | Enable support for the Intel(R) IOP Series RAID engines. | |
c13c8260 | 61 | |
3bfb1d20 HS |
62 | config DW_DMAC |
63 | tristate "Synopsys DesignWare AHB DMA support" | |
64 | depends on AVR32 | |
65 | select DMA_ENGINE | |
66 | default y if CPU_AT32AP7000 | |
67 | help | |
68 | Support the Synopsys DesignWare AHB DMA controller. This | |
69 | can be integrated in chips such as the Atmel AT32ap7000. | |
70 | ||
dc78baa2 NF |
71 | config AT_HDMAC |
72 | tristate "Atmel AHB DMA support" | |
cd3abf98 | 73 | depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 |
dc78baa2 NF |
74 | select DMA_ENGINE |
75 | help | |
76 | Support the Atmel AHB DMA controller. This can be integrated in | |
77 | chips such as the Atmel AT91SAM9RL. | |
78 | ||
173acc7c | 79 | config FSL_DMA |
77cd62e8 TT |
80 | tristate "Freescale Elo and Elo Plus DMA support" |
81 | depends on FSL_SOC | |
173acc7c ZW |
82 | select DMA_ENGINE |
83 | ---help--- | |
77cd62e8 TT |
84 | Enable support for the Freescale Elo and Elo Plus DMA controllers. |
85 | The Elo is the DMA controller on some 82xx and 83xx parts, and the | |
86 | Elo Plus is the DMA controller on 85xx and 86xx parts. | |
173acc7c | 87 | |
0fb6f739 PZ |
88 | config MPC512X_DMA |
89 | tristate "Freescale MPC512x built-in DMA engine support" | |
90 | depends on PPC_MPC512x | |
91 | select DMA_ENGINE | |
92 | ---help--- | |
93 | Enable support for the Freescale MPC512x built-in DMA engine. | |
94 | ||
ff7b0479 SB |
95 | config MV_XOR |
96 | bool "Marvell XOR engine support" | |
97 | depends on PLAT_ORION | |
ff7b0479 SB |
98 | select DMA_ENGINE |
99 | ---help--- | |
100 | Enable support for the Marvell XOR engine. | |
101 | ||
5296b56d GL |
102 | config MX3_IPU |
103 | bool "MX3x Image Processing Unit support" | |
104 | depends on ARCH_MX3 | |
105 | select DMA_ENGINE | |
106 | default y | |
107 | help | |
108 | If you plan to use the Image Processing unit in the i.MX3x, say | |
109 | Y here. If unsure, select Y. | |
110 | ||
111 | config MX3_IPU_IRQS | |
112 | int "Number of dynamically mapped interrupts for IPU" | |
113 | depends on MX3_IPU | |
114 | range 2 137 | |
115 | default 4 | |
116 | help | |
117 | Out of 137 interrupt sources on i.MX31 IPU only very few are used. | |
118 | To avoid bloating the irq_desc[] array we allocate a sufficient | |
119 | number of IRQ slots and map them dynamically to specific sources. | |
120 | ||
ea76f0b3 AN |
121 | config TXX9_DMAC |
122 | tristate "Toshiba TXx9 SoC DMA support" | |
123 | depends on MACH_TX49XX || MACH_TX39XX | |
124 | select DMA_ENGINE | |
125 | help | |
126 | Support the TXx9 SoC internal DMA controller. This can be | |
127 | integrated in chips such as the Toshiba TX4927/38/39. | |
128 | ||
d8902adc NI |
129 | config SH_DMAE |
130 | tristate "Renesas SuperH DMAC support" | |
131 | depends on SUPERH && SH_DMA | |
132 | depends on !SH_DMA_API | |
133 | select DMA_ENGINE | |
134 | help | |
135 | Enable support for the Renesas SuperH DMA controllers. | |
136 | ||
61f135b9 LW |
137 | config COH901318 |
138 | bool "ST-Ericsson COH901318 DMA support" | |
139 | select DMA_ENGINE | |
140 | depends on ARCH_U300 | |
141 | help | |
142 | Enable support for ST-Ericsson COH 901 318 DMA. | |
143 | ||
12458ea0 AG |
144 | config AMCC_PPC440SPE_ADMA |
145 | tristate "AMCC PPC440SPe ADMA support" | |
146 | depends on 440SPe || 440SP | |
147 | select DMA_ENGINE | |
148 | select ARCH_HAS_ASYNC_TX_FIND_CHANNEL | |
149 | help | |
150 | Enable support for the AMCC PPC440SPe RAID engines. | |
151 | ||
152 | config ARCH_HAS_ASYNC_TX_FIND_CHANNEL | |
153 | bool | |
154 | ||
c13c8260 | 155 | config DMA_ENGINE |
2ed6dc34 | 156 | bool |
c13c8260 | 157 | |
db217334 | 158 | comment "DMA Clients" |
2ed6dc34 | 159 | depends on DMA_ENGINE |
db217334 CL |
160 | |
161 | config NET_DMA | |
162 | bool "Network: TCP receive copy offload" | |
163 | depends on DMA_ENGINE && NET | |
9c402f4e | 164 | default (INTEL_IOATDMA || FSL_DMA) |
2ed6dc34 | 165 | help |
db217334 CL |
166 | This enables the use of DMA engines in the network stack to |
167 | offload receive copy-to-user operations, freeing CPU cycles. | |
9c402f4e DW |
168 | |
169 | Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise | |
170 | say N. | |
db217334 | 171 | |
729b5d1b DW |
172 | config ASYNC_TX_DMA |
173 | bool "Async_tx: Offload support for the async_tx api" | |
9a8de639 | 174 | depends on DMA_ENGINE |
729b5d1b DW |
175 | help |
176 | This allows the async_tx api to take advantage of offload engines for | |
177 | memcpy, memset, xor, and raid6 p+q operations. If your platform has | |
178 | a dma engine that can perform raid operations and you have enabled | |
179 | MD_RAID456 say Y. | |
180 | ||
181 | If unsure, say N. | |
182 | ||
4a776f0a HS |
183 | config DMATEST |
184 | tristate "DMA Test client" | |
185 | depends on DMA_ENGINE | |
186 | help | |
187 | Simple DMA test client. Say N unless you're debugging a | |
188 | DMA Device driver. | |
189 | ||
2ed6dc34 | 190 | endif |