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Commit | Line | Data |
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c13c8260 CL |
1 | # |
2 | # DMA engine configuration | |
3 | # | |
4 | ||
2ed6dc34 | 5 | menuconfig DMADEVICES |
6d4f5879 | 6 | bool "DMA Engine support" |
04ce9ab3 | 7 | depends on HAS_DMA |
2ed6dc34 | 8 | help |
6d4f5879 HS |
9 | DMA engines can do asynchronous data transfers without |
10 | involving the host CPU. Currently, this framework can be | |
11 | used to offload memory copies in the network stack and | |
9c402f4e DW |
12 | RAID operations in the MD driver. This menu only presents |
13 | DMA Device drivers supported by the configured arch, it may | |
14 | be empty in some cases. | |
2ed6dc34 | 15 | |
6c664a89 LW |
16 | config DMADEVICES_DEBUG |
17 | bool "DMA Engine debugging" | |
18 | depends on DMADEVICES != n | |
19 | help | |
20 | This is an option for use by developers; most people should | |
21 | say N here. This enables DMA engine core and driver debugging. | |
22 | ||
23 | config DMADEVICES_VDEBUG | |
24 | bool "DMA Engine verbose debugging" | |
25 | depends on DMADEVICES_DEBUG != n | |
26 | help | |
27 | This is an option for use by developers; most people should | |
28 | say N here. This enables deeper (more verbose) debugging of | |
29 | the DMA engine core and drivers. | |
30 | ||
31 | ||
2ed6dc34 SN |
32 | if DMADEVICES |
33 | ||
34 | comment "DMA Devices" | |
35 | ||
b3c567e4 VK |
36 | config INTEL_MID_DMAC |
37 | tristate "Intel MID DMA support for Peripheral DMA controllers" | |
38 | depends on PCI && X86 | |
39 | select DMA_ENGINE | |
40 | default n | |
41 | help | |
42 | Enable support for the Intel(R) MID DMA engine present | |
43 | in Intel MID chipsets. | |
44 | ||
45 | Say Y here if you have such a chipset. | |
46 | ||
47 | If unsure, say N. | |
48 | ||
5fc6d897 | 49 | config ASYNC_TX_ENABLE_CHANNEL_SWITCH |
138f4c35 DW |
50 | bool |
51 | ||
e8689e63 LW |
52 | config AMBA_PL08X |
53 | bool "ARM PrimeCell PL080 or PL081 support" | |
54 | depends on ARM_AMBA && EXPERIMENTAL | |
55 | select DMA_ENGINE | |
083be28a | 56 | select DMA_VIRTUAL_CHANNELS |
e8689e63 LW |
57 | help |
58 | Platform has a PL08x DMAC device | |
59 | which can provide DMA engine support | |
60 | ||
2ed6dc34 SN |
61 | config INTEL_IOATDMA |
62 | tristate "Intel I/OAT DMA support" | |
63 | depends on PCI && X86 | |
64 | select DMA_ENGINE | |
65 | select DCA | |
7b3cc2b1 DW |
66 | select ASYNC_TX_DISABLE_PQ_VAL_DMA |
67 | select ASYNC_TX_DISABLE_XOR_VAL_DMA | |
2ed6dc34 SN |
68 | help |
69 | Enable support for the Intel(R) I/OAT DMA engine present | |
70 | in recent Intel Xeon chipsets. | |
71 | ||
72 | Say Y here if you have such a chipset. | |
73 | ||
74 | If unsure, say N. | |
75 | ||
76 | config INTEL_IOP_ADMA | |
77 | tristate "Intel IOP ADMA support" | |
78 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX | |
2ed6dc34 | 79 | select DMA_ENGINE |
5fc6d897 | 80 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
2ed6dc34 SN |
81 | help |
82 | Enable support for the Intel(R) IOP Series RAID engines. | |
c13c8260 | 83 | |
3bfb1d20 HS |
84 | config DW_DMAC |
85 | tristate "Synopsys DesignWare AHB DMA support" | |
f44ad7e9 | 86 | depends on HAVE_CLK |
3bfb1d20 HS |
87 | select DMA_ENGINE |
88 | default y if CPU_AT32AP7000 | |
89 | help | |
90 | Support the Synopsys DesignWare AHB DMA controller. This | |
91 | can be integrated in chips such as the Atmel AT32ap7000. | |
92 | ||
dc78baa2 NF |
93 | config AT_HDMAC |
94 | tristate "Atmel AHB DMA support" | |
f898fed0 | 95 | depends on ARCH_AT91 |
dc78baa2 NF |
96 | select DMA_ENGINE |
97 | help | |
f898fed0 | 98 | Support the Atmel AHB DMA controller. |
dc78baa2 | 99 | |
173acc7c | 100 | config FSL_DMA |
77cd62e8 TT |
101 | tristate "Freescale Elo and Elo Plus DMA support" |
102 | depends on FSL_SOC | |
173acc7c | 103 | select DMA_ENGINE |
5fc6d897 | 104 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
173acc7c | 105 | ---help--- |
77cd62e8 TT |
106 | Enable support for the Freescale Elo and Elo Plus DMA controllers. |
107 | The Elo is the DMA controller on some 82xx and 83xx parts, and the | |
108 | Elo Plus is the DMA controller on 85xx and 86xx parts. | |
173acc7c | 109 | |
0fb6f739 PZ |
110 | config MPC512X_DMA |
111 | tristate "Freescale MPC512x built-in DMA engine support" | |
ba2eea25 | 112 | depends on PPC_MPC512x || PPC_MPC831x |
0fb6f739 PZ |
113 | select DMA_ENGINE |
114 | ---help--- | |
115 | Enable support for the Freescale MPC512x built-in DMA engine. | |
116 | ||
ff7b0479 SB |
117 | config MV_XOR |
118 | bool "Marvell XOR engine support" | |
119 | depends on PLAT_ORION | |
ff7b0479 | 120 | select DMA_ENGINE |
5fc6d897 | 121 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
ff7b0479 SB |
122 | ---help--- |
123 | Enable support for the Marvell XOR engine. | |
124 | ||
5296b56d GL |
125 | config MX3_IPU |
126 | bool "MX3x Image Processing Unit support" | |
8e2d41f8 | 127 | depends on ARCH_MXC |
5296b56d GL |
128 | select DMA_ENGINE |
129 | default y | |
130 | help | |
131 | If you plan to use the Image Processing unit in the i.MX3x, say | |
132 | Y here. If unsure, select Y. | |
133 | ||
134 | config MX3_IPU_IRQS | |
135 | int "Number of dynamically mapped interrupts for IPU" | |
136 | depends on MX3_IPU | |
137 | range 2 137 | |
138 | default 4 | |
139 | help | |
140 | Out of 137 interrupt sources on i.MX31 IPU only very few are used. | |
141 | To avoid bloating the irq_desc[] array we allocate a sufficient | |
142 | number of IRQ slots and map them dynamically to specific sources. | |
143 | ||
ea76f0b3 AN |
144 | config TXX9_DMAC |
145 | tristate "Toshiba TXx9 SoC DMA support" | |
146 | depends on MACH_TX49XX || MACH_TX39XX | |
147 | select DMA_ENGINE | |
148 | help | |
149 | Support the TXx9 SoC internal DMA controller. This can be | |
150 | integrated in chips such as the Toshiba TX4927/38/39. | |
151 | ||
ec8a1586 LD |
152 | config TEGRA20_APB_DMA |
153 | bool "NVIDIA Tegra20 APB DMA support" | |
154 | depends on ARCH_TEGRA | |
155 | select DMA_ENGINE | |
156 | help | |
157 | Support for the NVIDIA Tegra20 APB DMA controller driver. The | |
158 | DMA controller is having multiple DMA channel which can be | |
159 | configured for different peripherals like audio, UART, SPI, | |
160 | I2C etc which is in APB bus. | |
161 | This DMA controller transfers data from memory to peripheral fifo | |
162 | or vice versa. It does not support memory to memory data transfer. | |
163 | ||
164 | ||
165 | ||
d8902adc NI |
166 | config SH_DMAE |
167 | tristate "Renesas SuperH DMAC support" | |
927a7c9c | 168 | depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE) |
d8902adc NI |
169 | depends on !SH_DMA_API |
170 | select DMA_ENGINE | |
171 | help | |
172 | Enable support for the Renesas SuperH DMA controllers. | |
173 | ||
61f135b9 LW |
174 | config COH901318 |
175 | bool "ST-Ericsson COH901318 DMA support" | |
176 | select DMA_ENGINE | |
177 | depends on ARCH_U300 | |
178 | help | |
179 | Enable support for ST-Ericsson COH 901 318 DMA. | |
180 | ||
8d318a50 LW |
181 | config STE_DMA40 |
182 | bool "ST-Ericsson DMA40 support" | |
183 | depends on ARCH_U8500 | |
184 | select DMA_ENGINE | |
185 | help | |
186 | Support for ST-Ericsson DMA40 controller | |
187 | ||
12458ea0 AG |
188 | config AMCC_PPC440SPE_ADMA |
189 | tristate "AMCC PPC440SPe ADMA support" | |
190 | depends on 440SPe || 440SP | |
191 | select DMA_ENGINE | |
192 | select ARCH_HAS_ASYNC_TX_FIND_CHANNEL | |
5fc6d897 | 193 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
12458ea0 AG |
194 | help |
195 | Enable support for the AMCC PPC440SPe RAID engines. | |
196 | ||
de5d4453 RR |
197 | config TIMB_DMA |
198 | tristate "Timberdale FPGA DMA support" | |
199 | depends on MFD_TIMBERDALE || HAS_IOMEM | |
200 | select DMA_ENGINE | |
201 | help | |
202 | Enable support for the Timberdale FPGA DMA engine. | |
203 | ||
ca21a146 RY |
204 | config SIRF_DMA |
205 | tristate "CSR SiRFprimaII DMA support" | |
206 | depends on ARCH_PRIMA2 | |
207 | select DMA_ENGINE | |
208 | help | |
209 | Enable support for the CSR SiRFprimaII DMA engine. | |
210 | ||
12458ea0 AG |
211 | config ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
212 | bool | |
213 | ||
b3040e40 JB |
214 | config PL330_DMA |
215 | tristate "DMA API Driver for PL330" | |
216 | select DMA_ENGINE | |
1b9bb715 | 217 | depends on ARM_AMBA |
b3040e40 JB |
218 | help |
219 | Select if your platform has one or more PL330 DMACs. | |
220 | You need to provide platform specific settings via | |
221 | platform_data for a dma-pl330 device. | |
222 | ||
0c42bd0e | 223 | config PCH_DMA |
ca7fe2db | 224 | tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA" |
0c42bd0e YW |
225 | depends on PCI && X86 |
226 | select DMA_ENGINE | |
227 | help | |
2cdf2455 TM |
228 | Enable support for Intel EG20T PCH DMA engine. |
229 | ||
e79e72be | 230 | This driver also can be used for LAPIS Semiconductor IOH(Input/ |
ca7fe2db TM |
231 | Output Hub), ML7213, ML7223 and ML7831. |
232 | ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is | |
233 | for MP(Media Phone) use and ML7831 IOH is for general purpose use. | |
234 | ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series. | |
235 | ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH. | |
0c42bd0e | 236 | |
1ec1e82f SH |
237 | config IMX_SDMA |
238 | tristate "i.MX SDMA support" | |
8e2d41f8 | 239 | depends on ARCH_MXC |
1ec1e82f SH |
240 | select DMA_ENGINE |
241 | help | |
242 | Support the i.MX SDMA engine. This engine is integrated into | |
8e2d41f8 | 243 | Freescale i.MX25/31/35/51/53 chips. |
1ec1e82f | 244 | |
1f1846c6 SH |
245 | config IMX_DMA |
246 | tristate "i.MX DMA support" | |
5b2e02e4 | 247 | depends on ARCH_MXC |
1f1846c6 SH |
248 | select DMA_ENGINE |
249 | help | |
250 | Support the i.MX DMA engine. This engine is integrated into | |
251 | Freescale i.MX1/21/27 chips. | |
252 | ||
a580b8c5 SG |
253 | config MXS_DMA |
254 | bool "MXS DMA support" | |
f5c55847 | 255 | depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q |
f5b7efcc | 256 | select STMP_DEVICE |
a580b8c5 SG |
257 | select DMA_ENGINE |
258 | help | |
259 | Support the MXS DMA engine. This engine including APBH-DMA | |
260 | and APBX-DMA is integrated into Freescale i.MX23/28 chips. | |
261 | ||
760ee1c4 MW |
262 | config EP93XX_DMA |
263 | bool "Cirrus Logic EP93xx DMA support" | |
264 | depends on ARCH_EP93XX | |
265 | select DMA_ENGINE | |
266 | help | |
267 | Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller. | |
268 | ||
6365bead RK |
269 | config DMA_SA11X0 |
270 | tristate "SA-11x0 DMA support" | |
271 | depends on ARCH_SA1100 | |
272 | select DMA_ENGINE | |
50437bff | 273 | select DMA_VIRTUAL_CHANNELS |
6365bead RK |
274 | help |
275 | Support the DMA engine found on Intel StrongARM SA-1100 and | |
276 | SA-1110 SoCs. This DMA engine can only be used with on-chip | |
277 | devices. | |
278 | ||
c6da0ba8 ZG |
279 | config MMP_TDMA |
280 | bool "MMP Two-Channel DMA support" | |
49d57b5e | 281 | depends on ARCH_MMP |
c6da0ba8 ZG |
282 | select DMA_ENGINE |
283 | help | |
284 | Support the MMP Two-Channel DMA engine. | |
285 | This engine used for MMP Audio DMA and pxa910 SQU. | |
286 | ||
287 | Say Y here if you enabled MMP ADMA, otherwise say N. | |
288 | ||
7bedaa55 RK |
289 | config DMA_OMAP |
290 | tristate "OMAP DMA support" | |
291 | depends on ARCH_OMAP | |
292 | select DMA_ENGINE | |
293 | select DMA_VIRTUAL_CHANNELS | |
294 | ||
c13c8260 | 295 | config DMA_ENGINE |
2ed6dc34 | 296 | bool |
c13c8260 | 297 | |
50437bff RK |
298 | config DMA_VIRTUAL_CHANNELS |
299 | tristate | |
300 | ||
db217334 | 301 | comment "DMA Clients" |
2ed6dc34 | 302 | depends on DMA_ENGINE |
db217334 CL |
303 | |
304 | config NET_DMA | |
305 | bool "Network: TCP receive copy offload" | |
306 | depends on DMA_ENGINE && NET | |
9c402f4e | 307 | default (INTEL_IOATDMA || FSL_DMA) |
2ed6dc34 | 308 | help |
db217334 CL |
309 | This enables the use of DMA engines in the network stack to |
310 | offload receive copy-to-user operations, freeing CPU cycles. | |
9c402f4e DW |
311 | |
312 | Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise | |
313 | say N. | |
db217334 | 314 | |
729b5d1b DW |
315 | config ASYNC_TX_DMA |
316 | bool "Async_tx: Offload support for the async_tx api" | |
9a8de639 | 317 | depends on DMA_ENGINE |
729b5d1b DW |
318 | help |
319 | This allows the async_tx api to take advantage of offload engines for | |
320 | memcpy, memset, xor, and raid6 p+q operations. If your platform has | |
321 | a dma engine that can perform raid operations and you have enabled | |
322 | MD_RAID456 say Y. | |
323 | ||
324 | If unsure, say N. | |
325 | ||
4a776f0a HS |
326 | config DMATEST |
327 | tristate "DMA Test client" | |
328 | depends on DMA_ENGINE | |
329 | help | |
330 | Simple DMA test client. Say N unless you're debugging a | |
331 | DMA Device driver. | |
332 | ||
2ed6dc34 | 333 | endif |