projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| c13c8260 CL |
1 | # |
| 2 | # DMA engine configuration | |
| 3 | # | |
| 4 | ||
| 2ed6dc34 | 5 | menuconfig DMADEVICES |
| 6d4f5879 | 6 | bool "DMA Engine support" |
| 04ce9ab3 | 7 | depends on HAS_DMA |
| 2ed6dc34 | 8 | help |
| 6d4f5879 HS |
9 | DMA engines can do asynchronous data transfers without |
| 10 | involving the host CPU. Currently, this framework can be | |
| 11 | used to offload memory copies in the network stack and | |
| 9c402f4e DW |
12 | RAID operations in the MD driver. This menu only presents |
| 13 | DMA Device drivers supported by the configured arch, it may | |
| 14 | be empty in some cases. | |
| 2ed6dc34 SN |
15 | |
| 16 | if DMADEVICES | |
| 17 | ||
| 18 | comment "DMA Devices" | |
| 19 | ||
| 138f4c35 DW |
20 | config ASYNC_TX_DISABLE_CHANNEL_SWITCH |
| 21 | bool | |
| 22 | ||
| 2ed6dc34 SN |
23 | config INTEL_IOATDMA |
| 24 | tristate "Intel I/OAT DMA support" | |
| 25 | depends on PCI && X86 | |
| 26 | select DMA_ENGINE | |
| 27 | select DCA | |
| 138f4c35 | 28 | select ASYNC_TX_DISABLE_CHANNEL_SWITCH |
| 2ed6dc34 SN |
29 | help |
| 30 | Enable support for the Intel(R) I/OAT DMA engine present | |
| 31 | in recent Intel Xeon chipsets. | |
| 32 | ||
| 33 | Say Y here if you have such a chipset. | |
| 34 | ||
| 35 | If unsure, say N. | |
| 36 | ||
| 37 | config INTEL_IOP_ADMA | |
| 38 | tristate "Intel IOP ADMA support" | |
| 39 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX | |
| 2ed6dc34 SN |
40 | select DMA_ENGINE |
| 41 | help | |
| 42 | Enable support for the Intel(R) IOP Series RAID engines. | |
| c13c8260 | 43 | |
| 3bfb1d20 HS |
44 | config DW_DMAC |
| 45 | tristate "Synopsys DesignWare AHB DMA support" | |
| 46 | depends on AVR32 | |
| 47 | select DMA_ENGINE | |
| 48 | default y if CPU_AT32AP7000 | |
| 49 | help | |
| 50 | Support the Synopsys DesignWare AHB DMA controller. This | |
| 51 | can be integrated in chips such as the Atmel AT32ap7000. | |
| 52 | ||
| dc78baa2 NF |
53 | config AT_HDMAC |
| 54 | tristate "Atmel AHB DMA support" | |
| 55 | depends on ARCH_AT91SAM9RL | |
| 56 | select DMA_ENGINE | |
| 57 | help | |
| 58 | Support the Atmel AHB DMA controller. This can be integrated in | |
| 59 | chips such as the Atmel AT91SAM9RL. | |
| 60 | ||
| 173acc7c | 61 | config FSL_DMA |
| 77cd62e8 TT |
62 | tristate "Freescale Elo and Elo Plus DMA support" |
| 63 | depends on FSL_SOC | |
| 173acc7c ZW |
64 | select DMA_ENGINE |
| 65 | ---help--- | |
| 77cd62e8 TT |
66 | Enable support for the Freescale Elo and Elo Plus DMA controllers. |
| 67 | The Elo is the DMA controller on some 82xx and 83xx parts, and the | |
| 68 | Elo Plus is the DMA controller on 85xx and 86xx parts. | |
| 173acc7c | 69 | |
| ff7b0479 SB |
70 | config MV_XOR |
| 71 | bool "Marvell XOR engine support" | |
| 72 | depends on PLAT_ORION | |
| ff7b0479 SB |
73 | select DMA_ENGINE |
| 74 | ---help--- | |
| 75 | Enable support for the Marvell XOR engine. | |
| 76 | ||
| 5296b56d GL |
77 | config MX3_IPU |
| 78 | bool "MX3x Image Processing Unit support" | |
| 79 | depends on ARCH_MX3 | |
| 80 | select DMA_ENGINE | |
| 81 | default y | |
| 82 | help | |
| 83 | If you plan to use the Image Processing unit in the i.MX3x, say | |
| 84 | Y here. If unsure, select Y. | |
| 85 | ||
| 86 | config MX3_IPU_IRQS | |
| 87 | int "Number of dynamically mapped interrupts for IPU" | |
| 88 | depends on MX3_IPU | |
| 89 | range 2 137 | |
| 90 | default 4 | |
| 91 | help | |
| 92 | Out of 137 interrupt sources on i.MX31 IPU only very few are used. | |
| 93 | To avoid bloating the irq_desc[] array we allocate a sufficient | |
| 94 | number of IRQ slots and map them dynamically to specific sources. | |
| 95 | ||
| ea76f0b3 AN |
96 | config TXX9_DMAC |
| 97 | tristate "Toshiba TXx9 SoC DMA support" | |
| 98 | depends on MACH_TX49XX || MACH_TX39XX | |
| 99 | select DMA_ENGINE | |
| 100 | help | |
| 101 | Support the TXx9 SoC internal DMA controller. This can be | |
| 102 | integrated in chips such as the Toshiba TX4927/38/39. | |
| 103 | ||
| d8902adc NI |
104 | config SH_DMAE |
| 105 | tristate "Renesas SuperH DMAC support" | |
| 106 | depends on SUPERH && SH_DMA | |
| 107 | depends on !SH_DMA_API | |
| 108 | select DMA_ENGINE | |
| 109 | help | |
| 110 | Enable support for the Renesas SuperH DMA controllers. | |
| 111 | ||
| c13c8260 | 112 | config DMA_ENGINE |
| 2ed6dc34 | 113 | bool |
| c13c8260 | 114 | |
| db217334 | 115 | comment "DMA Clients" |
| 2ed6dc34 | 116 | depends on DMA_ENGINE |
| db217334 CL |
117 | |
| 118 | config NET_DMA | |
| 119 | bool "Network: TCP receive copy offload" | |
| 120 | depends on DMA_ENGINE && NET | |
| 9c402f4e | 121 | default (INTEL_IOATDMA || FSL_DMA) |
| 2ed6dc34 | 122 | help |
| db217334 CL |
123 | This enables the use of DMA engines in the network stack to |
| 124 | offload receive copy-to-user operations, freeing CPU cycles. | |
| 9c402f4e DW |
125 | |
| 126 | Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise | |
| 127 | say N. | |
| db217334 | 128 | |
| 729b5d1b DW |
129 | config ASYNC_TX_DMA |
| 130 | bool "Async_tx: Offload support for the async_tx api" | |
| 9a8de639 | 131 | depends on DMA_ENGINE |
| 729b5d1b DW |
132 | help |
| 133 | This allows the async_tx api to take advantage of offload engines for | |
| 134 | memcpy, memset, xor, and raid6 p+q operations. If your platform has | |
| 135 | a dma engine that can perform raid operations and you have enabled | |
| 136 | MD_RAID456 say Y. | |
| 137 | ||
| 138 | If unsure, say N. | |
| 139 | ||
| 4a776f0a HS |
140 | config DMATEST |
| 141 | tristate "DMA Test client" | |
| 142 | depends on DMA_ENGINE | |
| 143 | help | |
| 144 | Simple DMA test client. Say N unless you're debugging a | |
| 145 | DMA Device driver. | |
| 146 | ||
| 2ed6dc34 | 147 | endif |