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Commit | Line | Data |
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c13c8260 CL |
1 | # |
2 | # DMA engine configuration | |
3 | # | |
4 | ||
2ed6dc34 | 5 | menuconfig DMADEVICES |
6d4f5879 | 6 | bool "DMA Engine support" |
04ce9ab3 | 7 | depends on HAS_DMA |
2ed6dc34 | 8 | help |
6d4f5879 HS |
9 | DMA engines can do asynchronous data transfers without |
10 | involving the host CPU. Currently, this framework can be | |
11 | used to offload memory copies in the network stack and | |
9c402f4e DW |
12 | RAID operations in the MD driver. This menu only presents |
13 | DMA Device drivers supported by the configured arch, it may | |
14 | be empty in some cases. | |
2ed6dc34 | 15 | |
6c664a89 LW |
16 | config DMADEVICES_DEBUG |
17 | bool "DMA Engine debugging" | |
18 | depends on DMADEVICES != n | |
19 | help | |
20 | This is an option for use by developers; most people should | |
21 | say N here. This enables DMA engine core and driver debugging. | |
22 | ||
23 | config DMADEVICES_VDEBUG | |
24 | bool "DMA Engine verbose debugging" | |
25 | depends on DMADEVICES_DEBUG != n | |
26 | help | |
27 | This is an option for use by developers; most people should | |
28 | say N here. This enables deeper (more verbose) debugging of | |
29 | the DMA engine core and drivers. | |
30 | ||
31 | ||
2ed6dc34 SN |
32 | if DMADEVICES |
33 | ||
34 | comment "DMA Devices" | |
35 | ||
b3c567e4 VK |
36 | config INTEL_MID_DMAC |
37 | tristate "Intel MID DMA support for Peripheral DMA controllers" | |
38 | depends on PCI && X86 | |
39 | select DMA_ENGINE | |
40 | default n | |
41 | help | |
42 | Enable support for the Intel(R) MID DMA engine present | |
43 | in Intel MID chipsets. | |
44 | ||
45 | Say Y here if you have such a chipset. | |
46 | ||
47 | If unsure, say N. | |
48 | ||
5fc6d897 | 49 | config ASYNC_TX_ENABLE_CHANNEL_SWITCH |
138f4c35 DW |
50 | bool |
51 | ||
e8689e63 LW |
52 | config AMBA_PL08X |
53 | bool "ARM PrimeCell PL080 or PL081 support" | |
c6a0aec9 | 54 | depends on ARM_AMBA |
e8689e63 | 55 | select DMA_ENGINE |
083be28a | 56 | select DMA_VIRTUAL_CHANNELS |
e8689e63 LW |
57 | help |
58 | Platform has a PL08x DMAC device | |
59 | which can provide DMA engine support | |
60 | ||
2ed6dc34 SN |
61 | config INTEL_IOATDMA |
62 | tristate "Intel I/OAT DMA support" | |
63 | depends on PCI && X86 | |
64 | select DMA_ENGINE | |
65 | select DCA | |
66 | help | |
67 | Enable support for the Intel(R) I/OAT DMA engine present | |
68 | in recent Intel Xeon chipsets. | |
69 | ||
70 | Say Y here if you have such a chipset. | |
71 | ||
72 | If unsure, say N. | |
73 | ||
74 | config INTEL_IOP_ADMA | |
75 | tristate "Intel IOP ADMA support" | |
76 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX | |
2ed6dc34 | 77 | select DMA_ENGINE |
5fc6d897 | 78 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
2ed6dc34 SN |
79 | help |
80 | Enable support for the Intel(R) IOP Series RAID engines. | |
c13c8260 | 81 | |
3bfb1d20 HS |
82 | config DW_DMAC |
83 | tristate "Synopsys DesignWare AHB DMA support" | |
6c43a519 | 84 | depends on GENERIC_HARDIRQS |
3bfb1d20 HS |
85 | select DMA_ENGINE |
86 | default y if CPU_AT32AP7000 | |
87 | help | |
88 | Support the Synopsys DesignWare AHB DMA controller. This | |
89 | can be integrated in chips such as the Atmel AT32ap7000. | |
90 | ||
d5ea7b5e HT |
91 | config DW_DMAC_BIG_ENDIAN_IO |
92 | bool "Use big endian I/O register access" | |
93 | default y if AVR32 | |
94 | depends on DW_DMAC | |
95 | help | |
96 | Say yes here to use big endian I/O access when reading and writing | |
97 | to the DMA controller registers. This is needed on some platforms, | |
98 | like the Atmel AVR32 architecture. | |
99 | ||
100 | If unsure, use the default setting. | |
101 | ||
dc78baa2 NF |
102 | config AT_HDMAC |
103 | tristate "Atmel AHB DMA support" | |
f898fed0 | 104 | depends on ARCH_AT91 |
dc78baa2 NF |
105 | select DMA_ENGINE |
106 | help | |
f898fed0 | 107 | Support the Atmel AHB DMA controller. |
dc78baa2 | 108 | |
173acc7c | 109 | config FSL_DMA |
77cd62e8 TT |
110 | tristate "Freescale Elo and Elo Plus DMA support" |
111 | depends on FSL_SOC | |
173acc7c | 112 | select DMA_ENGINE |
5fc6d897 | 113 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
173acc7c | 114 | ---help--- |
77cd62e8 TT |
115 | Enable support for the Freescale Elo and Elo Plus DMA controllers. |
116 | The Elo is the DMA controller on some 82xx and 83xx parts, and the | |
117 | Elo Plus is the DMA controller on 85xx and 86xx parts. | |
173acc7c | 118 | |
0fb6f739 PZ |
119 | config MPC512X_DMA |
120 | tristate "Freescale MPC512x built-in DMA engine support" | |
ba2eea25 | 121 | depends on PPC_MPC512x || PPC_MPC831x |
0fb6f739 PZ |
122 | select DMA_ENGINE |
123 | ---help--- | |
124 | Enable support for the Freescale MPC512x built-in DMA engine. | |
125 | ||
9a322993 PDM |
126 | source "drivers/dma/bestcomm/Kconfig" |
127 | ||
ff7b0479 SB |
128 | config MV_XOR |
129 | bool "Marvell XOR engine support" | |
130 | depends on PLAT_ORION | |
ff7b0479 | 131 | select DMA_ENGINE |
5fc6d897 | 132 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
ff7b0479 SB |
133 | ---help--- |
134 | Enable support for the Marvell XOR engine. | |
135 | ||
5296b56d GL |
136 | config MX3_IPU |
137 | bool "MX3x Image Processing Unit support" | |
8e2d41f8 | 138 | depends on ARCH_MXC |
5296b56d GL |
139 | select DMA_ENGINE |
140 | default y | |
141 | help | |
142 | If you plan to use the Image Processing unit in the i.MX3x, say | |
143 | Y here. If unsure, select Y. | |
144 | ||
145 | config MX3_IPU_IRQS | |
146 | int "Number of dynamically mapped interrupts for IPU" | |
147 | depends on MX3_IPU | |
148 | range 2 137 | |
149 | default 4 | |
150 | help | |
151 | Out of 137 interrupt sources on i.MX31 IPU only very few are used. | |
152 | To avoid bloating the irq_desc[] array we allocate a sufficient | |
153 | number of IRQ slots and map them dynamically to specific sources. | |
154 | ||
ea76f0b3 AN |
155 | config TXX9_DMAC |
156 | tristate "Toshiba TXx9 SoC DMA support" | |
157 | depends on MACH_TX49XX || MACH_TX39XX | |
158 | select DMA_ENGINE | |
159 | help | |
160 | Support the TXx9 SoC internal DMA controller. This can be | |
161 | integrated in chips such as the Toshiba TX4927/38/39. | |
162 | ||
ec8a1586 LD |
163 | config TEGRA20_APB_DMA |
164 | bool "NVIDIA Tegra20 APB DMA support" | |
165 | depends on ARCH_TEGRA | |
166 | select DMA_ENGINE | |
167 | help | |
168 | Support for the NVIDIA Tegra20 APB DMA controller driver. The | |
169 | DMA controller is having multiple DMA channel which can be | |
170 | configured for different peripherals like audio, UART, SPI, | |
171 | I2C etc which is in APB bus. | |
172 | This DMA controller transfers data from memory to peripheral fifo | |
173 | or vice versa. It does not support memory to memory data transfer. | |
174 | ||
175 | ||
176 | ||
d8902adc NI |
177 | config SH_DMAE |
178 | tristate "Renesas SuperH DMAC support" | |
927a7c9c | 179 | depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE) |
d8902adc NI |
180 | depends on !SH_DMA_API |
181 | select DMA_ENGINE | |
182 | help | |
183 | Enable support for the Renesas SuperH DMA controllers. | |
184 | ||
61f135b9 LW |
185 | config COH901318 |
186 | bool "ST-Ericsson COH901318 DMA support" | |
187 | select DMA_ENGINE | |
188 | depends on ARCH_U300 | |
189 | help | |
190 | Enable support for ST-Ericsson COH 901 318 DMA. | |
191 | ||
8d318a50 LW |
192 | config STE_DMA40 |
193 | bool "ST-Ericsson DMA40 support" | |
194 | depends on ARCH_U8500 | |
195 | select DMA_ENGINE | |
196 | help | |
197 | Support for ST-Ericsson DMA40 controller | |
198 | ||
12458ea0 AG |
199 | config AMCC_PPC440SPE_ADMA |
200 | tristate "AMCC PPC440SPe ADMA support" | |
201 | depends on 440SPe || 440SP | |
202 | select DMA_ENGINE | |
203 | select ARCH_HAS_ASYNC_TX_FIND_CHANNEL | |
5fc6d897 | 204 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
12458ea0 AG |
205 | help |
206 | Enable support for the AMCC PPC440SPe RAID engines. | |
207 | ||
de5d4453 RR |
208 | config TIMB_DMA |
209 | tristate "Timberdale FPGA DMA support" | |
210 | depends on MFD_TIMBERDALE || HAS_IOMEM | |
211 | select DMA_ENGINE | |
212 | help | |
213 | Enable support for the Timberdale FPGA DMA engine. | |
214 | ||
ca21a146 | 215 | config SIRF_DMA |
f7d935dc BS |
216 | tristate "CSR SiRFprimaII/SiRFmarco DMA support" |
217 | depends on ARCH_SIRF | |
ca21a146 RY |
218 | select DMA_ENGINE |
219 | help | |
220 | Enable support for the CSR SiRFprimaII DMA engine. | |
221 | ||
c2dde5f8 MP |
222 | config TI_EDMA |
223 | tristate "TI EDMA support" | |
224 | depends on ARCH_DAVINCI | |
225 | select DMA_ENGINE | |
226 | select DMA_VIRTUAL_CHANNELS | |
227 | default n | |
228 | help | |
229 | Enable support for the TI EDMA controller. This DMA | |
230 | engine is found on TI DaVinci and AM33xx parts. | |
231 | ||
12458ea0 AG |
232 | config ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
233 | bool | |
234 | ||
b3040e40 JB |
235 | config PL330_DMA |
236 | tristate "DMA API Driver for PL330" | |
237 | select DMA_ENGINE | |
1b9bb715 | 238 | depends on ARM_AMBA |
b3040e40 JB |
239 | help |
240 | Select if your platform has one or more PL330 DMACs. | |
241 | You need to provide platform specific settings via | |
242 | platform_data for a dma-pl330 device. | |
243 | ||
0c42bd0e | 244 | config PCH_DMA |
ca7fe2db | 245 | tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA" |
0c42bd0e YW |
246 | depends on PCI && X86 |
247 | select DMA_ENGINE | |
248 | help | |
2cdf2455 TM |
249 | Enable support for Intel EG20T PCH DMA engine. |
250 | ||
e79e72be | 251 | This driver also can be used for LAPIS Semiconductor IOH(Input/ |
ca7fe2db TM |
252 | Output Hub), ML7213, ML7223 and ML7831. |
253 | ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is | |
254 | for MP(Media Phone) use and ML7831 IOH is for general purpose use. | |
255 | ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series. | |
256 | ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH. | |
0c42bd0e | 257 | |
1ec1e82f SH |
258 | config IMX_SDMA |
259 | tristate "i.MX SDMA support" | |
8e2d41f8 | 260 | depends on ARCH_MXC |
1ec1e82f SH |
261 | select DMA_ENGINE |
262 | help | |
263 | Support the i.MX SDMA engine. This engine is integrated into | |
8e2d41f8 | 264 | Freescale i.MX25/31/35/51/53 chips. |
1ec1e82f | 265 | |
1f1846c6 SH |
266 | config IMX_DMA |
267 | tristate "i.MX DMA support" | |
5b2e02e4 | 268 | depends on ARCH_MXC |
1f1846c6 SH |
269 | select DMA_ENGINE |
270 | help | |
271 | Support the i.MX DMA engine. This engine is integrated into | |
272 | Freescale i.MX1/21/27 chips. | |
273 | ||
a580b8c5 SG |
274 | config MXS_DMA |
275 | bool "MXS DMA support" | |
f5c55847 | 276 | depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q |
f5b7efcc | 277 | select STMP_DEVICE |
a580b8c5 SG |
278 | select DMA_ENGINE |
279 | help | |
280 | Support the MXS DMA engine. This engine including APBH-DMA | |
281 | and APBX-DMA is integrated into Freescale i.MX23/28 chips. | |
282 | ||
760ee1c4 MW |
283 | config EP93XX_DMA |
284 | bool "Cirrus Logic EP93xx DMA support" | |
285 | depends on ARCH_EP93XX | |
286 | select DMA_ENGINE | |
287 | help | |
288 | Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller. | |
289 | ||
6365bead RK |
290 | config DMA_SA11X0 |
291 | tristate "SA-11x0 DMA support" | |
292 | depends on ARCH_SA1100 | |
293 | select DMA_ENGINE | |
50437bff | 294 | select DMA_VIRTUAL_CHANNELS |
6365bead RK |
295 | help |
296 | Support the DMA engine found on Intel StrongARM SA-1100 and | |
297 | SA-1110 SoCs. This DMA engine can only be used with on-chip | |
298 | devices. | |
299 | ||
c6da0ba8 ZG |
300 | config MMP_TDMA |
301 | bool "MMP Two-Channel DMA support" | |
49d57b5e | 302 | depends on ARCH_MMP |
c6da0ba8 ZG |
303 | select DMA_ENGINE |
304 | help | |
305 | Support the MMP Two-Channel DMA engine. | |
306 | This engine used for MMP Audio DMA and pxa910 SQU. | |
307 | ||
308 | Say Y here if you enabled MMP ADMA, otherwise say N. | |
309 | ||
7bedaa55 RK |
310 | config DMA_OMAP |
311 | tristate "OMAP DMA support" | |
312 | depends on ARCH_OMAP | |
313 | select DMA_ENGINE | |
314 | select DMA_VIRTUAL_CHANNELS | |
315 | ||
c8acd6aa ZG |
316 | config MMP_PDMA |
317 | bool "MMP PDMA support" | |
318 | depends on (ARCH_MMP || ARCH_PXA) | |
319 | select DMA_ENGINE | |
320 | help | |
321 | Support the MMP PDMA engine for PXA and MMP platfrom. | |
322 | ||
c13c8260 | 323 | config DMA_ENGINE |
2ed6dc34 | 324 | bool |
c13c8260 | 325 | |
50437bff RK |
326 | config DMA_VIRTUAL_CHANNELS |
327 | tristate | |
328 | ||
1b2e98bc AS |
329 | config DMA_ACPI |
330 | def_bool y | |
331 | depends on ACPI | |
332 | ||
5fa422c9 VK |
333 | config DMA_OF |
334 | def_bool y | |
335 | depends on OF | |
336 | ||
db217334 | 337 | comment "DMA Clients" |
2ed6dc34 | 338 | depends on DMA_ENGINE |
db217334 CL |
339 | |
340 | config NET_DMA | |
341 | bool "Network: TCP receive copy offload" | |
342 | depends on DMA_ENGINE && NET | |
9c402f4e | 343 | default (INTEL_IOATDMA || FSL_DMA) |
2ed6dc34 | 344 | help |
db217334 CL |
345 | This enables the use of DMA engines in the network stack to |
346 | offload receive copy-to-user operations, freeing CPU cycles. | |
9c402f4e DW |
347 | |
348 | Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise | |
349 | say N. | |
db217334 | 350 | |
729b5d1b DW |
351 | config ASYNC_TX_DMA |
352 | bool "Async_tx: Offload support for the async_tx api" | |
9a8de639 | 353 | depends on DMA_ENGINE |
729b5d1b DW |
354 | help |
355 | This allows the async_tx api to take advantage of offload engines for | |
356 | memcpy, memset, xor, and raid6 p+q operations. If your platform has | |
357 | a dma engine that can perform raid operations and you have enabled | |
358 | MD_RAID456 say Y. | |
359 | ||
360 | If unsure, say N. | |
361 | ||
4a776f0a HS |
362 | config DMATEST |
363 | tristate "DMA Test client" | |
364 | depends on DMA_ENGINE | |
365 | help | |
366 | Simple DMA test client. Say N unless you're debugging a | |
367 | DMA Device driver. | |
368 | ||
2ed6dc34 | 369 | endif |