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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
94ae8522 RKAL |
22 | * The full GNU General Public License is in this distribution in the file |
23 | * called COPYING. | |
e8689e63 LW |
24 | * |
25 | * Documentation: ARM DDI 0196G == PL080 | |
94ae8522 | 26 | * Documentation: ARM DDI 0218E == PL081 |
da1b6c05 | 27 | * Documentation: S3C6410 User's Manual == PL080S |
e8689e63 | 28 | * |
94ae8522 RKAL |
29 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
30 | * channel. | |
e8689e63 LW |
31 | * |
32 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
33 | * has only two channels. So on these DMA controllers the number of channels | |
34 | * and the number of incoming DMA signals are two totally different things. | |
35 | * It is usually not possible to theoretically handle all physical signals, | |
36 | * so a multiplexing scheme with possible denial of use is necessary. | |
37 | * | |
38 | * The PL080 has a dual bus master, PL081 has a single master. | |
39 | * | |
da1b6c05 TF |
40 | * PL080S is a version modified by Samsung and used in S3C64xx SoCs. |
41 | * It differs in following aspects: | |
42 | * - CH_CONFIG register at different offset, | |
43 | * - separate CH_CONTROL2 register for transfer size, | |
44 | * - bigger maximum transfer size, | |
45 | * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word, | |
46 | * - no support for peripheral flow control. | |
47 | * | |
e8689e63 LW |
48 | * Memory to peripheral transfer may be visualized as |
49 | * Get data from memory to DMAC | |
50 | * Until no data left | |
51 | * On burst request from peripheral | |
52 | * Destination burst from DMAC to peripheral | |
53 | * Clear burst request | |
54 | * Raise terminal count interrupt | |
55 | * | |
56 | * For peripherals with a FIFO: | |
57 | * Source burst size == half the depth of the peripheral FIFO | |
58 | * Destination burst size == the depth of the peripheral FIFO | |
59 | * | |
60 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
61 | * signals, the DMA controller will simply facilitate its AHB master.) | |
62 | * | |
63 | * ASSUMES default (little) endianness for DMA transfers | |
64 | * | |
9dc2c200 RKAL |
65 | * The PL08x has two flow control settings: |
66 | * - DMAC flow control: the transfer size defines the number of transfers | |
67 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
68 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
69 | * to both the BREQ and SREQ signals (contrary to documented), | |
70 | * transferring data if either is active. The LBREQ and LSREQ signals | |
71 | * are ignored. | |
72 | * | |
73 | * - Peripheral flow control: the transfer size is ignored (and should be | |
74 | * zero). The data is transferred from the current LLI entry, until | |
75 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
da1b6c05 | 76 | * will then move to the next LLI entry. Unsupported by PL080S. |
e8689e63 | 77 | */ |
730404ac | 78 | #include <linux/amba/bus.h> |
e8689e63 LW |
79 | #include <linux/amba/pl08x.h> |
80 | #include <linux/debugfs.h> | |
0c38d701 VK |
81 | #include <linux/delay.h> |
82 | #include <linux/device.h> | |
83 | #include <linux/dmaengine.h> | |
84 | #include <linux/dmapool.h> | |
8516f52f | 85 | #include <linux/dma-mapping.h> |
6d05c9fa | 86 | #include <linux/export.h> |
0c38d701 VK |
87 | #include <linux/init.h> |
88 | #include <linux/interrupt.h> | |
89 | #include <linux/module.h> | |
b7b6018b | 90 | #include <linux/pm_runtime.h> |
e8689e63 | 91 | #include <linux/seq_file.h> |
0c38d701 | 92 | #include <linux/slab.h> |
3a95b9fb | 93 | #include <linux/amba/pl080.h> |
e8689e63 | 94 | |
d2ebfb33 | 95 | #include "dmaengine.h" |
01d8dc64 | 96 | #include "virt-dma.h" |
d2ebfb33 | 97 | |
e8689e63 LW |
98 | #define DRIVER_NAME "pl08xdmac" |
99 | ||
7703eac9 | 100 | static struct amba_driver pl08x_amba_driver; |
b23f204c | 101 | struct pl08x_driver_data; |
7703eac9 | 102 | |
e8689e63 | 103 | /** |
94ae8522 | 104 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
e8689e63 | 105 | * @channels: the number of channels available in this variant |
94ae8522 | 106 | * @dualmaster: whether this version supports dual AHB masters or not. |
affa115e LW |
107 | * @nomadik: whether the channels have Nomadik security extension bits |
108 | * that need to be checked for permission before use and some registers are | |
109 | * missing | |
da1b6c05 TF |
110 | * @pl080s: whether this version is a PL080S, which has separate register and |
111 | * LLI word for transfer size. | |
e8689e63 LW |
112 | */ |
113 | struct vendor_data { | |
d86ccea7 | 114 | u8 config_offset; |
e8689e63 LW |
115 | u8 channels; |
116 | bool dualmaster; | |
affa115e | 117 | bool nomadik; |
da1b6c05 | 118 | bool pl080s; |
5110e51d | 119 | u32 max_transfer_size; |
e8689e63 LW |
120 | }; |
121 | ||
b23f204c RK |
122 | /** |
123 | * struct pl08x_bus_data - information of source or destination | |
124 | * busses for a transfer | |
125 | * @addr: current address | |
126 | * @maxwidth: the maximum width of a transfer on this bus | |
127 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | |
128 | */ | |
129 | struct pl08x_bus_data { | |
130 | dma_addr_t addr; | |
131 | u8 maxwidth; | |
132 | u8 buswidth; | |
133 | }; | |
134 | ||
1c38b289 AP |
135 | #define IS_BUS_ALIGNED(bus) IS_ALIGNED((bus)->addr, (bus)->buswidth) |
136 | ||
b23f204c RK |
137 | /** |
138 | * struct pl08x_phy_chan - holder for the physical channels | |
139 | * @id: physical index to this channel | |
140 | * @lock: a lock to use when altering an instance of this struct | |
b23f204c RK |
141 | * @serving: the virtual channel currently being served by this physical |
142 | * channel | |
ad0de2ac RK |
143 | * @locked: channel unavailable for the system, e.g. dedicated to secure |
144 | * world | |
b23f204c RK |
145 | */ |
146 | struct pl08x_phy_chan { | |
147 | unsigned int id; | |
148 | void __iomem *base; | |
d86ccea7 | 149 | void __iomem *reg_config; |
b23f204c | 150 | spinlock_t lock; |
b23f204c | 151 | struct pl08x_dma_chan *serving; |
ad0de2ac | 152 | bool locked; |
b23f204c RK |
153 | }; |
154 | ||
155 | /** | |
156 | * struct pl08x_sg - structure containing data per sg | |
157 | * @src_addr: src address of sg | |
158 | * @dst_addr: dst address of sg | |
159 | * @len: transfer len in bytes | |
160 | * @node: node for txd's dsg_list | |
161 | */ | |
162 | struct pl08x_sg { | |
163 | dma_addr_t src_addr; | |
164 | dma_addr_t dst_addr; | |
165 | size_t len; | |
166 | struct list_head node; | |
167 | }; | |
168 | ||
169 | /** | |
170 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | |
01d8dc64 | 171 | * @vd: virtual DMA descriptor |
b23f204c | 172 | * @dsg_list: list of children sg's |
b23f204c RK |
173 | * @llis_bus: DMA memory address (physical) start for the LLIs |
174 | * @llis_va: virtual memory address start for the LLIs | |
175 | * @cctl: control reg values for current txd | |
176 | * @ccfg: config reg values for current txd | |
18536134 RK |
177 | * @done: this marks completed descriptors, which should not have their |
178 | * mux released. | |
3b24c20b | 179 | * @cyclic: indicate cyclic transfers |
b23f204c RK |
180 | */ |
181 | struct pl08x_txd { | |
01d8dc64 | 182 | struct virt_dma_desc vd; |
b23f204c | 183 | struct list_head dsg_list; |
b23f204c | 184 | dma_addr_t llis_bus; |
ba6785ff | 185 | u32 *llis_va; |
b23f204c RK |
186 | /* Default cctl value for LLIs */ |
187 | u32 cctl; | |
188 | /* | |
189 | * Settings to be put into the physical channel when we | |
190 | * trigger this txd. Other registers are in llis_va[0]. | |
191 | */ | |
192 | u32 ccfg; | |
18536134 | 193 | bool done; |
3b24c20b | 194 | bool cyclic; |
b23f204c RK |
195 | }; |
196 | ||
197 | /** | |
198 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel | |
199 | * states | |
200 | * @PL08X_CHAN_IDLE: the channel is idle | |
201 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | |
202 | * channel and is running a transfer on it | |
203 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport | |
204 | * channel, but the transfer is currently paused | |
205 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport | |
206 | * channel to become available (only pertains to memcpy channels) | |
207 | */ | |
208 | enum pl08x_dma_chan_state { | |
209 | PL08X_CHAN_IDLE, | |
210 | PL08X_CHAN_RUNNING, | |
211 | PL08X_CHAN_PAUSED, | |
212 | PL08X_CHAN_WAITING, | |
213 | }; | |
214 | ||
215 | /** | |
216 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | |
01d8dc64 | 217 | * @vc: wrappped virtual channel |
b23f204c | 218 | * @phychan: the physical channel utilized by this channel, if there is one |
b23f204c RK |
219 | * @name: name of channel |
220 | * @cd: channel platform data | |
221 | * @runtime_addr: address for RX/TX according to the runtime config | |
b23f204c RK |
222 | * @at: active transaction on this channel |
223 | * @lock: a lock for this channel data | |
224 | * @host: a pointer to the host (internal use) | |
225 | * @state: whether the channel is idle, paused, running etc | |
226 | * @slave: whether this channel is a device (slave) or for memcpy | |
ad0de2ac | 227 | * @signal: the physical DMA request signal which this channel is using |
5e2479bd | 228 | * @mux_use: count of descriptors using this DMA request signal setting |
b23f204c RK |
229 | */ |
230 | struct pl08x_dma_chan { | |
01d8dc64 | 231 | struct virt_dma_chan vc; |
b23f204c | 232 | struct pl08x_phy_chan *phychan; |
550ec36f | 233 | const char *name; |
b23f204c | 234 | const struct pl08x_channel_data *cd; |
ed91c13d | 235 | struct dma_slave_config cfg; |
b23f204c | 236 | struct pl08x_txd *at; |
b23f204c RK |
237 | struct pl08x_driver_data *host; |
238 | enum pl08x_dma_chan_state state; | |
239 | bool slave; | |
ad0de2ac | 240 | int signal; |
5e2479bd | 241 | unsigned mux_use; |
b23f204c RK |
242 | }; |
243 | ||
e8689e63 LW |
244 | /** |
245 | * struct pl08x_driver_data - the local state holder for the PL08x | |
246 | * @slave: slave engine for this instance | |
247 | * @memcpy: memcpy engine for this instance | |
248 | * @base: virtual memory base (remapped) for the PL08x | |
249 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
250 | * @vd: vendor data for this PL08x variant | |
251 | * @pd: platform data passed in from the platform/machine | |
252 | * @phy_chans: array of data for the physical channels | |
253 | * @pool: a pool for the LLI descriptors | |
3e27ee84 VK |
254 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
255 | * fetches | |
30749cb4 | 256 | * @mem_buses: set to indicate memory transfers on AHB2. |
e8689e63 LW |
257 | * @lock: a spinlock for this struct |
258 | */ | |
259 | struct pl08x_driver_data { | |
260 | struct dma_device slave; | |
261 | struct dma_device memcpy; | |
262 | void __iomem *base; | |
263 | struct amba_device *adev; | |
f96ca9ec | 264 | const struct vendor_data *vd; |
e8689e63 LW |
265 | struct pl08x_platform_data *pd; |
266 | struct pl08x_phy_chan *phy_chans; | |
267 | struct dma_pool *pool; | |
30749cb4 RKAL |
268 | u8 lli_buses; |
269 | u8 mem_buses; | |
ba6785ff | 270 | u8 lli_words; |
e8689e63 LW |
271 | }; |
272 | ||
273 | /* | |
274 | * PL08X specific defines | |
275 | */ | |
276 | ||
ba6785ff TF |
277 | /* The order of words in an LLI. */ |
278 | #define PL080_LLI_SRC 0 | |
279 | #define PL080_LLI_DST 1 | |
280 | #define PL080_LLI_LLI 2 | |
281 | #define PL080_LLI_CCTL 3 | |
da1b6c05 | 282 | #define PL080S_LLI_CCTL2 4 |
ba6785ff TF |
283 | |
284 | /* Total words in an LLI. */ | |
285 | #define PL080_LLI_WORDS 4 | |
da1b6c05 | 286 | #define PL080S_LLI_WORDS 8 |
e8689e63 | 287 | |
ba6785ff TF |
288 | /* |
289 | * Number of LLIs in each LLI buffer allocated for one transfer | |
290 | * (maximum times we call dma_pool_alloc on this pool without freeing) | |
291 | */ | |
292 | #define MAX_NUM_TSFR_LLIS 512 | |
e8689e63 LW |
293 | #define PL08X_ALIGN 8 |
294 | ||
295 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
296 | { | |
01d8dc64 | 297 | return container_of(chan, struct pl08x_dma_chan, vc.chan); |
e8689e63 LW |
298 | } |
299 | ||
501e67e8 RKAL |
300 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
301 | { | |
01d8dc64 | 302 | return container_of(tx, struct pl08x_txd, vd.tx); |
501e67e8 RKAL |
303 | } |
304 | ||
6b16c8b1 RK |
305 | /* |
306 | * Mux handling. | |
307 | * | |
308 | * This gives us the DMA request input to the PL08x primecell which the | |
309 | * peripheral described by the channel data will be routed to, possibly | |
310 | * via a board/SoC specific external MUX. One important point to note | |
311 | * here is that this does not depend on the physical channel. | |
312 | */ | |
ad0de2ac | 313 | static int pl08x_request_mux(struct pl08x_dma_chan *plchan) |
6b16c8b1 RK |
314 | { |
315 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
316 | int ret; | |
317 | ||
d7cabeed MB |
318 | if (plchan->mux_use++ == 0 && pd->get_xfer_signal) { |
319 | ret = pd->get_xfer_signal(plchan->cd); | |
5e2479bd RK |
320 | if (ret < 0) { |
321 | plchan->mux_use = 0; | |
6b16c8b1 | 322 | return ret; |
5e2479bd | 323 | } |
6b16c8b1 | 324 | |
ad0de2ac | 325 | plchan->signal = ret; |
6b16c8b1 RK |
326 | } |
327 | return 0; | |
328 | } | |
329 | ||
330 | static void pl08x_release_mux(struct pl08x_dma_chan *plchan) | |
331 | { | |
332 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
333 | ||
5e2479bd RK |
334 | if (plchan->signal >= 0) { |
335 | WARN_ON(plchan->mux_use == 0); | |
336 | ||
d7cabeed MB |
337 | if (--plchan->mux_use == 0 && pd->put_xfer_signal) { |
338 | pd->put_xfer_signal(plchan->cd, plchan->signal); | |
5e2479bd RK |
339 | plchan->signal = -1; |
340 | } | |
6b16c8b1 RK |
341 | } |
342 | } | |
343 | ||
e8689e63 LW |
344 | /* |
345 | * Physical channel handling | |
346 | */ | |
347 | ||
348 | /* Whether a certain channel is busy or not */ | |
349 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
350 | { | |
351 | unsigned int val; | |
352 | ||
d86ccea7 | 353 | val = readl(ch->reg_config); |
e8689e63 LW |
354 | return val & PL080_CONFIG_ACTIVE; |
355 | } | |
356 | ||
ba6785ff TF |
357 | static void pl08x_write_lli(struct pl08x_driver_data *pl08x, |
358 | struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg) | |
359 | { | |
da1b6c05 TF |
360 | if (pl08x->vd->pl080s) |
361 | dev_vdbg(&pl08x->adev->dev, | |
362 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
363 | "clli=0x%08x, cctl=0x%08x, cctl2=0x%08x, ccfg=0x%08x\n", | |
364 | phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST], | |
365 | lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], | |
366 | lli[PL080S_LLI_CCTL2], ccfg); | |
367 | else | |
368 | dev_vdbg(&pl08x->adev->dev, | |
369 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
370 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", | |
371 | phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST], | |
372 | lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg); | |
ba6785ff TF |
373 | |
374 | writel_relaxed(lli[PL080_LLI_SRC], phychan->base + PL080_CH_SRC_ADDR); | |
375 | writel_relaxed(lli[PL080_LLI_DST], phychan->base + PL080_CH_DST_ADDR); | |
376 | writel_relaxed(lli[PL080_LLI_LLI], phychan->base + PL080_CH_LLI); | |
377 | writel_relaxed(lli[PL080_LLI_CCTL], phychan->base + PL080_CH_CONTROL); | |
378 | ||
da1b6c05 TF |
379 | if (pl08x->vd->pl080s) |
380 | writel_relaxed(lli[PL080S_LLI_CCTL2], | |
381 | phychan->base + PL080S_CH_CONTROL2); | |
382 | ||
ba6785ff TF |
383 | writel(ccfg, phychan->reg_config); |
384 | } | |
385 | ||
e8689e63 LW |
386 | /* |
387 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 388 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
389 | * been set when the LLIs were constructed. Poke them into the hardware |
390 | * and start the transfer. | |
e8689e63 | 391 | */ |
eab82533 | 392 | static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) |
e8689e63 | 393 | { |
c885bee4 | 394 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 395 | struct pl08x_phy_chan *phychan = plchan->phychan; |
879f127b RK |
396 | struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc); |
397 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
09b3c323 | 398 | u32 val; |
c885bee4 | 399 | |
879f127b | 400 | list_del(&txd->vd.node); |
eab82533 | 401 | |
c885bee4 | 402 | plchan->at = txd; |
e8689e63 | 403 | |
c885bee4 RKAL |
404 | /* Wait for channel inactive */ |
405 | while (pl08x_phy_channel_busy(phychan)) | |
406 | cpu_relax(); | |
e8689e63 | 407 | |
ba6785ff | 408 | pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg); |
c885bee4 RKAL |
409 | |
410 | /* Enable the DMA channel */ | |
411 | /* Do not access config register until channel shows as disabled */ | |
412 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 413 | cpu_relax(); |
e8689e63 | 414 | |
c885bee4 | 415 | /* Do not access config register until channel shows as inactive */ |
d86ccea7 | 416 | val = readl(phychan->reg_config); |
e8689e63 | 417 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
d86ccea7 | 418 | val = readl(phychan->reg_config); |
e8689e63 | 419 | |
d86ccea7 | 420 | writel(val | PL080_CONFIG_ENABLE, phychan->reg_config); |
e8689e63 LW |
421 | } |
422 | ||
423 | /* | |
81796616 | 424 | * Pause the channel by setting the HALT bit. |
e8689e63 | 425 | * |
81796616 RKAL |
426 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
427 | * the FIFO can only drain if the peripheral is still requesting data. | |
428 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 429 | * |
81796616 RKAL |
430 | * For P->M transfers, disable the peripheral first to stop it filling |
431 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
432 | */ |
433 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
434 | { | |
435 | u32 val; | |
81796616 | 436 | int timeout; |
e8689e63 LW |
437 | |
438 | /* Set the HALT bit and wait for the FIFO to drain */ | |
d86ccea7 | 439 | val = readl(ch->reg_config); |
e8689e63 | 440 | val |= PL080_CONFIG_HALT; |
d86ccea7 | 441 | writel(val, ch->reg_config); |
e8689e63 LW |
442 | |
443 | /* Wait for channel inactive */ | |
81796616 RKAL |
444 | for (timeout = 1000; timeout; timeout--) { |
445 | if (!pl08x_phy_channel_busy(ch)) | |
446 | break; | |
447 | udelay(1); | |
448 | } | |
449 | if (pl08x_phy_channel_busy(ch)) | |
450 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
451 | } |
452 | ||
453 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
454 | { | |
455 | u32 val; | |
456 | ||
457 | /* Clear the HALT bit */ | |
d86ccea7 | 458 | val = readl(ch->reg_config); |
e8689e63 | 459 | val &= ~PL080_CONFIG_HALT; |
d86ccea7 | 460 | writel(val, ch->reg_config); |
e8689e63 LW |
461 | } |
462 | ||
fb526210 RKAL |
463 | /* |
464 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
465 | * clears any pending interrupt status. This should not be used for | |
466 | * an on-going transfer, but as a method of shutting down a channel | |
467 | * (eg, when it's no longer used) or terminating a transfer. | |
468 | */ | |
469 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
470 | struct pl08x_phy_chan *ch) | |
e8689e63 | 471 | { |
d86ccea7 | 472 | u32 val = readl(ch->reg_config); |
e8689e63 | 473 | |
fb526210 RKAL |
474 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
475 | PL080_CONFIG_TC_IRQ_MASK); | |
e8689e63 | 476 | |
d86ccea7 | 477 | writel(val, ch->reg_config); |
fb526210 RKAL |
478 | |
479 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); | |
480 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
481 | } |
482 | ||
483 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
484 | { | |
485 | /* The source width defines the number of bytes */ | |
486 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
487 | ||
f3287a52 AB |
488 | cctl &= PL080_CONTROL_SWIDTH_MASK; |
489 | ||
e8689e63 LW |
490 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { |
491 | case PL080_WIDTH_8BIT: | |
492 | break; | |
493 | case PL080_WIDTH_16BIT: | |
494 | bytes *= 2; | |
495 | break; | |
496 | case PL080_WIDTH_32BIT: | |
497 | bytes *= 4; | |
498 | break; | |
499 | } | |
500 | return bytes; | |
501 | } | |
502 | ||
da1b6c05 TF |
503 | static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1) |
504 | { | |
505 | /* The source width defines the number of bytes */ | |
506 | u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK; | |
507 | ||
f3287a52 AB |
508 | cctl &= PL080_CONTROL_SWIDTH_MASK; |
509 | ||
e8689e63 LW |
510 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { |
511 | case PL080_WIDTH_8BIT: | |
512 | break; | |
513 | case PL080_WIDTH_16BIT: | |
514 | bytes *= 2; | |
515 | break; | |
516 | case PL080_WIDTH_32BIT: | |
517 | bytes *= 4; | |
518 | break; | |
519 | } | |
520 | return bytes; | |
521 | } | |
522 | ||
523 | /* The channel should be paused when calling this */ | |
524 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
525 | { | |
ba6785ff TF |
526 | struct pl08x_driver_data *pl08x = plchan->host; |
527 | const u32 *llis_va, *llis_va_limit; | |
e8689e63 | 528 | struct pl08x_phy_chan *ch; |
68a7faa2 | 529 | dma_addr_t llis_bus; |
e8689e63 | 530 | struct pl08x_txd *txd; |
ba6785ff | 531 | u32 llis_max_words; |
68a7faa2 | 532 | size_t bytes; |
68a7faa2 | 533 | u32 clli; |
e8689e63 | 534 | |
e8689e63 LW |
535 | ch = plchan->phychan; |
536 | txd = plchan->at; | |
537 | ||
68a7faa2 TF |
538 | if (!ch || !txd) |
539 | return 0; | |
540 | ||
e8689e63 | 541 | /* |
db9f136a RKAL |
542 | * Follow the LLIs to get the number of remaining |
543 | * bytes in the currently active transaction. | |
e8689e63 | 544 | */ |
68a7faa2 | 545 | clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 546 | |
68a7faa2 | 547 | /* First get the remaining bytes in the active transfer */ |
da1b6c05 TF |
548 | if (pl08x->vd->pl080s) |
549 | bytes = get_bytes_in_cctl_pl080s( | |
550 | readl(ch->base + PL080_CH_CONTROL), | |
551 | readl(ch->base + PL080S_CH_CONTROL2)); | |
552 | else | |
e8689e63 LW |
553 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); |
554 | ||
68a7faa2 TF |
555 | if (!clli) |
556 | return bytes; | |
db9f136a | 557 | |
68a7faa2 TF |
558 | llis_va = txd->llis_va; |
559 | llis_bus = txd->llis_bus; | |
e8689e63 | 560 | |
ba6785ff | 561 | llis_max_words = pl08x->lli_words * MAX_NUM_TSFR_LLIS; |
68a7faa2 | 562 | BUG_ON(clli < llis_bus || clli >= llis_bus + |
ba6785ff | 563 | sizeof(u32) * llis_max_words); |
db9f136a | 564 | |
68a7faa2 TF |
565 | /* |
566 | * Locate the next LLI - as this is an array, | |
567 | * it's simple maths to find. | |
568 | */ | |
ba6785ff | 569 | llis_va += (clli - llis_bus) / sizeof(u32); |
e8689e63 | 570 | |
ba6785ff TF |
571 | llis_va_limit = llis_va + llis_max_words; |
572 | ||
573 | for (; llis_va < llis_va_limit; llis_va += pl08x->lli_words) { | |
da1b6c05 TF |
574 | if (pl08x->vd->pl080s) |
575 | bytes += get_bytes_in_cctl_pl080s( | |
576 | llis_va[PL080_LLI_CCTL], | |
577 | llis_va[PL080S_LLI_CCTL2]); | |
578 | else | |
579 | bytes += get_bytes_in_cctl(llis_va[PL080_LLI_CCTL]); | |
68a7faa2 TF |
580 | |
581 | /* | |
3b24c20b | 582 | * A LLI pointer going backward terminates the LLI list |
68a7faa2 | 583 | */ |
3b24c20b | 584 | if (llis_va[PL080_LLI_LLI] <= clli) |
68a7faa2 | 585 | break; |
e8689e63 LW |
586 | } |
587 | ||
e8689e63 LW |
588 | return bytes; |
589 | } | |
590 | ||
591 | /* | |
592 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
593 | * |
594 | * Try to locate a physical channel to be used for this transfer. If all | |
595 | * are taken return NULL and the requester will have to cope by using | |
596 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
597 | */ |
598 | static struct pl08x_phy_chan * | |
599 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
600 | struct pl08x_dma_chan *virt_chan) | |
601 | { | |
602 | struct pl08x_phy_chan *ch = NULL; | |
603 | unsigned long flags; | |
604 | int i; | |
605 | ||
e8689e63 LW |
606 | for (i = 0; i < pl08x->vd->channels; i++) { |
607 | ch = &pl08x->phy_chans[i]; | |
608 | ||
609 | spin_lock_irqsave(&ch->lock, flags); | |
610 | ||
affa115e | 611 | if (!ch->locked && !ch->serving) { |
e8689e63 | 612 | ch->serving = virt_chan; |
e8689e63 LW |
613 | spin_unlock_irqrestore(&ch->lock, flags); |
614 | break; | |
615 | } | |
616 | ||
617 | spin_unlock_irqrestore(&ch->lock, flags); | |
618 | } | |
619 | ||
620 | if (i == pl08x->vd->channels) { | |
621 | /* No physical channel available, cope with it */ | |
622 | return NULL; | |
623 | } | |
624 | ||
625 | return ch; | |
626 | } | |
627 | ||
a5a488db | 628 | /* Mark the physical channel as free. Note, this write is atomic. */ |
e8689e63 LW |
629 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, |
630 | struct pl08x_phy_chan *ch) | |
631 | { | |
a5a488db RK |
632 | ch->serving = NULL; |
633 | } | |
e8689e63 | 634 | |
a5a488db RK |
635 | /* |
636 | * Try to allocate a physical channel. When successful, assign it to | |
637 | * this virtual channel, and initiate the next descriptor. The | |
638 | * virtual channel lock must be held at this point. | |
639 | */ | |
640 | static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan) | |
641 | { | |
642 | struct pl08x_driver_data *pl08x = plchan->host; | |
643 | struct pl08x_phy_chan *ch; | |
fb526210 | 644 | |
a5a488db RK |
645 | ch = pl08x_get_phy_channel(pl08x, plchan); |
646 | if (!ch) { | |
647 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
648 | plchan->state = PL08X_CHAN_WAITING; | |
649 | return; | |
650 | } | |
e8689e63 | 651 | |
a5a488db RK |
652 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n", |
653 | ch->id, plchan->name); | |
654 | ||
655 | plchan->phychan = ch; | |
656 | plchan->state = PL08X_CHAN_RUNNING; | |
657 | pl08x_start_next_txd(plchan); | |
658 | } | |
659 | ||
660 | static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch, | |
661 | struct pl08x_dma_chan *plchan) | |
662 | { | |
663 | struct pl08x_driver_data *pl08x = plchan->host; | |
664 | ||
665 | dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n", | |
666 | ch->id, plchan->name); | |
667 | ||
668 | /* | |
669 | * We do this without taking the lock; we're really only concerned | |
670 | * about whether this pointer is NULL or not, and we're guaranteed | |
671 | * that this will only be called when it _already_ is non-NULL. | |
672 | */ | |
673 | ch->serving = plchan; | |
674 | plchan->phychan = ch; | |
675 | plchan->state = PL08X_CHAN_RUNNING; | |
676 | pl08x_start_next_txd(plchan); | |
677 | } | |
678 | ||
679 | /* | |
680 | * Free a physical DMA channel, potentially reallocating it to another | |
681 | * virtual channel if we have any pending. | |
682 | */ | |
683 | static void pl08x_phy_free(struct pl08x_dma_chan *plchan) | |
684 | { | |
685 | struct pl08x_driver_data *pl08x = plchan->host; | |
686 | struct pl08x_dma_chan *p, *next; | |
687 | ||
688 | retry: | |
689 | next = NULL; | |
690 | ||
691 | /* Find a waiting virtual channel for the next transfer. */ | |
01d8dc64 | 692 | list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node) |
a5a488db RK |
693 | if (p->state == PL08X_CHAN_WAITING) { |
694 | next = p; | |
695 | break; | |
696 | } | |
697 | ||
698 | if (!next) { | |
01d8dc64 | 699 | list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node) |
a5a488db RK |
700 | if (p->state == PL08X_CHAN_WAITING) { |
701 | next = p; | |
702 | break; | |
703 | } | |
704 | } | |
705 | ||
706 | /* Ensure that the physical channel is stopped */ | |
707 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); | |
708 | ||
709 | if (next) { | |
710 | bool success; | |
711 | ||
712 | /* | |
713 | * Eww. We know this isn't going to deadlock | |
714 | * but lockdep probably doesn't. | |
715 | */ | |
083be28a | 716 | spin_lock(&next->vc.lock); |
a5a488db RK |
717 | /* Re-check the state now that we have the lock */ |
718 | success = next->state == PL08X_CHAN_WAITING; | |
719 | if (success) | |
720 | pl08x_phy_reassign_start(plchan->phychan, next); | |
083be28a | 721 | spin_unlock(&next->vc.lock); |
a5a488db RK |
722 | |
723 | /* If the state changed, try to find another channel */ | |
724 | if (!success) | |
725 | goto retry; | |
726 | } else { | |
727 | /* No more jobs, so free up the physical channel */ | |
728 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
729 | } | |
730 | ||
731 | plchan->phychan = NULL; | |
732 | plchan->state = PL08X_CHAN_IDLE; | |
e8689e63 LW |
733 | } |
734 | ||
735 | /* | |
736 | * LLI handling | |
737 | */ | |
738 | ||
739 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
740 | { | |
741 | switch (coded) { | |
742 | case PL080_WIDTH_8BIT: | |
743 | return 1; | |
744 | case PL080_WIDTH_16BIT: | |
745 | return 2; | |
746 | case PL080_WIDTH_32BIT: | |
747 | return 4; | |
748 | default: | |
749 | break; | |
750 | } | |
751 | BUG(); | |
752 | return 0; | |
753 | } | |
754 | ||
755 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 756 | size_t tsize) |
e8689e63 LW |
757 | { |
758 | u32 retbits = cctl; | |
759 | ||
e8b5e11d | 760 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
761 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
762 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
763 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
764 | ||
765 | /* Then set the bits according to the parameters */ | |
766 | switch (srcwidth) { | |
767 | case 1: | |
768 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
769 | break; | |
770 | case 2: | |
771 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
772 | break; | |
773 | case 4: | |
774 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
775 | break; | |
776 | default: | |
777 | BUG(); | |
778 | break; | |
779 | } | |
780 | ||
781 | switch (dstwidth) { | |
782 | case 1: | |
783 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
784 | break; | |
785 | case 2: | |
786 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
787 | break; | |
788 | case 4: | |
789 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
790 | break; | |
791 | default: | |
792 | BUG(); | |
793 | break; | |
794 | } | |
795 | ||
5110e51d | 796 | tsize &= PL080_CONTROL_TRANSFER_SIZE_MASK; |
e8689e63 LW |
797 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; |
798 | return retbits; | |
799 | } | |
800 | ||
542361f8 RKAL |
801 | struct pl08x_lli_build_data { |
802 | struct pl08x_txd *txd; | |
542361f8 RKAL |
803 | struct pl08x_bus_data srcbus; |
804 | struct pl08x_bus_data dstbus; | |
805 | size_t remainder; | |
25c94f7f | 806 | u32 lli_bus; |
542361f8 RKAL |
807 | }; |
808 | ||
e8689e63 | 809 | /* |
0532e6fc VK |
810 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
811 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
812 | * masters address with width requirements of transfer (by sending few byte by | |
813 | * byte data), slave is still not aligned, then its width will be reduced to | |
814 | * BYTE. | |
815 | * - prefers the destination bus if both available | |
036f05fd | 816 | * - prefers bus with fixed address (i.e. peripheral) |
e8689e63 | 817 | */ |
542361f8 RKAL |
818 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
819 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) | |
e8689e63 LW |
820 | { |
821 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
542361f8 RKAL |
822 | *mbus = &bd->dstbus; |
823 | *sbus = &bd->srcbus; | |
036f05fd VK |
824 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
825 | *mbus = &bd->srcbus; | |
826 | *sbus = &bd->dstbus; | |
e8689e63 | 827 | } else { |
036f05fd | 828 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
542361f8 RKAL |
829 | *mbus = &bd->dstbus; |
830 | *sbus = &bd->srcbus; | |
036f05fd | 831 | } else { |
542361f8 RKAL |
832 | *mbus = &bd->srcbus; |
833 | *sbus = &bd->dstbus; | |
e8689e63 LW |
834 | } |
835 | } | |
836 | } | |
837 | ||
838 | /* | |
94ae8522 | 839 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 840 | */ |
ba6785ff TF |
841 | static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x, |
842 | struct pl08x_lli_build_data *bd, | |
da1b6c05 | 843 | int num_llis, int len, u32 cctl, u32 cctl2) |
e8689e63 | 844 | { |
ba6785ff TF |
845 | u32 offset = num_llis * pl08x->lli_words; |
846 | u32 *llis_va = bd->txd->llis_va + offset; | |
542361f8 | 847 | dma_addr_t llis_bus = bd->txd->llis_bus; |
e8689e63 LW |
848 | |
849 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
850 | ||
ba6785ff TF |
851 | /* Advance the offset to next LLI. */ |
852 | offset += pl08x->lli_words; | |
853 | ||
854 | llis_va[PL080_LLI_SRC] = bd->srcbus.addr; | |
855 | llis_va[PL080_LLI_DST] = bd->dstbus.addr; | |
856 | llis_va[PL080_LLI_LLI] = (llis_bus + sizeof(u32) * offset); | |
857 | llis_va[PL080_LLI_LLI] |= bd->lli_bus; | |
858 | llis_va[PL080_LLI_CCTL] = cctl; | |
da1b6c05 TF |
859 | if (pl08x->vd->pl080s) |
860 | llis_va[PL080S_LLI_CCTL2] = cctl2; | |
e8689e63 LW |
861 | |
862 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 | 863 | bd->srcbus.addr += len; |
e8689e63 | 864 | if (cctl & PL080_CONTROL_DST_INCR) |
542361f8 | 865 | bd->dstbus.addr += len; |
e8689e63 | 866 | |
542361f8 | 867 | BUG_ON(bd->remainder < len); |
cace6585 | 868 | |
542361f8 | 869 | bd->remainder -= len; |
e8689e63 LW |
870 | } |
871 | ||
ba6785ff TF |
872 | static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x, |
873 | struct pl08x_lli_build_data *bd, u32 *cctl, u32 len, | |
874 | int num_llis, size_t *total_bytes) | |
e8689e63 | 875 | { |
03af500f | 876 | *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); |
da1b6c05 | 877 | pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl, len); |
03af500f | 878 | (*total_bytes) += len; |
e8689e63 LW |
879 | } |
880 | ||
48924e42 TF |
881 | #ifdef VERBOSE_DEBUG |
882 | static void pl08x_dump_lli(struct pl08x_driver_data *pl08x, | |
883 | const u32 *llis_va, int num_llis) | |
884 | { | |
885 | int i; | |
886 | ||
da1b6c05 | 887 | if (pl08x->vd->pl080s) { |
48924e42 | 888 | dev_vdbg(&pl08x->adev->dev, |
da1b6c05 TF |
889 | "%-3s %-9s %-10s %-10s %-10s %-10s %s\n", |
890 | "lli", "", "csrc", "cdst", "clli", "cctl", "cctl2"); | |
891 | for (i = 0; i < num_llis; i++) { | |
892 | dev_vdbg(&pl08x->adev->dev, | |
893 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
894 | i, llis_va, llis_va[PL080_LLI_SRC], | |
895 | llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI], | |
896 | llis_va[PL080_LLI_CCTL], | |
897 | llis_va[PL080S_LLI_CCTL2]); | |
898 | llis_va += pl08x->lli_words; | |
899 | } | |
900 | } else { | |
901 | dev_vdbg(&pl08x->adev->dev, | |
902 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
903 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
904 | for (i = 0; i < num_llis; i++) { | |
905 | dev_vdbg(&pl08x->adev->dev, | |
906 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
907 | i, llis_va, llis_va[PL080_LLI_SRC], | |
908 | llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI], | |
909 | llis_va[PL080_LLI_CCTL]); | |
910 | llis_va += pl08x->lli_words; | |
911 | } | |
48924e42 TF |
912 | } |
913 | } | |
914 | #else | |
915 | static inline void pl08x_dump_lli(struct pl08x_driver_data *pl08x, | |
916 | const u32 *llis_va, int num_llis) {} | |
917 | #endif | |
918 | ||
e8689e63 LW |
919 | /* |
920 | * This fills in the table of LLIs for the transfer descriptor | |
921 | * Note that we assume we never have to change the burst sizes | |
922 | * Return 0 for error | |
923 | */ | |
924 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
925 | struct pl08x_txd *txd) | |
926 | { | |
e8689e63 | 927 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 928 | struct pl08x_lli_build_data bd; |
e8689e63 | 929 | int num_llis = 0; |
03af500f | 930 | u32 cctl, early_bytes = 0; |
b7f69d9d | 931 | size_t max_bytes_per_lli, total_bytes; |
ba6785ff | 932 | u32 *llis_va, *last_lli; |
b7f69d9d | 933 | struct pl08x_sg *dsg; |
e8689e63 | 934 | |
3e27ee84 | 935 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
936 | if (!txd->llis_va) { |
937 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
938 | return 0; | |
939 | } | |
940 | ||
542361f8 | 941 | bd.txd = txd; |
25c94f7f | 942 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
b7f69d9d | 943 | cctl = txd->cctl; |
542361f8 | 944 | |
e8689e63 | 945 | /* Find maximum width of the source bus */ |
542361f8 | 946 | bd.srcbus.maxwidth = |
e8689e63 LW |
947 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
948 | PL080_CONTROL_SWIDTH_SHIFT); | |
949 | ||
950 | /* Find maximum width of the destination bus */ | |
542361f8 | 951 | bd.dstbus.maxwidth = |
e8689e63 LW |
952 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
953 | PL080_CONTROL_DWIDTH_SHIFT); | |
954 | ||
b7f69d9d VK |
955 | list_for_each_entry(dsg, &txd->dsg_list, node) { |
956 | total_bytes = 0; | |
957 | cctl = txd->cctl; | |
e8689e63 | 958 | |
b7f69d9d VK |
959 | bd.srcbus.addr = dsg->src_addr; |
960 | bd.dstbus.addr = dsg->dst_addr; | |
961 | bd.remainder = dsg->len; | |
962 | bd.srcbus.buswidth = bd.srcbus.maxwidth; | |
963 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 | 964 | |
b7f69d9d | 965 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
e8689e63 | 966 | |
b90ca063 AP |
967 | dev_vdbg(&pl08x->adev->dev, |
968 | "src=0x%08llx%s/%u dst=0x%08llx%s/%u len=%zu\n", | |
969 | (u64)bd.srcbus.addr, | |
970 | cctl & PL080_CONTROL_SRC_INCR ? "+" : "", | |
b7f69d9d | 971 | bd.srcbus.buswidth, |
b90ca063 AP |
972 | (u64)bd.dstbus.addr, |
973 | cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
b7f69d9d VK |
974 | bd.dstbus.buswidth, |
975 | bd.remainder); | |
976 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", | |
977 | mbus == &bd.srcbus ? "src" : "dst", | |
978 | sbus == &bd.srcbus ? "src" : "dst"); | |
fc74eb79 | 979 | |
b7f69d9d VK |
980 | /* |
981 | * Zero length is only allowed if all these requirements are | |
982 | * met: | |
983 | * - flow controller is peripheral. | |
984 | * - src.addr is aligned to src.width | |
985 | * - dst.addr is aligned to dst.width | |
986 | * | |
987 | * sg_len == 1 should be true, as there can be two cases here: | |
988 | * | |
989 | * - Memory addresses are contiguous and are not scattered. | |
990 | * Here, Only one sg will be passed by user driver, with | |
991 | * memory address and zero length. We pass this to controller | |
992 | * and after the transfer it will receive the last burst | |
993 | * request from peripheral and so transfer finishes. | |
994 | * | |
995 | * - Memory addresses are scattered and are not contiguous. | |
996 | * Here, Obviously as DMA controller doesn't know when a lli's | |
997 | * transfer gets over, it can't load next lli. So in this | |
998 | * case, there has to be an assumption that only one lli is | |
999 | * supported. Thus, we can't have scattered addresses. | |
1000 | */ | |
1001 | if (!bd.remainder) { | |
1002 | u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> | |
1003 | PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1004 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && | |
0a235657 | 1005 | (fc <= PL080_FLOW_SRC2DST_SRC))) { |
b7f69d9d VK |
1006 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", |
1007 | __func__); | |
1008 | return 0; | |
1009 | } | |
0a235657 | 1010 | |
1c38b289 AP |
1011 | if (!IS_BUS_ALIGNED(&bd.srcbus) || |
1012 | !IS_BUS_ALIGNED(&bd.dstbus)) { | |
b7f69d9d VK |
1013 | dev_err(&pl08x->adev->dev, |
1014 | "%s src & dst address must be aligned to src" | |
1015 | " & dst width if peripheral is flow controller", | |
1016 | __func__); | |
1017 | return 0; | |
1018 | } | |
03af500f | 1019 | |
b7f69d9d VK |
1020 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
1021 | bd.dstbus.buswidth, 0); | |
ba6785ff | 1022 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
da1b6c05 | 1023 | 0, cctl, 0); |
b7f69d9d VK |
1024 | break; |
1025 | } | |
e8689e63 LW |
1026 | |
1027 | /* | |
b7f69d9d VK |
1028 | * Send byte by byte for following cases |
1029 | * - Less than a bus width available | |
1030 | * - until master bus is aligned | |
e8689e63 | 1031 | */ |
b7f69d9d VK |
1032 | if (bd.remainder < mbus->buswidth) |
1033 | early_bytes = bd.remainder; | |
1c38b289 AP |
1034 | else if (!IS_BUS_ALIGNED(mbus)) { |
1035 | early_bytes = mbus->buswidth - | |
1036 | (mbus->addr & (mbus->buswidth - 1)); | |
b7f69d9d VK |
1037 | if ((bd.remainder - early_bytes) < mbus->buswidth) |
1038 | early_bytes = bd.remainder; | |
1039 | } | |
e8689e63 | 1040 | |
b7f69d9d VK |
1041 | if (early_bytes) { |
1042 | dev_vdbg(&pl08x->adev->dev, | |
6fc8ae78 | 1043 | "%s byte width LLIs (remain 0x%08zx)\n", |
b7f69d9d | 1044 | __func__, bd.remainder); |
ba6785ff TF |
1045 | prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes, |
1046 | num_llis++, &total_bytes); | |
e8689e63 LW |
1047 | } |
1048 | ||
b7f69d9d VK |
1049 | if (bd.remainder) { |
1050 | /* | |
1051 | * Master now aligned | |
1052 | * - if slave is not then we must set its width down | |
1053 | */ | |
1c38b289 | 1054 | if (!IS_BUS_ALIGNED(sbus)) { |
b7f69d9d VK |
1055 | dev_dbg(&pl08x->adev->dev, |
1056 | "%s set down bus width to one byte\n", | |
1057 | __func__); | |
fa6a940b | 1058 | |
b7f69d9d VK |
1059 | sbus->buswidth = 1; |
1060 | } | |
e8689e63 LW |
1061 | |
1062 | /* | |
b7f69d9d VK |
1063 | * Bytes transferred = tsize * src width, not |
1064 | * MIN(buswidths) | |
e8689e63 | 1065 | */ |
b7f69d9d | 1066 | max_bytes_per_lli = bd.srcbus.buswidth * |
5110e51d | 1067 | pl08x->vd->max_transfer_size; |
b7f69d9d VK |
1068 | dev_vdbg(&pl08x->adev->dev, |
1069 | "%s max bytes per lli = %zu\n", | |
1070 | __func__, max_bytes_per_lli); | |
e8689e63 LW |
1071 | |
1072 | /* | |
b7f69d9d VK |
1073 | * Make largest possible LLIs until less than one bus |
1074 | * width left | |
e8689e63 | 1075 | */ |
b7f69d9d VK |
1076 | while (bd.remainder > (mbus->buswidth - 1)) { |
1077 | size_t lli_len, tsize, width; | |
e8689e63 | 1078 | |
b7f69d9d VK |
1079 | /* |
1080 | * If enough left try to send max possible, | |
1081 | * otherwise try to send the remainder | |
1082 | */ | |
1083 | lli_len = min(bd.remainder, max_bytes_per_lli); | |
16a2e7d3 | 1084 | |
b7f69d9d VK |
1085 | /* |
1086 | * Check against maximum bus alignment: | |
1087 | * Calculate actual transfer size in relation to | |
1088 | * bus width an get a maximum remainder of the | |
1089 | * highest bus width - 1 | |
1090 | */ | |
1091 | width = max(mbus->buswidth, sbus->buswidth); | |
1092 | lli_len = (lli_len / width) * width; | |
1093 | tsize = lli_len / bd.srcbus.buswidth; | |
1094 | ||
1095 | dev_vdbg(&pl08x->adev->dev, | |
1096 | "%s fill lli with single lli chunk of " | |
1097 | "size 0x%08zx (remainder 0x%08zx)\n", | |
1098 | __func__, lli_len, bd.remainder); | |
1099 | ||
1100 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, | |
16a2e7d3 | 1101 | bd.dstbus.buswidth, tsize); |
ba6785ff | 1102 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
da1b6c05 | 1103 | lli_len, cctl, tsize); |
b7f69d9d VK |
1104 | total_bytes += lli_len; |
1105 | } | |
e8689e63 | 1106 | |
b7f69d9d VK |
1107 | /* |
1108 | * Send any odd bytes | |
1109 | */ | |
1110 | if (bd.remainder) { | |
1111 | dev_vdbg(&pl08x->adev->dev, | |
1112 | "%s align with boundary, send odd bytes (remain %zu)\n", | |
1113 | __func__, bd.remainder); | |
ba6785ff TF |
1114 | prep_byte_width_lli(pl08x, &bd, &cctl, |
1115 | bd.remainder, num_llis++, &total_bytes); | |
b7f69d9d | 1116 | } |
e8689e63 | 1117 | } |
16a2e7d3 | 1118 | |
b7f69d9d VK |
1119 | if (total_bytes != dsg->len) { |
1120 | dev_err(&pl08x->adev->dev, | |
1121 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", | |
1122 | __func__, total_bytes, dsg->len); | |
1123 | return 0; | |
1124 | } | |
e8689e63 | 1125 | |
b7f69d9d VK |
1126 | if (num_llis >= MAX_NUM_TSFR_LLIS) { |
1127 | dev_err(&pl08x->adev->dev, | |
1128 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
ba6785ff | 1129 | __func__, MAX_NUM_TSFR_LLIS); |
b7f69d9d VK |
1130 | return 0; |
1131 | } | |
e8689e63 | 1132 | } |
b58b6b5b RKAL |
1133 | |
1134 | llis_va = txd->llis_va; | |
ba6785ff | 1135 | last_lli = llis_va + (num_llis - 1) * pl08x->lli_words; |
e8689e63 | 1136 | |
3b24c20b AB |
1137 | if (txd->cyclic) { |
1138 | /* Link back to the first LLI. */ | |
1139 | last_lli[PL080_LLI_LLI] = txd->llis_bus | bd.lli_bus; | |
1140 | } else { | |
1141 | /* The final LLI terminates the LLI. */ | |
1142 | last_lli[PL080_LLI_LLI] = 0; | |
1143 | /* The final LLI element shall also fire an interrupt. */ | |
1144 | last_lli[PL080_LLI_CCTL] |= PL080_CONTROL_TC_IRQ_EN; | |
e8689e63 | 1145 | } |
e8689e63 | 1146 | |
48924e42 | 1147 | pl08x_dump_lli(pl08x, llis_va, num_llis); |
e8689e63 LW |
1148 | |
1149 | return num_llis; | |
1150 | } | |
1151 | ||
e8689e63 LW |
1152 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, |
1153 | struct pl08x_txd *txd) | |
1154 | { | |
b7f69d9d VK |
1155 | struct pl08x_sg *dsg, *_dsg; |
1156 | ||
c1205646 VK |
1157 | if (txd->llis_va) |
1158 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); | |
e8689e63 | 1159 | |
b7f69d9d VK |
1160 | list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) { |
1161 | list_del(&dsg->node); | |
1162 | kfree(dsg); | |
1163 | } | |
1164 | ||
e8689e63 LW |
1165 | kfree(txd); |
1166 | } | |
1167 | ||
18536134 RK |
1168 | static void pl08x_desc_free(struct virt_dma_desc *vd) |
1169 | { | |
1170 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1171 | struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan); | |
18536134 | 1172 | |
89116bf9 | 1173 | dma_descriptor_unmap(&vd->tx); |
18536134 RK |
1174 | if (!txd->done) |
1175 | pl08x_release_mux(plchan); | |
1176 | ||
18536134 | 1177 | pl08x_free_txd(plchan->host, txd); |
18536134 RK |
1178 | } |
1179 | ||
e8689e63 LW |
1180 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, |
1181 | struct pl08x_dma_chan *plchan) | |
1182 | { | |
ea160561 | 1183 | LIST_HEAD(head); |
e8689e63 | 1184 | |
879f127b | 1185 | vchan_get_all_descriptors(&plchan->vc, &head); |
91998261 | 1186 | vchan_dma_desc_free_list(&plchan->vc, &head); |
e8689e63 LW |
1187 | } |
1188 | ||
1189 | /* | |
1190 | * The DMA ENGINE API | |
1191 | */ | |
1192 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
1193 | { | |
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
1198 | { | |
a068682c RK |
1199 | /* Ensure all queued descriptors are freed */ |
1200 | vchan_free_chan_resources(to_virt_chan(chan)); | |
e8689e63 LW |
1201 | } |
1202 | ||
e8689e63 LW |
1203 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( |
1204 | struct dma_chan *chan, unsigned long flags) | |
1205 | { | |
1206 | struct dma_async_tx_descriptor *retval = NULL; | |
1207 | ||
1208 | return retval; | |
1209 | } | |
1210 | ||
1211 | /* | |
94ae8522 RKAL |
1212 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
1213 | * If slaves are relying on interrupts to signal completion this function | |
1214 | * must not be called with interrupts disabled. | |
e8689e63 | 1215 | */ |
3e27ee84 VK |
1216 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
1217 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
1218 | { |
1219 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
06e885b7 RK |
1220 | struct virt_dma_desc *vd; |
1221 | unsigned long flags; | |
e8689e63 | 1222 | enum dma_status ret; |
06e885b7 | 1223 | size_t bytes = 0; |
e8689e63 | 1224 | |
96a2af41 | 1225 | ret = dma_cookie_status(chan, cookie, txstate); |
0996e895 | 1226 | if (ret == DMA_COMPLETE) |
e8689e63 | 1227 | return ret; |
e8689e63 | 1228 | |
06e885b7 RK |
1229 | /* |
1230 | * There's no point calculating the residue if there's | |
1231 | * no txstate to store the value. | |
1232 | */ | |
1233 | if (!txstate) { | |
1234 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1235 | ret = DMA_PAUSED; | |
1236 | return ret; | |
1237 | } | |
1238 | ||
1239 | spin_lock_irqsave(&plchan->vc.lock, flags); | |
1240 | ret = dma_cookie_status(chan, cookie, txstate); | |
0996e895 | 1241 | if (ret != DMA_COMPLETE) { |
06e885b7 RK |
1242 | vd = vchan_find_desc(&plchan->vc, cookie); |
1243 | if (vd) { | |
1244 | /* On the issued list, so hasn't been processed yet */ | |
1245 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1246 | struct pl08x_sg *dsg; | |
1247 | ||
1248 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1249 | bytes += dsg->len; | |
1250 | } else { | |
1251 | bytes = pl08x_getbytes_chan(plchan); | |
1252 | } | |
1253 | } | |
1254 | spin_unlock_irqrestore(&plchan->vc.lock, flags); | |
1255 | ||
e8689e63 LW |
1256 | /* |
1257 | * This cookie not complete yet | |
96a2af41 | 1258 | * Get number of bytes left in the active transactions and queue |
e8689e63 | 1259 | */ |
06e885b7 | 1260 | dma_set_residue(txstate, bytes); |
e8689e63 | 1261 | |
06e885b7 RK |
1262 | if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS) |
1263 | ret = DMA_PAUSED; | |
e8689e63 LW |
1264 | |
1265 | /* Whether waiting or running, we're in progress */ | |
06e885b7 | 1266 | return ret; |
e8689e63 LW |
1267 | } |
1268 | ||
1269 | /* PrimeCell DMA extension */ | |
1270 | struct burst_table { | |
760596c6 | 1271 | u32 burstwords; |
e8689e63 LW |
1272 | u32 reg; |
1273 | }; | |
1274 | ||
1275 | static const struct burst_table burst_sizes[] = { | |
1276 | { | |
1277 | .burstwords = 256, | |
760596c6 | 1278 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
1279 | }, |
1280 | { | |
1281 | .burstwords = 128, | |
760596c6 | 1282 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
1283 | }, |
1284 | { | |
1285 | .burstwords = 64, | |
760596c6 | 1286 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
1287 | }, |
1288 | { | |
1289 | .burstwords = 32, | |
760596c6 | 1290 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
1291 | }, |
1292 | { | |
1293 | .burstwords = 16, | |
760596c6 | 1294 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
1295 | }, |
1296 | { | |
1297 | .burstwords = 8, | |
760596c6 | 1298 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1299 | }, |
1300 | { | |
1301 | .burstwords = 4, | |
760596c6 | 1302 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1303 | }, |
1304 | { | |
760596c6 RKAL |
1305 | .burstwords = 0, |
1306 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1307 | }, |
1308 | }; | |
1309 | ||
121c8476 RKAL |
1310 | /* |
1311 | * Given the source and destination available bus masks, select which | |
1312 | * will be routed to each port. We try to have source and destination | |
1313 | * on separate ports, but always respect the allowable settings. | |
1314 | */ | |
1315 | static u32 pl08x_select_bus(u8 src, u8 dst) | |
1316 | { | |
1317 | u32 cctl = 0; | |
1318 | ||
1319 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1320 | cctl |= PL080_CONTROL_DST_AHB2; | |
1321 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1322 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1323 | ||
1324 | return cctl; | |
1325 | } | |
1326 | ||
f14c426c RKAL |
1327 | static u32 pl08x_cctl(u32 cctl) |
1328 | { | |
1329 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1330 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1331 | PL080_CONTROL_PROT_MASK); | |
1332 | ||
1333 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1334 | return cctl | PL080_CONTROL_PROT_SYS; | |
1335 | } | |
1336 | ||
aa88cdaa RKAL |
1337 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1338 | { | |
1339 | switch (width) { | |
1340 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1341 | return PL080_WIDTH_8BIT; | |
1342 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1343 | return PL080_WIDTH_16BIT; | |
1344 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1345 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1346 | default: |
1347 | return ~0; | |
aa88cdaa | 1348 | } |
aa88cdaa RKAL |
1349 | } |
1350 | ||
760596c6 RKAL |
1351 | static u32 pl08x_burst(u32 maxburst) |
1352 | { | |
1353 | int i; | |
1354 | ||
1355 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1356 | if (burst_sizes[i].burstwords <= maxburst) | |
1357 | break; | |
1358 | ||
1359 | return burst_sizes[i].reg; | |
1360 | } | |
1361 | ||
9862ba17 RK |
1362 | static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan, |
1363 | enum dma_slave_buswidth addr_width, u32 maxburst) | |
1364 | { | |
1365 | u32 width, burst, cctl = 0; | |
1366 | ||
1367 | width = pl08x_width(addr_width); | |
1368 | if (width == ~0) | |
1369 | return ~0; | |
1370 | ||
1371 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; | |
1372 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1373 | ||
1374 | /* | |
1375 | * If this channel will only request single transfers, set this | |
1376 | * down to ONE element. Also select one element if no maxburst | |
1377 | * is specified. | |
1378 | */ | |
1379 | if (plchan->cd->single) | |
1380 | maxburst = 1; | |
1381 | ||
1382 | burst = pl08x_burst(maxburst); | |
1383 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1384 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
1385 | ||
1386 | return pl08x_cctl(cctl); | |
1387 | } | |
1388 | ||
f0fd9446 RKAL |
1389 | static int dma_set_runtime_config(struct dma_chan *chan, |
1390 | struct dma_slave_config *config) | |
e8689e63 LW |
1391 | { |
1392 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
da1b6c05 | 1393 | struct pl08x_driver_data *pl08x = plchan->host; |
b7f75865 RKAL |
1394 | |
1395 | if (!plchan->slave) | |
1396 | return -EINVAL; | |
e8689e63 | 1397 | |
dc8d5f8d RK |
1398 | /* Reject definitely invalid configurations */ |
1399 | if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || | |
1400 | config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
f0fd9446 | 1401 | return -EINVAL; |
e8689e63 | 1402 | |
da1b6c05 TF |
1403 | if (config->device_fc && pl08x->vd->pl080s) { |
1404 | dev_err(&pl08x->adev->dev, | |
1405 | "%s: PL080S does not support peripheral flow control\n", | |
1406 | __func__); | |
1407 | return -EINVAL; | |
1408 | } | |
1409 | ||
ed91c13d RK |
1410 | plchan->cfg = *config; |
1411 | ||
f0fd9446 | 1412 | return 0; |
e8689e63 LW |
1413 | } |
1414 | ||
1415 | /* | |
1416 | * Slave transactions callback to the slave device to allow | |
1417 | * synchronization of slave DMA signals with the DMAC enable | |
1418 | */ | |
1419 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1420 | { | |
1421 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1422 | unsigned long flags; |
1423 | ||
083be28a | 1424 | spin_lock_irqsave(&plchan->vc.lock, flags); |
879f127b | 1425 | if (vchan_issue_pending(&plchan->vc)) { |
a5a488db RK |
1426 | if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING) |
1427 | pl08x_phy_alloc_and_start(plchan); | |
e8689e63 | 1428 | } |
083be28a | 1429 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1430 | } |
1431 | ||
879f127b | 1432 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan) |
ac3cd20d | 1433 | { |
b201c111 | 1434 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d RKAL |
1435 | |
1436 | if (txd) { | |
b7f69d9d | 1437 | INIT_LIST_HEAD(&txd->dsg_list); |
4983a04f RKAL |
1438 | |
1439 | /* Always enable error and terminal interrupts */ | |
1440 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1441 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1442 | } |
1443 | return txd; | |
1444 | } | |
1445 | ||
e8689e63 LW |
1446 | /* |
1447 | * Initialize a descriptor to be used by memcpy submit | |
1448 | */ | |
1449 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1450 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1451 | size_t len, unsigned long flags) | |
1452 | { | |
1453 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1454 | struct pl08x_driver_data *pl08x = plchan->host; | |
1455 | struct pl08x_txd *txd; | |
b7f69d9d | 1456 | struct pl08x_sg *dsg; |
e8689e63 LW |
1457 | int ret; |
1458 | ||
879f127b | 1459 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1460 | if (!txd) { |
1461 | dev_err(&pl08x->adev->dev, | |
1462 | "%s no memory for descriptor\n", __func__); | |
1463 | return NULL; | |
1464 | } | |
1465 | ||
b7f69d9d VK |
1466 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); |
1467 | if (!dsg) { | |
1468 | pl08x_free_txd(pl08x, txd); | |
1469 | dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n", | |
1470 | __func__); | |
1471 | return NULL; | |
1472 | } | |
1473 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1474 | ||
b7f69d9d VK |
1475 | dsg->src_addr = src; |
1476 | dsg->dst_addr = dest; | |
1477 | dsg->len = len; | |
e8689e63 LW |
1478 | |
1479 | /* Set platform data for m2m */ | |
4983a04f | 1480 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
dc8d5f8d | 1481 | txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy & |
c7da9a56 | 1482 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); |
4983a04f | 1483 | |
e8689e63 | 1484 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1485 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1486 | |
c7da9a56 | 1487 | if (pl08x->vd->dualmaster) |
121c8476 RKAL |
1488 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
1489 | pl08x->mem_buses); | |
e8689e63 | 1490 | |
aa4afb75 RK |
1491 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1492 | if (!ret) { | |
1493 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 1494 | return NULL; |
aa4afb75 | 1495 | } |
e8689e63 | 1496 | |
879f127b | 1497 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1498 | } |
1499 | ||
3b24c20b AB |
1500 | static struct pl08x_txd *pl08x_init_txd( |
1501 | struct dma_chan *chan, | |
1502 | enum dma_transfer_direction direction, | |
1503 | dma_addr_t *slave_addr) | |
e8689e63 LW |
1504 | { |
1505 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1506 | struct pl08x_driver_data *pl08x = plchan->host; | |
1507 | struct pl08x_txd *txd; | |
dc8d5f8d | 1508 | enum dma_slave_buswidth addr_width; |
0a235657 | 1509 | int ret, tmp; |
409ec8db | 1510 | u8 src_buses, dst_buses; |
dc8d5f8d | 1511 | u32 maxburst, cctl; |
e8689e63 | 1512 | |
879f127b | 1513 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1514 | if (!txd) { |
1515 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1516 | return NULL; | |
1517 | } | |
1518 | ||
e8689e63 LW |
1519 | /* |
1520 | * Set up addresses, the PrimeCell configured address | |
1521 | * will take precedence since this may configure the | |
1522 | * channel target address dynamically at runtime. | |
1523 | */ | |
db8196df | 1524 | if (direction == DMA_MEM_TO_DEV) { |
dc8d5f8d | 1525 | cctl = PL080_CONTROL_SRC_INCR; |
3b24c20b | 1526 | *slave_addr = plchan->cfg.dst_addr; |
dc8d5f8d RK |
1527 | addr_width = plchan->cfg.dst_addr_width; |
1528 | maxburst = plchan->cfg.dst_maxburst; | |
409ec8db RK |
1529 | src_buses = pl08x->mem_buses; |
1530 | dst_buses = plchan->cd->periph_buses; | |
db8196df | 1531 | } else if (direction == DMA_DEV_TO_MEM) { |
dc8d5f8d | 1532 | cctl = PL080_CONTROL_DST_INCR; |
3b24c20b | 1533 | *slave_addr = plchan->cfg.src_addr; |
dc8d5f8d RK |
1534 | addr_width = plchan->cfg.src_addr_width; |
1535 | maxburst = plchan->cfg.src_maxburst; | |
409ec8db RK |
1536 | src_buses = plchan->cd->periph_buses; |
1537 | dst_buses = pl08x->mem_buses; | |
e8689e63 | 1538 | } else { |
b7f69d9d | 1539 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1540 | dev_err(&pl08x->adev->dev, |
1541 | "%s direction unsupported\n", __func__); | |
1542 | return NULL; | |
1543 | } | |
e8689e63 | 1544 | |
dc8d5f8d | 1545 | cctl |= pl08x_get_cctl(plchan, addr_width, maxburst); |
800d683e RK |
1546 | if (cctl == ~0) { |
1547 | pl08x_free_txd(pl08x, txd); | |
1548 | dev_err(&pl08x->adev->dev, | |
1549 | "DMA slave configuration botched?\n"); | |
1550 | return NULL; | |
1551 | } | |
1552 | ||
409ec8db RK |
1553 | txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses); |
1554 | ||
95442b22 | 1555 | if (plchan->cfg.device_fc) |
db8196df | 1556 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : |
0a235657 VK |
1557 | PL080_FLOW_PER2MEM_PER; |
1558 | else | |
db8196df | 1559 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER : |
0a235657 VK |
1560 | PL080_FLOW_PER2MEM; |
1561 | ||
1562 | txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1563 | ||
c48d4963 RK |
1564 | ret = pl08x_request_mux(plchan); |
1565 | if (ret < 0) { | |
1566 | pl08x_free_txd(pl08x, txd); | |
1567 | dev_dbg(&pl08x->adev->dev, | |
1568 | "unable to mux for transfer on %s due to platform restrictions\n", | |
1569 | plchan->name); | |
1570 | return NULL; | |
1571 | } | |
1572 | ||
1573 | dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n", | |
1574 | plchan->signal, plchan->name); | |
1575 | ||
1576 | /* Assign the flow control signal to this channel */ | |
1577 | if (direction == DMA_MEM_TO_DEV) | |
1578 | txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
1579 | else | |
1580 | txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
1581 | ||
3b24c20b AB |
1582 | return txd; |
1583 | } | |
1584 | ||
1585 | static int pl08x_tx_add_sg(struct pl08x_txd *txd, | |
1586 | enum dma_transfer_direction direction, | |
1587 | dma_addr_t slave_addr, | |
1588 | dma_addr_t buf_addr, | |
1589 | unsigned int len) | |
1590 | { | |
1591 | struct pl08x_sg *dsg; | |
1592 | ||
1593 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); | |
1594 | if (!dsg) | |
1595 | return -ENOMEM; | |
1596 | ||
1597 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1598 | ||
1599 | dsg->len = len; | |
1600 | if (direction == DMA_MEM_TO_DEV) { | |
1601 | dsg->src_addr = buf_addr; | |
1602 | dsg->dst_addr = slave_addr; | |
1603 | } else { | |
1604 | dsg->src_addr = slave_addr; | |
1605 | dsg->dst_addr = buf_addr; | |
1606 | } | |
1607 | ||
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( | |
1612 | struct dma_chan *chan, struct scatterlist *sgl, | |
1613 | unsigned int sg_len, enum dma_transfer_direction direction, | |
1614 | unsigned long flags, void *context) | |
1615 | { | |
1616 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1617 | struct pl08x_driver_data *pl08x = plchan->host; | |
1618 | struct pl08x_txd *txd; | |
1619 | struct scatterlist *sg; | |
1620 | int ret, tmp; | |
1621 | dma_addr_t slave_addr; | |
1622 | ||
1623 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", | |
1624 | __func__, sg_dma_len(sgl), plchan->name); | |
1625 | ||
1626 | txd = pl08x_init_txd(chan, direction, &slave_addr); | |
1627 | if (!txd) | |
1628 | return NULL; | |
1629 | ||
b7f69d9d | 1630 | for_each_sg(sgl, sg, sg_len, tmp) { |
3b24c20b AB |
1631 | ret = pl08x_tx_add_sg(txd, direction, slave_addr, |
1632 | sg_dma_address(sg), | |
1633 | sg_dma_len(sg)); | |
1634 | if (ret) { | |
c48d4963 | 1635 | pl08x_release_mux(plchan); |
b7f69d9d VK |
1636 | pl08x_free_txd(pl08x, txd); |
1637 | dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n", | |
1638 | __func__); | |
1639 | return NULL; | |
1640 | } | |
3b24c20b | 1641 | } |
b7f69d9d | 1642 | |
3b24c20b AB |
1643 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1644 | if (!ret) { | |
1645 | pl08x_release_mux(plchan); | |
1646 | pl08x_free_txd(pl08x, txd); | |
1647 | return NULL; | |
1648 | } | |
1649 | ||
1650 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); | |
1651 | } | |
1652 | ||
1653 | static struct dma_async_tx_descriptor *pl08x_prep_dma_cyclic( | |
1654 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
1655 | size_t period_len, enum dma_transfer_direction direction, | |
31c1e5a1 | 1656 | unsigned long flags) |
3b24c20b AB |
1657 | { |
1658 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1659 | struct pl08x_driver_data *pl08x = plchan->host; | |
1660 | struct pl08x_txd *txd; | |
1661 | int ret, tmp; | |
1662 | dma_addr_t slave_addr; | |
1663 | ||
1664 | dev_dbg(&pl08x->adev->dev, | |
6fc8ae78 | 1665 | "%s prepare cyclic transaction of %zd/%zd bytes %s %s\n", |
3b24c20b AB |
1666 | __func__, period_len, buf_len, |
1667 | direction == DMA_MEM_TO_DEV ? "to" : "from", | |
1668 | plchan->name); | |
1669 | ||
1670 | txd = pl08x_init_txd(chan, direction, &slave_addr); | |
1671 | if (!txd) | |
1672 | return NULL; | |
1673 | ||
1674 | txd->cyclic = true; | |
1675 | txd->cctl |= PL080_CONTROL_TC_IRQ_EN; | |
1676 | for (tmp = 0; tmp < buf_len; tmp += period_len) { | |
1677 | ret = pl08x_tx_add_sg(txd, direction, slave_addr, | |
1678 | buf_addr + tmp, period_len); | |
1679 | if (ret) { | |
1680 | pl08x_release_mux(plchan); | |
1681 | pl08x_free_txd(pl08x, txd); | |
1682 | return NULL; | |
b7f69d9d VK |
1683 | } |
1684 | } | |
1685 | ||
aa4afb75 RK |
1686 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1687 | if (!ret) { | |
1688 | pl08x_release_mux(plchan); | |
1689 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 1690 | return NULL; |
aa4afb75 | 1691 | } |
e8689e63 | 1692 | |
879f127b | 1693 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1694 | } |
1695 | ||
1696 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1697 | unsigned long arg) | |
1698 | { | |
1699 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1700 | struct pl08x_driver_data *pl08x = plchan->host; | |
1701 | unsigned long flags; | |
1702 | int ret = 0; | |
1703 | ||
1704 | /* Controls applicable to inactive channels */ | |
1705 | if (cmd == DMA_SLAVE_CONFIG) { | |
f0fd9446 RKAL |
1706 | return dma_set_runtime_config(chan, |
1707 | (struct dma_slave_config *)arg); | |
e8689e63 LW |
1708 | } |
1709 | ||
1710 | /* | |
1711 | * Anything succeeds on channels with no physical allocation and | |
1712 | * no queued transfers. | |
1713 | */ | |
083be28a | 1714 | spin_lock_irqsave(&plchan->vc.lock, flags); |
e8689e63 | 1715 | if (!plchan->phychan && !plchan->at) { |
083be28a | 1716 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1717 | return 0; |
1718 | } | |
1719 | ||
1720 | switch (cmd) { | |
1721 | case DMA_TERMINATE_ALL: | |
1722 | plchan->state = PL08X_CHAN_IDLE; | |
1723 | ||
1724 | if (plchan->phychan) { | |
e8689e63 LW |
1725 | /* |
1726 | * Mark physical channel as free and free any slave | |
1727 | * signal | |
1728 | */ | |
a5a488db | 1729 | pl08x_phy_free(plchan); |
e8689e63 | 1730 | } |
e8689e63 LW |
1731 | /* Dequeue jobs and free LLIs */ |
1732 | if (plchan->at) { | |
18536134 | 1733 | pl08x_desc_free(&plchan->at->vd); |
e8689e63 LW |
1734 | plchan->at = NULL; |
1735 | } | |
1736 | /* Dequeue jobs not yet fired as well */ | |
1737 | pl08x_free_txd_list(pl08x, plchan); | |
1738 | break; | |
1739 | case DMA_PAUSE: | |
1740 | pl08x_pause_phy_chan(plchan->phychan); | |
1741 | plchan->state = PL08X_CHAN_PAUSED; | |
1742 | break; | |
1743 | case DMA_RESUME: | |
1744 | pl08x_resume_phy_chan(plchan->phychan); | |
1745 | plchan->state = PL08X_CHAN_RUNNING; | |
1746 | break; | |
1747 | default: | |
1748 | /* Unknown command */ | |
1749 | ret = -ENXIO; | |
1750 | break; | |
1751 | } | |
1752 | ||
083be28a | 1753 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1754 | |
1755 | return ret; | |
1756 | } | |
1757 | ||
1758 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1759 | { | |
7703eac9 | 1760 | struct pl08x_dma_chan *plchan; |
e8689e63 LW |
1761 | char *name = chan_id; |
1762 | ||
7703eac9 RKAL |
1763 | /* Reject channels for devices not bound to this driver */ |
1764 | if (chan->device->dev->driver != &pl08x_amba_driver.drv) | |
1765 | return false; | |
1766 | ||
1767 | plchan = to_pl08x_chan(chan); | |
1768 | ||
e8689e63 LW |
1769 | /* Check that the channel is not taken! */ |
1770 | if (!strcmp(plchan->name, name)) | |
1771 | return true; | |
1772 | ||
1773 | return false; | |
1774 | } | |
6d05c9fa | 1775 | EXPORT_SYMBOL_GPL(pl08x_filter_id); |
e8689e63 LW |
1776 | |
1777 | /* | |
1778 | * Just check that the device is there and active | |
94ae8522 RKAL |
1779 | * TODO: turn this bit on/off depending on the number of physical channels |
1780 | * actually used, if it is zero... well shut it off. That will save some | |
1781 | * power. Cut the clock at the same time. | |
e8689e63 LW |
1782 | */ |
1783 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1784 | { | |
affa115e LW |
1785 | /* The Nomadik variant does not have the config register */ |
1786 | if (pl08x->vd->nomadik) | |
1787 | return; | |
48a59ef3 | 1788 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
e8689e63 LW |
1789 | } |
1790 | ||
e8689e63 LW |
1791 | static irqreturn_t pl08x_irq(int irq, void *dev) |
1792 | { | |
1793 | struct pl08x_driver_data *pl08x = dev; | |
28da2836 VK |
1794 | u32 mask = 0, err, tc, i; |
1795 | ||
1796 | /* check & clear - ERR & TC interrupts */ | |
1797 | err = readl(pl08x->base + PL080_ERR_STATUS); | |
1798 | if (err) { | |
1799 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", | |
1800 | __func__, err); | |
1801 | writel(err, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 | 1802 | } |
d29bf019 | 1803 | tc = readl(pl08x->base + PL080_TC_STATUS); |
28da2836 VK |
1804 | if (tc) |
1805 | writel(tc, pl08x->base + PL080_TC_CLEAR); | |
1806 | ||
1807 | if (!err && !tc) | |
1808 | return IRQ_NONE; | |
1809 | ||
e8689e63 | 1810 | for (i = 0; i < pl08x->vd->channels; i++) { |
28da2836 | 1811 | if (((1 << i) & err) || ((1 << i) & tc)) { |
e8689e63 LW |
1812 | /* Locate physical channel */ |
1813 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1814 | struct pl08x_dma_chan *plchan = phychan->serving; | |
a936e793 | 1815 | struct pl08x_txd *tx; |
e8689e63 | 1816 | |
28da2836 VK |
1817 | if (!plchan) { |
1818 | dev_err(&pl08x->adev->dev, | |
1819 | "%s Error TC interrupt on unused channel: 0x%08x\n", | |
1820 | __func__, i); | |
1821 | continue; | |
1822 | } | |
1823 | ||
083be28a | 1824 | spin_lock(&plchan->vc.lock); |
a936e793 | 1825 | tx = plchan->at; |
3b24c20b AB |
1826 | if (tx && tx->cyclic) { |
1827 | vchan_cyclic_callback(&tx->vd); | |
1828 | } else if (tx) { | |
a936e793 | 1829 | plchan->at = NULL; |
c48d4963 RK |
1830 | /* |
1831 | * This descriptor is done, release its mux | |
1832 | * reservation. | |
1833 | */ | |
1834 | pl08x_release_mux(plchan); | |
18536134 RK |
1835 | tx->done = true; |
1836 | vchan_cookie_complete(&tx->vd); | |
c33b644c | 1837 | |
a5a488db RK |
1838 | /* |
1839 | * And start the next descriptor (if any), | |
1840 | * otherwise free this channel. | |
1841 | */ | |
879f127b | 1842 | if (vchan_next_desc(&plchan->vc)) |
c33b644c | 1843 | pl08x_start_next_txd(plchan); |
a5a488db RK |
1844 | else |
1845 | pl08x_phy_free(plchan); | |
a936e793 | 1846 | } |
083be28a | 1847 | spin_unlock(&plchan->vc.lock); |
a936e793 | 1848 | |
e8689e63 LW |
1849 | mask |= (1 << i); |
1850 | } | |
1851 | } | |
e8689e63 LW |
1852 | |
1853 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1854 | } | |
1855 | ||
121c8476 RKAL |
1856 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
1857 | { | |
121c8476 RKAL |
1858 | chan->slave = true; |
1859 | chan->name = chan->cd->bus_id; | |
ed91c13d RK |
1860 | chan->cfg.src_addr = chan->cd->addr; |
1861 | chan->cfg.dst_addr = chan->cd->addr; | |
121c8476 RKAL |
1862 | } |
1863 | ||
e8689e63 LW |
1864 | /* |
1865 | * Initialise the DMAC memcpy/slave channels. | |
1866 | * Make a local wrapper to hold required data | |
1867 | */ | |
1868 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 1869 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
1870 | { |
1871 | struct pl08x_dma_chan *chan; | |
1872 | int i; | |
1873 | ||
1874 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 1875 | |
e8689e63 LW |
1876 | /* |
1877 | * Register as many many memcpy as we have physical channels, | |
1878 | * we won't always be able to use all but the code will have | |
1879 | * to cope with that situation. | |
1880 | */ | |
1881 | for (i = 0; i < channels; i++) { | |
b201c111 | 1882 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
e8689e63 LW |
1883 | if (!chan) { |
1884 | dev_err(&pl08x->adev->dev, | |
1885 | "%s no memory for channel\n", __func__); | |
1886 | return -ENOMEM; | |
1887 | } | |
1888 | ||
1889 | chan->host = pl08x; | |
1890 | chan->state = PL08X_CHAN_IDLE; | |
ad0de2ac | 1891 | chan->signal = -1; |
e8689e63 LW |
1892 | |
1893 | if (slave) { | |
e8689e63 | 1894 | chan->cd = &pl08x->pd->slave_channels[i]; |
121c8476 | 1895 | pl08x_dma_slave_init(chan); |
e8689e63 LW |
1896 | } else { |
1897 | chan->cd = &pl08x->pd->memcpy_channel; | |
1898 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1899 | if (!chan->name) { | |
1900 | kfree(chan); | |
1901 | return -ENOMEM; | |
1902 | } | |
1903 | } | |
175a5e61 | 1904 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
1905 | "initialize virtual channel \"%s\"\n", |
1906 | chan->name); | |
1907 | ||
18536134 | 1908 | chan->vc.desc_free = pl08x_desc_free; |
083be28a | 1909 | vchan_init(&chan->vc, dmadev); |
e8689e63 LW |
1910 | } |
1911 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1912 | i, slave ? "slave" : "memcpy"); | |
1913 | return i; | |
1914 | } | |
1915 | ||
1916 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1917 | { | |
1918 | struct pl08x_dma_chan *chan = NULL; | |
1919 | struct pl08x_dma_chan *next; | |
1920 | ||
1921 | list_for_each_entry_safe(chan, | |
01d8dc64 RK |
1922 | next, &dmadev->channels, vc.chan.device_node) { |
1923 | list_del(&chan->vc.chan.device_node); | |
e8689e63 LW |
1924 | kfree(chan); |
1925 | } | |
1926 | } | |
1927 | ||
1928 | #ifdef CONFIG_DEBUG_FS | |
1929 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1930 | { | |
1931 | switch (state) { | |
1932 | case PL08X_CHAN_IDLE: | |
1933 | return "idle"; | |
1934 | case PL08X_CHAN_RUNNING: | |
1935 | return "running"; | |
1936 | case PL08X_CHAN_PAUSED: | |
1937 | return "paused"; | |
1938 | case PL08X_CHAN_WAITING: | |
1939 | return "waiting"; | |
1940 | default: | |
1941 | break; | |
1942 | } | |
1943 | return "UNKNOWN STATE"; | |
1944 | } | |
1945 | ||
1946 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1947 | { | |
1948 | struct pl08x_driver_data *pl08x = s->private; | |
1949 | struct pl08x_dma_chan *chan; | |
1950 | struct pl08x_phy_chan *ch; | |
1951 | unsigned long flags; | |
1952 | int i; | |
1953 | ||
1954 | seq_printf(s, "PL08x physical channels:\n"); | |
1955 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1956 | seq_printf(s, "--------\t-----\n"); | |
1957 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1958 | struct pl08x_dma_chan *virt_chan; | |
1959 | ||
1960 | ch = &pl08x->phy_chans[i]; | |
1961 | ||
1962 | spin_lock_irqsave(&ch->lock, flags); | |
1963 | virt_chan = ch->serving; | |
1964 | ||
affa115e LW |
1965 | seq_printf(s, "%d\t\t%s%s\n", |
1966 | ch->id, | |
1967 | virt_chan ? virt_chan->name : "(none)", | |
1968 | ch->locked ? " LOCKED" : ""); | |
e8689e63 LW |
1969 | |
1970 | spin_unlock_irqrestore(&ch->lock, flags); | |
1971 | } | |
1972 | ||
1973 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1974 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1975 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1976 | list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) { |
3e2a037c | 1977 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1978 | pl08x_state_str(chan->state)); |
1979 | } | |
1980 | ||
1981 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1982 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1983 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1984 | list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) { |
3e2a037c | 1985 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1986 | pl08x_state_str(chan->state)); |
1987 | } | |
1988 | ||
1989 | return 0; | |
1990 | } | |
1991 | ||
1992 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1993 | { | |
1994 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1995 | } | |
1996 | ||
1997 | static const struct file_operations pl08x_debugfs_operations = { | |
1998 | .open = pl08x_debugfs_open, | |
1999 | .read = seq_read, | |
2000 | .llseek = seq_lseek, | |
2001 | .release = single_release, | |
2002 | }; | |
2003 | ||
2004 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
2005 | { | |
2006 | /* Expose a simple debugfs interface to view all clocks */ | |
3e27ee84 VK |
2007 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
2008 | S_IFREG | S_IRUGO, NULL, pl08x, | |
2009 | &pl08x_debugfs_operations); | |
e8689e63 LW |
2010 | } |
2011 | ||
2012 | #else | |
2013 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
2014 | { | |
2015 | } | |
2016 | #endif | |
2017 | ||
aa25afad | 2018 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
2019 | { |
2020 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 2021 | const struct vendor_data *vd = id->data; |
ba6785ff | 2022 | u32 tsfr_size; |
e8689e63 LW |
2023 | int ret = 0; |
2024 | int i; | |
2025 | ||
2026 | ret = amba_request_regions(adev, NULL); | |
2027 | if (ret) | |
2028 | return ret; | |
2029 | ||
de1a2419 RK |
2030 | /* Ensure that we can do DMA */ |
2031 | ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); | |
2032 | if (ret) | |
2033 | goto out_no_pl08x; | |
2034 | ||
e8689e63 | 2035 | /* Create the driver state holder */ |
b201c111 | 2036 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
2037 | if (!pl08x) { |
2038 | ret = -ENOMEM; | |
2039 | goto out_no_pl08x; | |
2040 | } | |
2041 | ||
2042 | /* Initialize memcpy engine */ | |
2043 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
2044 | pl08x->memcpy.dev = &adev->dev; | |
2045 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
2046 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
2047 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
2048 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
2049 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
2050 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
2051 | pl08x->memcpy.device_control = pl08x_control; | |
2052 | ||
2053 | /* Initialize slave engine */ | |
2054 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
3b24c20b | 2055 | dma_cap_set(DMA_CYCLIC, pl08x->slave.cap_mask); |
e8689e63 LW |
2056 | pl08x->slave.dev = &adev->dev; |
2057 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
2058 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
2059 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
2060 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
2061 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
2062 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
3b24c20b | 2063 | pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic; |
e8689e63 LW |
2064 | pl08x->slave.device_control = pl08x_control; |
2065 | ||
2066 | /* Get the platform data */ | |
2067 | pl08x->pd = dev_get_platdata(&adev->dev); | |
2068 | if (!pl08x->pd) { | |
2069 | dev_err(&adev->dev, "no platform data supplied\n"); | |
983d7beb | 2070 | ret = -EINVAL; |
e8689e63 LW |
2071 | goto out_no_platdata; |
2072 | } | |
2073 | ||
2074 | /* Assign useful pointers to the driver state */ | |
2075 | pl08x->adev = adev; | |
2076 | pl08x->vd = vd; | |
2077 | ||
30749cb4 RKAL |
2078 | /* By default, AHB1 only. If dualmaster, from platform */ |
2079 | pl08x->lli_buses = PL08X_AHB1; | |
2080 | pl08x->mem_buses = PL08X_AHB1; | |
2081 | if (pl08x->vd->dualmaster) { | |
2082 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
2083 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
2084 | } | |
2085 | ||
da1b6c05 TF |
2086 | if (vd->pl080s) |
2087 | pl08x->lli_words = PL080S_LLI_WORDS; | |
2088 | else | |
2089 | pl08x->lli_words = PL080_LLI_WORDS; | |
ba6785ff TF |
2090 | tsfr_size = MAX_NUM_TSFR_LLIS * pl08x->lli_words * sizeof(u32); |
2091 | ||
e8689e63 LW |
2092 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
2093 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
ba6785ff | 2094 | tsfr_size, PL08X_ALIGN, 0); |
e8689e63 LW |
2095 | if (!pl08x->pool) { |
2096 | ret = -ENOMEM; | |
2097 | goto out_no_lli_pool; | |
2098 | } | |
2099 | ||
e8689e63 LW |
2100 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); |
2101 | if (!pl08x->base) { | |
2102 | ret = -ENOMEM; | |
2103 | goto out_no_ioremap; | |
2104 | } | |
2105 | ||
2106 | /* Turn on the PL08x */ | |
2107 | pl08x_ensure_on(pl08x); | |
2108 | ||
94ae8522 | 2109 | /* Attach the interrupt handler */ |
e8689e63 LW |
2110 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
2111 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
2112 | ||
174b537a | 2113 | ret = request_irq(adev->irq[0], pl08x_irq, 0, DRIVER_NAME, pl08x); |
e8689e63 LW |
2114 | if (ret) { |
2115 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
2116 | __func__, adev->irq[0]); | |
2117 | goto out_no_irq; | |
2118 | } | |
2119 | ||
2120 | /* Initialize physical channels */ | |
affa115e | 2121 | pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
2122 | GFP_KERNEL); |
2123 | if (!pl08x->phy_chans) { | |
2124 | dev_err(&adev->dev, "%s failed to allocate " | |
2125 | "physical channel holders\n", | |
2126 | __func__); | |
983d7beb | 2127 | ret = -ENOMEM; |
e8689e63 LW |
2128 | goto out_no_phychans; |
2129 | } | |
2130 | ||
2131 | for (i = 0; i < vd->channels; i++) { | |
2132 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
2133 | ||
2134 | ch->id = i; | |
2135 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
d86ccea7 | 2136 | ch->reg_config = ch->base + vd->config_offset; |
e8689e63 | 2137 | spin_lock_init(&ch->lock); |
affa115e LW |
2138 | |
2139 | /* | |
2140 | * Nomadik variants can have channels that are locked | |
2141 | * down for the secure world only. Lock up these channels | |
2142 | * by perpetually serving a dummy virtual channel. | |
2143 | */ | |
2144 | if (vd->nomadik) { | |
2145 | u32 val; | |
2146 | ||
d86ccea7 | 2147 | val = readl(ch->reg_config); |
affa115e LW |
2148 | if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { |
2149 | dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i); | |
2150 | ch->locked = true; | |
2151 | } | |
2152 | } | |
2153 | ||
175a5e61 VK |
2154 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
2155 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
2156 | } |
2157 | ||
2158 | /* Register as many memcpy channels as there are physical channels */ | |
2159 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
2160 | pl08x->vd->channels, false); | |
2161 | if (ret <= 0) { | |
2162 | dev_warn(&pl08x->adev->dev, | |
2163 | "%s failed to enumerate memcpy channels - %d\n", | |
2164 | __func__, ret); | |
2165 | goto out_no_memcpy; | |
2166 | } | |
2167 | pl08x->memcpy.chancnt = ret; | |
2168 | ||
2169 | /* Register slave channels */ | |
2170 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
3e27ee84 | 2171 | pl08x->pd->num_slave_channels, true); |
1080411c | 2172 | if (ret < 0) { |
e8689e63 LW |
2173 | dev_warn(&pl08x->adev->dev, |
2174 | "%s failed to enumerate slave channels - %d\n", | |
2175 | __func__, ret); | |
2176 | goto out_no_slave; | |
2177 | } | |
2178 | pl08x->slave.chancnt = ret; | |
2179 | ||
2180 | ret = dma_async_device_register(&pl08x->memcpy); | |
2181 | if (ret) { | |
2182 | dev_warn(&pl08x->adev->dev, | |
2183 | "%s failed to register memcpy as an async device - %d\n", | |
2184 | __func__, ret); | |
2185 | goto out_no_memcpy_reg; | |
2186 | } | |
2187 | ||
2188 | ret = dma_async_device_register(&pl08x->slave); | |
2189 | if (ret) { | |
2190 | dev_warn(&pl08x->adev->dev, | |
2191 | "%s failed to register slave as an async device - %d\n", | |
2192 | __func__, ret); | |
2193 | goto out_no_slave_reg; | |
2194 | } | |
2195 | ||
2196 | amba_set_drvdata(adev, pl08x); | |
2197 | init_pl08x_debugfs(pl08x); | |
da1b6c05 TF |
2198 | dev_info(&pl08x->adev->dev, "DMA: PL%03x%s rev%u at 0x%08llx irq %d\n", |
2199 | amba_part(adev), pl08x->vd->pl080s ? "s" : "", amba_rev(adev), | |
b05cd8f4 | 2200 | (unsigned long long)adev->res.start, adev->irq[0]); |
b7b6018b | 2201 | |
e8689e63 LW |
2202 | return 0; |
2203 | ||
2204 | out_no_slave_reg: | |
2205 | dma_async_device_unregister(&pl08x->memcpy); | |
2206 | out_no_memcpy_reg: | |
2207 | pl08x_free_virtual_channels(&pl08x->slave); | |
2208 | out_no_slave: | |
2209 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2210 | out_no_memcpy: | |
2211 | kfree(pl08x->phy_chans); | |
2212 | out_no_phychans: | |
2213 | free_irq(adev->irq[0], pl08x); | |
2214 | out_no_irq: | |
2215 | iounmap(pl08x->base); | |
2216 | out_no_ioremap: | |
2217 | dma_pool_destroy(pl08x->pool); | |
2218 | out_no_lli_pool: | |
2219 | out_no_platdata: | |
2220 | kfree(pl08x); | |
2221 | out_no_pl08x: | |
2222 | amba_release_regions(adev); | |
2223 | return ret; | |
2224 | } | |
2225 | ||
2226 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2227 | static struct vendor_data vendor_pl080 = { | |
d86ccea7 | 2228 | .config_offset = PL080_CH_CONFIG, |
e8689e63 LW |
2229 | .channels = 8, |
2230 | .dualmaster = true, | |
5110e51d | 2231 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
e8689e63 LW |
2232 | }; |
2233 | ||
affa115e | 2234 | static struct vendor_data vendor_nomadik = { |
d86ccea7 | 2235 | .config_offset = PL080_CH_CONFIG, |
affa115e LW |
2236 | .channels = 8, |
2237 | .dualmaster = true, | |
2238 | .nomadik = true, | |
5110e51d | 2239 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
affa115e LW |
2240 | }; |
2241 | ||
da1b6c05 TF |
2242 | static struct vendor_data vendor_pl080s = { |
2243 | .config_offset = PL080S_CH_CONFIG, | |
2244 | .channels = 8, | |
2245 | .pl080s = true, | |
5110e51d | 2246 | .max_transfer_size = PL080S_CONTROL_TRANSFER_SIZE_MASK, |
affa115e LW |
2247 | }; |
2248 | ||
e8689e63 | 2249 | static struct vendor_data vendor_pl081 = { |
d86ccea7 | 2250 | .config_offset = PL080_CH_CONFIG, |
e8689e63 LW |
2251 | .channels = 2, |
2252 | .dualmaster = false, | |
5110e51d | 2253 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
e8689e63 LW |
2254 | }; |
2255 | ||
2256 | static struct amba_id pl08x_ids[] = { | |
da1b6c05 TF |
2257 | /* Samsung PL080S variant */ |
2258 | { | |
2259 | .id = 0x0a141080, | |
2260 | .mask = 0xffffffff, | |
2261 | .data = &vendor_pl080s, | |
2262 | }, | |
e8689e63 LW |
2263 | /* PL080 */ |
2264 | { | |
2265 | .id = 0x00041080, | |
2266 | .mask = 0x000fffff, | |
2267 | .data = &vendor_pl080, | |
2268 | }, | |
2269 | /* PL081 */ | |
2270 | { | |
2271 | .id = 0x00041081, | |
2272 | .mask = 0x000fffff, | |
2273 | .data = &vendor_pl081, | |
2274 | }, | |
2275 | /* Nomadik 8815 PL080 variant */ | |
2276 | { | |
affa115e | 2277 | .id = 0x00280080, |
e8689e63 | 2278 | .mask = 0x00ffffff, |
affa115e | 2279 | .data = &vendor_nomadik, |
e8689e63 LW |
2280 | }, |
2281 | { 0, 0 }, | |
2282 | }; | |
2283 | ||
037566df DM |
2284 | MODULE_DEVICE_TABLE(amba, pl08x_ids); |
2285 | ||
e8689e63 LW |
2286 | static struct amba_driver pl08x_amba_driver = { |
2287 | .drv.name = DRIVER_NAME, | |
2288 | .id_table = pl08x_ids, | |
2289 | .probe = pl08x_probe, | |
2290 | }; | |
2291 | ||
2292 | static int __init pl08x_init(void) | |
2293 | { | |
2294 | int retval; | |
2295 | retval = amba_driver_register(&pl08x_amba_driver); | |
2296 | if (retval) | |
2297 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2298 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2299 | retval); |
2300 | return retval; | |
2301 | } | |
2302 | subsys_initcall(pl08x_init); |