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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
94ae8522 RKAL |
22 | * The full GNU General Public License is in this distribution in the file |
23 | * called COPYING. | |
e8689e63 LW |
24 | * |
25 | * Documentation: ARM DDI 0196G == PL080 | |
94ae8522 | 26 | * Documentation: ARM DDI 0218E == PL081 |
e8689e63 | 27 | * |
94ae8522 RKAL |
28 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
29 | * channel. | |
e8689e63 LW |
30 | * |
31 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
32 | * has only two channels. So on these DMA controllers the number of channels | |
33 | * and the number of incoming DMA signals are two totally different things. | |
34 | * It is usually not possible to theoretically handle all physical signals, | |
35 | * so a multiplexing scheme with possible denial of use is necessary. | |
36 | * | |
37 | * The PL080 has a dual bus master, PL081 has a single master. | |
38 | * | |
39 | * Memory to peripheral transfer may be visualized as | |
40 | * Get data from memory to DMAC | |
41 | * Until no data left | |
42 | * On burst request from peripheral | |
43 | * Destination burst from DMAC to peripheral | |
44 | * Clear burst request | |
45 | * Raise terminal count interrupt | |
46 | * | |
47 | * For peripherals with a FIFO: | |
48 | * Source burst size == half the depth of the peripheral FIFO | |
49 | * Destination burst size == the depth of the peripheral FIFO | |
50 | * | |
51 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
52 | * signals, the DMA controller will simply facilitate its AHB master.) | |
53 | * | |
54 | * ASSUMES default (little) endianness for DMA transfers | |
55 | * | |
9dc2c200 RKAL |
56 | * The PL08x has two flow control settings: |
57 | * - DMAC flow control: the transfer size defines the number of transfers | |
58 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
59 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
60 | * to both the BREQ and SREQ signals (contrary to documented), | |
61 | * transferring data if either is active. The LBREQ and LSREQ signals | |
62 | * are ignored. | |
63 | * | |
64 | * - Peripheral flow control: the transfer size is ignored (and should be | |
65 | * zero). The data is transferred from the current LLI entry, until | |
66 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
67 | * will then move to the next LLI entry. | |
68 | * | |
e8689e63 LW |
69 | * Global TODO: |
70 | * - Break out common code from arch/arm/mach-s3c64xx and share | |
71 | */ | |
730404ac | 72 | #include <linux/amba/bus.h> |
e8689e63 LW |
73 | #include <linux/amba/pl08x.h> |
74 | #include <linux/debugfs.h> | |
0c38d701 VK |
75 | #include <linux/delay.h> |
76 | #include <linux/device.h> | |
77 | #include <linux/dmaengine.h> | |
78 | #include <linux/dmapool.h> | |
8516f52f | 79 | #include <linux/dma-mapping.h> |
0c38d701 VK |
80 | #include <linux/init.h> |
81 | #include <linux/interrupt.h> | |
82 | #include <linux/module.h> | |
b7b6018b | 83 | #include <linux/pm_runtime.h> |
e8689e63 | 84 | #include <linux/seq_file.h> |
0c38d701 | 85 | #include <linux/slab.h> |
3a95b9fb | 86 | #include <linux/amba/pl080.h> |
e8689e63 | 87 | |
d2ebfb33 | 88 | #include "dmaengine.h" |
01d8dc64 | 89 | #include "virt-dma.h" |
d2ebfb33 | 90 | |
e8689e63 LW |
91 | #define DRIVER_NAME "pl08xdmac" |
92 | ||
7703eac9 | 93 | static struct amba_driver pl08x_amba_driver; |
b23f204c | 94 | struct pl08x_driver_data; |
7703eac9 | 95 | |
e8689e63 | 96 | /** |
94ae8522 | 97 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
e8689e63 | 98 | * @channels: the number of channels available in this variant |
94ae8522 | 99 | * @dualmaster: whether this version supports dual AHB masters or not. |
affa115e LW |
100 | * @nomadik: whether the channels have Nomadik security extension bits |
101 | * that need to be checked for permission before use and some registers are | |
102 | * missing | |
e8689e63 LW |
103 | */ |
104 | struct vendor_data { | |
e8689e63 LW |
105 | u8 channels; |
106 | bool dualmaster; | |
affa115e | 107 | bool nomadik; |
e8689e63 LW |
108 | }; |
109 | ||
110 | /* | |
111 | * PL08X private data structures | |
e8b5e11d | 112 | * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit, |
e25761d7 RKAL |
113 | * start & end do not - their bus bit info is in cctl. Also note that these |
114 | * are fixed 32-bit quantities. | |
e8689e63 | 115 | */ |
7cb72ad9 | 116 | struct pl08x_lli { |
e25761d7 RKAL |
117 | u32 src; |
118 | u32 dst; | |
bfddfb45 | 119 | u32 lli; |
e8689e63 LW |
120 | u32 cctl; |
121 | }; | |
122 | ||
b23f204c RK |
123 | /** |
124 | * struct pl08x_bus_data - information of source or destination | |
125 | * busses for a transfer | |
126 | * @addr: current address | |
127 | * @maxwidth: the maximum width of a transfer on this bus | |
128 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | |
129 | */ | |
130 | struct pl08x_bus_data { | |
131 | dma_addr_t addr; | |
132 | u8 maxwidth; | |
133 | u8 buswidth; | |
134 | }; | |
135 | ||
1c38b289 AP |
136 | #define IS_BUS_ALIGNED(bus) IS_ALIGNED((bus)->addr, (bus)->buswidth) |
137 | ||
b23f204c RK |
138 | /** |
139 | * struct pl08x_phy_chan - holder for the physical channels | |
140 | * @id: physical index to this channel | |
141 | * @lock: a lock to use when altering an instance of this struct | |
b23f204c RK |
142 | * @serving: the virtual channel currently being served by this physical |
143 | * channel | |
ad0de2ac RK |
144 | * @locked: channel unavailable for the system, e.g. dedicated to secure |
145 | * world | |
b23f204c RK |
146 | */ |
147 | struct pl08x_phy_chan { | |
148 | unsigned int id; | |
149 | void __iomem *base; | |
150 | spinlock_t lock; | |
b23f204c | 151 | struct pl08x_dma_chan *serving; |
ad0de2ac | 152 | bool locked; |
b23f204c RK |
153 | }; |
154 | ||
155 | /** | |
156 | * struct pl08x_sg - structure containing data per sg | |
157 | * @src_addr: src address of sg | |
158 | * @dst_addr: dst address of sg | |
159 | * @len: transfer len in bytes | |
160 | * @node: node for txd's dsg_list | |
161 | */ | |
162 | struct pl08x_sg { | |
163 | dma_addr_t src_addr; | |
164 | dma_addr_t dst_addr; | |
165 | size_t len; | |
166 | struct list_head node; | |
167 | }; | |
168 | ||
169 | /** | |
170 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | |
01d8dc64 | 171 | * @vd: virtual DMA descriptor |
b23f204c | 172 | * @dsg_list: list of children sg's |
b23f204c RK |
173 | * @llis_bus: DMA memory address (physical) start for the LLIs |
174 | * @llis_va: virtual memory address start for the LLIs | |
175 | * @cctl: control reg values for current txd | |
176 | * @ccfg: config reg values for current txd | |
18536134 RK |
177 | * @done: this marks completed descriptors, which should not have their |
178 | * mux released. | |
b23f204c RK |
179 | */ |
180 | struct pl08x_txd { | |
01d8dc64 | 181 | struct virt_dma_desc vd; |
b23f204c | 182 | struct list_head dsg_list; |
b23f204c RK |
183 | dma_addr_t llis_bus; |
184 | struct pl08x_lli *llis_va; | |
185 | /* Default cctl value for LLIs */ | |
186 | u32 cctl; | |
187 | /* | |
188 | * Settings to be put into the physical channel when we | |
189 | * trigger this txd. Other registers are in llis_va[0]. | |
190 | */ | |
191 | u32 ccfg; | |
18536134 | 192 | bool done; |
b23f204c RK |
193 | }; |
194 | ||
195 | /** | |
196 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel | |
197 | * states | |
198 | * @PL08X_CHAN_IDLE: the channel is idle | |
199 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | |
200 | * channel and is running a transfer on it | |
201 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport | |
202 | * channel, but the transfer is currently paused | |
203 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport | |
204 | * channel to become available (only pertains to memcpy channels) | |
205 | */ | |
206 | enum pl08x_dma_chan_state { | |
207 | PL08X_CHAN_IDLE, | |
208 | PL08X_CHAN_RUNNING, | |
209 | PL08X_CHAN_PAUSED, | |
210 | PL08X_CHAN_WAITING, | |
211 | }; | |
212 | ||
213 | /** | |
214 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | |
01d8dc64 | 215 | * @vc: wrappped virtual channel |
b23f204c | 216 | * @phychan: the physical channel utilized by this channel, if there is one |
b23f204c RK |
217 | * @name: name of channel |
218 | * @cd: channel platform data | |
219 | * @runtime_addr: address for RX/TX according to the runtime config | |
b23f204c RK |
220 | * @at: active transaction on this channel |
221 | * @lock: a lock for this channel data | |
222 | * @host: a pointer to the host (internal use) | |
223 | * @state: whether the channel is idle, paused, running etc | |
224 | * @slave: whether this channel is a device (slave) or for memcpy | |
ad0de2ac | 225 | * @signal: the physical DMA request signal which this channel is using |
5e2479bd | 226 | * @mux_use: count of descriptors using this DMA request signal setting |
b23f204c RK |
227 | */ |
228 | struct pl08x_dma_chan { | |
01d8dc64 | 229 | struct virt_dma_chan vc; |
b23f204c | 230 | struct pl08x_phy_chan *phychan; |
550ec36f | 231 | const char *name; |
b23f204c | 232 | const struct pl08x_channel_data *cd; |
ed91c13d | 233 | struct dma_slave_config cfg; |
b23f204c | 234 | struct pl08x_txd *at; |
b23f204c RK |
235 | struct pl08x_driver_data *host; |
236 | enum pl08x_dma_chan_state state; | |
237 | bool slave; | |
ad0de2ac | 238 | int signal; |
5e2479bd | 239 | unsigned mux_use; |
b23f204c RK |
240 | }; |
241 | ||
e8689e63 LW |
242 | /** |
243 | * struct pl08x_driver_data - the local state holder for the PL08x | |
244 | * @slave: slave engine for this instance | |
245 | * @memcpy: memcpy engine for this instance | |
246 | * @base: virtual memory base (remapped) for the PL08x | |
247 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
248 | * @vd: vendor data for this PL08x variant | |
249 | * @pd: platform data passed in from the platform/machine | |
250 | * @phy_chans: array of data for the physical channels | |
251 | * @pool: a pool for the LLI descriptors | |
3e27ee84 VK |
252 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
253 | * fetches | |
30749cb4 | 254 | * @mem_buses: set to indicate memory transfers on AHB2. |
e8689e63 LW |
255 | * @lock: a spinlock for this struct |
256 | */ | |
257 | struct pl08x_driver_data { | |
258 | struct dma_device slave; | |
259 | struct dma_device memcpy; | |
260 | void __iomem *base; | |
261 | struct amba_device *adev; | |
f96ca9ec | 262 | const struct vendor_data *vd; |
e8689e63 LW |
263 | struct pl08x_platform_data *pd; |
264 | struct pl08x_phy_chan *phy_chans; | |
265 | struct dma_pool *pool; | |
30749cb4 RKAL |
266 | u8 lli_buses; |
267 | u8 mem_buses; | |
e8689e63 LW |
268 | }; |
269 | ||
270 | /* | |
271 | * PL08X specific defines | |
272 | */ | |
273 | ||
e8689e63 LW |
274 | /* Size (bytes) of each LLI buffer allocated for one transfer */ |
275 | # define PL08X_LLI_TSFR_SIZE 0x2000 | |
276 | ||
e8b5e11d | 277 | /* Maximum times we call dma_pool_alloc on this pool without freeing */ |
7cb72ad9 | 278 | #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli)) |
e8689e63 LW |
279 | #define PL08X_ALIGN 8 |
280 | ||
281 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
282 | { | |
01d8dc64 | 283 | return container_of(chan, struct pl08x_dma_chan, vc.chan); |
e8689e63 LW |
284 | } |
285 | ||
501e67e8 RKAL |
286 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
287 | { | |
01d8dc64 | 288 | return container_of(tx, struct pl08x_txd, vd.tx); |
501e67e8 RKAL |
289 | } |
290 | ||
6b16c8b1 RK |
291 | /* |
292 | * Mux handling. | |
293 | * | |
294 | * This gives us the DMA request input to the PL08x primecell which the | |
295 | * peripheral described by the channel data will be routed to, possibly | |
296 | * via a board/SoC specific external MUX. One important point to note | |
297 | * here is that this does not depend on the physical channel. | |
298 | */ | |
ad0de2ac | 299 | static int pl08x_request_mux(struct pl08x_dma_chan *plchan) |
6b16c8b1 RK |
300 | { |
301 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
302 | int ret; | |
303 | ||
d7cabeed MB |
304 | if (plchan->mux_use++ == 0 && pd->get_xfer_signal) { |
305 | ret = pd->get_xfer_signal(plchan->cd); | |
5e2479bd RK |
306 | if (ret < 0) { |
307 | plchan->mux_use = 0; | |
6b16c8b1 | 308 | return ret; |
5e2479bd | 309 | } |
6b16c8b1 | 310 | |
ad0de2ac | 311 | plchan->signal = ret; |
6b16c8b1 RK |
312 | } |
313 | return 0; | |
314 | } | |
315 | ||
316 | static void pl08x_release_mux(struct pl08x_dma_chan *plchan) | |
317 | { | |
318 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
319 | ||
5e2479bd RK |
320 | if (plchan->signal >= 0) { |
321 | WARN_ON(plchan->mux_use == 0); | |
322 | ||
d7cabeed MB |
323 | if (--plchan->mux_use == 0 && pd->put_xfer_signal) { |
324 | pd->put_xfer_signal(plchan->cd, plchan->signal); | |
5e2479bd RK |
325 | plchan->signal = -1; |
326 | } | |
6b16c8b1 RK |
327 | } |
328 | } | |
329 | ||
e8689e63 LW |
330 | /* |
331 | * Physical channel handling | |
332 | */ | |
333 | ||
334 | /* Whether a certain channel is busy or not */ | |
335 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
336 | { | |
337 | unsigned int val; | |
338 | ||
339 | val = readl(ch->base + PL080_CH_CONFIG); | |
340 | return val & PL080_CONFIG_ACTIVE; | |
341 | } | |
342 | ||
343 | /* | |
344 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 345 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
346 | * been set when the LLIs were constructed. Poke them into the hardware |
347 | * and start the transfer. | |
e8689e63 | 348 | */ |
eab82533 | 349 | static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) |
e8689e63 | 350 | { |
c885bee4 | 351 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 352 | struct pl08x_phy_chan *phychan = plchan->phychan; |
879f127b RK |
353 | struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc); |
354 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
eab82533 | 355 | struct pl08x_lli *lli; |
09b3c323 | 356 | u32 val; |
c885bee4 | 357 | |
879f127b | 358 | list_del(&txd->vd.node); |
eab82533 | 359 | |
c885bee4 | 360 | plchan->at = txd; |
e8689e63 | 361 | |
c885bee4 RKAL |
362 | /* Wait for channel inactive */ |
363 | while (pl08x_phy_channel_busy(phychan)) | |
364 | cpu_relax(); | |
e8689e63 | 365 | |
eab82533 RK |
366 | lli = &txd->llis_va[0]; |
367 | ||
c885bee4 RKAL |
368 | dev_vdbg(&pl08x->adev->dev, |
369 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
19524d77 RKAL |
370 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", |
371 | phychan->id, lli->src, lli->dst, lli->lli, lli->cctl, | |
09b3c323 | 372 | txd->ccfg); |
19524d77 RKAL |
373 | |
374 | writel(lli->src, phychan->base + PL080_CH_SRC_ADDR); | |
375 | writel(lli->dst, phychan->base + PL080_CH_DST_ADDR); | |
376 | writel(lli->lli, phychan->base + PL080_CH_LLI); | |
377 | writel(lli->cctl, phychan->base + PL080_CH_CONTROL); | |
09b3c323 | 378 | writel(txd->ccfg, phychan->base + PL080_CH_CONFIG); |
c885bee4 RKAL |
379 | |
380 | /* Enable the DMA channel */ | |
381 | /* Do not access config register until channel shows as disabled */ | |
382 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 383 | cpu_relax(); |
e8689e63 | 384 | |
c885bee4 RKAL |
385 | /* Do not access config register until channel shows as inactive */ |
386 | val = readl(phychan->base + PL080_CH_CONFIG); | |
e8689e63 | 387 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
c885bee4 | 388 | val = readl(phychan->base + PL080_CH_CONFIG); |
e8689e63 | 389 | |
c885bee4 | 390 | writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG); |
e8689e63 LW |
391 | } |
392 | ||
393 | /* | |
81796616 | 394 | * Pause the channel by setting the HALT bit. |
e8689e63 | 395 | * |
81796616 RKAL |
396 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
397 | * the FIFO can only drain if the peripheral is still requesting data. | |
398 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 399 | * |
81796616 RKAL |
400 | * For P->M transfers, disable the peripheral first to stop it filling |
401 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
402 | */ |
403 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
404 | { | |
405 | u32 val; | |
81796616 | 406 | int timeout; |
e8689e63 LW |
407 | |
408 | /* Set the HALT bit and wait for the FIFO to drain */ | |
409 | val = readl(ch->base + PL080_CH_CONFIG); | |
410 | val |= PL080_CONFIG_HALT; | |
411 | writel(val, ch->base + PL080_CH_CONFIG); | |
412 | ||
413 | /* Wait for channel inactive */ | |
81796616 RKAL |
414 | for (timeout = 1000; timeout; timeout--) { |
415 | if (!pl08x_phy_channel_busy(ch)) | |
416 | break; | |
417 | udelay(1); | |
418 | } | |
419 | if (pl08x_phy_channel_busy(ch)) | |
420 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
421 | } |
422 | ||
423 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
424 | { | |
425 | u32 val; | |
426 | ||
427 | /* Clear the HALT bit */ | |
428 | val = readl(ch->base + PL080_CH_CONFIG); | |
429 | val &= ~PL080_CONFIG_HALT; | |
430 | writel(val, ch->base + PL080_CH_CONFIG); | |
431 | } | |
432 | ||
fb526210 RKAL |
433 | /* |
434 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
435 | * clears any pending interrupt status. This should not be used for | |
436 | * an on-going transfer, but as a method of shutting down a channel | |
437 | * (eg, when it's no longer used) or terminating a transfer. | |
438 | */ | |
439 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
440 | struct pl08x_phy_chan *ch) | |
e8689e63 | 441 | { |
fb526210 | 442 | u32 val = readl(ch->base + PL080_CH_CONFIG); |
e8689e63 | 443 | |
fb526210 RKAL |
444 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
445 | PL080_CONFIG_TC_IRQ_MASK); | |
e8689e63 | 446 | |
e8689e63 | 447 | writel(val, ch->base + PL080_CH_CONFIG); |
fb526210 RKAL |
448 | |
449 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); | |
450 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
451 | } |
452 | ||
453 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
454 | { | |
455 | /* The source width defines the number of bytes */ | |
456 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
457 | ||
458 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
459 | case PL080_WIDTH_8BIT: | |
460 | break; | |
461 | case PL080_WIDTH_16BIT: | |
462 | bytes *= 2; | |
463 | break; | |
464 | case PL080_WIDTH_32BIT: | |
465 | bytes *= 4; | |
466 | break; | |
467 | } | |
468 | return bytes; | |
469 | } | |
470 | ||
471 | /* The channel should be paused when calling this */ | |
472 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
473 | { | |
474 | struct pl08x_phy_chan *ch; | |
e8689e63 | 475 | struct pl08x_txd *txd; |
cace6585 | 476 | size_t bytes = 0; |
e8689e63 | 477 | |
e8689e63 LW |
478 | ch = plchan->phychan; |
479 | txd = plchan->at; | |
480 | ||
481 | /* | |
db9f136a RKAL |
482 | * Follow the LLIs to get the number of remaining |
483 | * bytes in the currently active transaction. | |
e8689e63 LW |
484 | */ |
485 | if (ch && txd) { | |
4c0df6a3 | 486 | u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 487 | |
db9f136a | 488 | /* First get the remaining bytes in the active transfer */ |
e8689e63 LW |
489 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); |
490 | ||
491 | if (clli) { | |
db9f136a RKAL |
492 | struct pl08x_lli *llis_va = txd->llis_va; |
493 | dma_addr_t llis_bus = txd->llis_bus; | |
494 | int index; | |
495 | ||
496 | BUG_ON(clli < llis_bus || clli >= llis_bus + | |
497 | sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS); | |
e8689e63 | 498 | |
db9f136a RKAL |
499 | /* |
500 | * Locate the next LLI - as this is an array, | |
501 | * it's simple maths to find. | |
502 | */ | |
503 | index = (clli - llis_bus) / sizeof(struct pl08x_lli); | |
504 | ||
505 | for (; index < MAX_NUM_TSFR_LLIS; index++) { | |
506 | bytes += get_bytes_in_cctl(llis_va[index].cctl); | |
e8689e63 | 507 | |
e8689e63 | 508 | /* |
e8b5e11d | 509 | * A LLI pointer of 0 terminates the LLI list |
e8689e63 | 510 | */ |
db9f136a RKAL |
511 | if (!llis_va[index].lli) |
512 | break; | |
e8689e63 LW |
513 | } |
514 | } | |
515 | } | |
516 | ||
e8689e63 LW |
517 | return bytes; |
518 | } | |
519 | ||
520 | /* | |
521 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
522 | * |
523 | * Try to locate a physical channel to be used for this transfer. If all | |
524 | * are taken return NULL and the requester will have to cope by using | |
525 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
526 | */ |
527 | static struct pl08x_phy_chan * | |
528 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
529 | struct pl08x_dma_chan *virt_chan) | |
530 | { | |
531 | struct pl08x_phy_chan *ch = NULL; | |
532 | unsigned long flags; | |
533 | int i; | |
534 | ||
e8689e63 LW |
535 | for (i = 0; i < pl08x->vd->channels; i++) { |
536 | ch = &pl08x->phy_chans[i]; | |
537 | ||
538 | spin_lock_irqsave(&ch->lock, flags); | |
539 | ||
affa115e | 540 | if (!ch->locked && !ch->serving) { |
e8689e63 | 541 | ch->serving = virt_chan; |
e8689e63 LW |
542 | spin_unlock_irqrestore(&ch->lock, flags); |
543 | break; | |
544 | } | |
545 | ||
546 | spin_unlock_irqrestore(&ch->lock, flags); | |
547 | } | |
548 | ||
549 | if (i == pl08x->vd->channels) { | |
550 | /* No physical channel available, cope with it */ | |
551 | return NULL; | |
552 | } | |
553 | ||
554 | return ch; | |
555 | } | |
556 | ||
a5a488db | 557 | /* Mark the physical channel as free. Note, this write is atomic. */ |
e8689e63 LW |
558 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, |
559 | struct pl08x_phy_chan *ch) | |
560 | { | |
a5a488db RK |
561 | ch->serving = NULL; |
562 | } | |
e8689e63 | 563 | |
a5a488db RK |
564 | /* |
565 | * Try to allocate a physical channel. When successful, assign it to | |
566 | * this virtual channel, and initiate the next descriptor. The | |
567 | * virtual channel lock must be held at this point. | |
568 | */ | |
569 | static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan) | |
570 | { | |
571 | struct pl08x_driver_data *pl08x = plchan->host; | |
572 | struct pl08x_phy_chan *ch; | |
fb526210 | 573 | |
a5a488db RK |
574 | ch = pl08x_get_phy_channel(pl08x, plchan); |
575 | if (!ch) { | |
576 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
577 | plchan->state = PL08X_CHAN_WAITING; | |
578 | return; | |
579 | } | |
e8689e63 | 580 | |
a5a488db RK |
581 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n", |
582 | ch->id, plchan->name); | |
583 | ||
584 | plchan->phychan = ch; | |
585 | plchan->state = PL08X_CHAN_RUNNING; | |
586 | pl08x_start_next_txd(plchan); | |
587 | } | |
588 | ||
589 | static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch, | |
590 | struct pl08x_dma_chan *plchan) | |
591 | { | |
592 | struct pl08x_driver_data *pl08x = plchan->host; | |
593 | ||
594 | dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n", | |
595 | ch->id, plchan->name); | |
596 | ||
597 | /* | |
598 | * We do this without taking the lock; we're really only concerned | |
599 | * about whether this pointer is NULL or not, and we're guaranteed | |
600 | * that this will only be called when it _already_ is non-NULL. | |
601 | */ | |
602 | ch->serving = plchan; | |
603 | plchan->phychan = ch; | |
604 | plchan->state = PL08X_CHAN_RUNNING; | |
605 | pl08x_start_next_txd(plchan); | |
606 | } | |
607 | ||
608 | /* | |
609 | * Free a physical DMA channel, potentially reallocating it to another | |
610 | * virtual channel if we have any pending. | |
611 | */ | |
612 | static void pl08x_phy_free(struct pl08x_dma_chan *plchan) | |
613 | { | |
614 | struct pl08x_driver_data *pl08x = plchan->host; | |
615 | struct pl08x_dma_chan *p, *next; | |
616 | ||
617 | retry: | |
618 | next = NULL; | |
619 | ||
620 | /* Find a waiting virtual channel for the next transfer. */ | |
01d8dc64 | 621 | list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node) |
a5a488db RK |
622 | if (p->state == PL08X_CHAN_WAITING) { |
623 | next = p; | |
624 | break; | |
625 | } | |
626 | ||
627 | if (!next) { | |
01d8dc64 | 628 | list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node) |
a5a488db RK |
629 | if (p->state == PL08X_CHAN_WAITING) { |
630 | next = p; | |
631 | break; | |
632 | } | |
633 | } | |
634 | ||
635 | /* Ensure that the physical channel is stopped */ | |
636 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); | |
637 | ||
638 | if (next) { | |
639 | bool success; | |
640 | ||
641 | /* | |
642 | * Eww. We know this isn't going to deadlock | |
643 | * but lockdep probably doesn't. | |
644 | */ | |
083be28a | 645 | spin_lock(&next->vc.lock); |
a5a488db RK |
646 | /* Re-check the state now that we have the lock */ |
647 | success = next->state == PL08X_CHAN_WAITING; | |
648 | if (success) | |
649 | pl08x_phy_reassign_start(plchan->phychan, next); | |
083be28a | 650 | spin_unlock(&next->vc.lock); |
a5a488db RK |
651 | |
652 | /* If the state changed, try to find another channel */ | |
653 | if (!success) | |
654 | goto retry; | |
655 | } else { | |
656 | /* No more jobs, so free up the physical channel */ | |
657 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
658 | } | |
659 | ||
660 | plchan->phychan = NULL; | |
661 | plchan->state = PL08X_CHAN_IDLE; | |
e8689e63 LW |
662 | } |
663 | ||
664 | /* | |
665 | * LLI handling | |
666 | */ | |
667 | ||
668 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
669 | { | |
670 | switch (coded) { | |
671 | case PL080_WIDTH_8BIT: | |
672 | return 1; | |
673 | case PL080_WIDTH_16BIT: | |
674 | return 2; | |
675 | case PL080_WIDTH_32BIT: | |
676 | return 4; | |
677 | default: | |
678 | break; | |
679 | } | |
680 | BUG(); | |
681 | return 0; | |
682 | } | |
683 | ||
684 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 685 | size_t tsize) |
e8689e63 LW |
686 | { |
687 | u32 retbits = cctl; | |
688 | ||
e8b5e11d | 689 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
690 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
691 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
692 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
693 | ||
694 | /* Then set the bits according to the parameters */ | |
695 | switch (srcwidth) { | |
696 | case 1: | |
697 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
698 | break; | |
699 | case 2: | |
700 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
701 | break; | |
702 | case 4: | |
703 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
704 | break; | |
705 | default: | |
706 | BUG(); | |
707 | break; | |
708 | } | |
709 | ||
710 | switch (dstwidth) { | |
711 | case 1: | |
712 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
713 | break; | |
714 | case 2: | |
715 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
716 | break; | |
717 | case 4: | |
718 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
719 | break; | |
720 | default: | |
721 | BUG(); | |
722 | break; | |
723 | } | |
724 | ||
725 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
726 | return retbits; | |
727 | } | |
728 | ||
542361f8 RKAL |
729 | struct pl08x_lli_build_data { |
730 | struct pl08x_txd *txd; | |
542361f8 RKAL |
731 | struct pl08x_bus_data srcbus; |
732 | struct pl08x_bus_data dstbus; | |
733 | size_t remainder; | |
25c94f7f | 734 | u32 lli_bus; |
542361f8 RKAL |
735 | }; |
736 | ||
e8689e63 | 737 | /* |
0532e6fc VK |
738 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
739 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
740 | * masters address with width requirements of transfer (by sending few byte by | |
741 | * byte data), slave is still not aligned, then its width will be reduced to | |
742 | * BYTE. | |
743 | * - prefers the destination bus if both available | |
036f05fd | 744 | * - prefers bus with fixed address (i.e. peripheral) |
e8689e63 | 745 | */ |
542361f8 RKAL |
746 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
747 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) | |
e8689e63 LW |
748 | { |
749 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
542361f8 RKAL |
750 | *mbus = &bd->dstbus; |
751 | *sbus = &bd->srcbus; | |
036f05fd VK |
752 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
753 | *mbus = &bd->srcbus; | |
754 | *sbus = &bd->dstbus; | |
e8689e63 | 755 | } else { |
036f05fd | 756 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
542361f8 RKAL |
757 | *mbus = &bd->dstbus; |
758 | *sbus = &bd->srcbus; | |
036f05fd | 759 | } else { |
542361f8 RKAL |
760 | *mbus = &bd->srcbus; |
761 | *sbus = &bd->dstbus; | |
e8689e63 LW |
762 | } |
763 | } | |
764 | } | |
765 | ||
766 | /* | |
94ae8522 | 767 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 768 | */ |
542361f8 RKAL |
769 | static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd, |
770 | int num_llis, int len, u32 cctl) | |
e8689e63 | 771 | { |
542361f8 RKAL |
772 | struct pl08x_lli *llis_va = bd->txd->llis_va; |
773 | dma_addr_t llis_bus = bd->txd->llis_bus; | |
e8689e63 LW |
774 | |
775 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
776 | ||
30749cb4 | 777 | llis_va[num_llis].cctl = cctl; |
542361f8 RKAL |
778 | llis_va[num_llis].src = bd->srcbus.addr; |
779 | llis_va[num_llis].dst = bd->dstbus.addr; | |
3e27ee84 VK |
780 | llis_va[num_llis].lli = llis_bus + (num_llis + 1) * |
781 | sizeof(struct pl08x_lli); | |
25c94f7f | 782 | llis_va[num_llis].lli |= bd->lli_bus; |
e8689e63 LW |
783 | |
784 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 | 785 | bd->srcbus.addr += len; |
e8689e63 | 786 | if (cctl & PL080_CONTROL_DST_INCR) |
542361f8 | 787 | bd->dstbus.addr += len; |
e8689e63 | 788 | |
542361f8 | 789 | BUG_ON(bd->remainder < len); |
cace6585 | 790 | |
542361f8 | 791 | bd->remainder -= len; |
e8689e63 LW |
792 | } |
793 | ||
03af500f VK |
794 | static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd, |
795 | u32 *cctl, u32 len, int num_llis, size_t *total_bytes) | |
e8689e63 | 796 | { |
03af500f VK |
797 | *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); |
798 | pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl); | |
799 | (*total_bytes) += len; | |
e8689e63 LW |
800 | } |
801 | ||
802 | /* | |
803 | * This fills in the table of LLIs for the transfer descriptor | |
804 | * Note that we assume we never have to change the burst sizes | |
805 | * Return 0 for error | |
806 | */ | |
807 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
808 | struct pl08x_txd *txd) | |
809 | { | |
e8689e63 | 810 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 811 | struct pl08x_lli_build_data bd; |
e8689e63 | 812 | int num_llis = 0; |
03af500f | 813 | u32 cctl, early_bytes = 0; |
b7f69d9d | 814 | size_t max_bytes_per_lli, total_bytes; |
7cb72ad9 | 815 | struct pl08x_lli *llis_va; |
b7f69d9d | 816 | struct pl08x_sg *dsg; |
e8689e63 | 817 | |
3e27ee84 | 818 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
819 | if (!txd->llis_va) { |
820 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
821 | return 0; | |
822 | } | |
823 | ||
542361f8 | 824 | bd.txd = txd; |
25c94f7f | 825 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
b7f69d9d | 826 | cctl = txd->cctl; |
542361f8 | 827 | |
e8689e63 | 828 | /* Find maximum width of the source bus */ |
542361f8 | 829 | bd.srcbus.maxwidth = |
e8689e63 LW |
830 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
831 | PL080_CONTROL_SWIDTH_SHIFT); | |
832 | ||
833 | /* Find maximum width of the destination bus */ | |
542361f8 | 834 | bd.dstbus.maxwidth = |
e8689e63 LW |
835 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
836 | PL080_CONTROL_DWIDTH_SHIFT); | |
837 | ||
b7f69d9d VK |
838 | list_for_each_entry(dsg, &txd->dsg_list, node) { |
839 | total_bytes = 0; | |
840 | cctl = txd->cctl; | |
e8689e63 | 841 | |
b7f69d9d VK |
842 | bd.srcbus.addr = dsg->src_addr; |
843 | bd.dstbus.addr = dsg->dst_addr; | |
844 | bd.remainder = dsg->len; | |
845 | bd.srcbus.buswidth = bd.srcbus.maxwidth; | |
846 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 | 847 | |
b7f69d9d | 848 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
e8689e63 | 849 | |
b7f69d9d VK |
850 | dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n", |
851 | bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", | |
852 | bd.srcbus.buswidth, | |
853 | bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
854 | bd.dstbus.buswidth, | |
855 | bd.remainder); | |
856 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", | |
857 | mbus == &bd.srcbus ? "src" : "dst", | |
858 | sbus == &bd.srcbus ? "src" : "dst"); | |
fc74eb79 | 859 | |
b7f69d9d VK |
860 | /* |
861 | * Zero length is only allowed if all these requirements are | |
862 | * met: | |
863 | * - flow controller is peripheral. | |
864 | * - src.addr is aligned to src.width | |
865 | * - dst.addr is aligned to dst.width | |
866 | * | |
867 | * sg_len == 1 should be true, as there can be two cases here: | |
868 | * | |
869 | * - Memory addresses are contiguous and are not scattered. | |
870 | * Here, Only one sg will be passed by user driver, with | |
871 | * memory address and zero length. We pass this to controller | |
872 | * and after the transfer it will receive the last burst | |
873 | * request from peripheral and so transfer finishes. | |
874 | * | |
875 | * - Memory addresses are scattered and are not contiguous. | |
876 | * Here, Obviously as DMA controller doesn't know when a lli's | |
877 | * transfer gets over, it can't load next lli. So in this | |
878 | * case, there has to be an assumption that only one lli is | |
879 | * supported. Thus, we can't have scattered addresses. | |
880 | */ | |
881 | if (!bd.remainder) { | |
882 | u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> | |
883 | PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
884 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && | |
0a235657 | 885 | (fc <= PL080_FLOW_SRC2DST_SRC))) { |
b7f69d9d VK |
886 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", |
887 | __func__); | |
888 | return 0; | |
889 | } | |
0a235657 | 890 | |
1c38b289 AP |
891 | if (!IS_BUS_ALIGNED(&bd.srcbus) || |
892 | !IS_BUS_ALIGNED(&bd.dstbus)) { | |
b7f69d9d VK |
893 | dev_err(&pl08x->adev->dev, |
894 | "%s src & dst address must be aligned to src" | |
895 | " & dst width if peripheral is flow controller", | |
896 | __func__); | |
897 | return 0; | |
898 | } | |
03af500f | 899 | |
b7f69d9d VK |
900 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
901 | bd.dstbus.buswidth, 0); | |
902 | pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl); | |
903 | break; | |
904 | } | |
e8689e63 LW |
905 | |
906 | /* | |
b7f69d9d VK |
907 | * Send byte by byte for following cases |
908 | * - Less than a bus width available | |
909 | * - until master bus is aligned | |
e8689e63 | 910 | */ |
b7f69d9d VK |
911 | if (bd.remainder < mbus->buswidth) |
912 | early_bytes = bd.remainder; | |
1c38b289 AP |
913 | else if (!IS_BUS_ALIGNED(mbus)) { |
914 | early_bytes = mbus->buswidth - | |
915 | (mbus->addr & (mbus->buswidth - 1)); | |
b7f69d9d VK |
916 | if ((bd.remainder - early_bytes) < mbus->buswidth) |
917 | early_bytes = bd.remainder; | |
918 | } | |
e8689e63 | 919 | |
b7f69d9d VK |
920 | if (early_bytes) { |
921 | dev_vdbg(&pl08x->adev->dev, | |
922 | "%s byte width LLIs (remain 0x%08x)\n", | |
923 | __func__, bd.remainder); | |
924 | prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++, | |
925 | &total_bytes); | |
e8689e63 LW |
926 | } |
927 | ||
b7f69d9d VK |
928 | if (bd.remainder) { |
929 | /* | |
930 | * Master now aligned | |
931 | * - if slave is not then we must set its width down | |
932 | */ | |
1c38b289 | 933 | if (!IS_BUS_ALIGNED(sbus)) { |
b7f69d9d VK |
934 | dev_dbg(&pl08x->adev->dev, |
935 | "%s set down bus width to one byte\n", | |
936 | __func__); | |
fa6a940b | 937 | |
b7f69d9d VK |
938 | sbus->buswidth = 1; |
939 | } | |
e8689e63 LW |
940 | |
941 | /* | |
b7f69d9d VK |
942 | * Bytes transferred = tsize * src width, not |
943 | * MIN(buswidths) | |
e8689e63 | 944 | */ |
b7f69d9d VK |
945 | max_bytes_per_lli = bd.srcbus.buswidth * |
946 | PL080_CONTROL_TRANSFER_SIZE_MASK; | |
947 | dev_vdbg(&pl08x->adev->dev, | |
948 | "%s max bytes per lli = %zu\n", | |
949 | __func__, max_bytes_per_lli); | |
e8689e63 LW |
950 | |
951 | /* | |
b7f69d9d VK |
952 | * Make largest possible LLIs until less than one bus |
953 | * width left | |
e8689e63 | 954 | */ |
b7f69d9d VK |
955 | while (bd.remainder > (mbus->buswidth - 1)) { |
956 | size_t lli_len, tsize, width; | |
e8689e63 | 957 | |
b7f69d9d VK |
958 | /* |
959 | * If enough left try to send max possible, | |
960 | * otherwise try to send the remainder | |
961 | */ | |
962 | lli_len = min(bd.remainder, max_bytes_per_lli); | |
16a2e7d3 | 963 | |
b7f69d9d VK |
964 | /* |
965 | * Check against maximum bus alignment: | |
966 | * Calculate actual transfer size in relation to | |
967 | * bus width an get a maximum remainder of the | |
968 | * highest bus width - 1 | |
969 | */ | |
970 | width = max(mbus->buswidth, sbus->buswidth); | |
971 | lli_len = (lli_len / width) * width; | |
972 | tsize = lli_len / bd.srcbus.buswidth; | |
973 | ||
974 | dev_vdbg(&pl08x->adev->dev, | |
975 | "%s fill lli with single lli chunk of " | |
976 | "size 0x%08zx (remainder 0x%08zx)\n", | |
977 | __func__, lli_len, bd.remainder); | |
978 | ||
979 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, | |
16a2e7d3 | 980 | bd.dstbus.buswidth, tsize); |
b7f69d9d VK |
981 | pl08x_fill_lli_for_desc(&bd, num_llis++, |
982 | lli_len, cctl); | |
983 | total_bytes += lli_len; | |
984 | } | |
e8689e63 | 985 | |
b7f69d9d VK |
986 | /* |
987 | * Send any odd bytes | |
988 | */ | |
989 | if (bd.remainder) { | |
990 | dev_vdbg(&pl08x->adev->dev, | |
991 | "%s align with boundary, send odd bytes (remain %zu)\n", | |
992 | __func__, bd.remainder); | |
993 | prep_byte_width_lli(&bd, &cctl, bd.remainder, | |
994 | num_llis++, &total_bytes); | |
995 | } | |
e8689e63 | 996 | } |
16a2e7d3 | 997 | |
b7f69d9d VK |
998 | if (total_bytes != dsg->len) { |
999 | dev_err(&pl08x->adev->dev, | |
1000 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", | |
1001 | __func__, total_bytes, dsg->len); | |
1002 | return 0; | |
1003 | } | |
e8689e63 | 1004 | |
b7f69d9d VK |
1005 | if (num_llis >= MAX_NUM_TSFR_LLIS) { |
1006 | dev_err(&pl08x->adev->dev, | |
1007 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
1008 | __func__, (u32) MAX_NUM_TSFR_LLIS); | |
1009 | return 0; | |
1010 | } | |
e8689e63 | 1011 | } |
b58b6b5b RKAL |
1012 | |
1013 | llis_va = txd->llis_va; | |
94ae8522 | 1014 | /* The final LLI terminates the LLI. */ |
bfddfb45 | 1015 | llis_va[num_llis - 1].lli = 0; |
94ae8522 | 1016 | /* The final LLI element shall also fire an interrupt. */ |
b58b6b5b | 1017 | llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN; |
e8689e63 | 1018 | |
e8689e63 LW |
1019 | #ifdef VERBOSE_DEBUG |
1020 | { | |
1021 | int i; | |
1022 | ||
fc74eb79 RKAL |
1023 | dev_vdbg(&pl08x->adev->dev, |
1024 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
1025 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
e8689e63 LW |
1026 | for (i = 0; i < num_llis; i++) { |
1027 | dev_vdbg(&pl08x->adev->dev, | |
fc74eb79 RKAL |
1028 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
1029 | i, &llis_va[i], llis_va[i].src, | |
1030 | llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl | |
e8689e63 LW |
1031 | ); |
1032 | } | |
1033 | } | |
1034 | #endif | |
1035 | ||
1036 | return num_llis; | |
1037 | } | |
1038 | ||
e8689e63 LW |
1039 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, |
1040 | struct pl08x_txd *txd) | |
1041 | { | |
b7f69d9d VK |
1042 | struct pl08x_sg *dsg, *_dsg; |
1043 | ||
c1205646 VK |
1044 | if (txd->llis_va) |
1045 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); | |
e8689e63 | 1046 | |
b7f69d9d VK |
1047 | list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) { |
1048 | list_del(&dsg->node); | |
1049 | kfree(dsg); | |
1050 | } | |
1051 | ||
e8689e63 LW |
1052 | kfree(txd); |
1053 | } | |
1054 | ||
18536134 RK |
1055 | static void pl08x_unmap_buffers(struct pl08x_txd *txd) |
1056 | { | |
1057 | struct device *dev = txd->vd.tx.chan->device->dev; | |
1058 | struct pl08x_sg *dsg; | |
1059 | ||
1060 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
1061 | if (txd->vd.tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
1062 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1063 | dma_unmap_single(dev, dsg->src_addr, dsg->len, | |
1064 | DMA_TO_DEVICE); | |
1065 | else { | |
1066 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1067 | dma_unmap_page(dev, dsg->src_addr, dsg->len, | |
1068 | DMA_TO_DEVICE); | |
1069 | } | |
1070 | } | |
1071 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
1072 | if (txd->vd.tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
1073 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1074 | dma_unmap_single(dev, dsg->dst_addr, dsg->len, | |
1075 | DMA_FROM_DEVICE); | |
1076 | else | |
1077 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1078 | dma_unmap_page(dev, dsg->dst_addr, dsg->len, | |
1079 | DMA_FROM_DEVICE); | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | static void pl08x_desc_free(struct virt_dma_desc *vd) | |
1084 | { | |
1085 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1086 | struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan); | |
18536134 RK |
1087 | |
1088 | if (!plchan->slave) | |
1089 | pl08x_unmap_buffers(txd); | |
1090 | ||
1091 | if (!txd->done) | |
1092 | pl08x_release_mux(plchan); | |
1093 | ||
18536134 | 1094 | pl08x_free_txd(plchan->host, txd); |
18536134 RK |
1095 | } |
1096 | ||
e8689e63 LW |
1097 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, |
1098 | struct pl08x_dma_chan *plchan) | |
1099 | { | |
ea160561 | 1100 | LIST_HEAD(head); |
e8689e63 | 1101 | |
879f127b | 1102 | vchan_get_all_descriptors(&plchan->vc, &head); |
91998261 | 1103 | vchan_dma_desc_free_list(&plchan->vc, &head); |
e8689e63 LW |
1104 | } |
1105 | ||
1106 | /* | |
1107 | * The DMA ENGINE API | |
1108 | */ | |
1109 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
1110 | { | |
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
1115 | { | |
a068682c RK |
1116 | /* Ensure all queued descriptors are freed */ |
1117 | vchan_free_chan_resources(to_virt_chan(chan)); | |
e8689e63 LW |
1118 | } |
1119 | ||
e8689e63 LW |
1120 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( |
1121 | struct dma_chan *chan, unsigned long flags) | |
1122 | { | |
1123 | struct dma_async_tx_descriptor *retval = NULL; | |
1124 | ||
1125 | return retval; | |
1126 | } | |
1127 | ||
1128 | /* | |
94ae8522 RKAL |
1129 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
1130 | * If slaves are relying on interrupts to signal completion this function | |
1131 | * must not be called with interrupts disabled. | |
e8689e63 | 1132 | */ |
3e27ee84 VK |
1133 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
1134 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
1135 | { |
1136 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
06e885b7 RK |
1137 | struct virt_dma_desc *vd; |
1138 | unsigned long flags; | |
e8689e63 | 1139 | enum dma_status ret; |
06e885b7 | 1140 | size_t bytes = 0; |
e8689e63 | 1141 | |
96a2af41 RKAL |
1142 | ret = dma_cookie_status(chan, cookie, txstate); |
1143 | if (ret == DMA_SUCCESS) | |
e8689e63 | 1144 | return ret; |
e8689e63 | 1145 | |
06e885b7 RK |
1146 | /* |
1147 | * There's no point calculating the residue if there's | |
1148 | * no txstate to store the value. | |
1149 | */ | |
1150 | if (!txstate) { | |
1151 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1152 | ret = DMA_PAUSED; | |
1153 | return ret; | |
1154 | } | |
1155 | ||
1156 | spin_lock_irqsave(&plchan->vc.lock, flags); | |
1157 | ret = dma_cookie_status(chan, cookie, txstate); | |
1158 | if (ret != DMA_SUCCESS) { | |
1159 | vd = vchan_find_desc(&plchan->vc, cookie); | |
1160 | if (vd) { | |
1161 | /* On the issued list, so hasn't been processed yet */ | |
1162 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1163 | struct pl08x_sg *dsg; | |
1164 | ||
1165 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1166 | bytes += dsg->len; | |
1167 | } else { | |
1168 | bytes = pl08x_getbytes_chan(plchan); | |
1169 | } | |
1170 | } | |
1171 | spin_unlock_irqrestore(&plchan->vc.lock, flags); | |
1172 | ||
e8689e63 LW |
1173 | /* |
1174 | * This cookie not complete yet | |
96a2af41 | 1175 | * Get number of bytes left in the active transactions and queue |
e8689e63 | 1176 | */ |
06e885b7 | 1177 | dma_set_residue(txstate, bytes); |
e8689e63 | 1178 | |
06e885b7 RK |
1179 | if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS) |
1180 | ret = DMA_PAUSED; | |
e8689e63 LW |
1181 | |
1182 | /* Whether waiting or running, we're in progress */ | |
06e885b7 | 1183 | return ret; |
e8689e63 LW |
1184 | } |
1185 | ||
1186 | /* PrimeCell DMA extension */ | |
1187 | struct burst_table { | |
760596c6 | 1188 | u32 burstwords; |
e8689e63 LW |
1189 | u32 reg; |
1190 | }; | |
1191 | ||
1192 | static const struct burst_table burst_sizes[] = { | |
1193 | { | |
1194 | .burstwords = 256, | |
760596c6 | 1195 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
1196 | }, |
1197 | { | |
1198 | .burstwords = 128, | |
760596c6 | 1199 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
1200 | }, |
1201 | { | |
1202 | .burstwords = 64, | |
760596c6 | 1203 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
1204 | }, |
1205 | { | |
1206 | .burstwords = 32, | |
760596c6 | 1207 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
1208 | }, |
1209 | { | |
1210 | .burstwords = 16, | |
760596c6 | 1211 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
1212 | }, |
1213 | { | |
1214 | .burstwords = 8, | |
760596c6 | 1215 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1216 | }, |
1217 | { | |
1218 | .burstwords = 4, | |
760596c6 | 1219 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1220 | }, |
1221 | { | |
760596c6 RKAL |
1222 | .burstwords = 0, |
1223 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1224 | }, |
1225 | }; | |
1226 | ||
121c8476 RKAL |
1227 | /* |
1228 | * Given the source and destination available bus masks, select which | |
1229 | * will be routed to each port. We try to have source and destination | |
1230 | * on separate ports, but always respect the allowable settings. | |
1231 | */ | |
1232 | static u32 pl08x_select_bus(u8 src, u8 dst) | |
1233 | { | |
1234 | u32 cctl = 0; | |
1235 | ||
1236 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1237 | cctl |= PL080_CONTROL_DST_AHB2; | |
1238 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1239 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1240 | ||
1241 | return cctl; | |
1242 | } | |
1243 | ||
f14c426c RKAL |
1244 | static u32 pl08x_cctl(u32 cctl) |
1245 | { | |
1246 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1247 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1248 | PL080_CONTROL_PROT_MASK); | |
1249 | ||
1250 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1251 | return cctl | PL080_CONTROL_PROT_SYS; | |
1252 | } | |
1253 | ||
aa88cdaa RKAL |
1254 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1255 | { | |
1256 | switch (width) { | |
1257 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1258 | return PL080_WIDTH_8BIT; | |
1259 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1260 | return PL080_WIDTH_16BIT; | |
1261 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1262 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1263 | default: |
1264 | return ~0; | |
aa88cdaa | 1265 | } |
aa88cdaa RKAL |
1266 | } |
1267 | ||
760596c6 RKAL |
1268 | static u32 pl08x_burst(u32 maxburst) |
1269 | { | |
1270 | int i; | |
1271 | ||
1272 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1273 | if (burst_sizes[i].burstwords <= maxburst) | |
1274 | break; | |
1275 | ||
1276 | return burst_sizes[i].reg; | |
1277 | } | |
1278 | ||
9862ba17 RK |
1279 | static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan, |
1280 | enum dma_slave_buswidth addr_width, u32 maxburst) | |
1281 | { | |
1282 | u32 width, burst, cctl = 0; | |
1283 | ||
1284 | width = pl08x_width(addr_width); | |
1285 | if (width == ~0) | |
1286 | return ~0; | |
1287 | ||
1288 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; | |
1289 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1290 | ||
1291 | /* | |
1292 | * If this channel will only request single transfers, set this | |
1293 | * down to ONE element. Also select one element if no maxburst | |
1294 | * is specified. | |
1295 | */ | |
1296 | if (plchan->cd->single) | |
1297 | maxburst = 1; | |
1298 | ||
1299 | burst = pl08x_burst(maxburst); | |
1300 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1301 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
1302 | ||
1303 | return pl08x_cctl(cctl); | |
1304 | } | |
1305 | ||
f0fd9446 RKAL |
1306 | static int dma_set_runtime_config(struct dma_chan *chan, |
1307 | struct dma_slave_config *config) | |
e8689e63 LW |
1308 | { |
1309 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
b7f75865 RKAL |
1310 | |
1311 | if (!plchan->slave) | |
1312 | return -EINVAL; | |
e8689e63 | 1313 | |
dc8d5f8d RK |
1314 | /* Reject definitely invalid configurations */ |
1315 | if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || | |
1316 | config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
f0fd9446 | 1317 | return -EINVAL; |
e8689e63 | 1318 | |
ed91c13d RK |
1319 | plchan->cfg = *config; |
1320 | ||
f0fd9446 | 1321 | return 0; |
e8689e63 LW |
1322 | } |
1323 | ||
1324 | /* | |
1325 | * Slave transactions callback to the slave device to allow | |
1326 | * synchronization of slave DMA signals with the DMAC enable | |
1327 | */ | |
1328 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1329 | { | |
1330 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1331 | unsigned long flags; |
1332 | ||
083be28a | 1333 | spin_lock_irqsave(&plchan->vc.lock, flags); |
879f127b | 1334 | if (vchan_issue_pending(&plchan->vc)) { |
a5a488db RK |
1335 | if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING) |
1336 | pl08x_phy_alloc_and_start(plchan); | |
e8689e63 | 1337 | } |
083be28a | 1338 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1339 | } |
1340 | ||
879f127b | 1341 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan) |
ac3cd20d | 1342 | { |
b201c111 | 1343 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d RKAL |
1344 | |
1345 | if (txd) { | |
b7f69d9d | 1346 | INIT_LIST_HEAD(&txd->dsg_list); |
4983a04f RKAL |
1347 | |
1348 | /* Always enable error and terminal interrupts */ | |
1349 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1350 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1351 | } |
1352 | return txd; | |
1353 | } | |
1354 | ||
e8689e63 LW |
1355 | /* |
1356 | * Initialize a descriptor to be used by memcpy submit | |
1357 | */ | |
1358 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1359 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1360 | size_t len, unsigned long flags) | |
1361 | { | |
1362 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1363 | struct pl08x_driver_data *pl08x = plchan->host; | |
1364 | struct pl08x_txd *txd; | |
b7f69d9d | 1365 | struct pl08x_sg *dsg; |
e8689e63 LW |
1366 | int ret; |
1367 | ||
879f127b | 1368 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1369 | if (!txd) { |
1370 | dev_err(&pl08x->adev->dev, | |
1371 | "%s no memory for descriptor\n", __func__); | |
1372 | return NULL; | |
1373 | } | |
1374 | ||
b7f69d9d VK |
1375 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); |
1376 | if (!dsg) { | |
1377 | pl08x_free_txd(pl08x, txd); | |
1378 | dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n", | |
1379 | __func__); | |
1380 | return NULL; | |
1381 | } | |
1382 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1383 | ||
b7f69d9d VK |
1384 | dsg->src_addr = src; |
1385 | dsg->dst_addr = dest; | |
1386 | dsg->len = len; | |
e8689e63 LW |
1387 | |
1388 | /* Set platform data for m2m */ | |
4983a04f | 1389 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
dc8d5f8d | 1390 | txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy & |
c7da9a56 | 1391 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); |
4983a04f | 1392 | |
e8689e63 | 1393 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1394 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1395 | |
c7da9a56 | 1396 | if (pl08x->vd->dualmaster) |
121c8476 RKAL |
1397 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
1398 | pl08x->mem_buses); | |
e8689e63 | 1399 | |
aa4afb75 RK |
1400 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1401 | if (!ret) { | |
1402 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 1403 | return NULL; |
aa4afb75 | 1404 | } |
e8689e63 | 1405 | |
879f127b | 1406 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1407 | } |
1408 | ||
3e2a037c | 1409 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 | 1410 | struct dma_chan *chan, struct scatterlist *sgl, |
db8196df | 1411 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1412 | unsigned long flags, void *context) |
e8689e63 LW |
1413 | { |
1414 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1415 | struct pl08x_driver_data *pl08x = plchan->host; | |
1416 | struct pl08x_txd *txd; | |
b7f69d9d VK |
1417 | struct pl08x_sg *dsg; |
1418 | struct scatterlist *sg; | |
dc8d5f8d | 1419 | enum dma_slave_buswidth addr_width; |
b7f69d9d | 1420 | dma_addr_t slave_addr; |
0a235657 | 1421 | int ret, tmp; |
409ec8db | 1422 | u8 src_buses, dst_buses; |
dc8d5f8d | 1423 | u32 maxburst, cctl; |
e8689e63 | 1424 | |
e8689e63 | 1425 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", |
fdaf9c4b | 1426 | __func__, sg_dma_len(sgl), plchan->name); |
e8689e63 | 1427 | |
879f127b | 1428 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1429 | if (!txd) { |
1430 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1431 | return NULL; | |
1432 | } | |
1433 | ||
e8689e63 LW |
1434 | /* |
1435 | * Set up addresses, the PrimeCell configured address | |
1436 | * will take precedence since this may configure the | |
1437 | * channel target address dynamically at runtime. | |
1438 | */ | |
db8196df | 1439 | if (direction == DMA_MEM_TO_DEV) { |
dc8d5f8d | 1440 | cctl = PL080_CONTROL_SRC_INCR; |
ed91c13d | 1441 | slave_addr = plchan->cfg.dst_addr; |
dc8d5f8d RK |
1442 | addr_width = plchan->cfg.dst_addr_width; |
1443 | maxburst = plchan->cfg.dst_maxburst; | |
409ec8db RK |
1444 | src_buses = pl08x->mem_buses; |
1445 | dst_buses = plchan->cd->periph_buses; | |
db8196df | 1446 | } else if (direction == DMA_DEV_TO_MEM) { |
dc8d5f8d | 1447 | cctl = PL080_CONTROL_DST_INCR; |
ed91c13d | 1448 | slave_addr = plchan->cfg.src_addr; |
dc8d5f8d RK |
1449 | addr_width = plchan->cfg.src_addr_width; |
1450 | maxburst = plchan->cfg.src_maxburst; | |
409ec8db RK |
1451 | src_buses = plchan->cd->periph_buses; |
1452 | dst_buses = pl08x->mem_buses; | |
e8689e63 | 1453 | } else { |
b7f69d9d | 1454 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1455 | dev_err(&pl08x->adev->dev, |
1456 | "%s direction unsupported\n", __func__); | |
1457 | return NULL; | |
1458 | } | |
e8689e63 | 1459 | |
dc8d5f8d | 1460 | cctl |= pl08x_get_cctl(plchan, addr_width, maxburst); |
800d683e RK |
1461 | if (cctl == ~0) { |
1462 | pl08x_free_txd(pl08x, txd); | |
1463 | dev_err(&pl08x->adev->dev, | |
1464 | "DMA slave configuration botched?\n"); | |
1465 | return NULL; | |
1466 | } | |
1467 | ||
409ec8db RK |
1468 | txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses); |
1469 | ||
95442b22 | 1470 | if (plchan->cfg.device_fc) |
db8196df | 1471 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : |
0a235657 VK |
1472 | PL080_FLOW_PER2MEM_PER; |
1473 | else | |
db8196df | 1474 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER : |
0a235657 VK |
1475 | PL080_FLOW_PER2MEM; |
1476 | ||
1477 | txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1478 | ||
c48d4963 RK |
1479 | ret = pl08x_request_mux(plchan); |
1480 | if (ret < 0) { | |
1481 | pl08x_free_txd(pl08x, txd); | |
1482 | dev_dbg(&pl08x->adev->dev, | |
1483 | "unable to mux for transfer on %s due to platform restrictions\n", | |
1484 | plchan->name); | |
1485 | return NULL; | |
1486 | } | |
1487 | ||
1488 | dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n", | |
1489 | plchan->signal, plchan->name); | |
1490 | ||
1491 | /* Assign the flow control signal to this channel */ | |
1492 | if (direction == DMA_MEM_TO_DEV) | |
1493 | txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
1494 | else | |
1495 | txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
1496 | ||
b7f69d9d VK |
1497 | for_each_sg(sgl, sg, sg_len, tmp) { |
1498 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); | |
1499 | if (!dsg) { | |
c48d4963 | 1500 | pl08x_release_mux(plchan); |
b7f69d9d VK |
1501 | pl08x_free_txd(pl08x, txd); |
1502 | dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n", | |
1503 | __func__); | |
1504 | return NULL; | |
1505 | } | |
1506 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1507 | ||
1508 | dsg->len = sg_dma_len(sg); | |
db8196df | 1509 | if (direction == DMA_MEM_TO_DEV) { |
cbb796cc | 1510 | dsg->src_addr = sg_dma_address(sg); |
b7f69d9d VK |
1511 | dsg->dst_addr = slave_addr; |
1512 | } else { | |
1513 | dsg->src_addr = slave_addr; | |
cbb796cc | 1514 | dsg->dst_addr = sg_dma_address(sg); |
b7f69d9d VK |
1515 | } |
1516 | } | |
1517 | ||
aa4afb75 RK |
1518 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1519 | if (!ret) { | |
1520 | pl08x_release_mux(plchan); | |
1521 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 1522 | return NULL; |
aa4afb75 | 1523 | } |
e8689e63 | 1524 | |
879f127b | 1525 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1526 | } |
1527 | ||
1528 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1529 | unsigned long arg) | |
1530 | { | |
1531 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1532 | struct pl08x_driver_data *pl08x = plchan->host; | |
1533 | unsigned long flags; | |
1534 | int ret = 0; | |
1535 | ||
1536 | /* Controls applicable to inactive channels */ | |
1537 | if (cmd == DMA_SLAVE_CONFIG) { | |
f0fd9446 RKAL |
1538 | return dma_set_runtime_config(chan, |
1539 | (struct dma_slave_config *)arg); | |
e8689e63 LW |
1540 | } |
1541 | ||
1542 | /* | |
1543 | * Anything succeeds on channels with no physical allocation and | |
1544 | * no queued transfers. | |
1545 | */ | |
083be28a | 1546 | spin_lock_irqsave(&plchan->vc.lock, flags); |
e8689e63 | 1547 | if (!plchan->phychan && !plchan->at) { |
083be28a | 1548 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1549 | return 0; |
1550 | } | |
1551 | ||
1552 | switch (cmd) { | |
1553 | case DMA_TERMINATE_ALL: | |
1554 | plchan->state = PL08X_CHAN_IDLE; | |
1555 | ||
1556 | if (plchan->phychan) { | |
e8689e63 LW |
1557 | /* |
1558 | * Mark physical channel as free and free any slave | |
1559 | * signal | |
1560 | */ | |
a5a488db | 1561 | pl08x_phy_free(plchan); |
e8689e63 | 1562 | } |
e8689e63 LW |
1563 | /* Dequeue jobs and free LLIs */ |
1564 | if (plchan->at) { | |
18536134 | 1565 | pl08x_desc_free(&plchan->at->vd); |
e8689e63 LW |
1566 | plchan->at = NULL; |
1567 | } | |
1568 | /* Dequeue jobs not yet fired as well */ | |
1569 | pl08x_free_txd_list(pl08x, plchan); | |
1570 | break; | |
1571 | case DMA_PAUSE: | |
1572 | pl08x_pause_phy_chan(plchan->phychan); | |
1573 | plchan->state = PL08X_CHAN_PAUSED; | |
1574 | break; | |
1575 | case DMA_RESUME: | |
1576 | pl08x_resume_phy_chan(plchan->phychan); | |
1577 | plchan->state = PL08X_CHAN_RUNNING; | |
1578 | break; | |
1579 | default: | |
1580 | /* Unknown command */ | |
1581 | ret = -ENXIO; | |
1582 | break; | |
1583 | } | |
1584 | ||
083be28a | 1585 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1586 | |
1587 | return ret; | |
1588 | } | |
1589 | ||
1590 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1591 | { | |
7703eac9 | 1592 | struct pl08x_dma_chan *plchan; |
e8689e63 LW |
1593 | char *name = chan_id; |
1594 | ||
7703eac9 RKAL |
1595 | /* Reject channels for devices not bound to this driver */ |
1596 | if (chan->device->dev->driver != &pl08x_amba_driver.drv) | |
1597 | return false; | |
1598 | ||
1599 | plchan = to_pl08x_chan(chan); | |
1600 | ||
e8689e63 LW |
1601 | /* Check that the channel is not taken! */ |
1602 | if (!strcmp(plchan->name, name)) | |
1603 | return true; | |
1604 | ||
1605 | return false; | |
1606 | } | |
1607 | ||
1608 | /* | |
1609 | * Just check that the device is there and active | |
94ae8522 RKAL |
1610 | * TODO: turn this bit on/off depending on the number of physical channels |
1611 | * actually used, if it is zero... well shut it off. That will save some | |
1612 | * power. Cut the clock at the same time. | |
e8689e63 LW |
1613 | */ |
1614 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1615 | { | |
affa115e LW |
1616 | /* The Nomadik variant does not have the config register */ |
1617 | if (pl08x->vd->nomadik) | |
1618 | return; | |
48a59ef3 | 1619 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
e8689e63 LW |
1620 | } |
1621 | ||
e8689e63 LW |
1622 | static irqreturn_t pl08x_irq(int irq, void *dev) |
1623 | { | |
1624 | struct pl08x_driver_data *pl08x = dev; | |
28da2836 VK |
1625 | u32 mask = 0, err, tc, i; |
1626 | ||
1627 | /* check & clear - ERR & TC interrupts */ | |
1628 | err = readl(pl08x->base + PL080_ERR_STATUS); | |
1629 | if (err) { | |
1630 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", | |
1631 | __func__, err); | |
1632 | writel(err, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 | 1633 | } |
d29bf019 | 1634 | tc = readl(pl08x->base + PL080_TC_STATUS); |
28da2836 VK |
1635 | if (tc) |
1636 | writel(tc, pl08x->base + PL080_TC_CLEAR); | |
1637 | ||
1638 | if (!err && !tc) | |
1639 | return IRQ_NONE; | |
1640 | ||
e8689e63 | 1641 | for (i = 0; i < pl08x->vd->channels; i++) { |
28da2836 | 1642 | if (((1 << i) & err) || ((1 << i) & tc)) { |
e8689e63 LW |
1643 | /* Locate physical channel */ |
1644 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1645 | struct pl08x_dma_chan *plchan = phychan->serving; | |
a936e793 | 1646 | struct pl08x_txd *tx; |
e8689e63 | 1647 | |
28da2836 VK |
1648 | if (!plchan) { |
1649 | dev_err(&pl08x->adev->dev, | |
1650 | "%s Error TC interrupt on unused channel: 0x%08x\n", | |
1651 | __func__, i); | |
1652 | continue; | |
1653 | } | |
1654 | ||
083be28a | 1655 | spin_lock(&plchan->vc.lock); |
a936e793 RK |
1656 | tx = plchan->at; |
1657 | if (tx) { | |
1658 | plchan->at = NULL; | |
c48d4963 RK |
1659 | /* |
1660 | * This descriptor is done, release its mux | |
1661 | * reservation. | |
1662 | */ | |
1663 | pl08x_release_mux(plchan); | |
18536134 RK |
1664 | tx->done = true; |
1665 | vchan_cookie_complete(&tx->vd); | |
c33b644c | 1666 | |
a5a488db RK |
1667 | /* |
1668 | * And start the next descriptor (if any), | |
1669 | * otherwise free this channel. | |
1670 | */ | |
879f127b | 1671 | if (vchan_next_desc(&plchan->vc)) |
c33b644c | 1672 | pl08x_start_next_txd(plchan); |
a5a488db RK |
1673 | else |
1674 | pl08x_phy_free(plchan); | |
a936e793 | 1675 | } |
083be28a | 1676 | spin_unlock(&plchan->vc.lock); |
a936e793 | 1677 | |
e8689e63 LW |
1678 | mask |= (1 << i); |
1679 | } | |
1680 | } | |
e8689e63 LW |
1681 | |
1682 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1683 | } | |
1684 | ||
121c8476 RKAL |
1685 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
1686 | { | |
121c8476 RKAL |
1687 | chan->slave = true; |
1688 | chan->name = chan->cd->bus_id; | |
ed91c13d RK |
1689 | chan->cfg.src_addr = chan->cd->addr; |
1690 | chan->cfg.dst_addr = chan->cd->addr; | |
121c8476 RKAL |
1691 | } |
1692 | ||
e8689e63 LW |
1693 | /* |
1694 | * Initialise the DMAC memcpy/slave channels. | |
1695 | * Make a local wrapper to hold required data | |
1696 | */ | |
1697 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 1698 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
1699 | { |
1700 | struct pl08x_dma_chan *chan; | |
1701 | int i; | |
1702 | ||
1703 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 1704 | |
e8689e63 LW |
1705 | /* |
1706 | * Register as many many memcpy as we have physical channels, | |
1707 | * we won't always be able to use all but the code will have | |
1708 | * to cope with that situation. | |
1709 | */ | |
1710 | for (i = 0; i < channels; i++) { | |
b201c111 | 1711 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
e8689e63 LW |
1712 | if (!chan) { |
1713 | dev_err(&pl08x->adev->dev, | |
1714 | "%s no memory for channel\n", __func__); | |
1715 | return -ENOMEM; | |
1716 | } | |
1717 | ||
1718 | chan->host = pl08x; | |
1719 | chan->state = PL08X_CHAN_IDLE; | |
ad0de2ac | 1720 | chan->signal = -1; |
e8689e63 LW |
1721 | |
1722 | if (slave) { | |
e8689e63 | 1723 | chan->cd = &pl08x->pd->slave_channels[i]; |
121c8476 | 1724 | pl08x_dma_slave_init(chan); |
e8689e63 LW |
1725 | } else { |
1726 | chan->cd = &pl08x->pd->memcpy_channel; | |
1727 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1728 | if (!chan->name) { | |
1729 | kfree(chan); | |
1730 | return -ENOMEM; | |
1731 | } | |
1732 | } | |
175a5e61 | 1733 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
1734 | "initialize virtual channel \"%s\"\n", |
1735 | chan->name); | |
1736 | ||
18536134 | 1737 | chan->vc.desc_free = pl08x_desc_free; |
083be28a | 1738 | vchan_init(&chan->vc, dmadev); |
e8689e63 LW |
1739 | } |
1740 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1741 | i, slave ? "slave" : "memcpy"); | |
1742 | return i; | |
1743 | } | |
1744 | ||
1745 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1746 | { | |
1747 | struct pl08x_dma_chan *chan = NULL; | |
1748 | struct pl08x_dma_chan *next; | |
1749 | ||
1750 | list_for_each_entry_safe(chan, | |
01d8dc64 RK |
1751 | next, &dmadev->channels, vc.chan.device_node) { |
1752 | list_del(&chan->vc.chan.device_node); | |
e8689e63 LW |
1753 | kfree(chan); |
1754 | } | |
1755 | } | |
1756 | ||
1757 | #ifdef CONFIG_DEBUG_FS | |
1758 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1759 | { | |
1760 | switch (state) { | |
1761 | case PL08X_CHAN_IDLE: | |
1762 | return "idle"; | |
1763 | case PL08X_CHAN_RUNNING: | |
1764 | return "running"; | |
1765 | case PL08X_CHAN_PAUSED: | |
1766 | return "paused"; | |
1767 | case PL08X_CHAN_WAITING: | |
1768 | return "waiting"; | |
1769 | default: | |
1770 | break; | |
1771 | } | |
1772 | return "UNKNOWN STATE"; | |
1773 | } | |
1774 | ||
1775 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1776 | { | |
1777 | struct pl08x_driver_data *pl08x = s->private; | |
1778 | struct pl08x_dma_chan *chan; | |
1779 | struct pl08x_phy_chan *ch; | |
1780 | unsigned long flags; | |
1781 | int i; | |
1782 | ||
1783 | seq_printf(s, "PL08x physical channels:\n"); | |
1784 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1785 | seq_printf(s, "--------\t-----\n"); | |
1786 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1787 | struct pl08x_dma_chan *virt_chan; | |
1788 | ||
1789 | ch = &pl08x->phy_chans[i]; | |
1790 | ||
1791 | spin_lock_irqsave(&ch->lock, flags); | |
1792 | virt_chan = ch->serving; | |
1793 | ||
affa115e LW |
1794 | seq_printf(s, "%d\t\t%s%s\n", |
1795 | ch->id, | |
1796 | virt_chan ? virt_chan->name : "(none)", | |
1797 | ch->locked ? " LOCKED" : ""); | |
e8689e63 LW |
1798 | |
1799 | spin_unlock_irqrestore(&ch->lock, flags); | |
1800 | } | |
1801 | ||
1802 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1803 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1804 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1805 | list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) { |
3e2a037c | 1806 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1807 | pl08x_state_str(chan->state)); |
1808 | } | |
1809 | ||
1810 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1811 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1812 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1813 | list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) { |
3e2a037c | 1814 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1815 | pl08x_state_str(chan->state)); |
1816 | } | |
1817 | ||
1818 | return 0; | |
1819 | } | |
1820 | ||
1821 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1822 | { | |
1823 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1824 | } | |
1825 | ||
1826 | static const struct file_operations pl08x_debugfs_operations = { | |
1827 | .open = pl08x_debugfs_open, | |
1828 | .read = seq_read, | |
1829 | .llseek = seq_lseek, | |
1830 | .release = single_release, | |
1831 | }; | |
1832 | ||
1833 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1834 | { | |
1835 | /* Expose a simple debugfs interface to view all clocks */ | |
3e27ee84 VK |
1836 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
1837 | S_IFREG | S_IRUGO, NULL, pl08x, | |
1838 | &pl08x_debugfs_operations); | |
e8689e63 LW |
1839 | } |
1840 | ||
1841 | #else | |
1842 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1843 | { | |
1844 | } | |
1845 | #endif | |
1846 | ||
aa25afad | 1847 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
1848 | { |
1849 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1850 | const struct vendor_data *vd = id->data; |
e8689e63 LW |
1851 | int ret = 0; |
1852 | int i; | |
1853 | ||
1854 | ret = amba_request_regions(adev, NULL); | |
1855 | if (ret) | |
1856 | return ret; | |
1857 | ||
1858 | /* Create the driver state holder */ | |
b201c111 | 1859 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
1860 | if (!pl08x) { |
1861 | ret = -ENOMEM; | |
1862 | goto out_no_pl08x; | |
1863 | } | |
1864 | ||
1865 | /* Initialize memcpy engine */ | |
1866 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1867 | pl08x->memcpy.dev = &adev->dev; | |
1868 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1869 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1870 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1871 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1872 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1873 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1874 | pl08x->memcpy.device_control = pl08x_control; | |
1875 | ||
1876 | /* Initialize slave engine */ | |
1877 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1878 | pl08x->slave.dev = &adev->dev; | |
1879 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1880 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1881 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1882 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1883 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1884 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1885 | pl08x->slave.device_control = pl08x_control; | |
1886 | ||
1887 | /* Get the platform data */ | |
1888 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1889 | if (!pl08x->pd) { | |
1890 | dev_err(&adev->dev, "no platform data supplied\n"); | |
983d7beb | 1891 | ret = -EINVAL; |
e8689e63 LW |
1892 | goto out_no_platdata; |
1893 | } | |
1894 | ||
1895 | /* Assign useful pointers to the driver state */ | |
1896 | pl08x->adev = adev; | |
1897 | pl08x->vd = vd; | |
1898 | ||
30749cb4 RKAL |
1899 | /* By default, AHB1 only. If dualmaster, from platform */ |
1900 | pl08x->lli_buses = PL08X_AHB1; | |
1901 | pl08x->mem_buses = PL08X_AHB1; | |
1902 | if (pl08x->vd->dualmaster) { | |
1903 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
1904 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
1905 | } | |
1906 | ||
e8689e63 LW |
1907 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
1908 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
1909 | PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0); | |
1910 | if (!pl08x->pool) { | |
1911 | ret = -ENOMEM; | |
1912 | goto out_no_lli_pool; | |
1913 | } | |
1914 | ||
e8689e63 LW |
1915 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); |
1916 | if (!pl08x->base) { | |
1917 | ret = -ENOMEM; | |
1918 | goto out_no_ioremap; | |
1919 | } | |
1920 | ||
1921 | /* Turn on the PL08x */ | |
1922 | pl08x_ensure_on(pl08x); | |
1923 | ||
94ae8522 | 1924 | /* Attach the interrupt handler */ |
e8689e63 LW |
1925 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
1926 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
1927 | ||
1928 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 1929 | DRIVER_NAME, pl08x); |
e8689e63 LW |
1930 | if (ret) { |
1931 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
1932 | __func__, adev->irq[0]); | |
1933 | goto out_no_irq; | |
1934 | } | |
1935 | ||
1936 | /* Initialize physical channels */ | |
affa115e | 1937 | pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
1938 | GFP_KERNEL); |
1939 | if (!pl08x->phy_chans) { | |
1940 | dev_err(&adev->dev, "%s failed to allocate " | |
1941 | "physical channel holders\n", | |
1942 | __func__); | |
983d7beb | 1943 | ret = -ENOMEM; |
e8689e63 LW |
1944 | goto out_no_phychans; |
1945 | } | |
1946 | ||
1947 | for (i = 0; i < vd->channels; i++) { | |
1948 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
1949 | ||
1950 | ch->id = i; | |
1951 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
1952 | spin_lock_init(&ch->lock); | |
affa115e LW |
1953 | |
1954 | /* | |
1955 | * Nomadik variants can have channels that are locked | |
1956 | * down for the secure world only. Lock up these channels | |
1957 | * by perpetually serving a dummy virtual channel. | |
1958 | */ | |
1959 | if (vd->nomadik) { | |
1960 | u32 val; | |
1961 | ||
1962 | val = readl(ch->base + PL080_CH_CONFIG); | |
1963 | if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { | |
1964 | dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i); | |
1965 | ch->locked = true; | |
1966 | } | |
1967 | } | |
1968 | ||
175a5e61 VK |
1969 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
1970 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
1971 | } |
1972 | ||
1973 | /* Register as many memcpy channels as there are physical channels */ | |
1974 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
1975 | pl08x->vd->channels, false); | |
1976 | if (ret <= 0) { | |
1977 | dev_warn(&pl08x->adev->dev, | |
1978 | "%s failed to enumerate memcpy channels - %d\n", | |
1979 | __func__, ret); | |
1980 | goto out_no_memcpy; | |
1981 | } | |
1982 | pl08x->memcpy.chancnt = ret; | |
1983 | ||
1984 | /* Register slave channels */ | |
1985 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
3e27ee84 | 1986 | pl08x->pd->num_slave_channels, true); |
e8689e63 LW |
1987 | if (ret <= 0) { |
1988 | dev_warn(&pl08x->adev->dev, | |
1989 | "%s failed to enumerate slave channels - %d\n", | |
1990 | __func__, ret); | |
1991 | goto out_no_slave; | |
1992 | } | |
1993 | pl08x->slave.chancnt = ret; | |
1994 | ||
1995 | ret = dma_async_device_register(&pl08x->memcpy); | |
1996 | if (ret) { | |
1997 | dev_warn(&pl08x->adev->dev, | |
1998 | "%s failed to register memcpy as an async device - %d\n", | |
1999 | __func__, ret); | |
2000 | goto out_no_memcpy_reg; | |
2001 | } | |
2002 | ||
2003 | ret = dma_async_device_register(&pl08x->slave); | |
2004 | if (ret) { | |
2005 | dev_warn(&pl08x->adev->dev, | |
2006 | "%s failed to register slave as an async device - %d\n", | |
2007 | __func__, ret); | |
2008 | goto out_no_slave_reg; | |
2009 | } | |
2010 | ||
2011 | amba_set_drvdata(adev, pl08x); | |
2012 | init_pl08x_debugfs(pl08x); | |
b05cd8f4 RKAL |
2013 | dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n", |
2014 | amba_part(adev), amba_rev(adev), | |
2015 | (unsigned long long)adev->res.start, adev->irq[0]); | |
b7b6018b | 2016 | |
e8689e63 LW |
2017 | return 0; |
2018 | ||
2019 | out_no_slave_reg: | |
2020 | dma_async_device_unregister(&pl08x->memcpy); | |
2021 | out_no_memcpy_reg: | |
2022 | pl08x_free_virtual_channels(&pl08x->slave); | |
2023 | out_no_slave: | |
2024 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2025 | out_no_memcpy: | |
2026 | kfree(pl08x->phy_chans); | |
2027 | out_no_phychans: | |
2028 | free_irq(adev->irq[0], pl08x); | |
2029 | out_no_irq: | |
2030 | iounmap(pl08x->base); | |
2031 | out_no_ioremap: | |
2032 | dma_pool_destroy(pl08x->pool); | |
2033 | out_no_lli_pool: | |
2034 | out_no_platdata: | |
2035 | kfree(pl08x); | |
2036 | out_no_pl08x: | |
2037 | amba_release_regions(adev); | |
2038 | return ret; | |
2039 | } | |
2040 | ||
2041 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2042 | static struct vendor_data vendor_pl080 = { | |
e8689e63 LW |
2043 | .channels = 8, |
2044 | .dualmaster = true, | |
2045 | }; | |
2046 | ||
affa115e LW |
2047 | static struct vendor_data vendor_nomadik = { |
2048 | .channels = 8, | |
2049 | .dualmaster = true, | |
2050 | .nomadik = true, | |
2051 | }; | |
2052 | ||
e8689e63 | 2053 | static struct vendor_data vendor_pl081 = { |
e8689e63 LW |
2054 | .channels = 2, |
2055 | .dualmaster = false, | |
2056 | }; | |
2057 | ||
2058 | static struct amba_id pl08x_ids[] = { | |
2059 | /* PL080 */ | |
2060 | { | |
2061 | .id = 0x00041080, | |
2062 | .mask = 0x000fffff, | |
2063 | .data = &vendor_pl080, | |
2064 | }, | |
2065 | /* PL081 */ | |
2066 | { | |
2067 | .id = 0x00041081, | |
2068 | .mask = 0x000fffff, | |
2069 | .data = &vendor_pl081, | |
2070 | }, | |
2071 | /* Nomadik 8815 PL080 variant */ | |
2072 | { | |
affa115e | 2073 | .id = 0x00280080, |
e8689e63 | 2074 | .mask = 0x00ffffff, |
affa115e | 2075 | .data = &vendor_nomadik, |
e8689e63 LW |
2076 | }, |
2077 | { 0, 0 }, | |
2078 | }; | |
2079 | ||
037566df DM |
2080 | MODULE_DEVICE_TABLE(amba, pl08x_ids); |
2081 | ||
e8689e63 LW |
2082 | static struct amba_driver pl08x_amba_driver = { |
2083 | .drv.name = DRIVER_NAME, | |
2084 | .id_table = pl08x_ids, | |
2085 | .probe = pl08x_probe, | |
2086 | }; | |
2087 | ||
2088 | static int __init pl08x_init(void) | |
2089 | { | |
2090 | int retval; | |
2091 | retval = amba_driver_register(&pl08x_amba_driver); | |
2092 | if (retval) | |
2093 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2094 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2095 | retval); |
2096 | return retval; | |
2097 | } | |
2098 | subsys_initcall(pl08x_init); |