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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
94ae8522 RKAL |
22 | * The full GNU General Public License is in this distribution in the file |
23 | * called COPYING. | |
e8689e63 LW |
24 | * |
25 | * Documentation: ARM DDI 0196G == PL080 | |
94ae8522 | 26 | * Documentation: ARM DDI 0218E == PL081 |
e8689e63 | 27 | * |
94ae8522 RKAL |
28 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
29 | * channel. | |
e8689e63 LW |
30 | * |
31 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
32 | * has only two channels. So on these DMA controllers the number of channels | |
33 | * and the number of incoming DMA signals are two totally different things. | |
34 | * It is usually not possible to theoretically handle all physical signals, | |
35 | * so a multiplexing scheme with possible denial of use is necessary. | |
36 | * | |
37 | * The PL080 has a dual bus master, PL081 has a single master. | |
38 | * | |
39 | * Memory to peripheral transfer may be visualized as | |
40 | * Get data from memory to DMAC | |
41 | * Until no data left | |
42 | * On burst request from peripheral | |
43 | * Destination burst from DMAC to peripheral | |
44 | * Clear burst request | |
45 | * Raise terminal count interrupt | |
46 | * | |
47 | * For peripherals with a FIFO: | |
48 | * Source burst size == half the depth of the peripheral FIFO | |
49 | * Destination burst size == the depth of the peripheral FIFO | |
50 | * | |
51 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
52 | * signals, the DMA controller will simply facilitate its AHB master.) | |
53 | * | |
54 | * ASSUMES default (little) endianness for DMA transfers | |
55 | * | |
9dc2c200 RKAL |
56 | * The PL08x has two flow control settings: |
57 | * - DMAC flow control: the transfer size defines the number of transfers | |
58 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
59 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
60 | * to both the BREQ and SREQ signals (contrary to documented), | |
61 | * transferring data if either is active. The LBREQ and LSREQ signals | |
62 | * are ignored. | |
63 | * | |
64 | * - Peripheral flow control: the transfer size is ignored (and should be | |
65 | * zero). The data is transferred from the current LLI entry, until | |
66 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
67 | * will then move to the next LLI entry. | |
68 | * | |
e8689e63 LW |
69 | * Global TODO: |
70 | * - Break out common code from arch/arm/mach-s3c64xx and share | |
71 | */ | |
730404ac | 72 | #include <linux/amba/bus.h> |
e8689e63 LW |
73 | #include <linux/amba/pl08x.h> |
74 | #include <linux/debugfs.h> | |
0c38d701 VK |
75 | #include <linux/delay.h> |
76 | #include <linux/device.h> | |
77 | #include <linux/dmaengine.h> | |
78 | #include <linux/dmapool.h> | |
8516f52f | 79 | #include <linux/dma-mapping.h> |
0c38d701 VK |
80 | #include <linux/init.h> |
81 | #include <linux/interrupt.h> | |
82 | #include <linux/module.h> | |
b7b6018b | 83 | #include <linux/pm_runtime.h> |
e8689e63 | 84 | #include <linux/seq_file.h> |
0c38d701 | 85 | #include <linux/slab.h> |
e8689e63 | 86 | #include <asm/hardware/pl080.h> |
e8689e63 LW |
87 | |
88 | #define DRIVER_NAME "pl08xdmac" | |
89 | ||
90 | /** | |
94ae8522 | 91 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
e8689e63 | 92 | * @channels: the number of channels available in this variant |
94ae8522 | 93 | * @dualmaster: whether this version supports dual AHB masters or not. |
e8689e63 LW |
94 | */ |
95 | struct vendor_data { | |
e8689e63 LW |
96 | u8 channels; |
97 | bool dualmaster; | |
98 | }; | |
99 | ||
100 | /* | |
101 | * PL08X private data structures | |
e8b5e11d | 102 | * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit, |
e25761d7 RKAL |
103 | * start & end do not - their bus bit info is in cctl. Also note that these |
104 | * are fixed 32-bit quantities. | |
e8689e63 | 105 | */ |
7cb72ad9 | 106 | struct pl08x_lli { |
e25761d7 RKAL |
107 | u32 src; |
108 | u32 dst; | |
bfddfb45 | 109 | u32 lli; |
e8689e63 LW |
110 | u32 cctl; |
111 | }; | |
112 | ||
113 | /** | |
114 | * struct pl08x_driver_data - the local state holder for the PL08x | |
115 | * @slave: slave engine for this instance | |
116 | * @memcpy: memcpy engine for this instance | |
117 | * @base: virtual memory base (remapped) for the PL08x | |
118 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
119 | * @vd: vendor data for this PL08x variant | |
120 | * @pd: platform data passed in from the platform/machine | |
121 | * @phy_chans: array of data for the physical channels | |
122 | * @pool: a pool for the LLI descriptors | |
123 | * @pool_ctr: counter of LLIs in the pool | |
3e27ee84 VK |
124 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
125 | * fetches | |
30749cb4 | 126 | * @mem_buses: set to indicate memory transfers on AHB2. |
e8689e63 LW |
127 | * @lock: a spinlock for this struct |
128 | */ | |
129 | struct pl08x_driver_data { | |
130 | struct dma_device slave; | |
131 | struct dma_device memcpy; | |
132 | void __iomem *base; | |
133 | struct amba_device *adev; | |
f96ca9ec | 134 | const struct vendor_data *vd; |
e8689e63 LW |
135 | struct pl08x_platform_data *pd; |
136 | struct pl08x_phy_chan *phy_chans; | |
137 | struct dma_pool *pool; | |
138 | int pool_ctr; | |
30749cb4 RKAL |
139 | u8 lli_buses; |
140 | u8 mem_buses; | |
e8689e63 LW |
141 | spinlock_t lock; |
142 | }; | |
143 | ||
144 | /* | |
145 | * PL08X specific defines | |
146 | */ | |
147 | ||
e8689e63 LW |
148 | /* Size (bytes) of each LLI buffer allocated for one transfer */ |
149 | # define PL08X_LLI_TSFR_SIZE 0x2000 | |
150 | ||
e8b5e11d | 151 | /* Maximum times we call dma_pool_alloc on this pool without freeing */ |
7cb72ad9 | 152 | #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli)) |
e8689e63 LW |
153 | #define PL08X_ALIGN 8 |
154 | ||
155 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
156 | { | |
157 | return container_of(chan, struct pl08x_dma_chan, chan); | |
158 | } | |
159 | ||
501e67e8 RKAL |
160 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
161 | { | |
162 | return container_of(tx, struct pl08x_txd, tx); | |
163 | } | |
164 | ||
e8689e63 LW |
165 | /* |
166 | * Physical channel handling | |
167 | */ | |
168 | ||
169 | /* Whether a certain channel is busy or not */ | |
170 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
171 | { | |
172 | unsigned int val; | |
173 | ||
174 | val = readl(ch->base + PL080_CH_CONFIG); | |
175 | return val & PL080_CONFIG_ACTIVE; | |
176 | } | |
177 | ||
178 | /* | |
179 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 180 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
181 | * been set when the LLIs were constructed. Poke them into the hardware |
182 | * and start the transfer. | |
e8689e63 | 183 | */ |
c885bee4 RKAL |
184 | static void pl08x_start_txd(struct pl08x_dma_chan *plchan, |
185 | struct pl08x_txd *txd) | |
e8689e63 | 186 | { |
c885bee4 | 187 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 188 | struct pl08x_phy_chan *phychan = plchan->phychan; |
19524d77 | 189 | struct pl08x_lli *lli = &txd->llis_va[0]; |
09b3c323 | 190 | u32 val; |
c885bee4 RKAL |
191 | |
192 | plchan->at = txd; | |
e8689e63 | 193 | |
c885bee4 RKAL |
194 | /* Wait for channel inactive */ |
195 | while (pl08x_phy_channel_busy(phychan)) | |
196 | cpu_relax(); | |
e8689e63 | 197 | |
c885bee4 RKAL |
198 | dev_vdbg(&pl08x->adev->dev, |
199 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
19524d77 RKAL |
200 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", |
201 | phychan->id, lli->src, lli->dst, lli->lli, lli->cctl, | |
09b3c323 | 202 | txd->ccfg); |
19524d77 RKAL |
203 | |
204 | writel(lli->src, phychan->base + PL080_CH_SRC_ADDR); | |
205 | writel(lli->dst, phychan->base + PL080_CH_DST_ADDR); | |
206 | writel(lli->lli, phychan->base + PL080_CH_LLI); | |
207 | writel(lli->cctl, phychan->base + PL080_CH_CONTROL); | |
09b3c323 | 208 | writel(txd->ccfg, phychan->base + PL080_CH_CONFIG); |
c885bee4 RKAL |
209 | |
210 | /* Enable the DMA channel */ | |
211 | /* Do not access config register until channel shows as disabled */ | |
212 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 213 | cpu_relax(); |
e8689e63 | 214 | |
c885bee4 RKAL |
215 | /* Do not access config register until channel shows as inactive */ |
216 | val = readl(phychan->base + PL080_CH_CONFIG); | |
e8689e63 | 217 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
c885bee4 | 218 | val = readl(phychan->base + PL080_CH_CONFIG); |
e8689e63 | 219 | |
c885bee4 | 220 | writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG); |
e8689e63 LW |
221 | } |
222 | ||
223 | /* | |
81796616 | 224 | * Pause the channel by setting the HALT bit. |
e8689e63 | 225 | * |
81796616 RKAL |
226 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
227 | * the FIFO can only drain if the peripheral is still requesting data. | |
228 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 229 | * |
81796616 RKAL |
230 | * For P->M transfers, disable the peripheral first to stop it filling |
231 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
232 | */ |
233 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
234 | { | |
235 | u32 val; | |
81796616 | 236 | int timeout; |
e8689e63 LW |
237 | |
238 | /* Set the HALT bit and wait for the FIFO to drain */ | |
239 | val = readl(ch->base + PL080_CH_CONFIG); | |
240 | val |= PL080_CONFIG_HALT; | |
241 | writel(val, ch->base + PL080_CH_CONFIG); | |
242 | ||
243 | /* Wait for channel inactive */ | |
81796616 RKAL |
244 | for (timeout = 1000; timeout; timeout--) { |
245 | if (!pl08x_phy_channel_busy(ch)) | |
246 | break; | |
247 | udelay(1); | |
248 | } | |
249 | if (pl08x_phy_channel_busy(ch)) | |
250 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
251 | } |
252 | ||
253 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
254 | { | |
255 | u32 val; | |
256 | ||
257 | /* Clear the HALT bit */ | |
258 | val = readl(ch->base + PL080_CH_CONFIG); | |
259 | val &= ~PL080_CONFIG_HALT; | |
260 | writel(val, ch->base + PL080_CH_CONFIG); | |
261 | } | |
262 | ||
fb526210 RKAL |
263 | /* |
264 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
265 | * clears any pending interrupt status. This should not be used for | |
266 | * an on-going transfer, but as a method of shutting down a channel | |
267 | * (eg, when it's no longer used) or terminating a transfer. | |
268 | */ | |
269 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
270 | struct pl08x_phy_chan *ch) | |
e8689e63 | 271 | { |
fb526210 | 272 | u32 val = readl(ch->base + PL080_CH_CONFIG); |
e8689e63 | 273 | |
fb526210 RKAL |
274 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
275 | PL080_CONFIG_TC_IRQ_MASK); | |
e8689e63 | 276 | |
e8689e63 | 277 | writel(val, ch->base + PL080_CH_CONFIG); |
fb526210 RKAL |
278 | |
279 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); | |
280 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
281 | } |
282 | ||
283 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
284 | { | |
285 | /* The source width defines the number of bytes */ | |
286 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
287 | ||
288 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
289 | case PL080_WIDTH_8BIT: | |
290 | break; | |
291 | case PL080_WIDTH_16BIT: | |
292 | bytes *= 2; | |
293 | break; | |
294 | case PL080_WIDTH_32BIT: | |
295 | bytes *= 4; | |
296 | break; | |
297 | } | |
298 | return bytes; | |
299 | } | |
300 | ||
301 | /* The channel should be paused when calling this */ | |
302 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
303 | { | |
304 | struct pl08x_phy_chan *ch; | |
e8689e63 LW |
305 | struct pl08x_txd *txd; |
306 | unsigned long flags; | |
cace6585 | 307 | size_t bytes = 0; |
e8689e63 LW |
308 | |
309 | spin_lock_irqsave(&plchan->lock, flags); | |
e8689e63 LW |
310 | ch = plchan->phychan; |
311 | txd = plchan->at; | |
312 | ||
313 | /* | |
db9f136a RKAL |
314 | * Follow the LLIs to get the number of remaining |
315 | * bytes in the currently active transaction. | |
e8689e63 LW |
316 | */ |
317 | if (ch && txd) { | |
4c0df6a3 | 318 | u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 319 | |
db9f136a | 320 | /* First get the remaining bytes in the active transfer */ |
e8689e63 LW |
321 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); |
322 | ||
323 | if (clli) { | |
db9f136a RKAL |
324 | struct pl08x_lli *llis_va = txd->llis_va; |
325 | dma_addr_t llis_bus = txd->llis_bus; | |
326 | int index; | |
327 | ||
328 | BUG_ON(clli < llis_bus || clli >= llis_bus + | |
329 | sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS); | |
e8689e63 | 330 | |
db9f136a RKAL |
331 | /* |
332 | * Locate the next LLI - as this is an array, | |
333 | * it's simple maths to find. | |
334 | */ | |
335 | index = (clli - llis_bus) / sizeof(struct pl08x_lli); | |
336 | ||
337 | for (; index < MAX_NUM_TSFR_LLIS; index++) { | |
338 | bytes += get_bytes_in_cctl(llis_va[index].cctl); | |
e8689e63 | 339 | |
e8689e63 | 340 | /* |
e8b5e11d | 341 | * A LLI pointer of 0 terminates the LLI list |
e8689e63 | 342 | */ |
db9f136a RKAL |
343 | if (!llis_va[index].lli) |
344 | break; | |
e8689e63 LW |
345 | } |
346 | } | |
347 | } | |
348 | ||
349 | /* Sum up all queued transactions */ | |
15c17232 | 350 | if (!list_empty(&plchan->pend_list)) { |
db9f136a | 351 | struct pl08x_txd *txdi; |
15c17232 | 352 | list_for_each_entry(txdi, &plchan->pend_list, node) { |
e8689e63 LW |
353 | bytes += txdi->len; |
354 | } | |
e8689e63 LW |
355 | } |
356 | ||
357 | spin_unlock_irqrestore(&plchan->lock, flags); | |
358 | ||
359 | return bytes; | |
360 | } | |
361 | ||
362 | /* | |
363 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
364 | * |
365 | * Try to locate a physical channel to be used for this transfer. If all | |
366 | * are taken return NULL and the requester will have to cope by using | |
367 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
368 | */ |
369 | static struct pl08x_phy_chan * | |
370 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
371 | struct pl08x_dma_chan *virt_chan) | |
372 | { | |
373 | struct pl08x_phy_chan *ch = NULL; | |
374 | unsigned long flags; | |
375 | int i; | |
376 | ||
e8689e63 LW |
377 | for (i = 0; i < pl08x->vd->channels; i++) { |
378 | ch = &pl08x->phy_chans[i]; | |
379 | ||
380 | spin_lock_irqsave(&ch->lock, flags); | |
381 | ||
382 | if (!ch->serving) { | |
383 | ch->serving = virt_chan; | |
384 | ch->signal = -1; | |
385 | spin_unlock_irqrestore(&ch->lock, flags); | |
386 | break; | |
387 | } | |
388 | ||
389 | spin_unlock_irqrestore(&ch->lock, flags); | |
390 | } | |
391 | ||
392 | if (i == pl08x->vd->channels) { | |
393 | /* No physical channel available, cope with it */ | |
394 | return NULL; | |
395 | } | |
396 | ||
b7b6018b | 397 | pm_runtime_get_sync(&pl08x->adev->dev); |
e8689e63 LW |
398 | return ch; |
399 | } | |
400 | ||
401 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, | |
402 | struct pl08x_phy_chan *ch) | |
403 | { | |
404 | unsigned long flags; | |
405 | ||
fb526210 RKAL |
406 | spin_lock_irqsave(&ch->lock, flags); |
407 | ||
e8689e63 | 408 | /* Stop the channel and clear its interrupts */ |
fb526210 | 409 | pl08x_terminate_phy_chan(pl08x, ch); |
e8689e63 | 410 | |
b7b6018b VK |
411 | pm_runtime_put(&pl08x->adev->dev); |
412 | ||
e8689e63 | 413 | /* Mark it as free */ |
e8689e63 LW |
414 | ch->serving = NULL; |
415 | spin_unlock_irqrestore(&ch->lock, flags); | |
416 | } | |
417 | ||
418 | /* | |
419 | * LLI handling | |
420 | */ | |
421 | ||
422 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
423 | { | |
424 | switch (coded) { | |
425 | case PL080_WIDTH_8BIT: | |
426 | return 1; | |
427 | case PL080_WIDTH_16BIT: | |
428 | return 2; | |
429 | case PL080_WIDTH_32BIT: | |
430 | return 4; | |
431 | default: | |
432 | break; | |
433 | } | |
434 | BUG(); | |
435 | return 0; | |
436 | } | |
437 | ||
438 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 439 | size_t tsize) |
e8689e63 LW |
440 | { |
441 | u32 retbits = cctl; | |
442 | ||
e8b5e11d | 443 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
444 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
445 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
446 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
447 | ||
448 | /* Then set the bits according to the parameters */ | |
449 | switch (srcwidth) { | |
450 | case 1: | |
451 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
452 | break; | |
453 | case 2: | |
454 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
455 | break; | |
456 | case 4: | |
457 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
458 | break; | |
459 | default: | |
460 | BUG(); | |
461 | break; | |
462 | } | |
463 | ||
464 | switch (dstwidth) { | |
465 | case 1: | |
466 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
467 | break; | |
468 | case 2: | |
469 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
470 | break; | |
471 | case 4: | |
472 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
473 | break; | |
474 | default: | |
475 | BUG(); | |
476 | break; | |
477 | } | |
478 | ||
479 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
480 | return retbits; | |
481 | } | |
482 | ||
542361f8 RKAL |
483 | struct pl08x_lli_build_data { |
484 | struct pl08x_txd *txd; | |
542361f8 RKAL |
485 | struct pl08x_bus_data srcbus; |
486 | struct pl08x_bus_data dstbus; | |
487 | size_t remainder; | |
25c94f7f | 488 | u32 lli_bus; |
542361f8 RKAL |
489 | }; |
490 | ||
e8689e63 | 491 | /* |
0532e6fc VK |
492 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
493 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
494 | * masters address with width requirements of transfer (by sending few byte by | |
495 | * byte data), slave is still not aligned, then its width will be reduced to | |
496 | * BYTE. | |
497 | * - prefers the destination bus if both available | |
036f05fd | 498 | * - prefers bus with fixed address (i.e. peripheral) |
e8689e63 | 499 | */ |
542361f8 RKAL |
500 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
501 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) | |
e8689e63 LW |
502 | { |
503 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
542361f8 RKAL |
504 | *mbus = &bd->dstbus; |
505 | *sbus = &bd->srcbus; | |
036f05fd VK |
506 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
507 | *mbus = &bd->srcbus; | |
508 | *sbus = &bd->dstbus; | |
e8689e63 | 509 | } else { |
036f05fd | 510 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
542361f8 RKAL |
511 | *mbus = &bd->dstbus; |
512 | *sbus = &bd->srcbus; | |
036f05fd | 513 | } else { |
542361f8 RKAL |
514 | *mbus = &bd->srcbus; |
515 | *sbus = &bd->dstbus; | |
e8689e63 LW |
516 | } |
517 | } | |
518 | } | |
519 | ||
520 | /* | |
94ae8522 | 521 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 522 | */ |
542361f8 RKAL |
523 | static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd, |
524 | int num_llis, int len, u32 cctl) | |
e8689e63 | 525 | { |
542361f8 RKAL |
526 | struct pl08x_lli *llis_va = bd->txd->llis_va; |
527 | dma_addr_t llis_bus = bd->txd->llis_bus; | |
e8689e63 LW |
528 | |
529 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
530 | ||
30749cb4 | 531 | llis_va[num_llis].cctl = cctl; |
542361f8 RKAL |
532 | llis_va[num_llis].src = bd->srcbus.addr; |
533 | llis_va[num_llis].dst = bd->dstbus.addr; | |
3e27ee84 VK |
534 | llis_va[num_llis].lli = llis_bus + (num_llis + 1) * |
535 | sizeof(struct pl08x_lli); | |
25c94f7f | 536 | llis_va[num_llis].lli |= bd->lli_bus; |
e8689e63 LW |
537 | |
538 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 | 539 | bd->srcbus.addr += len; |
e8689e63 | 540 | if (cctl & PL080_CONTROL_DST_INCR) |
542361f8 | 541 | bd->dstbus.addr += len; |
e8689e63 | 542 | |
542361f8 | 543 | BUG_ON(bd->remainder < len); |
cace6585 | 544 | |
542361f8 | 545 | bd->remainder -= len; |
e8689e63 LW |
546 | } |
547 | ||
03af500f VK |
548 | static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd, |
549 | u32 *cctl, u32 len, int num_llis, size_t *total_bytes) | |
e8689e63 | 550 | { |
03af500f VK |
551 | *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); |
552 | pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl); | |
553 | (*total_bytes) += len; | |
e8689e63 LW |
554 | } |
555 | ||
556 | /* | |
557 | * This fills in the table of LLIs for the transfer descriptor | |
558 | * Note that we assume we never have to change the burst sizes | |
559 | * Return 0 for error | |
560 | */ | |
561 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
562 | struct pl08x_txd *txd) | |
563 | { | |
e8689e63 | 564 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 565 | struct pl08x_lli_build_data bd; |
e8689e63 | 566 | int num_llis = 0; |
03af500f | 567 | u32 cctl, early_bytes = 0; |
3e27ee84 | 568 | size_t max_bytes_per_lli, total_bytes = 0; |
7cb72ad9 | 569 | struct pl08x_lli *llis_va; |
e8689e63 | 570 | |
3e27ee84 | 571 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
572 | if (!txd->llis_va) { |
573 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
574 | return 0; | |
575 | } | |
576 | ||
577 | pl08x->pool_ctr++; | |
578 | ||
70b5ed6b RKAL |
579 | /* Get the default CCTL */ |
580 | cctl = txd->cctl; | |
e8689e63 | 581 | |
542361f8 | 582 | bd.txd = txd; |
d7244e9a RKAL |
583 | bd.srcbus.addr = txd->src_addr; |
584 | bd.dstbus.addr = txd->dst_addr; | |
25c94f7f | 585 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
542361f8 | 586 | |
e8689e63 | 587 | /* Find maximum width of the source bus */ |
542361f8 | 588 | bd.srcbus.maxwidth = |
e8689e63 LW |
589 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
590 | PL080_CONTROL_SWIDTH_SHIFT); | |
591 | ||
592 | /* Find maximum width of the destination bus */ | |
542361f8 | 593 | bd.dstbus.maxwidth = |
e8689e63 LW |
594 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
595 | PL080_CONTROL_DWIDTH_SHIFT); | |
596 | ||
597 | /* Set up the bus widths to the maximum */ | |
542361f8 RKAL |
598 | bd.srcbus.buswidth = bd.srcbus.maxwidth; |
599 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 | 600 | |
e8689e63 | 601 | /* We need to count this down to zero */ |
542361f8 | 602 | bd.remainder = txd->len; |
e8689e63 | 603 | |
542361f8 | 604 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
e8689e63 | 605 | |
fa6a940b | 606 | dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n", |
fc74eb79 RKAL |
607 | bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", |
608 | bd.srcbus.buswidth, | |
609 | bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
610 | bd.dstbus.buswidth, | |
fa6a940b | 611 | bd.remainder); |
fc74eb79 RKAL |
612 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", |
613 | mbus == &bd.srcbus ? "src" : "dst", | |
614 | sbus == &bd.srcbus ? "src" : "dst"); | |
615 | ||
0a235657 VK |
616 | /* |
617 | * Zero length is only allowed if all these requirements are met: | |
618 | * - flow controller is peripheral. | |
619 | * - src.addr is aligned to src.width | |
620 | * - dst.addr is aligned to dst.width | |
621 | * | |
622 | * sg_len == 1 should be true, as there can be two cases here: | |
623 | * - Memory addresses are contiguous and are not scattered. Here, Only | |
624 | * one sg will be passed by user driver, with memory address and zero | |
625 | * length. We pass this to controller and after the transfer it will | |
626 | * receive the last burst request from peripheral and so transfer | |
627 | * finishes. | |
628 | * | |
629 | * - Memory addresses are scattered and are not contiguous. Here, | |
630 | * Obviously as DMA controller doesn't know when a lli's transfer gets | |
631 | * over, it can't load next lli. So in this case, there has to be an | |
632 | * assumption that only one lli is supported. Thus, we can't have | |
633 | * scattered addresses. | |
634 | */ | |
635 | if (!bd.remainder) { | |
636 | u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> | |
637 | PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
638 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && | |
639 | (fc <= PL080_FLOW_SRC2DST_SRC))) { | |
640 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", | |
641 | __func__); | |
642 | return 0; | |
e8689e63 | 643 | } |
0a235657 VK |
644 | |
645 | if ((bd.srcbus.addr % bd.srcbus.buswidth) || | |
646 | (bd.srcbus.addr % bd.srcbus.buswidth)) { | |
647 | dev_err(&pl08x->adev->dev, | |
648 | "%s src & dst address must be aligned to src" | |
649 | " & dst width if peripheral is flow controller", | |
650 | __func__); | |
651 | return 0; | |
e8689e63 LW |
652 | } |
653 | ||
0a235657 VK |
654 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
655 | bd.dstbus.buswidth, 0); | |
656 | pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl); | |
657 | } | |
658 | ||
03af500f VK |
659 | /* |
660 | * Send byte by byte for following cases | |
661 | * - Less than a bus width available | |
662 | * - until master bus is aligned | |
663 | */ | |
664 | if (bd.remainder < mbus->buswidth) | |
665 | early_bytes = bd.remainder; | |
666 | else if ((mbus->addr) % (mbus->buswidth)) { | |
667 | early_bytes = mbus->buswidth - (mbus->addr) % (mbus->buswidth); | |
668 | if ((bd.remainder - early_bytes) < mbus->buswidth) | |
669 | early_bytes = bd.remainder; | |
670 | } | |
671 | ||
672 | if (early_bytes) { | |
673 | dev_vdbg(&pl08x->adev->dev, "%s byte width LLIs " | |
674 | "(remain 0x%08x)\n", __func__, bd.remainder); | |
675 | prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++, | |
676 | &total_bytes); | |
677 | } | |
e8689e63 | 678 | |
03af500f | 679 | if (bd.remainder) { |
e8689e63 | 680 | /* |
94ae8522 | 681 | * Master now aligned |
e8689e63 LW |
682 | * - if slave is not then we must set its width down |
683 | */ | |
684 | if (sbus->addr % sbus->buswidth) { | |
685 | dev_dbg(&pl08x->adev->dev, | |
686 | "%s set down bus width to one byte\n", | |
687 | __func__); | |
688 | ||
689 | sbus->buswidth = 1; | |
690 | } | |
691 | ||
fa6a940b VK |
692 | /* Bytes transferred = tsize * src width, not MIN(buswidths) */ |
693 | max_bytes_per_lli = bd.srcbus.buswidth * | |
694 | PL080_CONTROL_TRANSFER_SIZE_MASK; | |
695 | ||
e8689e63 LW |
696 | /* |
697 | * Make largest possible LLIs until less than one bus | |
698 | * width left | |
699 | */ | |
542361f8 | 700 | while (bd.remainder > (mbus->buswidth - 1)) { |
e0719165 | 701 | size_t lli_len, tsize, width; |
e8689e63 LW |
702 | |
703 | /* | |
704 | * If enough left try to send max possible, | |
705 | * otherwise try to send the remainder | |
706 | */ | |
16a2e7d3 | 707 | lli_len = min(bd.remainder, max_bytes_per_lli); |
e8689e63 LW |
708 | |
709 | /* | |
e0719165 | 710 | * Check against maximum bus alignment: Calculate actual |
16a2e7d3 | 711 | * transfer size in relation to bus width and get a |
e0719165 | 712 | * maximum remainder of the highest bus width - 1 |
e8689e63 | 713 | */ |
e0719165 VK |
714 | width = max(mbus->buswidth, sbus->buswidth); |
715 | lli_len = (lli_len / width) * width; | |
716 | tsize = lli_len / bd.srcbus.buswidth; | |
e8689e63 | 717 | |
16a2e7d3 VK |
718 | dev_vdbg(&pl08x->adev->dev, |
719 | "%s fill lli with single lli chunk of " | |
720 | "size 0x%08zx (remainder 0x%08zx)\n", | |
721 | __func__, lli_len, bd.remainder); | |
722 | ||
723 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, | |
724 | bd.dstbus.buswidth, tsize); | |
725 | pl08x_fill_lli_for_desc(&bd, num_llis++, lli_len, cctl); | |
726 | total_bytes += lli_len; | |
e8689e63 LW |
727 | } |
728 | ||
729 | /* | |
730 | * Send any odd bytes | |
731 | */ | |
03af500f | 732 | if (bd.remainder) { |
e8689e63 | 733 | dev_vdbg(&pl08x->adev->dev, |
03af500f | 734 | "%s align with boundary, send odd bytes (remain %zu)\n", |
542361f8 | 735 | __func__, bd.remainder); |
03af500f VK |
736 | prep_byte_width_lli(&bd, &cctl, bd.remainder, |
737 | num_llis++, &total_bytes); | |
e8689e63 LW |
738 | } |
739 | } | |
16a2e7d3 | 740 | |
e8689e63 LW |
741 | if (total_bytes != txd->len) { |
742 | dev_err(&pl08x->adev->dev, | |
cace6585 | 743 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", |
e8689e63 LW |
744 | __func__, total_bytes, txd->len); |
745 | return 0; | |
746 | } | |
747 | ||
748 | if (num_llis >= MAX_NUM_TSFR_LLIS) { | |
749 | dev_err(&pl08x->adev->dev, | |
750 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
751 | __func__, (u32) MAX_NUM_TSFR_LLIS); | |
752 | return 0; | |
753 | } | |
b58b6b5b RKAL |
754 | |
755 | llis_va = txd->llis_va; | |
94ae8522 | 756 | /* The final LLI terminates the LLI. */ |
bfddfb45 | 757 | llis_va[num_llis - 1].lli = 0; |
94ae8522 | 758 | /* The final LLI element shall also fire an interrupt. */ |
b58b6b5b | 759 | llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN; |
e8689e63 | 760 | |
e8689e63 LW |
761 | #ifdef VERBOSE_DEBUG |
762 | { | |
763 | int i; | |
764 | ||
fc74eb79 RKAL |
765 | dev_vdbg(&pl08x->adev->dev, |
766 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
767 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
e8689e63 LW |
768 | for (i = 0; i < num_llis; i++) { |
769 | dev_vdbg(&pl08x->adev->dev, | |
fc74eb79 RKAL |
770 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
771 | i, &llis_va[i], llis_va[i].src, | |
772 | llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl | |
e8689e63 LW |
773 | ); |
774 | } | |
775 | } | |
776 | #endif | |
777 | ||
778 | return num_llis; | |
779 | } | |
780 | ||
781 | /* You should call this with the struct pl08x lock held */ | |
782 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, | |
783 | struct pl08x_txd *txd) | |
784 | { | |
e8689e63 | 785 | /* Free the LLI */ |
56b61882 | 786 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); |
e8689e63 LW |
787 | |
788 | pl08x->pool_ctr--; | |
789 | ||
790 | kfree(txd); | |
791 | } | |
792 | ||
793 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, | |
794 | struct pl08x_dma_chan *plchan) | |
795 | { | |
796 | struct pl08x_txd *txdi = NULL; | |
797 | struct pl08x_txd *next; | |
798 | ||
15c17232 | 799 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 | 800 | list_for_each_entry_safe(txdi, |
15c17232 | 801 | next, &plchan->pend_list, node) { |
e8689e63 LW |
802 | list_del(&txdi->node); |
803 | pl08x_free_txd(pl08x, txdi); | |
804 | } | |
e8689e63 LW |
805 | } |
806 | } | |
807 | ||
808 | /* | |
809 | * The DMA ENGINE API | |
810 | */ | |
811 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
812 | { | |
813 | return 0; | |
814 | } | |
815 | ||
816 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
817 | { | |
818 | } | |
819 | ||
820 | /* | |
821 | * This should be called with the channel plchan->lock held | |
822 | */ | |
823 | static int prep_phy_channel(struct pl08x_dma_chan *plchan, | |
824 | struct pl08x_txd *txd) | |
825 | { | |
826 | struct pl08x_driver_data *pl08x = plchan->host; | |
827 | struct pl08x_phy_chan *ch; | |
828 | int ret; | |
829 | ||
830 | /* Check if we already have a channel */ | |
831 | if (plchan->phychan) | |
832 | return 0; | |
833 | ||
834 | ch = pl08x_get_phy_channel(pl08x, plchan); | |
835 | if (!ch) { | |
836 | /* No physical channel available, cope with it */ | |
837 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
838 | return -EBUSY; | |
839 | } | |
840 | ||
841 | /* | |
842 | * OK we have a physical channel: for memcpy() this is all we | |
843 | * need, but for slaves the physical signals may be muxed! | |
844 | * Can the platform allow us to use this channel? | |
845 | */ | |
16ca8105 | 846 | if (plchan->slave && pl08x->pd->get_signal) { |
e8689e63 LW |
847 | ret = pl08x->pd->get_signal(plchan); |
848 | if (ret < 0) { | |
849 | dev_dbg(&pl08x->adev->dev, | |
850 | "unable to use physical channel %d for transfer on %s due to platform restrictions\n", | |
851 | ch->id, plchan->name); | |
852 | /* Release physical channel & return */ | |
853 | pl08x_put_phy_channel(pl08x, ch); | |
854 | return -EBUSY; | |
855 | } | |
856 | ch->signal = ret; | |
09b3c323 RKAL |
857 | |
858 | /* Assign the flow control signal to this channel */ | |
859 | if (txd->direction == DMA_TO_DEVICE) | |
860 | txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
861 | else if (txd->direction == DMA_FROM_DEVICE) | |
862 | txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
e8689e63 LW |
863 | } |
864 | ||
865 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n", | |
866 | ch->id, | |
867 | ch->signal, | |
868 | plchan->name); | |
869 | ||
8087aacd | 870 | plchan->phychan_hold++; |
e8689e63 LW |
871 | plchan->phychan = ch; |
872 | ||
873 | return 0; | |
874 | } | |
875 | ||
8c8cc2b1 RKAL |
876 | static void release_phy_channel(struct pl08x_dma_chan *plchan) |
877 | { | |
878 | struct pl08x_driver_data *pl08x = plchan->host; | |
879 | ||
880 | if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) { | |
881 | pl08x->pd->put_signal(plchan); | |
882 | plchan->phychan->signal = -1; | |
883 | } | |
884 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
885 | plchan->phychan = NULL; | |
886 | } | |
887 | ||
e8689e63 LW |
888 | static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) |
889 | { | |
890 | struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan); | |
501e67e8 | 891 | struct pl08x_txd *txd = to_pl08x_txd(tx); |
c370e594 RKAL |
892 | unsigned long flags; |
893 | ||
894 | spin_lock_irqsave(&plchan->lock, flags); | |
e8689e63 | 895 | |
91aa5fad RKAL |
896 | plchan->chan.cookie += 1; |
897 | if (plchan->chan.cookie < 0) | |
898 | plchan->chan.cookie = 1; | |
899 | tx->cookie = plchan->chan.cookie; | |
501e67e8 RKAL |
900 | |
901 | /* Put this onto the pending list */ | |
902 | list_add_tail(&txd->node, &plchan->pend_list); | |
903 | ||
904 | /* | |
905 | * If there was no physical channel available for this memcpy, | |
906 | * stack the request up and indicate that the channel is waiting | |
907 | * for a free physical channel. | |
908 | */ | |
909 | if (!plchan->slave && !plchan->phychan) { | |
910 | /* Do this memcpy whenever there is a channel ready */ | |
911 | plchan->state = PL08X_CHAN_WAITING; | |
912 | plchan->waiting = txd; | |
8087aacd RKAL |
913 | } else { |
914 | plchan->phychan_hold--; | |
501e67e8 RKAL |
915 | } |
916 | ||
c370e594 | 917 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 LW |
918 | |
919 | return tx->cookie; | |
920 | } | |
921 | ||
922 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( | |
923 | struct dma_chan *chan, unsigned long flags) | |
924 | { | |
925 | struct dma_async_tx_descriptor *retval = NULL; | |
926 | ||
927 | return retval; | |
928 | } | |
929 | ||
930 | /* | |
94ae8522 RKAL |
931 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
932 | * If slaves are relying on interrupts to signal completion this function | |
933 | * must not be called with interrupts disabled. | |
e8689e63 | 934 | */ |
3e27ee84 VK |
935 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
936 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
937 | { |
938 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
939 | dma_cookie_t last_used; | |
940 | dma_cookie_t last_complete; | |
941 | enum dma_status ret; | |
942 | u32 bytesleft = 0; | |
943 | ||
91aa5fad | 944 | last_used = plchan->chan.cookie; |
e8689e63 LW |
945 | last_complete = plchan->lc; |
946 | ||
947 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
948 | if (ret == DMA_SUCCESS) { | |
949 | dma_set_tx_state(txstate, last_complete, last_used, 0); | |
950 | return ret; | |
951 | } | |
952 | ||
e8689e63 LW |
953 | /* |
954 | * This cookie not complete yet | |
955 | */ | |
91aa5fad | 956 | last_used = plchan->chan.cookie; |
e8689e63 LW |
957 | last_complete = plchan->lc; |
958 | ||
959 | /* Get number of bytes left in the active transactions and queue */ | |
960 | bytesleft = pl08x_getbytes_chan(plchan); | |
961 | ||
962 | dma_set_tx_state(txstate, last_complete, last_used, | |
963 | bytesleft); | |
964 | ||
965 | if (plchan->state == PL08X_CHAN_PAUSED) | |
966 | return DMA_PAUSED; | |
967 | ||
968 | /* Whether waiting or running, we're in progress */ | |
969 | return DMA_IN_PROGRESS; | |
970 | } | |
971 | ||
972 | /* PrimeCell DMA extension */ | |
973 | struct burst_table { | |
760596c6 | 974 | u32 burstwords; |
e8689e63 LW |
975 | u32 reg; |
976 | }; | |
977 | ||
978 | static const struct burst_table burst_sizes[] = { | |
979 | { | |
980 | .burstwords = 256, | |
760596c6 | 981 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
982 | }, |
983 | { | |
984 | .burstwords = 128, | |
760596c6 | 985 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
986 | }, |
987 | { | |
988 | .burstwords = 64, | |
760596c6 | 989 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
990 | }, |
991 | { | |
992 | .burstwords = 32, | |
760596c6 | 993 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
994 | }, |
995 | { | |
996 | .burstwords = 16, | |
760596c6 | 997 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
998 | }, |
999 | { | |
1000 | .burstwords = 8, | |
760596c6 | 1001 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1002 | }, |
1003 | { | |
1004 | .burstwords = 4, | |
760596c6 | 1005 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1006 | }, |
1007 | { | |
760596c6 RKAL |
1008 | .burstwords = 0, |
1009 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1010 | }, |
1011 | }; | |
1012 | ||
121c8476 RKAL |
1013 | /* |
1014 | * Given the source and destination available bus masks, select which | |
1015 | * will be routed to each port. We try to have source and destination | |
1016 | * on separate ports, but always respect the allowable settings. | |
1017 | */ | |
1018 | static u32 pl08x_select_bus(u8 src, u8 dst) | |
1019 | { | |
1020 | u32 cctl = 0; | |
1021 | ||
1022 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1023 | cctl |= PL080_CONTROL_DST_AHB2; | |
1024 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1025 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1026 | ||
1027 | return cctl; | |
1028 | } | |
1029 | ||
f14c426c RKAL |
1030 | static u32 pl08x_cctl(u32 cctl) |
1031 | { | |
1032 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1033 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1034 | PL080_CONTROL_PROT_MASK); | |
1035 | ||
1036 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1037 | return cctl | PL080_CONTROL_PROT_SYS; | |
1038 | } | |
1039 | ||
aa88cdaa RKAL |
1040 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1041 | { | |
1042 | switch (width) { | |
1043 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1044 | return PL080_WIDTH_8BIT; | |
1045 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1046 | return PL080_WIDTH_16BIT; | |
1047 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1048 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1049 | default: |
1050 | return ~0; | |
aa88cdaa | 1051 | } |
aa88cdaa RKAL |
1052 | } |
1053 | ||
760596c6 RKAL |
1054 | static u32 pl08x_burst(u32 maxburst) |
1055 | { | |
1056 | int i; | |
1057 | ||
1058 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1059 | if (burst_sizes[i].burstwords <= maxburst) | |
1060 | break; | |
1061 | ||
1062 | return burst_sizes[i].reg; | |
1063 | } | |
1064 | ||
f0fd9446 RKAL |
1065 | static int dma_set_runtime_config(struct dma_chan *chan, |
1066 | struct dma_slave_config *config) | |
e8689e63 LW |
1067 | { |
1068 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1069 | struct pl08x_driver_data *pl08x = plchan->host; | |
e8689e63 | 1070 | enum dma_slave_buswidth addr_width; |
760596c6 | 1071 | u32 width, burst, maxburst; |
e8689e63 | 1072 | u32 cctl = 0; |
b7f75865 RKAL |
1073 | |
1074 | if (!plchan->slave) | |
1075 | return -EINVAL; | |
e8689e63 LW |
1076 | |
1077 | /* Transfer direction */ | |
1078 | plchan->runtime_direction = config->direction; | |
1079 | if (config->direction == DMA_TO_DEVICE) { | |
e8689e63 LW |
1080 | addr_width = config->dst_addr_width; |
1081 | maxburst = config->dst_maxburst; | |
1082 | } else if (config->direction == DMA_FROM_DEVICE) { | |
e8689e63 LW |
1083 | addr_width = config->src_addr_width; |
1084 | maxburst = config->src_maxburst; | |
1085 | } else { | |
1086 | dev_err(&pl08x->adev->dev, | |
1087 | "bad runtime_config: alien transfer direction\n"); | |
f0fd9446 | 1088 | return -EINVAL; |
e8689e63 LW |
1089 | } |
1090 | ||
aa88cdaa RKAL |
1091 | width = pl08x_width(addr_width); |
1092 | if (width == ~0) { | |
e8689e63 LW |
1093 | dev_err(&pl08x->adev->dev, |
1094 | "bad runtime_config: alien address width\n"); | |
f0fd9446 | 1095 | return -EINVAL; |
e8689e63 LW |
1096 | } |
1097 | ||
aa88cdaa RKAL |
1098 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; |
1099 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1100 | ||
e8689e63 | 1101 | /* |
4440aacf RKAL |
1102 | * If this channel will only request single transfers, set this |
1103 | * down to ONE element. Also select one element if no maxburst | |
1104 | * is specified. | |
e8689e63 | 1105 | */ |
760596c6 RKAL |
1106 | if (plchan->cd->single) |
1107 | maxburst = 1; | |
1108 | ||
1109 | burst = pl08x_burst(maxburst); | |
1110 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1111 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
e8689e63 | 1112 | |
b207b4d0 RKAL |
1113 | if (plchan->runtime_direction == DMA_FROM_DEVICE) { |
1114 | plchan->src_addr = config->src_addr; | |
121c8476 RKAL |
1115 | plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR | |
1116 | pl08x_select_bus(plchan->cd->periph_buses, | |
1117 | pl08x->mem_buses); | |
b207b4d0 RKAL |
1118 | } else { |
1119 | plchan->dst_addr = config->dst_addr; | |
121c8476 RKAL |
1120 | plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR | |
1121 | pl08x_select_bus(pl08x->mem_buses, | |
1122 | plchan->cd->periph_buses); | |
b207b4d0 | 1123 | } |
f0fd9446 | 1124 | |
e8689e63 LW |
1125 | dev_dbg(&pl08x->adev->dev, |
1126 | "configured channel %s (%s) for %s, data width %d, " | |
4983a04f | 1127 | "maxburst %d words, LE, CCTL=0x%08x\n", |
e8689e63 LW |
1128 | dma_chan_name(chan), plchan->name, |
1129 | (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", | |
1130 | addr_width, | |
1131 | maxburst, | |
4983a04f | 1132 | cctl); |
f0fd9446 RKAL |
1133 | |
1134 | return 0; | |
e8689e63 LW |
1135 | } |
1136 | ||
1137 | /* | |
1138 | * Slave transactions callback to the slave device to allow | |
1139 | * synchronization of slave DMA signals with the DMAC enable | |
1140 | */ | |
1141 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1142 | { | |
1143 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1144 | unsigned long flags; |
1145 | ||
1146 | spin_lock_irqsave(&plchan->lock, flags); | |
9c0bb43b RKAL |
1147 | /* Something is already active, or we're waiting for a channel... */ |
1148 | if (plchan->at || plchan->state == PL08X_CHAN_WAITING) { | |
1149 | spin_unlock_irqrestore(&plchan->lock, flags); | |
e8689e63 | 1150 | return; |
9c0bb43b | 1151 | } |
e8689e63 LW |
1152 | |
1153 | /* Take the first element in the queue and execute it */ | |
15c17232 | 1154 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 LW |
1155 | struct pl08x_txd *next; |
1156 | ||
15c17232 | 1157 | next = list_first_entry(&plchan->pend_list, |
e8689e63 LW |
1158 | struct pl08x_txd, |
1159 | node); | |
1160 | list_del(&next->node); | |
e8689e63 LW |
1161 | plchan->state = PL08X_CHAN_RUNNING; |
1162 | ||
c885bee4 | 1163 | pl08x_start_txd(plchan, next); |
e8689e63 LW |
1164 | } |
1165 | ||
1166 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1167 | } | |
1168 | ||
1169 | static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan, | |
1170 | struct pl08x_txd *txd) | |
1171 | { | |
e8689e63 | 1172 | struct pl08x_driver_data *pl08x = plchan->host; |
c370e594 RKAL |
1173 | unsigned long flags; |
1174 | int num_llis, ret; | |
e8689e63 LW |
1175 | |
1176 | num_llis = pl08x_fill_llis_for_desc(pl08x, txd); | |
dafa7317 | 1177 | if (!num_llis) { |
57001a60 VK |
1178 | spin_lock_irqsave(&plchan->lock, flags); |
1179 | pl08x_free_txd(pl08x, txd); | |
1180 | spin_unlock_irqrestore(&plchan->lock, flags); | |
e8689e63 | 1181 | return -EINVAL; |
dafa7317 | 1182 | } |
e8689e63 | 1183 | |
c370e594 | 1184 | spin_lock_irqsave(&plchan->lock, flags); |
e8689e63 | 1185 | |
e8689e63 LW |
1186 | /* |
1187 | * See if we already have a physical channel allocated, | |
1188 | * else this is the time to try to get one. | |
1189 | */ | |
1190 | ret = prep_phy_channel(plchan, txd); | |
1191 | if (ret) { | |
1192 | /* | |
501e67e8 RKAL |
1193 | * No physical channel was available. |
1194 | * | |
1195 | * memcpy transfers can be sorted out at submission time. | |
1196 | * | |
1197 | * Slave transfers may have been denied due to platform | |
1198 | * channel muxing restrictions. Since there is no guarantee | |
1199 | * that this will ever be resolved, and the signal must be | |
1200 | * acquired AFTER acquiring the physical channel, we will let | |
1201 | * them be NACK:ed with -EBUSY here. The drivers can retry | |
1202 | * the prep() call if they are eager on doing this using DMA. | |
e8689e63 LW |
1203 | */ |
1204 | if (plchan->slave) { | |
1205 | pl08x_free_txd_list(pl08x, plchan); | |
501e67e8 | 1206 | pl08x_free_txd(pl08x, txd); |
c370e594 | 1207 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 LW |
1208 | return -EBUSY; |
1209 | } | |
e8689e63 LW |
1210 | } else |
1211 | /* | |
94ae8522 RKAL |
1212 | * Else we're all set, paused and ready to roll, status |
1213 | * will switch to PL08X_CHAN_RUNNING when we call | |
1214 | * issue_pending(). If there is something running on the | |
1215 | * channel already we don't change its state. | |
e8689e63 LW |
1216 | */ |
1217 | if (plchan->state == PL08X_CHAN_IDLE) | |
1218 | plchan->state = PL08X_CHAN_PAUSED; | |
1219 | ||
c370e594 | 1220 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 LW |
1221 | |
1222 | return 0; | |
1223 | } | |
1224 | ||
c0428794 RKAL |
1225 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan, |
1226 | unsigned long flags) | |
ac3cd20d | 1227 | { |
b201c111 | 1228 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d RKAL |
1229 | |
1230 | if (txd) { | |
1231 | dma_async_tx_descriptor_init(&txd->tx, &plchan->chan); | |
c0428794 | 1232 | txd->tx.flags = flags; |
ac3cd20d RKAL |
1233 | txd->tx.tx_submit = pl08x_tx_submit; |
1234 | INIT_LIST_HEAD(&txd->node); | |
4983a04f RKAL |
1235 | |
1236 | /* Always enable error and terminal interrupts */ | |
1237 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1238 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1239 | } |
1240 | return txd; | |
1241 | } | |
1242 | ||
e8689e63 LW |
1243 | /* |
1244 | * Initialize a descriptor to be used by memcpy submit | |
1245 | */ | |
1246 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1247 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1248 | size_t len, unsigned long flags) | |
1249 | { | |
1250 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1251 | struct pl08x_driver_data *pl08x = plchan->host; | |
1252 | struct pl08x_txd *txd; | |
1253 | int ret; | |
1254 | ||
c0428794 | 1255 | txd = pl08x_get_txd(plchan, flags); |
e8689e63 LW |
1256 | if (!txd) { |
1257 | dev_err(&pl08x->adev->dev, | |
1258 | "%s no memory for descriptor\n", __func__); | |
1259 | return NULL; | |
1260 | } | |
1261 | ||
e8689e63 | 1262 | txd->direction = DMA_NONE; |
d7244e9a RKAL |
1263 | txd->src_addr = src; |
1264 | txd->dst_addr = dest; | |
c7da9a56 | 1265 | txd->len = len; |
e8689e63 LW |
1266 | |
1267 | /* Set platform data for m2m */ | |
4983a04f | 1268 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
c7da9a56 RKAL |
1269 | txd->cctl = pl08x->pd->memcpy_channel.cctl & |
1270 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); | |
4983a04f | 1271 | |
e8689e63 | 1272 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1273 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1274 | |
c7da9a56 | 1275 | if (pl08x->vd->dualmaster) |
121c8476 RKAL |
1276 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
1277 | pl08x->mem_buses); | |
e8689e63 | 1278 | |
e8689e63 LW |
1279 | ret = pl08x_prep_channel_resources(plchan, txd); |
1280 | if (ret) | |
1281 | return NULL; | |
e8689e63 LW |
1282 | |
1283 | return &txd->tx; | |
1284 | } | |
1285 | ||
3e2a037c | 1286 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 LW |
1287 | struct dma_chan *chan, struct scatterlist *sgl, |
1288 | unsigned int sg_len, enum dma_data_direction direction, | |
1289 | unsigned long flags) | |
1290 | { | |
1291 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1292 | struct pl08x_driver_data *pl08x = plchan->host; | |
1293 | struct pl08x_txd *txd; | |
0a235657 | 1294 | int ret, tmp; |
e8689e63 LW |
1295 | |
1296 | /* | |
1297 | * Current implementation ASSUMES only one sg | |
1298 | */ | |
1299 | if (sg_len != 1) { | |
1300 | dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n", | |
1301 | __func__); | |
1302 | BUG(); | |
1303 | } | |
1304 | ||
1305 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", | |
1306 | __func__, sgl->length, plchan->name); | |
1307 | ||
c0428794 | 1308 | txd = pl08x_get_txd(plchan, flags); |
e8689e63 LW |
1309 | if (!txd) { |
1310 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1311 | return NULL; | |
1312 | } | |
1313 | ||
e8689e63 LW |
1314 | if (direction != plchan->runtime_direction) |
1315 | dev_err(&pl08x->adev->dev, "%s DMA setup does not match " | |
1316 | "the direction configured for the PrimeCell\n", | |
1317 | __func__); | |
1318 | ||
1319 | /* | |
1320 | * Set up addresses, the PrimeCell configured address | |
1321 | * will take precedence since this may configure the | |
1322 | * channel target address dynamically at runtime. | |
1323 | */ | |
1324 | txd->direction = direction; | |
c7da9a56 RKAL |
1325 | txd->len = sgl->length; |
1326 | ||
e8689e63 | 1327 | if (direction == DMA_TO_DEVICE) { |
121c8476 | 1328 | txd->cctl = plchan->dst_cctl; |
d7244e9a | 1329 | txd->src_addr = sgl->dma_address; |
b207b4d0 | 1330 | txd->dst_addr = plchan->dst_addr; |
e8689e63 | 1331 | } else if (direction == DMA_FROM_DEVICE) { |
121c8476 | 1332 | txd->cctl = plchan->src_cctl; |
b207b4d0 | 1333 | txd->src_addr = plchan->src_addr; |
d7244e9a | 1334 | txd->dst_addr = sgl->dma_address; |
e8689e63 LW |
1335 | } else { |
1336 | dev_err(&pl08x->adev->dev, | |
1337 | "%s direction unsupported\n", __func__); | |
1338 | return NULL; | |
1339 | } | |
e8689e63 | 1340 | |
0a235657 VK |
1341 | if (plchan->cd->device_fc) |
1342 | tmp = (direction == DMA_TO_DEVICE) ? PL080_FLOW_MEM2PER_PER : | |
1343 | PL080_FLOW_PER2MEM_PER; | |
1344 | else | |
1345 | tmp = (direction == DMA_TO_DEVICE) ? PL080_FLOW_MEM2PER : | |
1346 | PL080_FLOW_PER2MEM; | |
1347 | ||
1348 | txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1349 | ||
e8689e63 LW |
1350 | ret = pl08x_prep_channel_resources(plchan, txd); |
1351 | if (ret) | |
1352 | return NULL; | |
e8689e63 LW |
1353 | |
1354 | return &txd->tx; | |
1355 | } | |
1356 | ||
1357 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1358 | unsigned long arg) | |
1359 | { | |
1360 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1361 | struct pl08x_driver_data *pl08x = plchan->host; | |
1362 | unsigned long flags; | |
1363 | int ret = 0; | |
1364 | ||
1365 | /* Controls applicable to inactive channels */ | |
1366 | if (cmd == DMA_SLAVE_CONFIG) { | |
f0fd9446 RKAL |
1367 | return dma_set_runtime_config(chan, |
1368 | (struct dma_slave_config *)arg); | |
e8689e63 LW |
1369 | } |
1370 | ||
1371 | /* | |
1372 | * Anything succeeds on channels with no physical allocation and | |
1373 | * no queued transfers. | |
1374 | */ | |
1375 | spin_lock_irqsave(&plchan->lock, flags); | |
1376 | if (!plchan->phychan && !plchan->at) { | |
1377 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1378 | return 0; | |
1379 | } | |
1380 | ||
1381 | switch (cmd) { | |
1382 | case DMA_TERMINATE_ALL: | |
1383 | plchan->state = PL08X_CHAN_IDLE; | |
1384 | ||
1385 | if (plchan->phychan) { | |
fb526210 | 1386 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); |
e8689e63 LW |
1387 | |
1388 | /* | |
1389 | * Mark physical channel as free and free any slave | |
1390 | * signal | |
1391 | */ | |
8c8cc2b1 | 1392 | release_phy_channel(plchan); |
e8689e63 | 1393 | } |
e8689e63 LW |
1394 | /* Dequeue jobs and free LLIs */ |
1395 | if (plchan->at) { | |
1396 | pl08x_free_txd(pl08x, plchan->at); | |
1397 | plchan->at = NULL; | |
1398 | } | |
1399 | /* Dequeue jobs not yet fired as well */ | |
1400 | pl08x_free_txd_list(pl08x, plchan); | |
1401 | break; | |
1402 | case DMA_PAUSE: | |
1403 | pl08x_pause_phy_chan(plchan->phychan); | |
1404 | plchan->state = PL08X_CHAN_PAUSED; | |
1405 | break; | |
1406 | case DMA_RESUME: | |
1407 | pl08x_resume_phy_chan(plchan->phychan); | |
1408 | plchan->state = PL08X_CHAN_RUNNING; | |
1409 | break; | |
1410 | default: | |
1411 | /* Unknown command */ | |
1412 | ret = -ENXIO; | |
1413 | break; | |
1414 | } | |
1415 | ||
1416 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1417 | ||
1418 | return ret; | |
1419 | } | |
1420 | ||
1421 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1422 | { | |
1423 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1424 | char *name = chan_id; | |
1425 | ||
1426 | /* Check that the channel is not taken! */ | |
1427 | if (!strcmp(plchan->name, name)) | |
1428 | return true; | |
1429 | ||
1430 | return false; | |
1431 | } | |
1432 | ||
1433 | /* | |
1434 | * Just check that the device is there and active | |
94ae8522 RKAL |
1435 | * TODO: turn this bit on/off depending on the number of physical channels |
1436 | * actually used, if it is zero... well shut it off. That will save some | |
1437 | * power. Cut the clock at the same time. | |
e8689e63 LW |
1438 | */ |
1439 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1440 | { | |
48a59ef3 | 1441 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
e8689e63 LW |
1442 | } |
1443 | ||
3d992e1a RKAL |
1444 | static void pl08x_unmap_buffers(struct pl08x_txd *txd) |
1445 | { | |
1446 | struct device *dev = txd->tx.chan->device->dev; | |
1447 | ||
1448 | if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
1449 | if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
1450 | dma_unmap_single(dev, txd->src_addr, txd->len, | |
1451 | DMA_TO_DEVICE); | |
1452 | else | |
1453 | dma_unmap_page(dev, txd->src_addr, txd->len, | |
1454 | DMA_TO_DEVICE); | |
1455 | } | |
1456 | if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
1457 | if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
1458 | dma_unmap_single(dev, txd->dst_addr, txd->len, | |
1459 | DMA_FROM_DEVICE); | |
1460 | else | |
1461 | dma_unmap_page(dev, txd->dst_addr, txd->len, | |
1462 | DMA_FROM_DEVICE); | |
1463 | } | |
1464 | } | |
1465 | ||
e8689e63 LW |
1466 | static void pl08x_tasklet(unsigned long data) |
1467 | { | |
1468 | struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data; | |
e8689e63 | 1469 | struct pl08x_driver_data *pl08x = plchan->host; |
858c21c0 | 1470 | struct pl08x_txd *txd; |
bf072af4 | 1471 | unsigned long flags; |
e8689e63 | 1472 | |
bf072af4 | 1473 | spin_lock_irqsave(&plchan->lock, flags); |
e8689e63 | 1474 | |
858c21c0 RKAL |
1475 | txd = plchan->at; |
1476 | plchan->at = NULL; | |
e8689e63 | 1477 | |
858c21c0 | 1478 | if (txd) { |
94ae8522 | 1479 | /* Update last completed */ |
858c21c0 | 1480 | plchan->lc = txd->tx.cookie; |
e8689e63 | 1481 | } |
8087aacd | 1482 | |
94ae8522 | 1483 | /* If a new descriptor is queued, set it up plchan->at is NULL here */ |
15c17232 | 1484 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 LW |
1485 | struct pl08x_txd *next; |
1486 | ||
15c17232 | 1487 | next = list_first_entry(&plchan->pend_list, |
e8689e63 LW |
1488 | struct pl08x_txd, |
1489 | node); | |
1490 | list_del(&next->node); | |
c885bee4 RKAL |
1491 | |
1492 | pl08x_start_txd(plchan, next); | |
8087aacd RKAL |
1493 | } else if (plchan->phychan_hold) { |
1494 | /* | |
1495 | * This channel is still in use - we have a new txd being | |
1496 | * prepared and will soon be queued. Don't give up the | |
1497 | * physical channel. | |
1498 | */ | |
e8689e63 LW |
1499 | } else { |
1500 | struct pl08x_dma_chan *waiting = NULL; | |
1501 | ||
1502 | /* | |
1503 | * No more jobs, so free up the physical channel | |
1504 | * Free any allocated signal on slave transfers too | |
1505 | */ | |
8c8cc2b1 | 1506 | release_phy_channel(plchan); |
e8689e63 LW |
1507 | plchan->state = PL08X_CHAN_IDLE; |
1508 | ||
1509 | /* | |
94ae8522 RKAL |
1510 | * And NOW before anyone else can grab that free:d up |
1511 | * physical channel, see if there is some memcpy pending | |
1512 | * that seriously needs to start because of being stacked | |
1513 | * up while we were choking the physical channels with data. | |
e8689e63 LW |
1514 | */ |
1515 | list_for_each_entry(waiting, &pl08x->memcpy.channels, | |
1516 | chan.device_node) { | |
3e27ee84 VK |
1517 | if (waiting->state == PL08X_CHAN_WAITING && |
1518 | waiting->waiting != NULL) { | |
e8689e63 LW |
1519 | int ret; |
1520 | ||
1521 | /* This should REALLY not fail now */ | |
1522 | ret = prep_phy_channel(waiting, | |
1523 | waiting->waiting); | |
1524 | BUG_ON(ret); | |
8087aacd | 1525 | waiting->phychan_hold--; |
e8689e63 LW |
1526 | waiting->state = PL08X_CHAN_RUNNING; |
1527 | waiting->waiting = NULL; | |
1528 | pl08x_issue_pending(&waiting->chan); | |
1529 | break; | |
1530 | } | |
1531 | } | |
1532 | } | |
1533 | ||
bf072af4 | 1534 | spin_unlock_irqrestore(&plchan->lock, flags); |
858c21c0 | 1535 | |
3d992e1a RKAL |
1536 | if (txd) { |
1537 | dma_async_tx_callback callback = txd->tx.callback; | |
1538 | void *callback_param = txd->tx.callback_param; | |
1539 | ||
1540 | /* Don't try to unmap buffers on slave channels */ | |
1541 | if (!plchan->slave) | |
1542 | pl08x_unmap_buffers(txd); | |
1543 | ||
1544 | /* Free the descriptor */ | |
1545 | spin_lock_irqsave(&plchan->lock, flags); | |
1546 | pl08x_free_txd(pl08x, txd); | |
1547 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1548 | ||
1549 | /* Callback to signal completion */ | |
1550 | if (callback) | |
1551 | callback(callback_param); | |
1552 | } | |
e8689e63 LW |
1553 | } |
1554 | ||
1555 | static irqreturn_t pl08x_irq(int irq, void *dev) | |
1556 | { | |
1557 | struct pl08x_driver_data *pl08x = dev; | |
28da2836 VK |
1558 | u32 mask = 0, err, tc, i; |
1559 | ||
1560 | /* check & clear - ERR & TC interrupts */ | |
1561 | err = readl(pl08x->base + PL080_ERR_STATUS); | |
1562 | if (err) { | |
1563 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", | |
1564 | __func__, err); | |
1565 | writel(err, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 | 1566 | } |
28da2836 VK |
1567 | tc = readl(pl08x->base + PL080_INT_STATUS); |
1568 | if (tc) | |
1569 | writel(tc, pl08x->base + PL080_TC_CLEAR); | |
1570 | ||
1571 | if (!err && !tc) | |
1572 | return IRQ_NONE; | |
1573 | ||
e8689e63 | 1574 | for (i = 0; i < pl08x->vd->channels; i++) { |
28da2836 | 1575 | if (((1 << i) & err) || ((1 << i) & tc)) { |
e8689e63 LW |
1576 | /* Locate physical channel */ |
1577 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1578 | struct pl08x_dma_chan *plchan = phychan->serving; | |
1579 | ||
28da2836 VK |
1580 | if (!plchan) { |
1581 | dev_err(&pl08x->adev->dev, | |
1582 | "%s Error TC interrupt on unused channel: 0x%08x\n", | |
1583 | __func__, i); | |
1584 | continue; | |
1585 | } | |
1586 | ||
e8689e63 LW |
1587 | /* Schedule tasklet on this channel */ |
1588 | tasklet_schedule(&plchan->tasklet); | |
e8689e63 LW |
1589 | mask |= (1 << i); |
1590 | } | |
1591 | } | |
e8689e63 LW |
1592 | |
1593 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1594 | } | |
1595 | ||
121c8476 RKAL |
1596 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
1597 | { | |
1598 | u32 cctl = pl08x_cctl(chan->cd->cctl); | |
1599 | ||
1600 | chan->slave = true; | |
1601 | chan->name = chan->cd->bus_id; | |
1602 | chan->src_addr = chan->cd->addr; | |
1603 | chan->dst_addr = chan->cd->addr; | |
1604 | chan->src_cctl = cctl | PL080_CONTROL_DST_INCR | | |
1605 | pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses); | |
1606 | chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR | | |
1607 | pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses); | |
1608 | } | |
1609 | ||
e8689e63 LW |
1610 | /* |
1611 | * Initialise the DMAC memcpy/slave channels. | |
1612 | * Make a local wrapper to hold required data | |
1613 | */ | |
1614 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 1615 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
1616 | { |
1617 | struct pl08x_dma_chan *chan; | |
1618 | int i; | |
1619 | ||
1620 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 1621 | |
e8689e63 LW |
1622 | /* |
1623 | * Register as many many memcpy as we have physical channels, | |
1624 | * we won't always be able to use all but the code will have | |
1625 | * to cope with that situation. | |
1626 | */ | |
1627 | for (i = 0; i < channels; i++) { | |
b201c111 | 1628 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
e8689e63 LW |
1629 | if (!chan) { |
1630 | dev_err(&pl08x->adev->dev, | |
1631 | "%s no memory for channel\n", __func__); | |
1632 | return -ENOMEM; | |
1633 | } | |
1634 | ||
1635 | chan->host = pl08x; | |
1636 | chan->state = PL08X_CHAN_IDLE; | |
1637 | ||
1638 | if (slave) { | |
e8689e63 | 1639 | chan->cd = &pl08x->pd->slave_channels[i]; |
121c8476 | 1640 | pl08x_dma_slave_init(chan); |
e8689e63 LW |
1641 | } else { |
1642 | chan->cd = &pl08x->pd->memcpy_channel; | |
1643 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1644 | if (!chan->name) { | |
1645 | kfree(chan); | |
1646 | return -ENOMEM; | |
1647 | } | |
1648 | } | |
b58b6b5b RKAL |
1649 | if (chan->cd->circular_buffer) { |
1650 | dev_err(&pl08x->adev->dev, | |
1651 | "channel %s: circular buffers not supported\n", | |
1652 | chan->name); | |
1653 | kfree(chan); | |
1654 | continue; | |
1655 | } | |
175a5e61 | 1656 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
1657 | "initialize virtual channel \"%s\"\n", |
1658 | chan->name); | |
1659 | ||
1660 | chan->chan.device = dmadev; | |
91aa5fad RKAL |
1661 | chan->chan.cookie = 0; |
1662 | chan->lc = 0; | |
e8689e63 LW |
1663 | |
1664 | spin_lock_init(&chan->lock); | |
15c17232 | 1665 | INIT_LIST_HEAD(&chan->pend_list); |
e8689e63 LW |
1666 | tasklet_init(&chan->tasklet, pl08x_tasklet, |
1667 | (unsigned long) chan); | |
1668 | ||
1669 | list_add_tail(&chan->chan.device_node, &dmadev->channels); | |
1670 | } | |
1671 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1672 | i, slave ? "slave" : "memcpy"); | |
1673 | return i; | |
1674 | } | |
1675 | ||
1676 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1677 | { | |
1678 | struct pl08x_dma_chan *chan = NULL; | |
1679 | struct pl08x_dma_chan *next; | |
1680 | ||
1681 | list_for_each_entry_safe(chan, | |
1682 | next, &dmadev->channels, chan.device_node) { | |
1683 | list_del(&chan->chan.device_node); | |
1684 | kfree(chan); | |
1685 | } | |
1686 | } | |
1687 | ||
1688 | #ifdef CONFIG_DEBUG_FS | |
1689 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1690 | { | |
1691 | switch (state) { | |
1692 | case PL08X_CHAN_IDLE: | |
1693 | return "idle"; | |
1694 | case PL08X_CHAN_RUNNING: | |
1695 | return "running"; | |
1696 | case PL08X_CHAN_PAUSED: | |
1697 | return "paused"; | |
1698 | case PL08X_CHAN_WAITING: | |
1699 | return "waiting"; | |
1700 | default: | |
1701 | break; | |
1702 | } | |
1703 | return "UNKNOWN STATE"; | |
1704 | } | |
1705 | ||
1706 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1707 | { | |
1708 | struct pl08x_driver_data *pl08x = s->private; | |
1709 | struct pl08x_dma_chan *chan; | |
1710 | struct pl08x_phy_chan *ch; | |
1711 | unsigned long flags; | |
1712 | int i; | |
1713 | ||
1714 | seq_printf(s, "PL08x physical channels:\n"); | |
1715 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1716 | seq_printf(s, "--------\t-----\n"); | |
1717 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1718 | struct pl08x_dma_chan *virt_chan; | |
1719 | ||
1720 | ch = &pl08x->phy_chans[i]; | |
1721 | ||
1722 | spin_lock_irqsave(&ch->lock, flags); | |
1723 | virt_chan = ch->serving; | |
1724 | ||
1725 | seq_printf(s, "%d\t\t%s\n", | |
1726 | ch->id, virt_chan ? virt_chan->name : "(none)"); | |
1727 | ||
1728 | spin_unlock_irqrestore(&ch->lock, flags); | |
1729 | } | |
1730 | ||
1731 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1732 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1733 | seq_printf(s, "--------\t------\n"); | |
1734 | list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) { | |
3e2a037c | 1735 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1736 | pl08x_state_str(chan->state)); |
1737 | } | |
1738 | ||
1739 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1740 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1741 | seq_printf(s, "--------\t------\n"); | |
1742 | list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) { | |
3e2a037c | 1743 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1744 | pl08x_state_str(chan->state)); |
1745 | } | |
1746 | ||
1747 | return 0; | |
1748 | } | |
1749 | ||
1750 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1751 | { | |
1752 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1753 | } | |
1754 | ||
1755 | static const struct file_operations pl08x_debugfs_operations = { | |
1756 | .open = pl08x_debugfs_open, | |
1757 | .read = seq_read, | |
1758 | .llseek = seq_lseek, | |
1759 | .release = single_release, | |
1760 | }; | |
1761 | ||
1762 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1763 | { | |
1764 | /* Expose a simple debugfs interface to view all clocks */ | |
3e27ee84 VK |
1765 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
1766 | S_IFREG | S_IRUGO, NULL, pl08x, | |
1767 | &pl08x_debugfs_operations); | |
e8689e63 LW |
1768 | } |
1769 | ||
1770 | #else | |
1771 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1772 | { | |
1773 | } | |
1774 | #endif | |
1775 | ||
aa25afad | 1776 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
1777 | { |
1778 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1779 | const struct vendor_data *vd = id->data; |
e8689e63 LW |
1780 | int ret = 0; |
1781 | int i; | |
1782 | ||
1783 | ret = amba_request_regions(adev, NULL); | |
1784 | if (ret) | |
1785 | return ret; | |
1786 | ||
1787 | /* Create the driver state holder */ | |
b201c111 | 1788 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
1789 | if (!pl08x) { |
1790 | ret = -ENOMEM; | |
1791 | goto out_no_pl08x; | |
1792 | } | |
1793 | ||
b7b6018b VK |
1794 | pm_runtime_set_active(&adev->dev); |
1795 | pm_runtime_enable(&adev->dev); | |
1796 | ||
e8689e63 LW |
1797 | /* Initialize memcpy engine */ |
1798 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1799 | pl08x->memcpy.dev = &adev->dev; | |
1800 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1801 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1802 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1803 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1804 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1805 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1806 | pl08x->memcpy.device_control = pl08x_control; | |
1807 | ||
1808 | /* Initialize slave engine */ | |
1809 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1810 | pl08x->slave.dev = &adev->dev; | |
1811 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1812 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1813 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1814 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1815 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1816 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1817 | pl08x->slave.device_control = pl08x_control; | |
1818 | ||
1819 | /* Get the platform data */ | |
1820 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1821 | if (!pl08x->pd) { | |
1822 | dev_err(&adev->dev, "no platform data supplied\n"); | |
1823 | goto out_no_platdata; | |
1824 | } | |
1825 | ||
1826 | /* Assign useful pointers to the driver state */ | |
1827 | pl08x->adev = adev; | |
1828 | pl08x->vd = vd; | |
1829 | ||
30749cb4 RKAL |
1830 | /* By default, AHB1 only. If dualmaster, from platform */ |
1831 | pl08x->lli_buses = PL08X_AHB1; | |
1832 | pl08x->mem_buses = PL08X_AHB1; | |
1833 | if (pl08x->vd->dualmaster) { | |
1834 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
1835 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
1836 | } | |
1837 | ||
e8689e63 LW |
1838 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
1839 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
1840 | PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0); | |
1841 | if (!pl08x->pool) { | |
1842 | ret = -ENOMEM; | |
1843 | goto out_no_lli_pool; | |
1844 | } | |
1845 | ||
1846 | spin_lock_init(&pl08x->lock); | |
1847 | ||
1848 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); | |
1849 | if (!pl08x->base) { | |
1850 | ret = -ENOMEM; | |
1851 | goto out_no_ioremap; | |
1852 | } | |
1853 | ||
1854 | /* Turn on the PL08x */ | |
1855 | pl08x_ensure_on(pl08x); | |
1856 | ||
94ae8522 | 1857 | /* Attach the interrupt handler */ |
e8689e63 LW |
1858 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
1859 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
1860 | ||
1861 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 1862 | DRIVER_NAME, pl08x); |
e8689e63 LW |
1863 | if (ret) { |
1864 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
1865 | __func__, adev->irq[0]); | |
1866 | goto out_no_irq; | |
1867 | } | |
1868 | ||
1869 | /* Initialize physical channels */ | |
b201c111 | 1870 | pl08x->phy_chans = kmalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
1871 | GFP_KERNEL); |
1872 | if (!pl08x->phy_chans) { | |
1873 | dev_err(&adev->dev, "%s failed to allocate " | |
1874 | "physical channel holders\n", | |
1875 | __func__); | |
1876 | goto out_no_phychans; | |
1877 | } | |
1878 | ||
1879 | for (i = 0; i < vd->channels; i++) { | |
1880 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
1881 | ||
1882 | ch->id = i; | |
1883 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
1884 | spin_lock_init(&ch->lock); | |
1885 | ch->serving = NULL; | |
1886 | ch->signal = -1; | |
175a5e61 VK |
1887 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
1888 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
1889 | } |
1890 | ||
1891 | /* Register as many memcpy channels as there are physical channels */ | |
1892 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
1893 | pl08x->vd->channels, false); | |
1894 | if (ret <= 0) { | |
1895 | dev_warn(&pl08x->adev->dev, | |
1896 | "%s failed to enumerate memcpy channels - %d\n", | |
1897 | __func__, ret); | |
1898 | goto out_no_memcpy; | |
1899 | } | |
1900 | pl08x->memcpy.chancnt = ret; | |
1901 | ||
1902 | /* Register slave channels */ | |
1903 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
3e27ee84 | 1904 | pl08x->pd->num_slave_channels, true); |
e8689e63 LW |
1905 | if (ret <= 0) { |
1906 | dev_warn(&pl08x->adev->dev, | |
1907 | "%s failed to enumerate slave channels - %d\n", | |
1908 | __func__, ret); | |
1909 | goto out_no_slave; | |
1910 | } | |
1911 | pl08x->slave.chancnt = ret; | |
1912 | ||
1913 | ret = dma_async_device_register(&pl08x->memcpy); | |
1914 | if (ret) { | |
1915 | dev_warn(&pl08x->adev->dev, | |
1916 | "%s failed to register memcpy as an async device - %d\n", | |
1917 | __func__, ret); | |
1918 | goto out_no_memcpy_reg; | |
1919 | } | |
1920 | ||
1921 | ret = dma_async_device_register(&pl08x->slave); | |
1922 | if (ret) { | |
1923 | dev_warn(&pl08x->adev->dev, | |
1924 | "%s failed to register slave as an async device - %d\n", | |
1925 | __func__, ret); | |
1926 | goto out_no_slave_reg; | |
1927 | } | |
1928 | ||
1929 | amba_set_drvdata(adev, pl08x); | |
1930 | init_pl08x_debugfs(pl08x); | |
b05cd8f4 RKAL |
1931 | dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n", |
1932 | amba_part(adev), amba_rev(adev), | |
1933 | (unsigned long long)adev->res.start, adev->irq[0]); | |
b7b6018b VK |
1934 | |
1935 | pm_runtime_put(&adev->dev); | |
e8689e63 LW |
1936 | return 0; |
1937 | ||
1938 | out_no_slave_reg: | |
1939 | dma_async_device_unregister(&pl08x->memcpy); | |
1940 | out_no_memcpy_reg: | |
1941 | pl08x_free_virtual_channels(&pl08x->slave); | |
1942 | out_no_slave: | |
1943 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
1944 | out_no_memcpy: | |
1945 | kfree(pl08x->phy_chans); | |
1946 | out_no_phychans: | |
1947 | free_irq(adev->irq[0], pl08x); | |
1948 | out_no_irq: | |
1949 | iounmap(pl08x->base); | |
1950 | out_no_ioremap: | |
1951 | dma_pool_destroy(pl08x->pool); | |
1952 | out_no_lli_pool: | |
1953 | out_no_platdata: | |
b7b6018b VK |
1954 | pm_runtime_put(&adev->dev); |
1955 | pm_runtime_disable(&adev->dev); | |
1956 | ||
e8689e63 LW |
1957 | kfree(pl08x); |
1958 | out_no_pl08x: | |
1959 | amba_release_regions(adev); | |
1960 | return ret; | |
1961 | } | |
1962 | ||
1963 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
1964 | static struct vendor_data vendor_pl080 = { | |
e8689e63 LW |
1965 | .channels = 8, |
1966 | .dualmaster = true, | |
1967 | }; | |
1968 | ||
1969 | static struct vendor_data vendor_pl081 = { | |
e8689e63 LW |
1970 | .channels = 2, |
1971 | .dualmaster = false, | |
1972 | }; | |
1973 | ||
1974 | static struct amba_id pl08x_ids[] = { | |
1975 | /* PL080 */ | |
1976 | { | |
1977 | .id = 0x00041080, | |
1978 | .mask = 0x000fffff, | |
1979 | .data = &vendor_pl080, | |
1980 | }, | |
1981 | /* PL081 */ | |
1982 | { | |
1983 | .id = 0x00041081, | |
1984 | .mask = 0x000fffff, | |
1985 | .data = &vendor_pl081, | |
1986 | }, | |
1987 | /* Nomadik 8815 PL080 variant */ | |
1988 | { | |
1989 | .id = 0x00280880, | |
1990 | .mask = 0x00ffffff, | |
1991 | .data = &vendor_pl080, | |
1992 | }, | |
1993 | { 0, 0 }, | |
1994 | }; | |
1995 | ||
1996 | static struct amba_driver pl08x_amba_driver = { | |
1997 | .drv.name = DRIVER_NAME, | |
1998 | .id_table = pl08x_ids, | |
1999 | .probe = pl08x_probe, | |
2000 | }; | |
2001 | ||
2002 | static int __init pl08x_init(void) | |
2003 | { | |
2004 | int retval; | |
2005 | retval = amba_driver_register(&pl08x_amba_driver); | |
2006 | if (retval) | |
2007 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2008 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2009 | retval); |
2010 | return retval; | |
2011 | } | |
2012 | subsys_initcall(pl08x_init); |