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dmaengine/amba-pl08x: Complete doc comment for struct pl08x_txd
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1/*
2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
4 *
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 *
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22 * The full GNU General Public License is in this distribution in the file
23 * called COPYING.
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24 *
25 * Documentation: ARM DDI 0196G == PL080
94ae8522 26 * Documentation: ARM DDI 0218E == PL081
e8689e63 27 *
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28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
29 * channel.
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30 *
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
36 *
37 * The PL080 has a dual bus master, PL081 has a single master.
38 *
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
41 * Until no data left
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
44 * Clear burst request
45 * Raise terminal count interrupt
46 *
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
50 *
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
53 *
54 * ASSUMES default (little) endianness for DMA transfers
55 *
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56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
62 * are ignored.
63 *
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
68 *
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
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73 *
74 * Global TODO:
75 * - Break out common code from arch/arm/mach-s3c64xx and share
76 */
730404ac 77#include <linux/amba/bus.h>
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78#include <linux/amba/pl08x.h>
79#include <linux/debugfs.h>
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80#include <linux/delay.h>
81#include <linux/device.h>
82#include <linux/dmaengine.h>
83#include <linux/dmapool.h>
84#include <linux/init.h>
85#include <linux/interrupt.h>
86#include <linux/module.h>
e8689e63 87#include <linux/seq_file.h>
0c38d701 88#include <linux/slab.h>
e8689e63 89#include <asm/hardware/pl080.h>
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90
91#define DRIVER_NAME "pl08xdmac"
92
93/**
94ae8522 94 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
e8689e63 95 * @channels: the number of channels available in this variant
94ae8522 96 * @dualmaster: whether this version supports dual AHB masters or not.
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97 */
98struct vendor_data {
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99 u8 channels;
100 bool dualmaster;
101};
102
103/*
104 * PL08X private data structures
e8b5e11d 105 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
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106 * start & end do not - their bus bit info is in cctl. Also note that these
107 * are fixed 32-bit quantities.
e8689e63 108 */
7cb72ad9 109struct pl08x_lli {
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110 u32 src;
111 u32 dst;
bfddfb45 112 u32 lli;
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113 u32 cctl;
114};
115
116/**
117 * struct pl08x_driver_data - the local state holder for the PL08x
118 * @slave: slave engine for this instance
119 * @memcpy: memcpy engine for this instance
120 * @base: virtual memory base (remapped) for the PL08x
121 * @adev: the corresponding AMBA (PrimeCell) bus entry
122 * @vd: vendor data for this PL08x variant
123 * @pd: platform data passed in from the platform/machine
124 * @phy_chans: array of data for the physical channels
125 * @pool: a pool for the LLI descriptors
126 * @pool_ctr: counter of LLIs in the pool
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127 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
128 * fetches
30749cb4 129 * @mem_buses: set to indicate memory transfers on AHB2.
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130 * @lock: a spinlock for this struct
131 */
132struct pl08x_driver_data {
133 struct dma_device slave;
134 struct dma_device memcpy;
135 void __iomem *base;
136 struct amba_device *adev;
f96ca9ec 137 const struct vendor_data *vd;
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138 struct pl08x_platform_data *pd;
139 struct pl08x_phy_chan *phy_chans;
140 struct dma_pool *pool;
141 int pool_ctr;
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142 u8 lli_buses;
143 u8 mem_buses;
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144 spinlock_t lock;
145};
146
147/*
148 * PL08X specific defines
149 */
150
151/*
152 * Memory boundaries: the manual for PL08x says that the controller
153 * cannot read past a 1KiB boundary, so these defines are used to
154 * create transfer LLIs that do not cross such boundaries.
155 */
156#define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
157#define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
158
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159/* Size (bytes) of each LLI buffer allocated for one transfer */
160# define PL08X_LLI_TSFR_SIZE 0x2000
161
e8b5e11d 162/* Maximum times we call dma_pool_alloc on this pool without freeing */
7cb72ad9 163#define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
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164#define PL08X_ALIGN 8
165
166static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
167{
168 return container_of(chan, struct pl08x_dma_chan, chan);
169}
170
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171static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
172{
173 return container_of(tx, struct pl08x_txd, tx);
174}
175
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176/*
177 * Physical channel handling
178 */
179
180/* Whether a certain channel is busy or not */
181static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
182{
183 unsigned int val;
184
185 val = readl(ch->base + PL080_CH_CONFIG);
186 return val & PL080_CONFIG_ACTIVE;
187}
188
189/*
190 * Set the initial DMA register values i.e. those for the first LLI
e8b5e11d 191 * The next LLI pointer and the configuration interrupt bit have
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192 * been set when the LLIs were constructed. Poke them into the hardware
193 * and start the transfer.
e8689e63 194 */
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195static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
196 struct pl08x_txd *txd)
e8689e63 197{
c885bee4 198 struct pl08x_driver_data *pl08x = plchan->host;
e8689e63 199 struct pl08x_phy_chan *phychan = plchan->phychan;
19524d77 200 struct pl08x_lli *lli = &txd->llis_va[0];
09b3c323 201 u32 val;
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202
203 plchan->at = txd;
e8689e63 204
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205 /* Wait for channel inactive */
206 while (pl08x_phy_channel_busy(phychan))
207 cpu_relax();
e8689e63 208
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209 dev_vdbg(&pl08x->adev->dev,
210 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
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211 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
212 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
09b3c323 213 txd->ccfg);
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214
215 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
216 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
217 writel(lli->lli, phychan->base + PL080_CH_LLI);
218 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
09b3c323 219 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
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220
221 /* Enable the DMA channel */
222 /* Do not access config register until channel shows as disabled */
223 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
19386b32 224 cpu_relax();
e8689e63 225
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226 /* Do not access config register until channel shows as inactive */
227 val = readl(phychan->base + PL080_CH_CONFIG);
e8689e63 228 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
c885bee4 229 val = readl(phychan->base + PL080_CH_CONFIG);
e8689e63 230
c885bee4 231 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
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232}
233
234/*
81796616 235 * Pause the channel by setting the HALT bit.
e8689e63 236 *
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237 * For M->P transfers, pause the DMAC first and then stop the peripheral -
238 * the FIFO can only drain if the peripheral is still requesting data.
239 * (note: this can still timeout if the DMAC FIFO never drains of data.)
e8689e63 240 *
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241 * For P->M transfers, disable the peripheral first to stop it filling
242 * the DMAC FIFO, and then pause the DMAC.
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243 */
244static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
245{
246 u32 val;
81796616 247 int timeout;
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248
249 /* Set the HALT bit and wait for the FIFO to drain */
250 val = readl(ch->base + PL080_CH_CONFIG);
251 val |= PL080_CONFIG_HALT;
252 writel(val, ch->base + PL080_CH_CONFIG);
253
254 /* Wait for channel inactive */
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255 for (timeout = 1000; timeout; timeout--) {
256 if (!pl08x_phy_channel_busy(ch))
257 break;
258 udelay(1);
259 }
260 if (pl08x_phy_channel_busy(ch))
261 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
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262}
263
264static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
265{
266 u32 val;
267
268 /* Clear the HALT bit */
269 val = readl(ch->base + PL080_CH_CONFIG);
270 val &= ~PL080_CONFIG_HALT;
271 writel(val, ch->base + PL080_CH_CONFIG);
272}
273
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274/*
275 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
276 * clears any pending interrupt status. This should not be used for
277 * an on-going transfer, but as a method of shutting down a channel
278 * (eg, when it's no longer used) or terminating a transfer.
279 */
280static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
281 struct pl08x_phy_chan *ch)
e8689e63 282{
fb526210 283 u32 val = readl(ch->base + PL080_CH_CONFIG);
e8689e63 284
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285 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
286 PL080_CONFIG_TC_IRQ_MASK);
e8689e63 287
e8689e63 288 writel(val, ch->base + PL080_CH_CONFIG);
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289
290 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
291 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
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292}
293
294static inline u32 get_bytes_in_cctl(u32 cctl)
295{
296 /* The source width defines the number of bytes */
297 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
298
299 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
300 case PL080_WIDTH_8BIT:
301 break;
302 case PL080_WIDTH_16BIT:
303 bytes *= 2;
304 break;
305 case PL080_WIDTH_32BIT:
306 bytes *= 4;
307 break;
308 }
309 return bytes;
310}
311
312/* The channel should be paused when calling this */
313static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
314{
315 struct pl08x_phy_chan *ch;
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316 struct pl08x_txd *txd;
317 unsigned long flags;
cace6585 318 size_t bytes = 0;
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319
320 spin_lock_irqsave(&plchan->lock, flags);
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321 ch = plchan->phychan;
322 txd = plchan->at;
323
324 /*
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325 * Follow the LLIs to get the number of remaining
326 * bytes in the currently active transaction.
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327 */
328 if (ch && txd) {
4c0df6a3 329 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
e8689e63 330
db9f136a 331 /* First get the remaining bytes in the active transfer */
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332 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
333
334 if (clli) {
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335 struct pl08x_lli *llis_va = txd->llis_va;
336 dma_addr_t llis_bus = txd->llis_bus;
337 int index;
338
339 BUG_ON(clli < llis_bus || clli >= llis_bus +
340 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
e8689e63 341
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342 /*
343 * Locate the next LLI - as this is an array,
344 * it's simple maths to find.
345 */
346 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
347
348 for (; index < MAX_NUM_TSFR_LLIS; index++) {
349 bytes += get_bytes_in_cctl(llis_va[index].cctl);
e8689e63 350
e8689e63 351 /*
e8b5e11d 352 * A LLI pointer of 0 terminates the LLI list
e8689e63 353 */
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354 if (!llis_va[index].lli)
355 break;
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356 }
357 }
358 }
359
360 /* Sum up all queued transactions */
15c17232 361 if (!list_empty(&plchan->pend_list)) {
db9f136a 362 struct pl08x_txd *txdi;
15c17232 363 list_for_each_entry(txdi, &plchan->pend_list, node) {
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364 bytes += txdi->len;
365 }
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366 }
367
368 spin_unlock_irqrestore(&plchan->lock, flags);
369
370 return bytes;
371}
372
373/*
374 * Allocate a physical channel for a virtual channel
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375 *
376 * Try to locate a physical channel to be used for this transfer. If all
377 * are taken return NULL and the requester will have to cope by using
378 * some fallback PIO mode or retrying later.
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379 */
380static struct pl08x_phy_chan *
381pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
382 struct pl08x_dma_chan *virt_chan)
383{
384 struct pl08x_phy_chan *ch = NULL;
385 unsigned long flags;
386 int i;
387
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388 for (i = 0; i < pl08x->vd->channels; i++) {
389 ch = &pl08x->phy_chans[i];
390
391 spin_lock_irqsave(&ch->lock, flags);
392
393 if (!ch->serving) {
394 ch->serving = virt_chan;
395 ch->signal = -1;
396 spin_unlock_irqrestore(&ch->lock, flags);
397 break;
398 }
399
400 spin_unlock_irqrestore(&ch->lock, flags);
401 }
402
403 if (i == pl08x->vd->channels) {
404 /* No physical channel available, cope with it */
405 return NULL;
406 }
407
408 return ch;
409}
410
411static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
412 struct pl08x_phy_chan *ch)
413{
414 unsigned long flags;
415
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416 spin_lock_irqsave(&ch->lock, flags);
417
e8689e63 418 /* Stop the channel and clear its interrupts */
fb526210 419 pl08x_terminate_phy_chan(pl08x, ch);
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420
421 /* Mark it as free */
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422 ch->serving = NULL;
423 spin_unlock_irqrestore(&ch->lock, flags);
424}
425
426/*
427 * LLI handling
428 */
429
430static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
431{
432 switch (coded) {
433 case PL080_WIDTH_8BIT:
434 return 1;
435 case PL080_WIDTH_16BIT:
436 return 2;
437 case PL080_WIDTH_32BIT:
438 return 4;
439 default:
440 break;
441 }
442 BUG();
443 return 0;
444}
445
446static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
cace6585 447 size_t tsize)
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448{
449 u32 retbits = cctl;
450
e8b5e11d 451 /* Remove all src, dst and transfer size bits */
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452 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
453 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
454 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
455
456 /* Then set the bits according to the parameters */
457 switch (srcwidth) {
458 case 1:
459 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
460 break;
461 case 2:
462 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
463 break;
464 case 4:
465 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
466 break;
467 default:
468 BUG();
469 break;
470 }
471
472 switch (dstwidth) {
473 case 1:
474 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
475 break;
476 case 2:
477 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
478 break;
479 case 4:
480 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
481 break;
482 default:
483 BUG();
484 break;
485 }
486
487 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
488 return retbits;
489}
490
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491struct pl08x_lli_build_data {
492 struct pl08x_txd *txd;
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493 struct pl08x_bus_data srcbus;
494 struct pl08x_bus_data dstbus;
495 size_t remainder;
25c94f7f 496 u32 lli_bus;
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497};
498
e8689e63 499/*
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500 * Autoselect a master bus to use for the transfer this prefers the
501 * destination bus if both available if fixed address on one bus the
502 * other will be chosen
e8689e63 503 */
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504static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
505 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
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506{
507 if (!(cctl & PL080_CONTROL_DST_INCR)) {
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508 *mbus = &bd->srcbus;
509 *sbus = &bd->dstbus;
e8689e63 510 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
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511 *mbus = &bd->dstbus;
512 *sbus = &bd->srcbus;
e8689e63 513 } else {
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514 if (bd->dstbus.buswidth == 4) {
515 *mbus = &bd->dstbus;
516 *sbus = &bd->srcbus;
517 } else if (bd->srcbus.buswidth == 4) {
518 *mbus = &bd->srcbus;
519 *sbus = &bd->dstbus;
520 } else if (bd->dstbus.buswidth == 2) {
521 *mbus = &bd->dstbus;
522 *sbus = &bd->srcbus;
523 } else if (bd->srcbus.buswidth == 2) {
524 *mbus = &bd->srcbus;
525 *sbus = &bd->dstbus;
e8689e63 526 } else {
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527 /* bd->srcbus.buswidth == 1 */
528 *mbus = &bd->dstbus;
529 *sbus = &bd->srcbus;
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530 }
531 }
532}
533
534/*
94ae8522 535 * Fills in one LLI for a certain transfer descriptor and advance the counter
e8689e63 536 */
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537static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
538 int num_llis, int len, u32 cctl)
e8689e63 539{
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540 struct pl08x_lli *llis_va = bd->txd->llis_va;
541 dma_addr_t llis_bus = bd->txd->llis_bus;
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542
543 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
544
30749cb4 545 llis_va[num_llis].cctl = cctl;
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546 llis_va[num_llis].src = bd->srcbus.addr;
547 llis_va[num_llis].dst = bd->dstbus.addr;
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548 llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
549 sizeof(struct pl08x_lli);
25c94f7f 550 llis_va[num_llis].lli |= bd->lli_bus;
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551
552 if (cctl & PL080_CONTROL_SRC_INCR)
542361f8 553 bd->srcbus.addr += len;
e8689e63 554 if (cctl & PL080_CONTROL_DST_INCR)
542361f8 555 bd->dstbus.addr += len;
e8689e63 556
542361f8 557 BUG_ON(bd->remainder < len);
cace6585 558
542361f8 559 bd->remainder -= len;
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560}
561
562/*
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563 * Return number of bytes to fill to boundary, or len.
564 * This calculation works for any value of addr.
e8689e63 565 */
cace6585 566static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
e8689e63 567{
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568 size_t boundary_len = PL08X_BOUNDARY_SIZE -
569 (addr & (PL08X_BOUNDARY_SIZE - 1));
e8689e63 570
b61be8d7 571 return min(boundary_len, len);
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572}
573
574/*
575 * This fills in the table of LLIs for the transfer descriptor
576 * Note that we assume we never have to change the burst sizes
577 * Return 0 for error
578 */
579static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
580 struct pl08x_txd *txd)
581{
e8689e63 582 struct pl08x_bus_data *mbus, *sbus;
542361f8 583 struct pl08x_lli_build_data bd;
e8689e63
LW
584 int num_llis = 0;
585 u32 cctl;
3e27ee84 586 size_t max_bytes_per_lli, total_bytes = 0;
7cb72ad9 587 struct pl08x_lli *llis_va;
e8689e63 588
3e27ee84 589 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
e8689e63
LW
590 if (!txd->llis_va) {
591 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
592 return 0;
593 }
594
595 pl08x->pool_ctr++;
596
70b5ed6b
RKAL
597 /* Get the default CCTL */
598 cctl = txd->cctl;
e8689e63 599
542361f8 600 bd.txd = txd;
d7244e9a
RKAL
601 bd.srcbus.addr = txd->src_addr;
602 bd.dstbus.addr = txd->dst_addr;
25c94f7f 603 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
542361f8 604
e8689e63 605 /* Find maximum width of the source bus */
542361f8 606 bd.srcbus.maxwidth =
e8689e63
LW
607 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
608 PL080_CONTROL_SWIDTH_SHIFT);
609
610 /* Find maximum width of the destination bus */
542361f8 611 bd.dstbus.maxwidth =
e8689e63
LW
612 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
613 PL080_CONTROL_DWIDTH_SHIFT);
614
615 /* Set up the bus widths to the maximum */
542361f8
RKAL
616 bd.srcbus.buswidth = bd.srcbus.maxwidth;
617 bd.dstbus.buswidth = bd.dstbus.maxwidth;
e8689e63
LW
618
619 /*
620 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
621 */
542361f8 622 max_bytes_per_lli = min(bd.srcbus.buswidth, bd.dstbus.buswidth) *
e8689e63 623 PL080_CONTROL_TRANSFER_SIZE_MASK;
e8689e63
LW
624
625 /* We need to count this down to zero */
542361f8 626 bd.remainder = txd->len;
e8689e63
LW
627
628 /*
629 * Choose bus to align to
630 * - prefers destination bus if both available
631 * - if fixed address on one bus chooses other
e8689e63 632 */
542361f8 633 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
e8689e63 634
fc74eb79
RKAL
635 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu llimax=%zu\n",
636 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
637 bd.srcbus.buswidth,
638 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
639 bd.dstbus.buswidth,
640 bd.remainder, max_bytes_per_lli);
641 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
642 mbus == &bd.srcbus ? "src" : "dst",
643 sbus == &bd.srcbus ? "src" : "dst");
644
e8689e63 645 if (txd->len < mbus->buswidth) {
94ae8522 646 /* Less than a bus width available - send as single bytes */
542361f8 647 while (bd.remainder) {
e8689e63
LW
648 dev_vdbg(&pl08x->adev->dev,
649 "%s single byte LLIs for a transfer of "
9c132992 650 "less than a bus width (remain 0x%08x)\n",
542361f8 651 __func__, bd.remainder);
e8689e63 652 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
542361f8 653 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
e8689e63
LW
654 total_bytes++;
655 }
656 } else {
94ae8522 657 /* Make one byte LLIs until master bus is aligned */
e8689e63
LW
658 while ((mbus->addr) % (mbus->buswidth)) {
659 dev_vdbg(&pl08x->adev->dev,
660 "%s adjustment lli for less than bus width "
9c132992 661 "(remain 0x%08x)\n",
542361f8 662 __func__, bd.remainder);
e8689e63 663 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
542361f8 664 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
e8689e63
LW
665 total_bytes++;
666 }
667
668 /*
94ae8522 669 * Master now aligned
e8689e63
LW
670 * - if slave is not then we must set its width down
671 */
672 if (sbus->addr % sbus->buswidth) {
673 dev_dbg(&pl08x->adev->dev,
674 "%s set down bus width to one byte\n",
675 __func__);
676
677 sbus->buswidth = 1;
678 }
679
680 /*
681 * Make largest possible LLIs until less than one bus
682 * width left
683 */
542361f8 684 while (bd.remainder > (mbus->buswidth - 1)) {
cace6585 685 size_t lli_len, target_len, tsize, odd_bytes;
e8689e63
LW
686
687 /*
688 * If enough left try to send max possible,
689 * otherwise try to send the remainder
690 */
542361f8 691 target_len = min(bd.remainder, max_bytes_per_lli);
e8689e63
LW
692
693 /*
5f638b4f
RKAL
694 * Set bus lengths for incrementing buses to the
695 * number of bytes which fill to next memory boundary,
696 * limiting on the target length calculated above.
e8689e63
LW
697 */
698 if (cctl & PL080_CONTROL_SRC_INCR)
542361f8
RKAL
699 bd.srcbus.fill_bytes =
700 pl08x_pre_boundary(bd.srcbus.addr,
5f638b4f 701 target_len);
e8689e63 702 else
542361f8 703 bd.srcbus.fill_bytes = target_len;
e8689e63
LW
704
705 if (cctl & PL080_CONTROL_DST_INCR)
542361f8
RKAL
706 bd.dstbus.fill_bytes =
707 pl08x_pre_boundary(bd.dstbus.addr,
5f638b4f 708 target_len);
e8689e63 709 else
542361f8 710 bd.dstbus.fill_bytes = target_len;
e8689e63 711
5f638b4f 712 /* Find the nearest */
542361f8
RKAL
713 lli_len = min(bd.srcbus.fill_bytes,
714 bd.dstbus.fill_bytes);
e8689e63 715
542361f8 716 BUG_ON(lli_len > bd.remainder);
e8689e63
LW
717
718 if (lli_len <= 0) {
719 dev_err(&pl08x->adev->dev,
cace6585 720 "%s lli_len is %zu, <= 0\n",
e8689e63
LW
721 __func__, lli_len);
722 return 0;
723 }
724
725 if (lli_len == target_len) {
726 /*
94ae8522
RKAL
727 * Can send what we wanted.
728 * Maintain alignment
e8689e63
LW
729 */
730 lli_len = (lli_len/mbus->buswidth) *
731 mbus->buswidth;
732 odd_bytes = 0;
733 } else {
734 /*
735 * So now we know how many bytes to transfer
94ae8522
RKAL
736 * to get to the nearest boundary. The next
737 * LLI will past the boundary. However, we
738 * may be working to a boundary on the slave
739 * bus. We need to ensure the master stays
740 * aligned, and that we are working in
741 * multiples of the bus widths.
e8689e63
LW
742 */
743 odd_bytes = lli_len % mbus->buswidth;
e8689e63
LW
744 lli_len -= odd_bytes;
745
746 }
747
748 if (lli_len) {
749 /*
750 * Check against minimum bus alignment:
751 * Calculate actual transfer size in relation
752 * to bus width an get a maximum remainder of
753 * the smallest bus width - 1
754 */
755 /* FIXME: use round_down()? */
756 tsize = lli_len / min(mbus->buswidth,
757 sbus->buswidth);
758 lli_len = tsize * min(mbus->buswidth,
759 sbus->buswidth);
760
761 if (target_len != lli_len) {
762 dev_vdbg(&pl08x->adev->dev,
cace6585 763 "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
e8689e63
LW
764 __func__, target_len, lli_len, txd->len);
765 }
766
767 cctl = pl08x_cctl_bits(cctl,
542361f8
RKAL
768 bd.srcbus.buswidth,
769 bd.dstbus.buswidth,
e8689e63
LW
770 tsize);
771
772 dev_vdbg(&pl08x->adev->dev,
cace6585 773 "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
542361f8
RKAL
774 __func__, lli_len, bd.remainder);
775 pl08x_fill_lli_for_desc(&bd, num_llis++,
776 lli_len, cctl);
e8689e63
LW
777 total_bytes += lli_len;
778 }
779
e8689e63
LW
780 if (odd_bytes) {
781 /*
94ae8522
RKAL
782 * Creep past the boundary, maintaining
783 * master alignment
e8689e63
LW
784 */
785 int j;
786 for (j = 0; (j < mbus->buswidth)
542361f8 787 && (bd.remainder); j++) {
e8689e63
LW
788 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
789 dev_vdbg(&pl08x->adev->dev,
cace6585 790 "%s align with boundary, single byte (remain 0x%08zx)\n",
542361f8
RKAL
791 __func__, bd.remainder);
792 pl08x_fill_lli_for_desc(&bd,
793 num_llis++, 1, cctl);
e8689e63
LW
794 total_bytes++;
795 }
796 }
797 }
798
799 /*
800 * Send any odd bytes
801 */
542361f8 802 while (bd.remainder) {
e8689e63
LW
803 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
804 dev_vdbg(&pl08x->adev->dev,
cace6585 805 "%s align with boundary, single odd byte (remain %zu)\n",
542361f8
RKAL
806 __func__, bd.remainder);
807 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
e8689e63
LW
808 total_bytes++;
809 }
810 }
811 if (total_bytes != txd->len) {
812 dev_err(&pl08x->adev->dev,
cace6585 813 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
e8689e63
LW
814 __func__, total_bytes, txd->len);
815 return 0;
816 }
817
818 if (num_llis >= MAX_NUM_TSFR_LLIS) {
819 dev_err(&pl08x->adev->dev,
820 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
821 __func__, (u32) MAX_NUM_TSFR_LLIS);
822 return 0;
823 }
b58b6b5b
RKAL
824
825 llis_va = txd->llis_va;
94ae8522 826 /* The final LLI terminates the LLI. */
bfddfb45 827 llis_va[num_llis - 1].lli = 0;
94ae8522 828 /* The final LLI element shall also fire an interrupt. */
b58b6b5b 829 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
e8689e63 830
e8689e63
LW
831#ifdef VERBOSE_DEBUG
832 {
833 int i;
834
fc74eb79
RKAL
835 dev_vdbg(&pl08x->adev->dev,
836 "%-3s %-9s %-10s %-10s %-10s %s\n",
837 "lli", "", "csrc", "cdst", "clli", "cctl");
e8689e63
LW
838 for (i = 0; i < num_llis; i++) {
839 dev_vdbg(&pl08x->adev->dev,
fc74eb79
RKAL
840 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
841 i, &llis_va[i], llis_va[i].src,
842 llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl
e8689e63
LW
843 );
844 }
845 }
846#endif
847
848 return num_llis;
849}
850
851/* You should call this with the struct pl08x lock held */
852static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
853 struct pl08x_txd *txd)
854{
e8689e63 855 /* Free the LLI */
56b61882 856 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
e8689e63
LW
857
858 pl08x->pool_ctr--;
859
860 kfree(txd);
861}
862
863static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
864 struct pl08x_dma_chan *plchan)
865{
866 struct pl08x_txd *txdi = NULL;
867 struct pl08x_txd *next;
868
15c17232 869 if (!list_empty(&plchan->pend_list)) {
e8689e63 870 list_for_each_entry_safe(txdi,
15c17232 871 next, &plchan->pend_list, node) {
e8689e63
LW
872 list_del(&txdi->node);
873 pl08x_free_txd(pl08x, txdi);
874 }
e8689e63
LW
875 }
876}
877
878/*
879 * The DMA ENGINE API
880 */
881static int pl08x_alloc_chan_resources(struct dma_chan *chan)
882{
883 return 0;
884}
885
886static void pl08x_free_chan_resources(struct dma_chan *chan)
887{
888}
889
890/*
891 * This should be called with the channel plchan->lock held
892 */
893static int prep_phy_channel(struct pl08x_dma_chan *plchan,
894 struct pl08x_txd *txd)
895{
896 struct pl08x_driver_data *pl08x = plchan->host;
897 struct pl08x_phy_chan *ch;
898 int ret;
899
900 /* Check if we already have a channel */
901 if (plchan->phychan)
902 return 0;
903
904 ch = pl08x_get_phy_channel(pl08x, plchan);
905 if (!ch) {
906 /* No physical channel available, cope with it */
907 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
908 return -EBUSY;
909 }
910
911 /*
912 * OK we have a physical channel: for memcpy() this is all we
913 * need, but for slaves the physical signals may be muxed!
914 * Can the platform allow us to use this channel?
915 */
3e27ee84 916 if (plchan->slave && ch->signal < 0 && pl08x->pd->get_signal) {
e8689e63
LW
917 ret = pl08x->pd->get_signal(plchan);
918 if (ret < 0) {
919 dev_dbg(&pl08x->adev->dev,
920 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
921 ch->id, plchan->name);
922 /* Release physical channel & return */
923 pl08x_put_phy_channel(pl08x, ch);
924 return -EBUSY;
925 }
926 ch->signal = ret;
09b3c323
RKAL
927
928 /* Assign the flow control signal to this channel */
929 if (txd->direction == DMA_TO_DEVICE)
930 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
931 else if (txd->direction == DMA_FROM_DEVICE)
932 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
e8689e63
LW
933 }
934
935 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
936 ch->id,
937 ch->signal,
938 plchan->name);
939
8087aacd 940 plchan->phychan_hold++;
e8689e63
LW
941 plchan->phychan = ch;
942
943 return 0;
944}
945
8c8cc2b1
RKAL
946static void release_phy_channel(struct pl08x_dma_chan *plchan)
947{
948 struct pl08x_driver_data *pl08x = plchan->host;
949
950 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
951 pl08x->pd->put_signal(plchan);
952 plchan->phychan->signal = -1;
953 }
954 pl08x_put_phy_channel(pl08x, plchan->phychan);
955 plchan->phychan = NULL;
956}
957
e8689e63
LW
958static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
959{
960 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
501e67e8 961 struct pl08x_txd *txd = to_pl08x_txd(tx);
c370e594
RKAL
962 unsigned long flags;
963
964 spin_lock_irqsave(&plchan->lock, flags);
e8689e63 965
91aa5fad
RKAL
966 plchan->chan.cookie += 1;
967 if (plchan->chan.cookie < 0)
968 plchan->chan.cookie = 1;
969 tx->cookie = plchan->chan.cookie;
501e67e8
RKAL
970
971 /* Put this onto the pending list */
972 list_add_tail(&txd->node, &plchan->pend_list);
973
974 /*
975 * If there was no physical channel available for this memcpy,
976 * stack the request up and indicate that the channel is waiting
977 * for a free physical channel.
978 */
979 if (!plchan->slave && !plchan->phychan) {
980 /* Do this memcpy whenever there is a channel ready */
981 plchan->state = PL08X_CHAN_WAITING;
982 plchan->waiting = txd;
8087aacd
RKAL
983 } else {
984 plchan->phychan_hold--;
501e67e8
RKAL
985 }
986
c370e594 987 spin_unlock_irqrestore(&plchan->lock, flags);
e8689e63
LW
988
989 return tx->cookie;
990}
991
992static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
993 struct dma_chan *chan, unsigned long flags)
994{
995 struct dma_async_tx_descriptor *retval = NULL;
996
997 return retval;
998}
999
1000/*
94ae8522
RKAL
1001 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1002 * If slaves are relying on interrupts to signal completion this function
1003 * must not be called with interrupts disabled.
e8689e63 1004 */
3e27ee84
VK
1005static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
1006 dma_cookie_t cookie, struct dma_tx_state *txstate)
e8689e63
LW
1007{
1008 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1009 dma_cookie_t last_used;
1010 dma_cookie_t last_complete;
1011 enum dma_status ret;
1012 u32 bytesleft = 0;
1013
91aa5fad 1014 last_used = plchan->chan.cookie;
e8689e63
LW
1015 last_complete = plchan->lc;
1016
1017 ret = dma_async_is_complete(cookie, last_complete, last_used);
1018 if (ret == DMA_SUCCESS) {
1019 dma_set_tx_state(txstate, last_complete, last_used, 0);
1020 return ret;
1021 }
1022
e8689e63
LW
1023 /*
1024 * This cookie not complete yet
1025 */
91aa5fad 1026 last_used = plchan->chan.cookie;
e8689e63
LW
1027 last_complete = plchan->lc;
1028
1029 /* Get number of bytes left in the active transactions and queue */
1030 bytesleft = pl08x_getbytes_chan(plchan);
1031
1032 dma_set_tx_state(txstate, last_complete, last_used,
1033 bytesleft);
1034
1035 if (plchan->state == PL08X_CHAN_PAUSED)
1036 return DMA_PAUSED;
1037
1038 /* Whether waiting or running, we're in progress */
1039 return DMA_IN_PROGRESS;
1040}
1041
1042/* PrimeCell DMA extension */
1043struct burst_table {
760596c6 1044 u32 burstwords;
e8689e63
LW
1045 u32 reg;
1046};
1047
1048static const struct burst_table burst_sizes[] = {
1049 {
1050 .burstwords = 256,
760596c6 1051 .reg = PL080_BSIZE_256,
e8689e63
LW
1052 },
1053 {
1054 .burstwords = 128,
760596c6 1055 .reg = PL080_BSIZE_128,
e8689e63
LW
1056 },
1057 {
1058 .burstwords = 64,
760596c6 1059 .reg = PL080_BSIZE_64,
e8689e63
LW
1060 },
1061 {
1062 .burstwords = 32,
760596c6 1063 .reg = PL080_BSIZE_32,
e8689e63
LW
1064 },
1065 {
1066 .burstwords = 16,
760596c6 1067 .reg = PL080_BSIZE_16,
e8689e63
LW
1068 },
1069 {
1070 .burstwords = 8,
760596c6 1071 .reg = PL080_BSIZE_8,
e8689e63
LW
1072 },
1073 {
1074 .burstwords = 4,
760596c6 1075 .reg = PL080_BSIZE_4,
e8689e63
LW
1076 },
1077 {
760596c6
RKAL
1078 .burstwords = 0,
1079 .reg = PL080_BSIZE_1,
e8689e63
LW
1080 },
1081};
1082
121c8476
RKAL
1083/*
1084 * Given the source and destination available bus masks, select which
1085 * will be routed to each port. We try to have source and destination
1086 * on separate ports, but always respect the allowable settings.
1087 */
1088static u32 pl08x_select_bus(u8 src, u8 dst)
1089{
1090 u32 cctl = 0;
1091
1092 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1093 cctl |= PL080_CONTROL_DST_AHB2;
1094 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1095 cctl |= PL080_CONTROL_SRC_AHB2;
1096
1097 return cctl;
1098}
1099
f14c426c
RKAL
1100static u32 pl08x_cctl(u32 cctl)
1101{
1102 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1103 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1104 PL080_CONTROL_PROT_MASK);
1105
1106 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1107 return cctl | PL080_CONTROL_PROT_SYS;
1108}
1109
aa88cdaa
RKAL
1110static u32 pl08x_width(enum dma_slave_buswidth width)
1111{
1112 switch (width) {
1113 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1114 return PL080_WIDTH_8BIT;
1115 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1116 return PL080_WIDTH_16BIT;
1117 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1118 return PL080_WIDTH_32BIT;
f32807f1
VK
1119 default:
1120 return ~0;
aa88cdaa 1121 }
aa88cdaa
RKAL
1122}
1123
760596c6
RKAL
1124static u32 pl08x_burst(u32 maxburst)
1125{
1126 int i;
1127
1128 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1129 if (burst_sizes[i].burstwords <= maxburst)
1130 break;
1131
1132 return burst_sizes[i].reg;
1133}
1134
f0fd9446
RKAL
1135static int dma_set_runtime_config(struct dma_chan *chan,
1136 struct dma_slave_config *config)
e8689e63
LW
1137{
1138 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1139 struct pl08x_driver_data *pl08x = plchan->host;
e8689e63 1140 enum dma_slave_buswidth addr_width;
760596c6 1141 u32 width, burst, maxburst;
e8689e63 1142 u32 cctl = 0;
b7f75865
RKAL
1143
1144 if (!plchan->slave)
1145 return -EINVAL;
e8689e63
LW
1146
1147 /* Transfer direction */
1148 plchan->runtime_direction = config->direction;
1149 if (config->direction == DMA_TO_DEVICE) {
e8689e63
LW
1150 addr_width = config->dst_addr_width;
1151 maxburst = config->dst_maxburst;
1152 } else if (config->direction == DMA_FROM_DEVICE) {
e8689e63
LW
1153 addr_width = config->src_addr_width;
1154 maxburst = config->src_maxburst;
1155 } else {
1156 dev_err(&pl08x->adev->dev,
1157 "bad runtime_config: alien transfer direction\n");
f0fd9446 1158 return -EINVAL;
e8689e63
LW
1159 }
1160
aa88cdaa
RKAL
1161 width = pl08x_width(addr_width);
1162 if (width == ~0) {
e8689e63
LW
1163 dev_err(&pl08x->adev->dev,
1164 "bad runtime_config: alien address width\n");
f0fd9446 1165 return -EINVAL;
e8689e63
LW
1166 }
1167
aa88cdaa
RKAL
1168 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1169 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1170
e8689e63 1171 /*
4440aacf
RKAL
1172 * If this channel will only request single transfers, set this
1173 * down to ONE element. Also select one element if no maxburst
1174 * is specified.
e8689e63 1175 */
760596c6
RKAL
1176 if (plchan->cd->single)
1177 maxburst = 1;
1178
1179 burst = pl08x_burst(maxburst);
1180 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1181 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
e8689e63 1182
b207b4d0
RKAL
1183 if (plchan->runtime_direction == DMA_FROM_DEVICE) {
1184 plchan->src_addr = config->src_addr;
121c8476
RKAL
1185 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
1186 pl08x_select_bus(plchan->cd->periph_buses,
1187 pl08x->mem_buses);
b207b4d0
RKAL
1188 } else {
1189 plchan->dst_addr = config->dst_addr;
121c8476
RKAL
1190 plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR |
1191 pl08x_select_bus(pl08x->mem_buses,
1192 plchan->cd->periph_buses);
b207b4d0 1193 }
f0fd9446 1194
e8689e63
LW
1195 dev_dbg(&pl08x->adev->dev,
1196 "configured channel %s (%s) for %s, data width %d, "
4983a04f 1197 "maxburst %d words, LE, CCTL=0x%08x\n",
e8689e63
LW
1198 dma_chan_name(chan), plchan->name,
1199 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1200 addr_width,
1201 maxburst,
4983a04f 1202 cctl);
f0fd9446
RKAL
1203
1204 return 0;
e8689e63
LW
1205}
1206
1207/*
1208 * Slave transactions callback to the slave device to allow
1209 * synchronization of slave DMA signals with the DMAC enable
1210 */
1211static void pl08x_issue_pending(struct dma_chan *chan)
1212{
1213 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
e8689e63
LW
1214 unsigned long flags;
1215
1216 spin_lock_irqsave(&plchan->lock, flags);
9c0bb43b
RKAL
1217 /* Something is already active, or we're waiting for a channel... */
1218 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1219 spin_unlock_irqrestore(&plchan->lock, flags);
e8689e63 1220 return;
9c0bb43b 1221 }
e8689e63
LW
1222
1223 /* Take the first element in the queue and execute it */
15c17232 1224 if (!list_empty(&plchan->pend_list)) {
e8689e63
LW
1225 struct pl08x_txd *next;
1226
15c17232 1227 next = list_first_entry(&plchan->pend_list,
e8689e63
LW
1228 struct pl08x_txd,
1229 node);
1230 list_del(&next->node);
e8689e63
LW
1231 plchan->state = PL08X_CHAN_RUNNING;
1232
c885bee4 1233 pl08x_start_txd(plchan, next);
e8689e63
LW
1234 }
1235
1236 spin_unlock_irqrestore(&plchan->lock, flags);
1237}
1238
1239static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1240 struct pl08x_txd *txd)
1241{
e8689e63 1242 struct pl08x_driver_data *pl08x = plchan->host;
c370e594
RKAL
1243 unsigned long flags;
1244 int num_llis, ret;
e8689e63
LW
1245
1246 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
dafa7317
RKAL
1247 if (!num_llis) {
1248 kfree(txd);
e8689e63 1249 return -EINVAL;
dafa7317 1250 }
e8689e63 1251
c370e594 1252 spin_lock_irqsave(&plchan->lock, flags);
e8689e63 1253
e8689e63
LW
1254 /*
1255 * See if we already have a physical channel allocated,
1256 * else this is the time to try to get one.
1257 */
1258 ret = prep_phy_channel(plchan, txd);
1259 if (ret) {
1260 /*
501e67e8
RKAL
1261 * No physical channel was available.
1262 *
1263 * memcpy transfers can be sorted out at submission time.
1264 *
1265 * Slave transfers may have been denied due to platform
1266 * channel muxing restrictions. Since there is no guarantee
1267 * that this will ever be resolved, and the signal must be
1268 * acquired AFTER acquiring the physical channel, we will let
1269 * them be NACK:ed with -EBUSY here. The drivers can retry
1270 * the prep() call if they are eager on doing this using DMA.
e8689e63
LW
1271 */
1272 if (plchan->slave) {
1273 pl08x_free_txd_list(pl08x, plchan);
501e67e8 1274 pl08x_free_txd(pl08x, txd);
c370e594 1275 spin_unlock_irqrestore(&plchan->lock, flags);
e8689e63
LW
1276 return -EBUSY;
1277 }
e8689e63
LW
1278 } else
1279 /*
94ae8522
RKAL
1280 * Else we're all set, paused and ready to roll, status
1281 * will switch to PL08X_CHAN_RUNNING when we call
1282 * issue_pending(). If there is something running on the
1283 * channel already we don't change its state.
e8689e63
LW
1284 */
1285 if (plchan->state == PL08X_CHAN_IDLE)
1286 plchan->state = PL08X_CHAN_PAUSED;
1287
c370e594 1288 spin_unlock_irqrestore(&plchan->lock, flags);
e8689e63
LW
1289
1290 return 0;
1291}
1292
c0428794
RKAL
1293static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1294 unsigned long flags)
ac3cd20d 1295{
b201c111 1296 struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
ac3cd20d
RKAL
1297
1298 if (txd) {
1299 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
c0428794 1300 txd->tx.flags = flags;
ac3cd20d
RKAL
1301 txd->tx.tx_submit = pl08x_tx_submit;
1302 INIT_LIST_HEAD(&txd->node);
4983a04f
RKAL
1303
1304 /* Always enable error and terminal interrupts */
1305 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1306 PL080_CONFIG_TC_IRQ_MASK;
ac3cd20d
RKAL
1307 }
1308 return txd;
1309}
1310
e8689e63
LW
1311/*
1312 * Initialize a descriptor to be used by memcpy submit
1313 */
1314static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1315 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1316 size_t len, unsigned long flags)
1317{
1318 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1319 struct pl08x_driver_data *pl08x = plchan->host;
1320 struct pl08x_txd *txd;
1321 int ret;
1322
c0428794 1323 txd = pl08x_get_txd(plchan, flags);
e8689e63
LW
1324 if (!txd) {
1325 dev_err(&pl08x->adev->dev,
1326 "%s no memory for descriptor\n", __func__);
1327 return NULL;
1328 }
1329
e8689e63 1330 txd->direction = DMA_NONE;
d7244e9a
RKAL
1331 txd->src_addr = src;
1332 txd->dst_addr = dest;
c7da9a56 1333 txd->len = len;
e8689e63
LW
1334
1335 /* Set platform data for m2m */
4983a04f 1336 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
c7da9a56
RKAL
1337 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1338 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
4983a04f 1339
e8689e63 1340 /* Both to be incremented or the code will break */
70b5ed6b 1341 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
c7da9a56 1342
c7da9a56 1343 if (pl08x->vd->dualmaster)
121c8476
RKAL
1344 txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
1345 pl08x->mem_buses);
e8689e63 1346
e8689e63
LW
1347 ret = pl08x_prep_channel_resources(plchan, txd);
1348 if (ret)
1349 return NULL;
e8689e63
LW
1350
1351 return &txd->tx;
1352}
1353
3e2a037c 1354static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
e8689e63
LW
1355 struct dma_chan *chan, struct scatterlist *sgl,
1356 unsigned int sg_len, enum dma_data_direction direction,
1357 unsigned long flags)
1358{
1359 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1360 struct pl08x_driver_data *pl08x = plchan->host;
1361 struct pl08x_txd *txd;
1362 int ret;
1363
1364 /*
1365 * Current implementation ASSUMES only one sg
1366 */
1367 if (sg_len != 1) {
1368 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1369 __func__);
1370 BUG();
1371 }
1372
1373 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1374 __func__, sgl->length, plchan->name);
1375
c0428794 1376 txd = pl08x_get_txd(plchan, flags);
e8689e63
LW
1377 if (!txd) {
1378 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1379 return NULL;
1380 }
1381
e8689e63
LW
1382 if (direction != plchan->runtime_direction)
1383 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1384 "the direction configured for the PrimeCell\n",
1385 __func__);
1386
1387 /*
1388 * Set up addresses, the PrimeCell configured address
1389 * will take precedence since this may configure the
1390 * channel target address dynamically at runtime.
1391 */
1392 txd->direction = direction;
c7da9a56
RKAL
1393 txd->len = sgl->length;
1394
e8689e63 1395 if (direction == DMA_TO_DEVICE) {
4983a04f 1396 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
121c8476 1397 txd->cctl = plchan->dst_cctl;
d7244e9a 1398 txd->src_addr = sgl->dma_address;
b207b4d0 1399 txd->dst_addr = plchan->dst_addr;
e8689e63 1400 } else if (direction == DMA_FROM_DEVICE) {
4983a04f 1401 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
121c8476 1402 txd->cctl = plchan->src_cctl;
b207b4d0 1403 txd->src_addr = plchan->src_addr;
d7244e9a 1404 txd->dst_addr = sgl->dma_address;
e8689e63
LW
1405 } else {
1406 dev_err(&pl08x->adev->dev,
1407 "%s direction unsupported\n", __func__);
1408 return NULL;
1409 }
e8689e63
LW
1410
1411 ret = pl08x_prep_channel_resources(plchan, txd);
1412 if (ret)
1413 return NULL;
e8689e63
LW
1414
1415 return &txd->tx;
1416}
1417
1418static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1419 unsigned long arg)
1420{
1421 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1422 struct pl08x_driver_data *pl08x = plchan->host;
1423 unsigned long flags;
1424 int ret = 0;
1425
1426 /* Controls applicable to inactive channels */
1427 if (cmd == DMA_SLAVE_CONFIG) {
f0fd9446
RKAL
1428 return dma_set_runtime_config(chan,
1429 (struct dma_slave_config *)arg);
e8689e63
LW
1430 }
1431
1432 /*
1433 * Anything succeeds on channels with no physical allocation and
1434 * no queued transfers.
1435 */
1436 spin_lock_irqsave(&plchan->lock, flags);
1437 if (!plchan->phychan && !plchan->at) {
1438 spin_unlock_irqrestore(&plchan->lock, flags);
1439 return 0;
1440 }
1441
1442 switch (cmd) {
1443 case DMA_TERMINATE_ALL:
1444 plchan->state = PL08X_CHAN_IDLE;
1445
1446 if (plchan->phychan) {
fb526210 1447 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
e8689e63
LW
1448
1449 /*
1450 * Mark physical channel as free and free any slave
1451 * signal
1452 */
8c8cc2b1 1453 release_phy_channel(plchan);
e8689e63 1454 }
e8689e63
LW
1455 /* Dequeue jobs and free LLIs */
1456 if (plchan->at) {
1457 pl08x_free_txd(pl08x, plchan->at);
1458 plchan->at = NULL;
1459 }
1460 /* Dequeue jobs not yet fired as well */
1461 pl08x_free_txd_list(pl08x, plchan);
1462 break;
1463 case DMA_PAUSE:
1464 pl08x_pause_phy_chan(plchan->phychan);
1465 plchan->state = PL08X_CHAN_PAUSED;
1466 break;
1467 case DMA_RESUME:
1468 pl08x_resume_phy_chan(plchan->phychan);
1469 plchan->state = PL08X_CHAN_RUNNING;
1470 break;
1471 default:
1472 /* Unknown command */
1473 ret = -ENXIO;
1474 break;
1475 }
1476
1477 spin_unlock_irqrestore(&plchan->lock, flags);
1478
1479 return ret;
1480}
1481
1482bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1483{
1484 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1485 char *name = chan_id;
1486
1487 /* Check that the channel is not taken! */
1488 if (!strcmp(plchan->name, name))
1489 return true;
1490
1491 return false;
1492}
1493
1494/*
1495 * Just check that the device is there and active
94ae8522
RKAL
1496 * TODO: turn this bit on/off depending on the number of physical channels
1497 * actually used, if it is zero... well shut it off. That will save some
1498 * power. Cut the clock at the same time.
e8689e63
LW
1499 */
1500static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1501{
1502 u32 val;
1503
1504 val = readl(pl08x->base + PL080_CONFIG);
1505 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
e8b5e11d 1506 /* We implicitly clear bit 1 and that means little-endian mode */
e8689e63
LW
1507 val |= PL080_CONFIG_ENABLE;
1508 writel(val, pl08x->base + PL080_CONFIG);
1509}
1510
3d992e1a
RKAL
1511static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1512{
1513 struct device *dev = txd->tx.chan->device->dev;
1514
1515 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1516 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1517 dma_unmap_single(dev, txd->src_addr, txd->len,
1518 DMA_TO_DEVICE);
1519 else
1520 dma_unmap_page(dev, txd->src_addr, txd->len,
1521 DMA_TO_DEVICE);
1522 }
1523 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1524 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1525 dma_unmap_single(dev, txd->dst_addr, txd->len,
1526 DMA_FROM_DEVICE);
1527 else
1528 dma_unmap_page(dev, txd->dst_addr, txd->len,
1529 DMA_FROM_DEVICE);
1530 }
1531}
1532
e8689e63
LW
1533static void pl08x_tasklet(unsigned long data)
1534{
1535 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
e8689e63 1536 struct pl08x_driver_data *pl08x = plchan->host;
858c21c0 1537 struct pl08x_txd *txd;
bf072af4 1538 unsigned long flags;
e8689e63 1539
bf072af4 1540 spin_lock_irqsave(&plchan->lock, flags);
e8689e63 1541
858c21c0
RKAL
1542 txd = plchan->at;
1543 plchan->at = NULL;
e8689e63 1544
858c21c0 1545 if (txd) {
94ae8522 1546 /* Update last completed */
858c21c0 1547 plchan->lc = txd->tx.cookie;
e8689e63 1548 }
8087aacd 1549
94ae8522 1550 /* If a new descriptor is queued, set it up plchan->at is NULL here */
15c17232 1551 if (!list_empty(&plchan->pend_list)) {
e8689e63
LW
1552 struct pl08x_txd *next;
1553
15c17232 1554 next = list_first_entry(&plchan->pend_list,
e8689e63
LW
1555 struct pl08x_txd,
1556 node);
1557 list_del(&next->node);
c885bee4
RKAL
1558
1559 pl08x_start_txd(plchan, next);
8087aacd
RKAL
1560 } else if (plchan->phychan_hold) {
1561 /*
1562 * This channel is still in use - we have a new txd being
1563 * prepared and will soon be queued. Don't give up the
1564 * physical channel.
1565 */
e8689e63
LW
1566 } else {
1567 struct pl08x_dma_chan *waiting = NULL;
1568
1569 /*
1570 * No more jobs, so free up the physical channel
1571 * Free any allocated signal on slave transfers too
1572 */
8c8cc2b1 1573 release_phy_channel(plchan);
e8689e63
LW
1574 plchan->state = PL08X_CHAN_IDLE;
1575
1576 /*
94ae8522
RKAL
1577 * And NOW before anyone else can grab that free:d up
1578 * physical channel, see if there is some memcpy pending
1579 * that seriously needs to start because of being stacked
1580 * up while we were choking the physical channels with data.
e8689e63
LW
1581 */
1582 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1583 chan.device_node) {
3e27ee84
VK
1584 if (waiting->state == PL08X_CHAN_WAITING &&
1585 waiting->waiting != NULL) {
e8689e63
LW
1586 int ret;
1587
1588 /* This should REALLY not fail now */
1589 ret = prep_phy_channel(waiting,
1590 waiting->waiting);
1591 BUG_ON(ret);
8087aacd 1592 waiting->phychan_hold--;
e8689e63
LW
1593 waiting->state = PL08X_CHAN_RUNNING;
1594 waiting->waiting = NULL;
1595 pl08x_issue_pending(&waiting->chan);
1596 break;
1597 }
1598 }
1599 }
1600
bf072af4 1601 spin_unlock_irqrestore(&plchan->lock, flags);
858c21c0 1602
3d992e1a
RKAL
1603 if (txd) {
1604 dma_async_tx_callback callback = txd->tx.callback;
1605 void *callback_param = txd->tx.callback_param;
1606
1607 /* Don't try to unmap buffers on slave channels */
1608 if (!plchan->slave)
1609 pl08x_unmap_buffers(txd);
1610
1611 /* Free the descriptor */
1612 spin_lock_irqsave(&plchan->lock, flags);
1613 pl08x_free_txd(pl08x, txd);
1614 spin_unlock_irqrestore(&plchan->lock, flags);
1615
1616 /* Callback to signal completion */
1617 if (callback)
1618 callback(callback_param);
1619 }
e8689e63
LW
1620}
1621
1622static irqreturn_t pl08x_irq(int irq, void *dev)
1623{
1624 struct pl08x_driver_data *pl08x = dev;
1625 u32 mask = 0;
1626 u32 val;
1627 int i;
1628
1629 val = readl(pl08x->base + PL080_ERR_STATUS);
1630 if (val) {
94ae8522 1631 /* An error interrupt (on one or more channels) */
e8689e63
LW
1632 dev_err(&pl08x->adev->dev,
1633 "%s error interrupt, register value 0x%08x\n",
1634 __func__, val);
1635 /*
1636 * Simply clear ALL PL08X error interrupts,
1637 * regardless of channel and cause
1638 * FIXME: should be 0x00000003 on PL081 really.
1639 */
1640 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1641 }
1642 val = readl(pl08x->base + PL080_INT_STATUS);
1643 for (i = 0; i < pl08x->vd->channels; i++) {
1644 if ((1 << i) & val) {
1645 /* Locate physical channel */
1646 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1647 struct pl08x_dma_chan *plchan = phychan->serving;
1648
1649 /* Schedule tasklet on this channel */
1650 tasklet_schedule(&plchan->tasklet);
1651
1652 mask |= (1 << i);
1653 }
1654 }
94ae8522 1655 /* Clear only the terminal interrupts on channels we processed */
e8689e63
LW
1656 writel(mask, pl08x->base + PL080_TC_CLEAR);
1657
1658 return mask ? IRQ_HANDLED : IRQ_NONE;
1659}
1660
121c8476
RKAL
1661static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
1662{
1663 u32 cctl = pl08x_cctl(chan->cd->cctl);
1664
1665 chan->slave = true;
1666 chan->name = chan->cd->bus_id;
1667 chan->src_addr = chan->cd->addr;
1668 chan->dst_addr = chan->cd->addr;
1669 chan->src_cctl = cctl | PL080_CONTROL_DST_INCR |
1670 pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses);
1671 chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR |
1672 pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses);
1673}
1674
e8689e63
LW
1675/*
1676 * Initialise the DMAC memcpy/slave channels.
1677 * Make a local wrapper to hold required data
1678 */
1679static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
3e27ee84 1680 struct dma_device *dmadev, unsigned int channels, bool slave)
e8689e63
LW
1681{
1682 struct pl08x_dma_chan *chan;
1683 int i;
1684
1685 INIT_LIST_HEAD(&dmadev->channels);
94ae8522 1686
e8689e63
LW
1687 /*
1688 * Register as many many memcpy as we have physical channels,
1689 * we won't always be able to use all but the code will have
1690 * to cope with that situation.
1691 */
1692 for (i = 0; i < channels; i++) {
b201c111 1693 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
e8689e63
LW
1694 if (!chan) {
1695 dev_err(&pl08x->adev->dev,
1696 "%s no memory for channel\n", __func__);
1697 return -ENOMEM;
1698 }
1699
1700 chan->host = pl08x;
1701 chan->state = PL08X_CHAN_IDLE;
1702
1703 if (slave) {
e8689e63 1704 chan->cd = &pl08x->pd->slave_channels[i];
121c8476 1705 pl08x_dma_slave_init(chan);
e8689e63
LW
1706 } else {
1707 chan->cd = &pl08x->pd->memcpy_channel;
1708 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1709 if (!chan->name) {
1710 kfree(chan);
1711 return -ENOMEM;
1712 }
1713 }
b58b6b5b
RKAL
1714 if (chan->cd->circular_buffer) {
1715 dev_err(&pl08x->adev->dev,
1716 "channel %s: circular buffers not supported\n",
1717 chan->name);
1718 kfree(chan);
1719 continue;
1720 }
e8689e63
LW
1721 dev_info(&pl08x->adev->dev,
1722 "initialize virtual channel \"%s\"\n",
1723 chan->name);
1724
1725 chan->chan.device = dmadev;
91aa5fad
RKAL
1726 chan->chan.cookie = 0;
1727 chan->lc = 0;
e8689e63
LW
1728
1729 spin_lock_init(&chan->lock);
15c17232 1730 INIT_LIST_HEAD(&chan->pend_list);
e8689e63
LW
1731 tasklet_init(&chan->tasklet, pl08x_tasklet,
1732 (unsigned long) chan);
1733
1734 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1735 }
1736 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1737 i, slave ? "slave" : "memcpy");
1738 return i;
1739}
1740
1741static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1742{
1743 struct pl08x_dma_chan *chan = NULL;
1744 struct pl08x_dma_chan *next;
1745
1746 list_for_each_entry_safe(chan,
1747 next, &dmadev->channels, chan.device_node) {
1748 list_del(&chan->chan.device_node);
1749 kfree(chan);
1750 }
1751}
1752
1753#ifdef CONFIG_DEBUG_FS
1754static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1755{
1756 switch (state) {
1757 case PL08X_CHAN_IDLE:
1758 return "idle";
1759 case PL08X_CHAN_RUNNING:
1760 return "running";
1761 case PL08X_CHAN_PAUSED:
1762 return "paused";
1763 case PL08X_CHAN_WAITING:
1764 return "waiting";
1765 default:
1766 break;
1767 }
1768 return "UNKNOWN STATE";
1769}
1770
1771static int pl08x_debugfs_show(struct seq_file *s, void *data)
1772{
1773 struct pl08x_driver_data *pl08x = s->private;
1774 struct pl08x_dma_chan *chan;
1775 struct pl08x_phy_chan *ch;
1776 unsigned long flags;
1777 int i;
1778
1779 seq_printf(s, "PL08x physical channels:\n");
1780 seq_printf(s, "CHANNEL:\tUSER:\n");
1781 seq_printf(s, "--------\t-----\n");
1782 for (i = 0; i < pl08x->vd->channels; i++) {
1783 struct pl08x_dma_chan *virt_chan;
1784
1785 ch = &pl08x->phy_chans[i];
1786
1787 spin_lock_irqsave(&ch->lock, flags);
1788 virt_chan = ch->serving;
1789
1790 seq_printf(s, "%d\t\t%s\n",
1791 ch->id, virt_chan ? virt_chan->name : "(none)");
1792
1793 spin_unlock_irqrestore(&ch->lock, flags);
1794 }
1795
1796 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1797 seq_printf(s, "CHANNEL:\tSTATE:\n");
1798 seq_printf(s, "--------\t------\n");
1799 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
3e2a037c 1800 seq_printf(s, "%s\t\t%s\n", chan->name,
e8689e63
LW
1801 pl08x_state_str(chan->state));
1802 }
1803
1804 seq_printf(s, "\nPL08x virtual slave channels:\n");
1805 seq_printf(s, "CHANNEL:\tSTATE:\n");
1806 seq_printf(s, "--------\t------\n");
1807 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
3e2a037c 1808 seq_printf(s, "%s\t\t%s\n", chan->name,
e8689e63
LW
1809 pl08x_state_str(chan->state));
1810 }
1811
1812 return 0;
1813}
1814
1815static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1816{
1817 return single_open(file, pl08x_debugfs_show, inode->i_private);
1818}
1819
1820static const struct file_operations pl08x_debugfs_operations = {
1821 .open = pl08x_debugfs_open,
1822 .read = seq_read,
1823 .llseek = seq_lseek,
1824 .release = single_release,
1825};
1826
1827static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1828{
1829 /* Expose a simple debugfs interface to view all clocks */
3e27ee84
VK
1830 (void) debugfs_create_file(dev_name(&pl08x->adev->dev),
1831 S_IFREG | S_IRUGO, NULL, pl08x,
1832 &pl08x_debugfs_operations);
e8689e63
LW
1833}
1834
1835#else
1836static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1837{
1838}
1839#endif
1840
aa25afad 1841static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
e8689e63
LW
1842{
1843 struct pl08x_driver_data *pl08x;
f96ca9ec 1844 const struct vendor_data *vd = id->data;
e8689e63
LW
1845 int ret = 0;
1846 int i;
1847
1848 ret = amba_request_regions(adev, NULL);
1849 if (ret)
1850 return ret;
1851
1852 /* Create the driver state holder */
b201c111 1853 pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
e8689e63
LW
1854 if (!pl08x) {
1855 ret = -ENOMEM;
1856 goto out_no_pl08x;
1857 }
1858
1859 /* Initialize memcpy engine */
1860 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1861 pl08x->memcpy.dev = &adev->dev;
1862 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1863 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1864 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1865 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1866 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1867 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1868 pl08x->memcpy.device_control = pl08x_control;
1869
1870 /* Initialize slave engine */
1871 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1872 pl08x->slave.dev = &adev->dev;
1873 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1874 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1875 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1876 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1877 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1878 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1879 pl08x->slave.device_control = pl08x_control;
1880
1881 /* Get the platform data */
1882 pl08x->pd = dev_get_platdata(&adev->dev);
1883 if (!pl08x->pd) {
1884 dev_err(&adev->dev, "no platform data supplied\n");
1885 goto out_no_platdata;
1886 }
1887
1888 /* Assign useful pointers to the driver state */
1889 pl08x->adev = adev;
1890 pl08x->vd = vd;
1891
30749cb4
RKAL
1892 /* By default, AHB1 only. If dualmaster, from platform */
1893 pl08x->lli_buses = PL08X_AHB1;
1894 pl08x->mem_buses = PL08X_AHB1;
1895 if (pl08x->vd->dualmaster) {
1896 pl08x->lli_buses = pl08x->pd->lli_buses;
1897 pl08x->mem_buses = pl08x->pd->mem_buses;
1898 }
1899
e8689e63
LW
1900 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1901 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1902 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1903 if (!pl08x->pool) {
1904 ret = -ENOMEM;
1905 goto out_no_lli_pool;
1906 }
1907
1908 spin_lock_init(&pl08x->lock);
1909
1910 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1911 if (!pl08x->base) {
1912 ret = -ENOMEM;
1913 goto out_no_ioremap;
1914 }
1915
1916 /* Turn on the PL08x */
1917 pl08x_ensure_on(pl08x);
1918
94ae8522 1919 /* Attach the interrupt handler */
e8689e63
LW
1920 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1921 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1922
1923 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
b05cd8f4 1924 DRIVER_NAME, pl08x);
e8689e63
LW
1925 if (ret) {
1926 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1927 __func__, adev->irq[0]);
1928 goto out_no_irq;
1929 }
1930
1931 /* Initialize physical channels */
b201c111 1932 pl08x->phy_chans = kmalloc((vd->channels * sizeof(*pl08x->phy_chans)),
e8689e63
LW
1933 GFP_KERNEL);
1934 if (!pl08x->phy_chans) {
1935 dev_err(&adev->dev, "%s failed to allocate "
1936 "physical channel holders\n",
1937 __func__);
1938 goto out_no_phychans;
1939 }
1940
1941 for (i = 0; i < vd->channels; i++) {
1942 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1943
1944 ch->id = i;
1945 ch->base = pl08x->base + PL080_Cx_BASE(i);
1946 spin_lock_init(&ch->lock);
1947 ch->serving = NULL;
1948 ch->signal = -1;
1949 dev_info(&adev->dev,
1950 "physical channel %d is %s\n", i,
1951 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1952 }
1953
1954 /* Register as many memcpy channels as there are physical channels */
1955 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1956 pl08x->vd->channels, false);
1957 if (ret <= 0) {
1958 dev_warn(&pl08x->adev->dev,
1959 "%s failed to enumerate memcpy channels - %d\n",
1960 __func__, ret);
1961 goto out_no_memcpy;
1962 }
1963 pl08x->memcpy.chancnt = ret;
1964
1965 /* Register slave channels */
1966 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
3e27ee84 1967 pl08x->pd->num_slave_channels, true);
e8689e63
LW
1968 if (ret <= 0) {
1969 dev_warn(&pl08x->adev->dev,
1970 "%s failed to enumerate slave channels - %d\n",
1971 __func__, ret);
1972 goto out_no_slave;
1973 }
1974 pl08x->slave.chancnt = ret;
1975
1976 ret = dma_async_device_register(&pl08x->memcpy);
1977 if (ret) {
1978 dev_warn(&pl08x->adev->dev,
1979 "%s failed to register memcpy as an async device - %d\n",
1980 __func__, ret);
1981 goto out_no_memcpy_reg;
1982 }
1983
1984 ret = dma_async_device_register(&pl08x->slave);
1985 if (ret) {
1986 dev_warn(&pl08x->adev->dev,
1987 "%s failed to register slave as an async device - %d\n",
1988 __func__, ret);
1989 goto out_no_slave_reg;
1990 }
1991
1992 amba_set_drvdata(adev, pl08x);
1993 init_pl08x_debugfs(pl08x);
b05cd8f4
RKAL
1994 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1995 amba_part(adev), amba_rev(adev),
1996 (unsigned long long)adev->res.start, adev->irq[0]);
e8689e63
LW
1997 return 0;
1998
1999out_no_slave_reg:
2000 dma_async_device_unregister(&pl08x->memcpy);
2001out_no_memcpy_reg:
2002 pl08x_free_virtual_channels(&pl08x->slave);
2003out_no_slave:
2004 pl08x_free_virtual_channels(&pl08x->memcpy);
2005out_no_memcpy:
2006 kfree(pl08x->phy_chans);
2007out_no_phychans:
2008 free_irq(adev->irq[0], pl08x);
2009out_no_irq:
2010 iounmap(pl08x->base);
2011out_no_ioremap:
2012 dma_pool_destroy(pl08x->pool);
2013out_no_lli_pool:
2014out_no_platdata:
2015 kfree(pl08x);
2016out_no_pl08x:
2017 amba_release_regions(adev);
2018 return ret;
2019}
2020
2021/* PL080 has 8 channels and the PL080 have just 2 */
2022static struct vendor_data vendor_pl080 = {
e8689e63
LW
2023 .channels = 8,
2024 .dualmaster = true,
2025};
2026
2027static struct vendor_data vendor_pl081 = {
e8689e63
LW
2028 .channels = 2,
2029 .dualmaster = false,
2030};
2031
2032static struct amba_id pl08x_ids[] = {
2033 /* PL080 */
2034 {
2035 .id = 0x00041080,
2036 .mask = 0x000fffff,
2037 .data = &vendor_pl080,
2038 },
2039 /* PL081 */
2040 {
2041 .id = 0x00041081,
2042 .mask = 0x000fffff,
2043 .data = &vendor_pl081,
2044 },
2045 /* Nomadik 8815 PL080 variant */
2046 {
2047 .id = 0x00280880,
2048 .mask = 0x00ffffff,
2049 .data = &vendor_pl080,
2050 },
2051 { 0, 0 },
2052};
2053
2054static struct amba_driver pl08x_amba_driver = {
2055 .drv.name = DRIVER_NAME,
2056 .id_table = pl08x_ids,
2057 .probe = pl08x_probe,
2058};
2059
2060static int __init pl08x_init(void)
2061{
2062 int retval;
2063 retval = amba_driver_register(&pl08x_amba_driver);
2064 if (retval)
2065 printk(KERN_WARNING DRIVER_NAME
e8b5e11d 2066 "failed to register as an AMBA device (%d)\n",
e8689e63
LW
2067 retval);
2068 return retval;
2069}
2070subsys_initcall(pl08x_init);