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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
94ae8522 RKAL |
22 | * The full GNU General Public License is in this distribution in the file |
23 | * called COPYING. | |
e8689e63 LW |
24 | * |
25 | * Documentation: ARM DDI 0196G == PL080 | |
94ae8522 | 26 | * Documentation: ARM DDI 0218E == PL081 |
e8689e63 | 27 | * |
94ae8522 RKAL |
28 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
29 | * channel. | |
e8689e63 LW |
30 | * |
31 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
32 | * has only two channels. So on these DMA controllers the number of channels | |
33 | * and the number of incoming DMA signals are two totally different things. | |
34 | * It is usually not possible to theoretically handle all physical signals, | |
35 | * so a multiplexing scheme with possible denial of use is necessary. | |
36 | * | |
37 | * The PL080 has a dual bus master, PL081 has a single master. | |
38 | * | |
39 | * Memory to peripheral transfer may be visualized as | |
40 | * Get data from memory to DMAC | |
41 | * Until no data left | |
42 | * On burst request from peripheral | |
43 | * Destination burst from DMAC to peripheral | |
44 | * Clear burst request | |
45 | * Raise terminal count interrupt | |
46 | * | |
47 | * For peripherals with a FIFO: | |
48 | * Source burst size == half the depth of the peripheral FIFO | |
49 | * Destination burst size == the depth of the peripheral FIFO | |
50 | * | |
51 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
52 | * signals, the DMA controller will simply facilitate its AHB master.) | |
53 | * | |
54 | * ASSUMES default (little) endianness for DMA transfers | |
55 | * | |
9dc2c200 RKAL |
56 | * The PL08x has two flow control settings: |
57 | * - DMAC flow control: the transfer size defines the number of transfers | |
58 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
59 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
60 | * to both the BREQ and SREQ signals (contrary to documented), | |
61 | * transferring data if either is active. The LBREQ and LSREQ signals | |
62 | * are ignored. | |
63 | * | |
64 | * - Peripheral flow control: the transfer size is ignored (and should be | |
65 | * zero). The data is transferred from the current LLI entry, until | |
66 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
67 | * will then move to the next LLI entry. | |
68 | * | |
e8689e63 LW |
69 | * Global TODO: |
70 | * - Break out common code from arch/arm/mach-s3c64xx and share | |
71 | */ | |
730404ac | 72 | #include <linux/amba/bus.h> |
e8689e63 LW |
73 | #include <linux/amba/pl08x.h> |
74 | #include <linux/debugfs.h> | |
0c38d701 VK |
75 | #include <linux/delay.h> |
76 | #include <linux/device.h> | |
77 | #include <linux/dmaengine.h> | |
78 | #include <linux/dmapool.h> | |
8516f52f | 79 | #include <linux/dma-mapping.h> |
0c38d701 VK |
80 | #include <linux/init.h> |
81 | #include <linux/interrupt.h> | |
82 | #include <linux/module.h> | |
b7b6018b | 83 | #include <linux/pm_runtime.h> |
e8689e63 | 84 | #include <linux/seq_file.h> |
0c38d701 | 85 | #include <linux/slab.h> |
3a95b9fb | 86 | #include <linux/amba/pl080.h> |
e8689e63 | 87 | |
d2ebfb33 | 88 | #include "dmaengine.h" |
01d8dc64 | 89 | #include "virt-dma.h" |
d2ebfb33 | 90 | |
e8689e63 LW |
91 | #define DRIVER_NAME "pl08xdmac" |
92 | ||
7703eac9 | 93 | static struct amba_driver pl08x_amba_driver; |
b23f204c | 94 | struct pl08x_driver_data; |
7703eac9 | 95 | |
e8689e63 | 96 | /** |
94ae8522 | 97 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
e8689e63 | 98 | * @channels: the number of channels available in this variant |
94ae8522 | 99 | * @dualmaster: whether this version supports dual AHB masters or not. |
affa115e LW |
100 | * @nomadik: whether the channels have Nomadik security extension bits |
101 | * that need to be checked for permission before use and some registers are | |
102 | * missing | |
e8689e63 LW |
103 | */ |
104 | struct vendor_data { | |
d86ccea7 | 105 | u8 config_offset; |
e8689e63 LW |
106 | u8 channels; |
107 | bool dualmaster; | |
affa115e | 108 | bool nomadik; |
e8689e63 LW |
109 | }; |
110 | ||
b23f204c RK |
111 | /** |
112 | * struct pl08x_bus_data - information of source or destination | |
113 | * busses for a transfer | |
114 | * @addr: current address | |
115 | * @maxwidth: the maximum width of a transfer on this bus | |
116 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | |
117 | */ | |
118 | struct pl08x_bus_data { | |
119 | dma_addr_t addr; | |
120 | u8 maxwidth; | |
121 | u8 buswidth; | |
122 | }; | |
123 | ||
124 | /** | |
125 | * struct pl08x_phy_chan - holder for the physical channels | |
126 | * @id: physical index to this channel | |
127 | * @lock: a lock to use when altering an instance of this struct | |
b23f204c RK |
128 | * @serving: the virtual channel currently being served by this physical |
129 | * channel | |
ad0de2ac RK |
130 | * @locked: channel unavailable for the system, e.g. dedicated to secure |
131 | * world | |
b23f204c RK |
132 | */ |
133 | struct pl08x_phy_chan { | |
134 | unsigned int id; | |
135 | void __iomem *base; | |
d86ccea7 | 136 | void __iomem *reg_config; |
b23f204c | 137 | spinlock_t lock; |
b23f204c | 138 | struct pl08x_dma_chan *serving; |
ad0de2ac | 139 | bool locked; |
b23f204c RK |
140 | }; |
141 | ||
142 | /** | |
143 | * struct pl08x_sg - structure containing data per sg | |
144 | * @src_addr: src address of sg | |
145 | * @dst_addr: dst address of sg | |
146 | * @len: transfer len in bytes | |
147 | * @node: node for txd's dsg_list | |
148 | */ | |
149 | struct pl08x_sg { | |
150 | dma_addr_t src_addr; | |
151 | dma_addr_t dst_addr; | |
152 | size_t len; | |
153 | struct list_head node; | |
154 | }; | |
155 | ||
156 | /** | |
157 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | |
01d8dc64 | 158 | * @vd: virtual DMA descriptor |
b23f204c | 159 | * @dsg_list: list of children sg's |
b23f204c RK |
160 | * @llis_bus: DMA memory address (physical) start for the LLIs |
161 | * @llis_va: virtual memory address start for the LLIs | |
162 | * @cctl: control reg values for current txd | |
163 | * @ccfg: config reg values for current txd | |
18536134 RK |
164 | * @done: this marks completed descriptors, which should not have their |
165 | * mux released. | |
b23f204c RK |
166 | */ |
167 | struct pl08x_txd { | |
01d8dc64 | 168 | struct virt_dma_desc vd; |
b23f204c | 169 | struct list_head dsg_list; |
b23f204c | 170 | dma_addr_t llis_bus; |
ba6785ff | 171 | u32 *llis_va; |
b23f204c RK |
172 | /* Default cctl value for LLIs */ |
173 | u32 cctl; | |
174 | /* | |
175 | * Settings to be put into the physical channel when we | |
176 | * trigger this txd. Other registers are in llis_va[0]. | |
177 | */ | |
178 | u32 ccfg; | |
18536134 | 179 | bool done; |
b23f204c RK |
180 | }; |
181 | ||
182 | /** | |
183 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel | |
184 | * states | |
185 | * @PL08X_CHAN_IDLE: the channel is idle | |
186 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | |
187 | * channel and is running a transfer on it | |
188 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport | |
189 | * channel, but the transfer is currently paused | |
190 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport | |
191 | * channel to become available (only pertains to memcpy channels) | |
192 | */ | |
193 | enum pl08x_dma_chan_state { | |
194 | PL08X_CHAN_IDLE, | |
195 | PL08X_CHAN_RUNNING, | |
196 | PL08X_CHAN_PAUSED, | |
197 | PL08X_CHAN_WAITING, | |
198 | }; | |
199 | ||
200 | /** | |
201 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | |
01d8dc64 | 202 | * @vc: wrappped virtual channel |
b23f204c | 203 | * @phychan: the physical channel utilized by this channel, if there is one |
b23f204c RK |
204 | * @name: name of channel |
205 | * @cd: channel platform data | |
206 | * @runtime_addr: address for RX/TX according to the runtime config | |
b23f204c RK |
207 | * @at: active transaction on this channel |
208 | * @lock: a lock for this channel data | |
209 | * @host: a pointer to the host (internal use) | |
210 | * @state: whether the channel is idle, paused, running etc | |
211 | * @slave: whether this channel is a device (slave) or for memcpy | |
ad0de2ac | 212 | * @signal: the physical DMA request signal which this channel is using |
5e2479bd | 213 | * @mux_use: count of descriptors using this DMA request signal setting |
b23f204c RK |
214 | */ |
215 | struct pl08x_dma_chan { | |
01d8dc64 | 216 | struct virt_dma_chan vc; |
b23f204c | 217 | struct pl08x_phy_chan *phychan; |
550ec36f | 218 | const char *name; |
b23f204c | 219 | const struct pl08x_channel_data *cd; |
ed91c13d | 220 | struct dma_slave_config cfg; |
b23f204c | 221 | struct pl08x_txd *at; |
b23f204c RK |
222 | struct pl08x_driver_data *host; |
223 | enum pl08x_dma_chan_state state; | |
224 | bool slave; | |
ad0de2ac | 225 | int signal; |
5e2479bd | 226 | unsigned mux_use; |
b23f204c RK |
227 | }; |
228 | ||
e8689e63 LW |
229 | /** |
230 | * struct pl08x_driver_data - the local state holder for the PL08x | |
231 | * @slave: slave engine for this instance | |
232 | * @memcpy: memcpy engine for this instance | |
233 | * @base: virtual memory base (remapped) for the PL08x | |
234 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
235 | * @vd: vendor data for this PL08x variant | |
236 | * @pd: platform data passed in from the platform/machine | |
237 | * @phy_chans: array of data for the physical channels | |
238 | * @pool: a pool for the LLI descriptors | |
3e27ee84 VK |
239 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
240 | * fetches | |
30749cb4 | 241 | * @mem_buses: set to indicate memory transfers on AHB2. |
e8689e63 LW |
242 | * @lock: a spinlock for this struct |
243 | */ | |
244 | struct pl08x_driver_data { | |
245 | struct dma_device slave; | |
246 | struct dma_device memcpy; | |
247 | void __iomem *base; | |
248 | struct amba_device *adev; | |
f96ca9ec | 249 | const struct vendor_data *vd; |
e8689e63 LW |
250 | struct pl08x_platform_data *pd; |
251 | struct pl08x_phy_chan *phy_chans; | |
252 | struct dma_pool *pool; | |
30749cb4 RKAL |
253 | u8 lli_buses; |
254 | u8 mem_buses; | |
ba6785ff | 255 | u8 lli_words; |
e8689e63 LW |
256 | }; |
257 | ||
258 | /* | |
259 | * PL08X specific defines | |
260 | */ | |
261 | ||
ba6785ff TF |
262 | /* The order of words in an LLI. */ |
263 | #define PL080_LLI_SRC 0 | |
264 | #define PL080_LLI_DST 1 | |
265 | #define PL080_LLI_LLI 2 | |
266 | #define PL080_LLI_CCTL 3 | |
267 | ||
268 | /* Total words in an LLI. */ | |
269 | #define PL080_LLI_WORDS 4 | |
e8689e63 | 270 | |
ba6785ff TF |
271 | /* |
272 | * Number of LLIs in each LLI buffer allocated for one transfer | |
273 | * (maximum times we call dma_pool_alloc on this pool without freeing) | |
274 | */ | |
275 | #define MAX_NUM_TSFR_LLIS 512 | |
e8689e63 LW |
276 | #define PL08X_ALIGN 8 |
277 | ||
278 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
279 | { | |
01d8dc64 | 280 | return container_of(chan, struct pl08x_dma_chan, vc.chan); |
e8689e63 LW |
281 | } |
282 | ||
501e67e8 RKAL |
283 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
284 | { | |
01d8dc64 | 285 | return container_of(tx, struct pl08x_txd, vd.tx); |
501e67e8 RKAL |
286 | } |
287 | ||
6b16c8b1 RK |
288 | /* |
289 | * Mux handling. | |
290 | * | |
291 | * This gives us the DMA request input to the PL08x primecell which the | |
292 | * peripheral described by the channel data will be routed to, possibly | |
293 | * via a board/SoC specific external MUX. One important point to note | |
294 | * here is that this does not depend on the physical channel. | |
295 | */ | |
ad0de2ac | 296 | static int pl08x_request_mux(struct pl08x_dma_chan *plchan) |
6b16c8b1 RK |
297 | { |
298 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
299 | int ret; | |
300 | ||
d7cabeed MB |
301 | if (plchan->mux_use++ == 0 && pd->get_xfer_signal) { |
302 | ret = pd->get_xfer_signal(plchan->cd); | |
5e2479bd RK |
303 | if (ret < 0) { |
304 | plchan->mux_use = 0; | |
6b16c8b1 | 305 | return ret; |
5e2479bd | 306 | } |
6b16c8b1 | 307 | |
ad0de2ac | 308 | plchan->signal = ret; |
6b16c8b1 RK |
309 | } |
310 | return 0; | |
311 | } | |
312 | ||
313 | static void pl08x_release_mux(struct pl08x_dma_chan *plchan) | |
314 | { | |
315 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
316 | ||
5e2479bd RK |
317 | if (plchan->signal >= 0) { |
318 | WARN_ON(plchan->mux_use == 0); | |
319 | ||
d7cabeed MB |
320 | if (--plchan->mux_use == 0 && pd->put_xfer_signal) { |
321 | pd->put_xfer_signal(plchan->cd, plchan->signal); | |
5e2479bd RK |
322 | plchan->signal = -1; |
323 | } | |
6b16c8b1 RK |
324 | } |
325 | } | |
326 | ||
e8689e63 LW |
327 | /* |
328 | * Physical channel handling | |
329 | */ | |
330 | ||
331 | /* Whether a certain channel is busy or not */ | |
332 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
333 | { | |
334 | unsigned int val; | |
335 | ||
d86ccea7 | 336 | val = readl(ch->reg_config); |
e8689e63 LW |
337 | return val & PL080_CONFIG_ACTIVE; |
338 | } | |
339 | ||
ba6785ff TF |
340 | static void pl08x_write_lli(struct pl08x_driver_data *pl08x, |
341 | struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg) | |
342 | { | |
343 | dev_vdbg(&pl08x->adev->dev, | |
344 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
345 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", | |
346 | phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST], | |
347 | lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg); | |
348 | ||
349 | writel_relaxed(lli[PL080_LLI_SRC], phychan->base + PL080_CH_SRC_ADDR); | |
350 | writel_relaxed(lli[PL080_LLI_DST], phychan->base + PL080_CH_DST_ADDR); | |
351 | writel_relaxed(lli[PL080_LLI_LLI], phychan->base + PL080_CH_LLI); | |
352 | writel_relaxed(lli[PL080_LLI_CCTL], phychan->base + PL080_CH_CONTROL); | |
353 | ||
354 | writel(ccfg, phychan->reg_config); | |
355 | } | |
356 | ||
e8689e63 LW |
357 | /* |
358 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 359 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
360 | * been set when the LLIs were constructed. Poke them into the hardware |
361 | * and start the transfer. | |
e8689e63 | 362 | */ |
eab82533 | 363 | static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) |
e8689e63 | 364 | { |
c885bee4 | 365 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 366 | struct pl08x_phy_chan *phychan = plchan->phychan; |
879f127b RK |
367 | struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc); |
368 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
09b3c323 | 369 | u32 val; |
c885bee4 | 370 | |
879f127b | 371 | list_del(&txd->vd.node); |
eab82533 | 372 | |
c885bee4 | 373 | plchan->at = txd; |
e8689e63 | 374 | |
c885bee4 RKAL |
375 | /* Wait for channel inactive */ |
376 | while (pl08x_phy_channel_busy(phychan)) | |
377 | cpu_relax(); | |
e8689e63 | 378 | |
ba6785ff | 379 | pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg); |
c885bee4 RKAL |
380 | |
381 | /* Enable the DMA channel */ | |
382 | /* Do not access config register until channel shows as disabled */ | |
383 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 384 | cpu_relax(); |
e8689e63 | 385 | |
c885bee4 | 386 | /* Do not access config register until channel shows as inactive */ |
d86ccea7 | 387 | val = readl(phychan->reg_config); |
e8689e63 | 388 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
d86ccea7 | 389 | val = readl(phychan->reg_config); |
e8689e63 | 390 | |
d86ccea7 | 391 | writel(val | PL080_CONFIG_ENABLE, phychan->reg_config); |
e8689e63 LW |
392 | } |
393 | ||
394 | /* | |
81796616 | 395 | * Pause the channel by setting the HALT bit. |
e8689e63 | 396 | * |
81796616 RKAL |
397 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
398 | * the FIFO can only drain if the peripheral is still requesting data. | |
399 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 400 | * |
81796616 RKAL |
401 | * For P->M transfers, disable the peripheral first to stop it filling |
402 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
403 | */ |
404 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
405 | { | |
406 | u32 val; | |
81796616 | 407 | int timeout; |
e8689e63 LW |
408 | |
409 | /* Set the HALT bit and wait for the FIFO to drain */ | |
d86ccea7 | 410 | val = readl(ch->reg_config); |
e8689e63 | 411 | val |= PL080_CONFIG_HALT; |
d86ccea7 | 412 | writel(val, ch->reg_config); |
e8689e63 LW |
413 | |
414 | /* Wait for channel inactive */ | |
81796616 RKAL |
415 | for (timeout = 1000; timeout; timeout--) { |
416 | if (!pl08x_phy_channel_busy(ch)) | |
417 | break; | |
418 | udelay(1); | |
419 | } | |
420 | if (pl08x_phy_channel_busy(ch)) | |
421 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
422 | } |
423 | ||
424 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
425 | { | |
426 | u32 val; | |
427 | ||
428 | /* Clear the HALT bit */ | |
d86ccea7 | 429 | val = readl(ch->reg_config); |
e8689e63 | 430 | val &= ~PL080_CONFIG_HALT; |
d86ccea7 | 431 | writel(val, ch->reg_config); |
e8689e63 LW |
432 | } |
433 | ||
fb526210 RKAL |
434 | /* |
435 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
436 | * clears any pending interrupt status. This should not be used for | |
437 | * an on-going transfer, but as a method of shutting down a channel | |
438 | * (eg, when it's no longer used) or terminating a transfer. | |
439 | */ | |
440 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
441 | struct pl08x_phy_chan *ch) | |
e8689e63 | 442 | { |
d86ccea7 | 443 | u32 val = readl(ch->reg_config); |
e8689e63 | 444 | |
fb526210 RKAL |
445 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
446 | PL080_CONFIG_TC_IRQ_MASK); | |
e8689e63 | 447 | |
d86ccea7 | 448 | writel(val, ch->reg_config); |
fb526210 RKAL |
449 | |
450 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); | |
451 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
452 | } |
453 | ||
454 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
455 | { | |
456 | /* The source width defines the number of bytes */ | |
457 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
458 | ||
459 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
460 | case PL080_WIDTH_8BIT: | |
461 | break; | |
462 | case PL080_WIDTH_16BIT: | |
463 | bytes *= 2; | |
464 | break; | |
465 | case PL080_WIDTH_32BIT: | |
466 | bytes *= 4; | |
467 | break; | |
468 | } | |
469 | return bytes; | |
470 | } | |
471 | ||
472 | /* The channel should be paused when calling this */ | |
473 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
474 | { | |
ba6785ff TF |
475 | struct pl08x_driver_data *pl08x = plchan->host; |
476 | const u32 *llis_va, *llis_va_limit; | |
e8689e63 | 477 | struct pl08x_phy_chan *ch; |
68a7faa2 | 478 | dma_addr_t llis_bus; |
e8689e63 | 479 | struct pl08x_txd *txd; |
ba6785ff | 480 | u32 llis_max_words; |
68a7faa2 | 481 | size_t bytes; |
68a7faa2 | 482 | u32 clli; |
e8689e63 | 483 | |
e8689e63 LW |
484 | ch = plchan->phychan; |
485 | txd = plchan->at; | |
486 | ||
68a7faa2 TF |
487 | if (!ch || !txd) |
488 | return 0; | |
489 | ||
e8689e63 | 490 | /* |
db9f136a RKAL |
491 | * Follow the LLIs to get the number of remaining |
492 | * bytes in the currently active transaction. | |
e8689e63 | 493 | */ |
68a7faa2 | 494 | clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 495 | |
68a7faa2 TF |
496 | /* First get the remaining bytes in the active transfer */ |
497 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); | |
e8689e63 | 498 | |
68a7faa2 TF |
499 | if (!clli) |
500 | return bytes; | |
db9f136a | 501 | |
68a7faa2 TF |
502 | llis_va = txd->llis_va; |
503 | llis_bus = txd->llis_bus; | |
504 | ||
ba6785ff | 505 | llis_max_words = pl08x->lli_words * MAX_NUM_TSFR_LLIS; |
68a7faa2 | 506 | BUG_ON(clli < llis_bus || clli >= llis_bus + |
ba6785ff | 507 | sizeof(u32) * llis_max_words); |
e8689e63 | 508 | |
68a7faa2 TF |
509 | /* |
510 | * Locate the next LLI - as this is an array, | |
511 | * it's simple maths to find. | |
512 | */ | |
ba6785ff | 513 | llis_va += (clli - llis_bus) / sizeof(u32); |
68a7faa2 | 514 | |
ba6785ff TF |
515 | llis_va_limit = llis_va + llis_max_words; |
516 | ||
517 | for (; llis_va < llis_va_limit; llis_va += pl08x->lli_words) { | |
518 | bytes += get_bytes_in_cctl(llis_va[PL080_LLI_CCTL]); | |
68a7faa2 TF |
519 | |
520 | /* | |
521 | * A LLI pointer of 0 terminates the LLI list | |
522 | */ | |
ba6785ff | 523 | if (!llis_va[PL080_LLI_LLI]) |
68a7faa2 | 524 | break; |
e8689e63 LW |
525 | } |
526 | ||
e8689e63 LW |
527 | return bytes; |
528 | } | |
529 | ||
530 | /* | |
531 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
532 | * |
533 | * Try to locate a physical channel to be used for this transfer. If all | |
534 | * are taken return NULL and the requester will have to cope by using | |
535 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
536 | */ |
537 | static struct pl08x_phy_chan * | |
538 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
539 | struct pl08x_dma_chan *virt_chan) | |
540 | { | |
541 | struct pl08x_phy_chan *ch = NULL; | |
542 | unsigned long flags; | |
543 | int i; | |
544 | ||
e8689e63 LW |
545 | for (i = 0; i < pl08x->vd->channels; i++) { |
546 | ch = &pl08x->phy_chans[i]; | |
547 | ||
548 | spin_lock_irqsave(&ch->lock, flags); | |
549 | ||
affa115e | 550 | if (!ch->locked && !ch->serving) { |
e8689e63 | 551 | ch->serving = virt_chan; |
e8689e63 LW |
552 | spin_unlock_irqrestore(&ch->lock, flags); |
553 | break; | |
554 | } | |
555 | ||
556 | spin_unlock_irqrestore(&ch->lock, flags); | |
557 | } | |
558 | ||
559 | if (i == pl08x->vd->channels) { | |
560 | /* No physical channel available, cope with it */ | |
561 | return NULL; | |
562 | } | |
563 | ||
564 | return ch; | |
565 | } | |
566 | ||
a5a488db | 567 | /* Mark the physical channel as free. Note, this write is atomic. */ |
e8689e63 LW |
568 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, |
569 | struct pl08x_phy_chan *ch) | |
570 | { | |
a5a488db RK |
571 | ch->serving = NULL; |
572 | } | |
e8689e63 | 573 | |
a5a488db RK |
574 | /* |
575 | * Try to allocate a physical channel. When successful, assign it to | |
576 | * this virtual channel, and initiate the next descriptor. The | |
577 | * virtual channel lock must be held at this point. | |
578 | */ | |
579 | static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan) | |
580 | { | |
581 | struct pl08x_driver_data *pl08x = plchan->host; | |
582 | struct pl08x_phy_chan *ch; | |
fb526210 | 583 | |
a5a488db RK |
584 | ch = pl08x_get_phy_channel(pl08x, plchan); |
585 | if (!ch) { | |
586 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
587 | plchan->state = PL08X_CHAN_WAITING; | |
588 | return; | |
589 | } | |
e8689e63 | 590 | |
a5a488db RK |
591 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n", |
592 | ch->id, plchan->name); | |
593 | ||
594 | plchan->phychan = ch; | |
595 | plchan->state = PL08X_CHAN_RUNNING; | |
596 | pl08x_start_next_txd(plchan); | |
597 | } | |
598 | ||
599 | static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch, | |
600 | struct pl08x_dma_chan *plchan) | |
601 | { | |
602 | struct pl08x_driver_data *pl08x = plchan->host; | |
603 | ||
604 | dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n", | |
605 | ch->id, plchan->name); | |
606 | ||
607 | /* | |
608 | * We do this without taking the lock; we're really only concerned | |
609 | * about whether this pointer is NULL or not, and we're guaranteed | |
610 | * that this will only be called when it _already_ is non-NULL. | |
611 | */ | |
612 | ch->serving = plchan; | |
613 | plchan->phychan = ch; | |
614 | plchan->state = PL08X_CHAN_RUNNING; | |
615 | pl08x_start_next_txd(plchan); | |
616 | } | |
617 | ||
618 | /* | |
619 | * Free a physical DMA channel, potentially reallocating it to another | |
620 | * virtual channel if we have any pending. | |
621 | */ | |
622 | static void pl08x_phy_free(struct pl08x_dma_chan *plchan) | |
623 | { | |
624 | struct pl08x_driver_data *pl08x = plchan->host; | |
625 | struct pl08x_dma_chan *p, *next; | |
626 | ||
627 | retry: | |
628 | next = NULL; | |
629 | ||
630 | /* Find a waiting virtual channel for the next transfer. */ | |
01d8dc64 | 631 | list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node) |
a5a488db RK |
632 | if (p->state == PL08X_CHAN_WAITING) { |
633 | next = p; | |
634 | break; | |
635 | } | |
636 | ||
637 | if (!next) { | |
01d8dc64 | 638 | list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node) |
a5a488db RK |
639 | if (p->state == PL08X_CHAN_WAITING) { |
640 | next = p; | |
641 | break; | |
642 | } | |
643 | } | |
644 | ||
645 | /* Ensure that the physical channel is stopped */ | |
646 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); | |
647 | ||
648 | if (next) { | |
649 | bool success; | |
650 | ||
651 | /* | |
652 | * Eww. We know this isn't going to deadlock | |
653 | * but lockdep probably doesn't. | |
654 | */ | |
083be28a | 655 | spin_lock(&next->vc.lock); |
a5a488db RK |
656 | /* Re-check the state now that we have the lock */ |
657 | success = next->state == PL08X_CHAN_WAITING; | |
658 | if (success) | |
659 | pl08x_phy_reassign_start(plchan->phychan, next); | |
083be28a | 660 | spin_unlock(&next->vc.lock); |
a5a488db RK |
661 | |
662 | /* If the state changed, try to find another channel */ | |
663 | if (!success) | |
664 | goto retry; | |
665 | } else { | |
666 | /* No more jobs, so free up the physical channel */ | |
667 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
668 | } | |
669 | ||
670 | plchan->phychan = NULL; | |
671 | plchan->state = PL08X_CHAN_IDLE; | |
e8689e63 LW |
672 | } |
673 | ||
674 | /* | |
675 | * LLI handling | |
676 | */ | |
677 | ||
678 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
679 | { | |
680 | switch (coded) { | |
681 | case PL080_WIDTH_8BIT: | |
682 | return 1; | |
683 | case PL080_WIDTH_16BIT: | |
684 | return 2; | |
685 | case PL080_WIDTH_32BIT: | |
686 | return 4; | |
687 | default: | |
688 | break; | |
689 | } | |
690 | BUG(); | |
691 | return 0; | |
692 | } | |
693 | ||
694 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 695 | size_t tsize) |
e8689e63 LW |
696 | { |
697 | u32 retbits = cctl; | |
698 | ||
e8b5e11d | 699 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
700 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
701 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
702 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
703 | ||
704 | /* Then set the bits according to the parameters */ | |
705 | switch (srcwidth) { | |
706 | case 1: | |
707 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
708 | break; | |
709 | case 2: | |
710 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
711 | break; | |
712 | case 4: | |
713 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
714 | break; | |
715 | default: | |
716 | BUG(); | |
717 | break; | |
718 | } | |
719 | ||
720 | switch (dstwidth) { | |
721 | case 1: | |
722 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
723 | break; | |
724 | case 2: | |
725 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
726 | break; | |
727 | case 4: | |
728 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
729 | break; | |
730 | default: | |
731 | BUG(); | |
732 | break; | |
733 | } | |
734 | ||
735 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
736 | return retbits; | |
737 | } | |
738 | ||
542361f8 RKAL |
739 | struct pl08x_lli_build_data { |
740 | struct pl08x_txd *txd; | |
542361f8 RKAL |
741 | struct pl08x_bus_data srcbus; |
742 | struct pl08x_bus_data dstbus; | |
743 | size_t remainder; | |
25c94f7f | 744 | u32 lli_bus; |
542361f8 RKAL |
745 | }; |
746 | ||
e8689e63 | 747 | /* |
0532e6fc VK |
748 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
749 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
750 | * masters address with width requirements of transfer (by sending few byte by | |
751 | * byte data), slave is still not aligned, then its width will be reduced to | |
752 | * BYTE. | |
753 | * - prefers the destination bus if both available | |
036f05fd | 754 | * - prefers bus with fixed address (i.e. peripheral) |
e8689e63 | 755 | */ |
542361f8 RKAL |
756 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
757 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) | |
e8689e63 LW |
758 | { |
759 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
542361f8 RKAL |
760 | *mbus = &bd->dstbus; |
761 | *sbus = &bd->srcbus; | |
036f05fd VK |
762 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
763 | *mbus = &bd->srcbus; | |
764 | *sbus = &bd->dstbus; | |
e8689e63 | 765 | } else { |
036f05fd | 766 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
542361f8 RKAL |
767 | *mbus = &bd->dstbus; |
768 | *sbus = &bd->srcbus; | |
036f05fd | 769 | } else { |
542361f8 RKAL |
770 | *mbus = &bd->srcbus; |
771 | *sbus = &bd->dstbus; | |
e8689e63 LW |
772 | } |
773 | } | |
774 | } | |
775 | ||
776 | /* | |
94ae8522 | 777 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 778 | */ |
ba6785ff TF |
779 | static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x, |
780 | struct pl08x_lli_build_data *bd, | |
781 | int num_llis, int len, u32 cctl) | |
e8689e63 | 782 | { |
ba6785ff TF |
783 | u32 offset = num_llis * pl08x->lli_words; |
784 | u32 *llis_va = bd->txd->llis_va + offset; | |
542361f8 | 785 | dma_addr_t llis_bus = bd->txd->llis_bus; |
e8689e63 LW |
786 | |
787 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
788 | ||
ba6785ff TF |
789 | /* Advance the offset to next LLI. */ |
790 | offset += pl08x->lli_words; | |
791 | ||
792 | llis_va[PL080_LLI_SRC] = bd->srcbus.addr; | |
793 | llis_va[PL080_LLI_DST] = bd->dstbus.addr; | |
794 | llis_va[PL080_LLI_LLI] = (llis_bus + sizeof(u32) * offset); | |
795 | llis_va[PL080_LLI_LLI] |= bd->lli_bus; | |
796 | llis_va[PL080_LLI_CCTL] = cctl; | |
e8689e63 LW |
797 | |
798 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 | 799 | bd->srcbus.addr += len; |
e8689e63 | 800 | if (cctl & PL080_CONTROL_DST_INCR) |
542361f8 | 801 | bd->dstbus.addr += len; |
e8689e63 | 802 | |
542361f8 | 803 | BUG_ON(bd->remainder < len); |
cace6585 | 804 | |
542361f8 | 805 | bd->remainder -= len; |
e8689e63 LW |
806 | } |
807 | ||
ba6785ff TF |
808 | static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x, |
809 | struct pl08x_lli_build_data *bd, u32 *cctl, u32 len, | |
810 | int num_llis, size_t *total_bytes) | |
e8689e63 | 811 | { |
03af500f | 812 | *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); |
ba6785ff | 813 | pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl); |
03af500f | 814 | (*total_bytes) += len; |
e8689e63 LW |
815 | } |
816 | ||
817 | /* | |
818 | * This fills in the table of LLIs for the transfer descriptor | |
819 | * Note that we assume we never have to change the burst sizes | |
820 | * Return 0 for error | |
821 | */ | |
822 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
823 | struct pl08x_txd *txd) | |
824 | { | |
e8689e63 | 825 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 826 | struct pl08x_lli_build_data bd; |
e8689e63 | 827 | int num_llis = 0; |
03af500f | 828 | u32 cctl, early_bytes = 0; |
b7f69d9d | 829 | size_t max_bytes_per_lli, total_bytes; |
ba6785ff | 830 | u32 *llis_va, *last_lli; |
b7f69d9d | 831 | struct pl08x_sg *dsg; |
e8689e63 | 832 | |
3e27ee84 | 833 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
834 | if (!txd->llis_va) { |
835 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
836 | return 0; | |
837 | } | |
838 | ||
542361f8 | 839 | bd.txd = txd; |
25c94f7f | 840 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
b7f69d9d | 841 | cctl = txd->cctl; |
542361f8 | 842 | |
e8689e63 | 843 | /* Find maximum width of the source bus */ |
542361f8 | 844 | bd.srcbus.maxwidth = |
e8689e63 LW |
845 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
846 | PL080_CONTROL_SWIDTH_SHIFT); | |
847 | ||
848 | /* Find maximum width of the destination bus */ | |
542361f8 | 849 | bd.dstbus.maxwidth = |
e8689e63 LW |
850 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
851 | PL080_CONTROL_DWIDTH_SHIFT); | |
852 | ||
b7f69d9d VK |
853 | list_for_each_entry(dsg, &txd->dsg_list, node) { |
854 | total_bytes = 0; | |
855 | cctl = txd->cctl; | |
e8689e63 | 856 | |
b7f69d9d VK |
857 | bd.srcbus.addr = dsg->src_addr; |
858 | bd.dstbus.addr = dsg->dst_addr; | |
859 | bd.remainder = dsg->len; | |
860 | bd.srcbus.buswidth = bd.srcbus.maxwidth; | |
861 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 | 862 | |
b7f69d9d | 863 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
e8689e63 | 864 | |
b7f69d9d VK |
865 | dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n", |
866 | bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", | |
867 | bd.srcbus.buswidth, | |
868 | bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
869 | bd.dstbus.buswidth, | |
870 | bd.remainder); | |
871 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", | |
872 | mbus == &bd.srcbus ? "src" : "dst", | |
873 | sbus == &bd.srcbus ? "src" : "dst"); | |
fc74eb79 | 874 | |
b7f69d9d VK |
875 | /* |
876 | * Zero length is only allowed if all these requirements are | |
877 | * met: | |
878 | * - flow controller is peripheral. | |
879 | * - src.addr is aligned to src.width | |
880 | * - dst.addr is aligned to dst.width | |
881 | * | |
882 | * sg_len == 1 should be true, as there can be two cases here: | |
883 | * | |
884 | * - Memory addresses are contiguous and are not scattered. | |
885 | * Here, Only one sg will be passed by user driver, with | |
886 | * memory address and zero length. We pass this to controller | |
887 | * and after the transfer it will receive the last burst | |
888 | * request from peripheral and so transfer finishes. | |
889 | * | |
890 | * - Memory addresses are scattered and are not contiguous. | |
891 | * Here, Obviously as DMA controller doesn't know when a lli's | |
892 | * transfer gets over, it can't load next lli. So in this | |
893 | * case, there has to be an assumption that only one lli is | |
894 | * supported. Thus, we can't have scattered addresses. | |
895 | */ | |
896 | if (!bd.remainder) { | |
897 | u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> | |
898 | PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
899 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && | |
0a235657 | 900 | (fc <= PL080_FLOW_SRC2DST_SRC))) { |
b7f69d9d VK |
901 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", |
902 | __func__); | |
903 | return 0; | |
904 | } | |
0a235657 | 905 | |
b7f69d9d | 906 | if ((bd.srcbus.addr % bd.srcbus.buswidth) || |
880db3ff | 907 | (bd.dstbus.addr % bd.dstbus.buswidth)) { |
b7f69d9d VK |
908 | dev_err(&pl08x->adev->dev, |
909 | "%s src & dst address must be aligned to src" | |
910 | " & dst width if peripheral is flow controller", | |
911 | __func__); | |
912 | return 0; | |
913 | } | |
03af500f | 914 | |
b7f69d9d VK |
915 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
916 | bd.dstbus.buswidth, 0); | |
ba6785ff TF |
917 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
918 | 0, cctl); | |
b7f69d9d VK |
919 | break; |
920 | } | |
e8689e63 LW |
921 | |
922 | /* | |
b7f69d9d VK |
923 | * Send byte by byte for following cases |
924 | * - Less than a bus width available | |
925 | * - until master bus is aligned | |
e8689e63 | 926 | */ |
b7f69d9d VK |
927 | if (bd.remainder < mbus->buswidth) |
928 | early_bytes = bd.remainder; | |
929 | else if ((mbus->addr) % (mbus->buswidth)) { | |
930 | early_bytes = mbus->buswidth - (mbus->addr) % | |
931 | (mbus->buswidth); | |
932 | if ((bd.remainder - early_bytes) < mbus->buswidth) | |
933 | early_bytes = bd.remainder; | |
934 | } | |
e8689e63 | 935 | |
b7f69d9d VK |
936 | if (early_bytes) { |
937 | dev_vdbg(&pl08x->adev->dev, | |
938 | "%s byte width LLIs (remain 0x%08x)\n", | |
939 | __func__, bd.remainder); | |
ba6785ff TF |
940 | prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes, |
941 | num_llis++, &total_bytes); | |
e8689e63 LW |
942 | } |
943 | ||
b7f69d9d VK |
944 | if (bd.remainder) { |
945 | /* | |
946 | * Master now aligned | |
947 | * - if slave is not then we must set its width down | |
948 | */ | |
949 | if (sbus->addr % sbus->buswidth) { | |
950 | dev_dbg(&pl08x->adev->dev, | |
951 | "%s set down bus width to one byte\n", | |
952 | __func__); | |
fa6a940b | 953 | |
b7f69d9d VK |
954 | sbus->buswidth = 1; |
955 | } | |
e8689e63 LW |
956 | |
957 | /* | |
b7f69d9d VK |
958 | * Bytes transferred = tsize * src width, not |
959 | * MIN(buswidths) | |
e8689e63 | 960 | */ |
b7f69d9d VK |
961 | max_bytes_per_lli = bd.srcbus.buswidth * |
962 | PL080_CONTROL_TRANSFER_SIZE_MASK; | |
963 | dev_vdbg(&pl08x->adev->dev, | |
964 | "%s max bytes per lli = %zu\n", | |
965 | __func__, max_bytes_per_lli); | |
e8689e63 LW |
966 | |
967 | /* | |
b7f69d9d VK |
968 | * Make largest possible LLIs until less than one bus |
969 | * width left | |
e8689e63 | 970 | */ |
b7f69d9d VK |
971 | while (bd.remainder > (mbus->buswidth - 1)) { |
972 | size_t lli_len, tsize, width; | |
e8689e63 | 973 | |
b7f69d9d VK |
974 | /* |
975 | * If enough left try to send max possible, | |
976 | * otherwise try to send the remainder | |
977 | */ | |
978 | lli_len = min(bd.remainder, max_bytes_per_lli); | |
16a2e7d3 | 979 | |
b7f69d9d VK |
980 | /* |
981 | * Check against maximum bus alignment: | |
982 | * Calculate actual transfer size in relation to | |
983 | * bus width an get a maximum remainder of the | |
984 | * highest bus width - 1 | |
985 | */ | |
986 | width = max(mbus->buswidth, sbus->buswidth); | |
987 | lli_len = (lli_len / width) * width; | |
988 | tsize = lli_len / bd.srcbus.buswidth; | |
989 | ||
990 | dev_vdbg(&pl08x->adev->dev, | |
991 | "%s fill lli with single lli chunk of " | |
992 | "size 0x%08zx (remainder 0x%08zx)\n", | |
993 | __func__, lli_len, bd.remainder); | |
994 | ||
995 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, | |
16a2e7d3 | 996 | bd.dstbus.buswidth, tsize); |
ba6785ff | 997 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
b7f69d9d VK |
998 | lli_len, cctl); |
999 | total_bytes += lli_len; | |
1000 | } | |
e8689e63 | 1001 | |
b7f69d9d VK |
1002 | /* |
1003 | * Send any odd bytes | |
1004 | */ | |
1005 | if (bd.remainder) { | |
1006 | dev_vdbg(&pl08x->adev->dev, | |
1007 | "%s align with boundary, send odd bytes (remain %zu)\n", | |
1008 | __func__, bd.remainder); | |
ba6785ff TF |
1009 | prep_byte_width_lli(pl08x, &bd, &cctl, |
1010 | bd.remainder, num_llis++, &total_bytes); | |
b7f69d9d | 1011 | } |
e8689e63 | 1012 | } |
16a2e7d3 | 1013 | |
b7f69d9d VK |
1014 | if (total_bytes != dsg->len) { |
1015 | dev_err(&pl08x->adev->dev, | |
1016 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", | |
1017 | __func__, total_bytes, dsg->len); | |
1018 | return 0; | |
1019 | } | |
e8689e63 | 1020 | |
b7f69d9d VK |
1021 | if (num_llis >= MAX_NUM_TSFR_LLIS) { |
1022 | dev_err(&pl08x->adev->dev, | |
1023 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
ba6785ff | 1024 | __func__, MAX_NUM_TSFR_LLIS); |
b7f69d9d VK |
1025 | return 0; |
1026 | } | |
e8689e63 | 1027 | } |
b58b6b5b RKAL |
1028 | |
1029 | llis_va = txd->llis_va; | |
ba6785ff | 1030 | last_lli = llis_va + (num_llis - 1) * pl08x->lli_words; |
94ae8522 | 1031 | /* The final LLI terminates the LLI. */ |
ba6785ff | 1032 | last_lli[PL080_LLI_LLI] = 0; |
94ae8522 | 1033 | /* The final LLI element shall also fire an interrupt. */ |
ba6785ff | 1034 | last_lli[PL080_LLI_CCTL] |= PL080_CONTROL_TC_IRQ_EN; |
e8689e63 | 1035 | |
e8689e63 LW |
1036 | #ifdef VERBOSE_DEBUG |
1037 | { | |
1038 | int i; | |
1039 | ||
fc74eb79 RKAL |
1040 | dev_vdbg(&pl08x->adev->dev, |
1041 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
1042 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
e8689e63 LW |
1043 | for (i = 0; i < num_llis; i++) { |
1044 | dev_vdbg(&pl08x->adev->dev, | |
fc74eb79 | 1045 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
ba6785ff TF |
1046 | i, llis_va, llis_va[PL080_LLI_SRC], |
1047 | llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI], | |
1048 | llis_va[PL080_LLI_CCTL]); | |
1049 | llis_va += pl08x->lli_words; | |
e8689e63 LW |
1050 | } |
1051 | } | |
1052 | #endif | |
1053 | ||
1054 | return num_llis; | |
1055 | } | |
1056 | ||
e8689e63 LW |
1057 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, |
1058 | struct pl08x_txd *txd) | |
1059 | { | |
b7f69d9d VK |
1060 | struct pl08x_sg *dsg, *_dsg; |
1061 | ||
c1205646 VK |
1062 | if (txd->llis_va) |
1063 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); | |
e8689e63 | 1064 | |
b7f69d9d VK |
1065 | list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) { |
1066 | list_del(&dsg->node); | |
1067 | kfree(dsg); | |
1068 | } | |
1069 | ||
e8689e63 LW |
1070 | kfree(txd); |
1071 | } | |
1072 | ||
18536134 RK |
1073 | static void pl08x_unmap_buffers(struct pl08x_txd *txd) |
1074 | { | |
1075 | struct device *dev = txd->vd.tx.chan->device->dev; | |
1076 | struct pl08x_sg *dsg; | |
1077 | ||
1078 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
1079 | if (txd->vd.tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
1080 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1081 | dma_unmap_single(dev, dsg->src_addr, dsg->len, | |
1082 | DMA_TO_DEVICE); | |
1083 | else { | |
1084 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1085 | dma_unmap_page(dev, dsg->src_addr, dsg->len, | |
1086 | DMA_TO_DEVICE); | |
1087 | } | |
1088 | } | |
1089 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
1090 | if (txd->vd.tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
1091 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1092 | dma_unmap_single(dev, dsg->dst_addr, dsg->len, | |
1093 | DMA_FROM_DEVICE); | |
1094 | else | |
1095 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1096 | dma_unmap_page(dev, dsg->dst_addr, dsg->len, | |
1097 | DMA_FROM_DEVICE); | |
1098 | } | |
1099 | } | |
1100 | ||
1101 | static void pl08x_desc_free(struct virt_dma_desc *vd) | |
1102 | { | |
1103 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1104 | struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan); | |
18536134 RK |
1105 | |
1106 | if (!plchan->slave) | |
1107 | pl08x_unmap_buffers(txd); | |
1108 | ||
1109 | if (!txd->done) | |
1110 | pl08x_release_mux(plchan); | |
1111 | ||
18536134 | 1112 | pl08x_free_txd(plchan->host, txd); |
18536134 RK |
1113 | } |
1114 | ||
e8689e63 LW |
1115 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, |
1116 | struct pl08x_dma_chan *plchan) | |
1117 | { | |
ea160561 | 1118 | LIST_HEAD(head); |
e8689e63 | 1119 | |
879f127b | 1120 | vchan_get_all_descriptors(&plchan->vc, &head); |
91998261 | 1121 | vchan_dma_desc_free_list(&plchan->vc, &head); |
e8689e63 LW |
1122 | } |
1123 | ||
1124 | /* | |
1125 | * The DMA ENGINE API | |
1126 | */ | |
1127 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
1128 | { | |
1129 | return 0; | |
1130 | } | |
1131 | ||
1132 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
1133 | { | |
a068682c RK |
1134 | /* Ensure all queued descriptors are freed */ |
1135 | vchan_free_chan_resources(to_virt_chan(chan)); | |
e8689e63 LW |
1136 | } |
1137 | ||
e8689e63 LW |
1138 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( |
1139 | struct dma_chan *chan, unsigned long flags) | |
1140 | { | |
1141 | struct dma_async_tx_descriptor *retval = NULL; | |
1142 | ||
1143 | return retval; | |
1144 | } | |
1145 | ||
1146 | /* | |
94ae8522 RKAL |
1147 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
1148 | * If slaves are relying on interrupts to signal completion this function | |
1149 | * must not be called with interrupts disabled. | |
e8689e63 | 1150 | */ |
3e27ee84 VK |
1151 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
1152 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
1153 | { |
1154 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
06e885b7 RK |
1155 | struct virt_dma_desc *vd; |
1156 | unsigned long flags; | |
e8689e63 | 1157 | enum dma_status ret; |
06e885b7 | 1158 | size_t bytes = 0; |
e8689e63 | 1159 | |
96a2af41 RKAL |
1160 | ret = dma_cookie_status(chan, cookie, txstate); |
1161 | if (ret == DMA_SUCCESS) | |
e8689e63 | 1162 | return ret; |
e8689e63 | 1163 | |
06e885b7 RK |
1164 | /* |
1165 | * There's no point calculating the residue if there's | |
1166 | * no txstate to store the value. | |
1167 | */ | |
1168 | if (!txstate) { | |
1169 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1170 | ret = DMA_PAUSED; | |
1171 | return ret; | |
1172 | } | |
1173 | ||
1174 | spin_lock_irqsave(&plchan->vc.lock, flags); | |
1175 | ret = dma_cookie_status(chan, cookie, txstate); | |
1176 | if (ret != DMA_SUCCESS) { | |
1177 | vd = vchan_find_desc(&plchan->vc, cookie); | |
1178 | if (vd) { | |
1179 | /* On the issued list, so hasn't been processed yet */ | |
1180 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1181 | struct pl08x_sg *dsg; | |
1182 | ||
1183 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1184 | bytes += dsg->len; | |
1185 | } else { | |
1186 | bytes = pl08x_getbytes_chan(plchan); | |
1187 | } | |
1188 | } | |
1189 | spin_unlock_irqrestore(&plchan->vc.lock, flags); | |
1190 | ||
e8689e63 LW |
1191 | /* |
1192 | * This cookie not complete yet | |
96a2af41 | 1193 | * Get number of bytes left in the active transactions and queue |
e8689e63 | 1194 | */ |
06e885b7 | 1195 | dma_set_residue(txstate, bytes); |
e8689e63 | 1196 | |
06e885b7 RK |
1197 | if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS) |
1198 | ret = DMA_PAUSED; | |
e8689e63 LW |
1199 | |
1200 | /* Whether waiting or running, we're in progress */ | |
06e885b7 | 1201 | return ret; |
e8689e63 LW |
1202 | } |
1203 | ||
1204 | /* PrimeCell DMA extension */ | |
1205 | struct burst_table { | |
760596c6 | 1206 | u32 burstwords; |
e8689e63 LW |
1207 | u32 reg; |
1208 | }; | |
1209 | ||
1210 | static const struct burst_table burst_sizes[] = { | |
1211 | { | |
1212 | .burstwords = 256, | |
760596c6 | 1213 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
1214 | }, |
1215 | { | |
1216 | .burstwords = 128, | |
760596c6 | 1217 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
1218 | }, |
1219 | { | |
1220 | .burstwords = 64, | |
760596c6 | 1221 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
1222 | }, |
1223 | { | |
1224 | .burstwords = 32, | |
760596c6 | 1225 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
1226 | }, |
1227 | { | |
1228 | .burstwords = 16, | |
760596c6 | 1229 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
1230 | }, |
1231 | { | |
1232 | .burstwords = 8, | |
760596c6 | 1233 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1234 | }, |
1235 | { | |
1236 | .burstwords = 4, | |
760596c6 | 1237 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1238 | }, |
1239 | { | |
760596c6 RKAL |
1240 | .burstwords = 0, |
1241 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1242 | }, |
1243 | }; | |
1244 | ||
121c8476 RKAL |
1245 | /* |
1246 | * Given the source and destination available bus masks, select which | |
1247 | * will be routed to each port. We try to have source and destination | |
1248 | * on separate ports, but always respect the allowable settings. | |
1249 | */ | |
1250 | static u32 pl08x_select_bus(u8 src, u8 dst) | |
1251 | { | |
1252 | u32 cctl = 0; | |
1253 | ||
1254 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1255 | cctl |= PL080_CONTROL_DST_AHB2; | |
1256 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1257 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1258 | ||
1259 | return cctl; | |
1260 | } | |
1261 | ||
f14c426c RKAL |
1262 | static u32 pl08x_cctl(u32 cctl) |
1263 | { | |
1264 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1265 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1266 | PL080_CONTROL_PROT_MASK); | |
1267 | ||
1268 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1269 | return cctl | PL080_CONTROL_PROT_SYS; | |
1270 | } | |
1271 | ||
aa88cdaa RKAL |
1272 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1273 | { | |
1274 | switch (width) { | |
1275 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1276 | return PL080_WIDTH_8BIT; | |
1277 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1278 | return PL080_WIDTH_16BIT; | |
1279 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1280 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1281 | default: |
1282 | return ~0; | |
aa88cdaa | 1283 | } |
aa88cdaa RKAL |
1284 | } |
1285 | ||
760596c6 RKAL |
1286 | static u32 pl08x_burst(u32 maxburst) |
1287 | { | |
1288 | int i; | |
1289 | ||
1290 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1291 | if (burst_sizes[i].burstwords <= maxburst) | |
1292 | break; | |
1293 | ||
1294 | return burst_sizes[i].reg; | |
1295 | } | |
1296 | ||
9862ba17 RK |
1297 | static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan, |
1298 | enum dma_slave_buswidth addr_width, u32 maxburst) | |
1299 | { | |
1300 | u32 width, burst, cctl = 0; | |
1301 | ||
1302 | width = pl08x_width(addr_width); | |
1303 | if (width == ~0) | |
1304 | return ~0; | |
1305 | ||
1306 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; | |
1307 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1308 | ||
1309 | /* | |
1310 | * If this channel will only request single transfers, set this | |
1311 | * down to ONE element. Also select one element if no maxburst | |
1312 | * is specified. | |
1313 | */ | |
1314 | if (plchan->cd->single) | |
1315 | maxburst = 1; | |
1316 | ||
1317 | burst = pl08x_burst(maxburst); | |
1318 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1319 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
1320 | ||
1321 | return pl08x_cctl(cctl); | |
1322 | } | |
1323 | ||
f0fd9446 RKAL |
1324 | static int dma_set_runtime_config(struct dma_chan *chan, |
1325 | struct dma_slave_config *config) | |
e8689e63 LW |
1326 | { |
1327 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
b7f75865 RKAL |
1328 | |
1329 | if (!plchan->slave) | |
1330 | return -EINVAL; | |
e8689e63 | 1331 | |
dc8d5f8d RK |
1332 | /* Reject definitely invalid configurations */ |
1333 | if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || | |
1334 | config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
f0fd9446 | 1335 | return -EINVAL; |
e8689e63 | 1336 | |
ed91c13d RK |
1337 | plchan->cfg = *config; |
1338 | ||
f0fd9446 | 1339 | return 0; |
e8689e63 LW |
1340 | } |
1341 | ||
1342 | /* | |
1343 | * Slave transactions callback to the slave device to allow | |
1344 | * synchronization of slave DMA signals with the DMAC enable | |
1345 | */ | |
1346 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1347 | { | |
1348 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1349 | unsigned long flags; |
1350 | ||
083be28a | 1351 | spin_lock_irqsave(&plchan->vc.lock, flags); |
879f127b | 1352 | if (vchan_issue_pending(&plchan->vc)) { |
a5a488db RK |
1353 | if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING) |
1354 | pl08x_phy_alloc_and_start(plchan); | |
e8689e63 | 1355 | } |
083be28a | 1356 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1357 | } |
1358 | ||
879f127b | 1359 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan) |
ac3cd20d | 1360 | { |
b201c111 | 1361 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d RKAL |
1362 | |
1363 | if (txd) { | |
b7f69d9d | 1364 | INIT_LIST_HEAD(&txd->dsg_list); |
4983a04f RKAL |
1365 | |
1366 | /* Always enable error and terminal interrupts */ | |
1367 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1368 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1369 | } |
1370 | return txd; | |
1371 | } | |
1372 | ||
e8689e63 LW |
1373 | /* |
1374 | * Initialize a descriptor to be used by memcpy submit | |
1375 | */ | |
1376 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1377 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1378 | size_t len, unsigned long flags) | |
1379 | { | |
1380 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1381 | struct pl08x_driver_data *pl08x = plchan->host; | |
1382 | struct pl08x_txd *txd; | |
b7f69d9d | 1383 | struct pl08x_sg *dsg; |
e8689e63 LW |
1384 | int ret; |
1385 | ||
879f127b | 1386 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1387 | if (!txd) { |
1388 | dev_err(&pl08x->adev->dev, | |
1389 | "%s no memory for descriptor\n", __func__); | |
1390 | return NULL; | |
1391 | } | |
1392 | ||
b7f69d9d VK |
1393 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); |
1394 | if (!dsg) { | |
1395 | pl08x_free_txd(pl08x, txd); | |
1396 | dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n", | |
1397 | __func__); | |
1398 | return NULL; | |
1399 | } | |
1400 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1401 | ||
b7f69d9d VK |
1402 | dsg->src_addr = src; |
1403 | dsg->dst_addr = dest; | |
1404 | dsg->len = len; | |
e8689e63 LW |
1405 | |
1406 | /* Set platform data for m2m */ | |
4983a04f | 1407 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
dc8d5f8d | 1408 | txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy & |
c7da9a56 | 1409 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); |
4983a04f | 1410 | |
e8689e63 | 1411 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1412 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1413 | |
c7da9a56 | 1414 | if (pl08x->vd->dualmaster) |
121c8476 RKAL |
1415 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
1416 | pl08x->mem_buses); | |
e8689e63 | 1417 | |
aa4afb75 RK |
1418 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1419 | if (!ret) { | |
1420 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 1421 | return NULL; |
aa4afb75 | 1422 | } |
e8689e63 | 1423 | |
879f127b | 1424 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1425 | } |
1426 | ||
3e2a037c | 1427 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 | 1428 | struct dma_chan *chan, struct scatterlist *sgl, |
db8196df | 1429 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1430 | unsigned long flags, void *context) |
e8689e63 LW |
1431 | { |
1432 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1433 | struct pl08x_driver_data *pl08x = plchan->host; | |
1434 | struct pl08x_txd *txd; | |
b7f69d9d VK |
1435 | struct pl08x_sg *dsg; |
1436 | struct scatterlist *sg; | |
dc8d5f8d | 1437 | enum dma_slave_buswidth addr_width; |
b7f69d9d | 1438 | dma_addr_t slave_addr; |
0a235657 | 1439 | int ret, tmp; |
409ec8db | 1440 | u8 src_buses, dst_buses; |
dc8d5f8d | 1441 | u32 maxburst, cctl; |
e8689e63 | 1442 | |
e8689e63 | 1443 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", |
fdaf9c4b | 1444 | __func__, sg_dma_len(sgl), plchan->name); |
e8689e63 | 1445 | |
879f127b | 1446 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1447 | if (!txd) { |
1448 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1449 | return NULL; | |
1450 | } | |
1451 | ||
e8689e63 LW |
1452 | /* |
1453 | * Set up addresses, the PrimeCell configured address | |
1454 | * will take precedence since this may configure the | |
1455 | * channel target address dynamically at runtime. | |
1456 | */ | |
db8196df | 1457 | if (direction == DMA_MEM_TO_DEV) { |
dc8d5f8d | 1458 | cctl = PL080_CONTROL_SRC_INCR; |
ed91c13d | 1459 | slave_addr = plchan->cfg.dst_addr; |
dc8d5f8d RK |
1460 | addr_width = plchan->cfg.dst_addr_width; |
1461 | maxburst = plchan->cfg.dst_maxburst; | |
409ec8db RK |
1462 | src_buses = pl08x->mem_buses; |
1463 | dst_buses = plchan->cd->periph_buses; | |
db8196df | 1464 | } else if (direction == DMA_DEV_TO_MEM) { |
dc8d5f8d | 1465 | cctl = PL080_CONTROL_DST_INCR; |
ed91c13d | 1466 | slave_addr = plchan->cfg.src_addr; |
dc8d5f8d RK |
1467 | addr_width = plchan->cfg.src_addr_width; |
1468 | maxburst = plchan->cfg.src_maxburst; | |
409ec8db RK |
1469 | src_buses = plchan->cd->periph_buses; |
1470 | dst_buses = pl08x->mem_buses; | |
e8689e63 | 1471 | } else { |
b7f69d9d | 1472 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1473 | dev_err(&pl08x->adev->dev, |
1474 | "%s direction unsupported\n", __func__); | |
1475 | return NULL; | |
1476 | } | |
e8689e63 | 1477 | |
dc8d5f8d | 1478 | cctl |= pl08x_get_cctl(plchan, addr_width, maxburst); |
800d683e RK |
1479 | if (cctl == ~0) { |
1480 | pl08x_free_txd(pl08x, txd); | |
1481 | dev_err(&pl08x->adev->dev, | |
1482 | "DMA slave configuration botched?\n"); | |
1483 | return NULL; | |
1484 | } | |
1485 | ||
409ec8db RK |
1486 | txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses); |
1487 | ||
95442b22 | 1488 | if (plchan->cfg.device_fc) |
db8196df | 1489 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : |
0a235657 VK |
1490 | PL080_FLOW_PER2MEM_PER; |
1491 | else | |
db8196df | 1492 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER : |
0a235657 VK |
1493 | PL080_FLOW_PER2MEM; |
1494 | ||
1495 | txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1496 | ||
c48d4963 RK |
1497 | ret = pl08x_request_mux(plchan); |
1498 | if (ret < 0) { | |
1499 | pl08x_free_txd(pl08x, txd); | |
1500 | dev_dbg(&pl08x->adev->dev, | |
1501 | "unable to mux for transfer on %s due to platform restrictions\n", | |
1502 | plchan->name); | |
1503 | return NULL; | |
1504 | } | |
1505 | ||
1506 | dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n", | |
1507 | plchan->signal, plchan->name); | |
1508 | ||
1509 | /* Assign the flow control signal to this channel */ | |
1510 | if (direction == DMA_MEM_TO_DEV) | |
1511 | txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
1512 | else | |
1513 | txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
1514 | ||
b7f69d9d VK |
1515 | for_each_sg(sgl, sg, sg_len, tmp) { |
1516 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); | |
1517 | if (!dsg) { | |
c48d4963 | 1518 | pl08x_release_mux(plchan); |
b7f69d9d VK |
1519 | pl08x_free_txd(pl08x, txd); |
1520 | dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n", | |
1521 | __func__); | |
1522 | return NULL; | |
1523 | } | |
1524 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1525 | ||
1526 | dsg->len = sg_dma_len(sg); | |
db8196df | 1527 | if (direction == DMA_MEM_TO_DEV) { |
cbb796cc | 1528 | dsg->src_addr = sg_dma_address(sg); |
b7f69d9d VK |
1529 | dsg->dst_addr = slave_addr; |
1530 | } else { | |
1531 | dsg->src_addr = slave_addr; | |
cbb796cc | 1532 | dsg->dst_addr = sg_dma_address(sg); |
b7f69d9d VK |
1533 | } |
1534 | } | |
1535 | ||
aa4afb75 RK |
1536 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1537 | if (!ret) { | |
1538 | pl08x_release_mux(plchan); | |
1539 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 1540 | return NULL; |
aa4afb75 | 1541 | } |
e8689e63 | 1542 | |
879f127b | 1543 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1544 | } |
1545 | ||
1546 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1547 | unsigned long arg) | |
1548 | { | |
1549 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1550 | struct pl08x_driver_data *pl08x = plchan->host; | |
1551 | unsigned long flags; | |
1552 | int ret = 0; | |
1553 | ||
1554 | /* Controls applicable to inactive channels */ | |
1555 | if (cmd == DMA_SLAVE_CONFIG) { | |
f0fd9446 RKAL |
1556 | return dma_set_runtime_config(chan, |
1557 | (struct dma_slave_config *)arg); | |
e8689e63 LW |
1558 | } |
1559 | ||
1560 | /* | |
1561 | * Anything succeeds on channels with no physical allocation and | |
1562 | * no queued transfers. | |
1563 | */ | |
083be28a | 1564 | spin_lock_irqsave(&plchan->vc.lock, flags); |
e8689e63 | 1565 | if (!plchan->phychan && !plchan->at) { |
083be28a | 1566 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1567 | return 0; |
1568 | } | |
1569 | ||
1570 | switch (cmd) { | |
1571 | case DMA_TERMINATE_ALL: | |
1572 | plchan->state = PL08X_CHAN_IDLE; | |
1573 | ||
1574 | if (plchan->phychan) { | |
e8689e63 LW |
1575 | /* |
1576 | * Mark physical channel as free and free any slave | |
1577 | * signal | |
1578 | */ | |
a5a488db | 1579 | pl08x_phy_free(plchan); |
e8689e63 | 1580 | } |
e8689e63 LW |
1581 | /* Dequeue jobs and free LLIs */ |
1582 | if (plchan->at) { | |
18536134 | 1583 | pl08x_desc_free(&plchan->at->vd); |
e8689e63 LW |
1584 | plchan->at = NULL; |
1585 | } | |
1586 | /* Dequeue jobs not yet fired as well */ | |
1587 | pl08x_free_txd_list(pl08x, plchan); | |
1588 | break; | |
1589 | case DMA_PAUSE: | |
1590 | pl08x_pause_phy_chan(plchan->phychan); | |
1591 | plchan->state = PL08X_CHAN_PAUSED; | |
1592 | break; | |
1593 | case DMA_RESUME: | |
1594 | pl08x_resume_phy_chan(plchan->phychan); | |
1595 | plchan->state = PL08X_CHAN_RUNNING; | |
1596 | break; | |
1597 | default: | |
1598 | /* Unknown command */ | |
1599 | ret = -ENXIO; | |
1600 | break; | |
1601 | } | |
1602 | ||
083be28a | 1603 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1604 | |
1605 | return ret; | |
1606 | } | |
1607 | ||
1608 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1609 | { | |
7703eac9 | 1610 | struct pl08x_dma_chan *plchan; |
e8689e63 LW |
1611 | char *name = chan_id; |
1612 | ||
7703eac9 RKAL |
1613 | /* Reject channels for devices not bound to this driver */ |
1614 | if (chan->device->dev->driver != &pl08x_amba_driver.drv) | |
1615 | return false; | |
1616 | ||
1617 | plchan = to_pl08x_chan(chan); | |
1618 | ||
e8689e63 LW |
1619 | /* Check that the channel is not taken! */ |
1620 | if (!strcmp(plchan->name, name)) | |
1621 | return true; | |
1622 | ||
1623 | return false; | |
1624 | } | |
1625 | ||
1626 | /* | |
1627 | * Just check that the device is there and active | |
94ae8522 RKAL |
1628 | * TODO: turn this bit on/off depending on the number of physical channels |
1629 | * actually used, if it is zero... well shut it off. That will save some | |
1630 | * power. Cut the clock at the same time. | |
e8689e63 LW |
1631 | */ |
1632 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1633 | { | |
affa115e LW |
1634 | /* The Nomadik variant does not have the config register */ |
1635 | if (pl08x->vd->nomadik) | |
1636 | return; | |
48a59ef3 | 1637 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
e8689e63 LW |
1638 | } |
1639 | ||
e8689e63 LW |
1640 | static irqreturn_t pl08x_irq(int irq, void *dev) |
1641 | { | |
1642 | struct pl08x_driver_data *pl08x = dev; | |
28da2836 VK |
1643 | u32 mask = 0, err, tc, i; |
1644 | ||
1645 | /* check & clear - ERR & TC interrupts */ | |
1646 | err = readl(pl08x->base + PL080_ERR_STATUS); | |
1647 | if (err) { | |
1648 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", | |
1649 | __func__, err); | |
1650 | writel(err, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 | 1651 | } |
d29bf019 | 1652 | tc = readl(pl08x->base + PL080_TC_STATUS); |
28da2836 VK |
1653 | if (tc) |
1654 | writel(tc, pl08x->base + PL080_TC_CLEAR); | |
1655 | ||
1656 | if (!err && !tc) | |
1657 | return IRQ_NONE; | |
1658 | ||
e8689e63 | 1659 | for (i = 0; i < pl08x->vd->channels; i++) { |
28da2836 | 1660 | if (((1 << i) & err) || ((1 << i) & tc)) { |
e8689e63 LW |
1661 | /* Locate physical channel */ |
1662 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1663 | struct pl08x_dma_chan *plchan = phychan->serving; | |
a936e793 | 1664 | struct pl08x_txd *tx; |
e8689e63 | 1665 | |
28da2836 VK |
1666 | if (!plchan) { |
1667 | dev_err(&pl08x->adev->dev, | |
1668 | "%s Error TC interrupt on unused channel: 0x%08x\n", | |
1669 | __func__, i); | |
1670 | continue; | |
1671 | } | |
1672 | ||
083be28a | 1673 | spin_lock(&plchan->vc.lock); |
a936e793 RK |
1674 | tx = plchan->at; |
1675 | if (tx) { | |
1676 | plchan->at = NULL; | |
c48d4963 RK |
1677 | /* |
1678 | * This descriptor is done, release its mux | |
1679 | * reservation. | |
1680 | */ | |
1681 | pl08x_release_mux(plchan); | |
18536134 RK |
1682 | tx->done = true; |
1683 | vchan_cookie_complete(&tx->vd); | |
c33b644c | 1684 | |
a5a488db RK |
1685 | /* |
1686 | * And start the next descriptor (if any), | |
1687 | * otherwise free this channel. | |
1688 | */ | |
879f127b | 1689 | if (vchan_next_desc(&plchan->vc)) |
c33b644c | 1690 | pl08x_start_next_txd(plchan); |
a5a488db RK |
1691 | else |
1692 | pl08x_phy_free(plchan); | |
a936e793 | 1693 | } |
083be28a | 1694 | spin_unlock(&plchan->vc.lock); |
a936e793 | 1695 | |
e8689e63 LW |
1696 | mask |= (1 << i); |
1697 | } | |
1698 | } | |
e8689e63 LW |
1699 | |
1700 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1701 | } | |
1702 | ||
121c8476 RKAL |
1703 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
1704 | { | |
121c8476 RKAL |
1705 | chan->slave = true; |
1706 | chan->name = chan->cd->bus_id; | |
ed91c13d RK |
1707 | chan->cfg.src_addr = chan->cd->addr; |
1708 | chan->cfg.dst_addr = chan->cd->addr; | |
121c8476 RKAL |
1709 | } |
1710 | ||
e8689e63 LW |
1711 | /* |
1712 | * Initialise the DMAC memcpy/slave channels. | |
1713 | * Make a local wrapper to hold required data | |
1714 | */ | |
1715 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 1716 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
1717 | { |
1718 | struct pl08x_dma_chan *chan; | |
1719 | int i; | |
1720 | ||
1721 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 1722 | |
e8689e63 LW |
1723 | /* |
1724 | * Register as many many memcpy as we have physical channels, | |
1725 | * we won't always be able to use all but the code will have | |
1726 | * to cope with that situation. | |
1727 | */ | |
1728 | for (i = 0; i < channels; i++) { | |
b201c111 | 1729 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
e8689e63 LW |
1730 | if (!chan) { |
1731 | dev_err(&pl08x->adev->dev, | |
1732 | "%s no memory for channel\n", __func__); | |
1733 | return -ENOMEM; | |
1734 | } | |
1735 | ||
1736 | chan->host = pl08x; | |
1737 | chan->state = PL08X_CHAN_IDLE; | |
ad0de2ac | 1738 | chan->signal = -1; |
e8689e63 LW |
1739 | |
1740 | if (slave) { | |
e8689e63 | 1741 | chan->cd = &pl08x->pd->slave_channels[i]; |
121c8476 | 1742 | pl08x_dma_slave_init(chan); |
e8689e63 LW |
1743 | } else { |
1744 | chan->cd = &pl08x->pd->memcpy_channel; | |
1745 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1746 | if (!chan->name) { | |
1747 | kfree(chan); | |
1748 | return -ENOMEM; | |
1749 | } | |
1750 | } | |
175a5e61 | 1751 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
1752 | "initialize virtual channel \"%s\"\n", |
1753 | chan->name); | |
1754 | ||
18536134 | 1755 | chan->vc.desc_free = pl08x_desc_free; |
083be28a | 1756 | vchan_init(&chan->vc, dmadev); |
e8689e63 LW |
1757 | } |
1758 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1759 | i, slave ? "slave" : "memcpy"); | |
1760 | return i; | |
1761 | } | |
1762 | ||
1763 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1764 | { | |
1765 | struct pl08x_dma_chan *chan = NULL; | |
1766 | struct pl08x_dma_chan *next; | |
1767 | ||
1768 | list_for_each_entry_safe(chan, | |
01d8dc64 RK |
1769 | next, &dmadev->channels, vc.chan.device_node) { |
1770 | list_del(&chan->vc.chan.device_node); | |
e8689e63 LW |
1771 | kfree(chan); |
1772 | } | |
1773 | } | |
1774 | ||
1775 | #ifdef CONFIG_DEBUG_FS | |
1776 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1777 | { | |
1778 | switch (state) { | |
1779 | case PL08X_CHAN_IDLE: | |
1780 | return "idle"; | |
1781 | case PL08X_CHAN_RUNNING: | |
1782 | return "running"; | |
1783 | case PL08X_CHAN_PAUSED: | |
1784 | return "paused"; | |
1785 | case PL08X_CHAN_WAITING: | |
1786 | return "waiting"; | |
1787 | default: | |
1788 | break; | |
1789 | } | |
1790 | return "UNKNOWN STATE"; | |
1791 | } | |
1792 | ||
1793 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1794 | { | |
1795 | struct pl08x_driver_data *pl08x = s->private; | |
1796 | struct pl08x_dma_chan *chan; | |
1797 | struct pl08x_phy_chan *ch; | |
1798 | unsigned long flags; | |
1799 | int i; | |
1800 | ||
1801 | seq_printf(s, "PL08x physical channels:\n"); | |
1802 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1803 | seq_printf(s, "--------\t-----\n"); | |
1804 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1805 | struct pl08x_dma_chan *virt_chan; | |
1806 | ||
1807 | ch = &pl08x->phy_chans[i]; | |
1808 | ||
1809 | spin_lock_irqsave(&ch->lock, flags); | |
1810 | virt_chan = ch->serving; | |
1811 | ||
affa115e LW |
1812 | seq_printf(s, "%d\t\t%s%s\n", |
1813 | ch->id, | |
1814 | virt_chan ? virt_chan->name : "(none)", | |
1815 | ch->locked ? " LOCKED" : ""); | |
e8689e63 LW |
1816 | |
1817 | spin_unlock_irqrestore(&ch->lock, flags); | |
1818 | } | |
1819 | ||
1820 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1821 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1822 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1823 | list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) { |
3e2a037c | 1824 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1825 | pl08x_state_str(chan->state)); |
1826 | } | |
1827 | ||
1828 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1829 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1830 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1831 | list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) { |
3e2a037c | 1832 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1833 | pl08x_state_str(chan->state)); |
1834 | } | |
1835 | ||
1836 | return 0; | |
1837 | } | |
1838 | ||
1839 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1840 | { | |
1841 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1842 | } | |
1843 | ||
1844 | static const struct file_operations pl08x_debugfs_operations = { | |
1845 | .open = pl08x_debugfs_open, | |
1846 | .read = seq_read, | |
1847 | .llseek = seq_lseek, | |
1848 | .release = single_release, | |
1849 | }; | |
1850 | ||
1851 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1852 | { | |
1853 | /* Expose a simple debugfs interface to view all clocks */ | |
3e27ee84 VK |
1854 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
1855 | S_IFREG | S_IRUGO, NULL, pl08x, | |
1856 | &pl08x_debugfs_operations); | |
e8689e63 LW |
1857 | } |
1858 | ||
1859 | #else | |
1860 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1861 | { | |
1862 | } | |
1863 | #endif | |
1864 | ||
aa25afad | 1865 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
1866 | { |
1867 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1868 | const struct vendor_data *vd = id->data; |
ba6785ff | 1869 | u32 tsfr_size; |
e8689e63 LW |
1870 | int ret = 0; |
1871 | int i; | |
1872 | ||
1873 | ret = amba_request_regions(adev, NULL); | |
1874 | if (ret) | |
1875 | return ret; | |
1876 | ||
1877 | /* Create the driver state holder */ | |
b201c111 | 1878 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
1879 | if (!pl08x) { |
1880 | ret = -ENOMEM; | |
1881 | goto out_no_pl08x; | |
1882 | } | |
1883 | ||
1884 | /* Initialize memcpy engine */ | |
1885 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1886 | pl08x->memcpy.dev = &adev->dev; | |
1887 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1888 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1889 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1890 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1891 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1892 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1893 | pl08x->memcpy.device_control = pl08x_control; | |
1894 | ||
1895 | /* Initialize slave engine */ | |
1896 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1897 | pl08x->slave.dev = &adev->dev; | |
1898 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1899 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1900 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1901 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1902 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1903 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1904 | pl08x->slave.device_control = pl08x_control; | |
1905 | ||
1906 | /* Get the platform data */ | |
1907 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1908 | if (!pl08x->pd) { | |
1909 | dev_err(&adev->dev, "no platform data supplied\n"); | |
983d7beb | 1910 | ret = -EINVAL; |
e8689e63 LW |
1911 | goto out_no_platdata; |
1912 | } | |
1913 | ||
1914 | /* Assign useful pointers to the driver state */ | |
1915 | pl08x->adev = adev; | |
1916 | pl08x->vd = vd; | |
1917 | ||
30749cb4 RKAL |
1918 | /* By default, AHB1 only. If dualmaster, from platform */ |
1919 | pl08x->lli_buses = PL08X_AHB1; | |
1920 | pl08x->mem_buses = PL08X_AHB1; | |
1921 | if (pl08x->vd->dualmaster) { | |
1922 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
1923 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
1924 | } | |
1925 | ||
ba6785ff TF |
1926 | pl08x->lli_words = PL080_LLI_WORDS; |
1927 | tsfr_size = MAX_NUM_TSFR_LLIS * pl08x->lli_words * sizeof(u32); | |
1928 | ||
e8689e63 LW |
1929 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
1930 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
ba6785ff | 1931 | tsfr_size, PL08X_ALIGN, 0); |
e8689e63 LW |
1932 | if (!pl08x->pool) { |
1933 | ret = -ENOMEM; | |
1934 | goto out_no_lli_pool; | |
1935 | } | |
1936 | ||
e8689e63 LW |
1937 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); |
1938 | if (!pl08x->base) { | |
1939 | ret = -ENOMEM; | |
1940 | goto out_no_ioremap; | |
1941 | } | |
1942 | ||
1943 | /* Turn on the PL08x */ | |
1944 | pl08x_ensure_on(pl08x); | |
1945 | ||
94ae8522 | 1946 | /* Attach the interrupt handler */ |
e8689e63 LW |
1947 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
1948 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
1949 | ||
1950 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 1951 | DRIVER_NAME, pl08x); |
e8689e63 LW |
1952 | if (ret) { |
1953 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
1954 | __func__, adev->irq[0]); | |
1955 | goto out_no_irq; | |
1956 | } | |
1957 | ||
1958 | /* Initialize physical channels */ | |
affa115e | 1959 | pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
1960 | GFP_KERNEL); |
1961 | if (!pl08x->phy_chans) { | |
1962 | dev_err(&adev->dev, "%s failed to allocate " | |
1963 | "physical channel holders\n", | |
1964 | __func__); | |
983d7beb | 1965 | ret = -ENOMEM; |
e8689e63 LW |
1966 | goto out_no_phychans; |
1967 | } | |
1968 | ||
1969 | for (i = 0; i < vd->channels; i++) { | |
1970 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
1971 | ||
1972 | ch->id = i; | |
1973 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
d86ccea7 | 1974 | ch->reg_config = ch->base + vd->config_offset; |
e8689e63 | 1975 | spin_lock_init(&ch->lock); |
affa115e LW |
1976 | |
1977 | /* | |
1978 | * Nomadik variants can have channels that are locked | |
1979 | * down for the secure world only. Lock up these channels | |
1980 | * by perpetually serving a dummy virtual channel. | |
1981 | */ | |
1982 | if (vd->nomadik) { | |
1983 | u32 val; | |
1984 | ||
d86ccea7 | 1985 | val = readl(ch->reg_config); |
affa115e LW |
1986 | if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { |
1987 | dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i); | |
1988 | ch->locked = true; | |
1989 | } | |
1990 | } | |
1991 | ||
175a5e61 VK |
1992 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
1993 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
1994 | } |
1995 | ||
1996 | /* Register as many memcpy channels as there are physical channels */ | |
1997 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
1998 | pl08x->vd->channels, false); | |
1999 | if (ret <= 0) { | |
2000 | dev_warn(&pl08x->adev->dev, | |
2001 | "%s failed to enumerate memcpy channels - %d\n", | |
2002 | __func__, ret); | |
2003 | goto out_no_memcpy; | |
2004 | } | |
2005 | pl08x->memcpy.chancnt = ret; | |
2006 | ||
2007 | /* Register slave channels */ | |
2008 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
3e27ee84 | 2009 | pl08x->pd->num_slave_channels, true); |
e8689e63 LW |
2010 | if (ret <= 0) { |
2011 | dev_warn(&pl08x->adev->dev, | |
2012 | "%s failed to enumerate slave channels - %d\n", | |
2013 | __func__, ret); | |
2014 | goto out_no_slave; | |
2015 | } | |
2016 | pl08x->slave.chancnt = ret; | |
2017 | ||
2018 | ret = dma_async_device_register(&pl08x->memcpy); | |
2019 | if (ret) { | |
2020 | dev_warn(&pl08x->adev->dev, | |
2021 | "%s failed to register memcpy as an async device - %d\n", | |
2022 | __func__, ret); | |
2023 | goto out_no_memcpy_reg; | |
2024 | } | |
2025 | ||
2026 | ret = dma_async_device_register(&pl08x->slave); | |
2027 | if (ret) { | |
2028 | dev_warn(&pl08x->adev->dev, | |
2029 | "%s failed to register slave as an async device - %d\n", | |
2030 | __func__, ret); | |
2031 | goto out_no_slave_reg; | |
2032 | } | |
2033 | ||
2034 | amba_set_drvdata(adev, pl08x); | |
2035 | init_pl08x_debugfs(pl08x); | |
b05cd8f4 RKAL |
2036 | dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n", |
2037 | amba_part(adev), amba_rev(adev), | |
2038 | (unsigned long long)adev->res.start, adev->irq[0]); | |
b7b6018b | 2039 | |
e8689e63 LW |
2040 | return 0; |
2041 | ||
2042 | out_no_slave_reg: | |
2043 | dma_async_device_unregister(&pl08x->memcpy); | |
2044 | out_no_memcpy_reg: | |
2045 | pl08x_free_virtual_channels(&pl08x->slave); | |
2046 | out_no_slave: | |
2047 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2048 | out_no_memcpy: | |
2049 | kfree(pl08x->phy_chans); | |
2050 | out_no_phychans: | |
2051 | free_irq(adev->irq[0], pl08x); | |
2052 | out_no_irq: | |
2053 | iounmap(pl08x->base); | |
2054 | out_no_ioremap: | |
2055 | dma_pool_destroy(pl08x->pool); | |
2056 | out_no_lli_pool: | |
2057 | out_no_platdata: | |
2058 | kfree(pl08x); | |
2059 | out_no_pl08x: | |
2060 | amba_release_regions(adev); | |
2061 | return ret; | |
2062 | } | |
2063 | ||
2064 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2065 | static struct vendor_data vendor_pl080 = { | |
d86ccea7 | 2066 | .config_offset = PL080_CH_CONFIG, |
e8689e63 LW |
2067 | .channels = 8, |
2068 | .dualmaster = true, | |
2069 | }; | |
2070 | ||
affa115e | 2071 | static struct vendor_data vendor_nomadik = { |
d86ccea7 | 2072 | .config_offset = PL080_CH_CONFIG, |
affa115e LW |
2073 | .channels = 8, |
2074 | .dualmaster = true, | |
2075 | .nomadik = true, | |
2076 | }; | |
2077 | ||
e8689e63 | 2078 | static struct vendor_data vendor_pl081 = { |
d86ccea7 | 2079 | .config_offset = PL080_CH_CONFIG, |
e8689e63 LW |
2080 | .channels = 2, |
2081 | .dualmaster = false, | |
2082 | }; | |
2083 | ||
2084 | static struct amba_id pl08x_ids[] = { | |
2085 | /* PL080 */ | |
2086 | { | |
2087 | .id = 0x00041080, | |
2088 | .mask = 0x000fffff, | |
2089 | .data = &vendor_pl080, | |
2090 | }, | |
2091 | /* PL081 */ | |
2092 | { | |
2093 | .id = 0x00041081, | |
2094 | .mask = 0x000fffff, | |
2095 | .data = &vendor_pl081, | |
2096 | }, | |
2097 | /* Nomadik 8815 PL080 variant */ | |
2098 | { | |
affa115e | 2099 | .id = 0x00280080, |
e8689e63 | 2100 | .mask = 0x00ffffff, |
affa115e | 2101 | .data = &vendor_nomadik, |
e8689e63 LW |
2102 | }, |
2103 | { 0, 0 }, | |
2104 | }; | |
2105 | ||
037566df DM |
2106 | MODULE_DEVICE_TABLE(amba, pl08x_ids); |
2107 | ||
e8689e63 LW |
2108 | static struct amba_driver pl08x_amba_driver = { |
2109 | .drv.name = DRIVER_NAME, | |
2110 | .id_table = pl08x_ids, | |
2111 | .probe = pl08x_probe, | |
2112 | }; | |
2113 | ||
2114 | static int __init pl08x_init(void) | |
2115 | { | |
2116 | int retval; | |
2117 | retval = amba_driver_register(&pl08x_amba_driver); | |
2118 | if (retval) | |
2119 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2120 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2121 | retval); |
2122 | return retval; | |
2123 | } | |
2124 | subsys_initcall(pl08x_init); |