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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
94ae8522 RKAL |
22 | * The full GNU General Public License is in this distribution in the file |
23 | * called COPYING. | |
e8689e63 LW |
24 | * |
25 | * Documentation: ARM DDI 0196G == PL080 | |
94ae8522 | 26 | * Documentation: ARM DDI 0218E == PL081 |
da1b6c05 | 27 | * Documentation: S3C6410 User's Manual == PL080S |
e8689e63 | 28 | * |
94ae8522 RKAL |
29 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
30 | * channel. | |
e8689e63 LW |
31 | * |
32 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
33 | * has only two channels. So on these DMA controllers the number of channels | |
34 | * and the number of incoming DMA signals are two totally different things. | |
35 | * It is usually not possible to theoretically handle all physical signals, | |
36 | * so a multiplexing scheme with possible denial of use is necessary. | |
37 | * | |
38 | * The PL080 has a dual bus master, PL081 has a single master. | |
39 | * | |
da1b6c05 TF |
40 | * PL080S is a version modified by Samsung and used in S3C64xx SoCs. |
41 | * It differs in following aspects: | |
42 | * - CH_CONFIG register at different offset, | |
43 | * - separate CH_CONTROL2 register for transfer size, | |
44 | * - bigger maximum transfer size, | |
45 | * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word, | |
46 | * - no support for peripheral flow control. | |
47 | * | |
e8689e63 LW |
48 | * Memory to peripheral transfer may be visualized as |
49 | * Get data from memory to DMAC | |
50 | * Until no data left | |
51 | * On burst request from peripheral | |
52 | * Destination burst from DMAC to peripheral | |
53 | * Clear burst request | |
54 | * Raise terminal count interrupt | |
55 | * | |
56 | * For peripherals with a FIFO: | |
57 | * Source burst size == half the depth of the peripheral FIFO | |
58 | * Destination burst size == the depth of the peripheral FIFO | |
59 | * | |
60 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
61 | * signals, the DMA controller will simply facilitate its AHB master.) | |
62 | * | |
63 | * ASSUMES default (little) endianness for DMA transfers | |
64 | * | |
9dc2c200 RKAL |
65 | * The PL08x has two flow control settings: |
66 | * - DMAC flow control: the transfer size defines the number of transfers | |
67 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
68 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
69 | * to both the BREQ and SREQ signals (contrary to documented), | |
70 | * transferring data if either is active. The LBREQ and LSREQ signals | |
71 | * are ignored. | |
72 | * | |
73 | * - Peripheral flow control: the transfer size is ignored (and should be | |
74 | * zero). The data is transferred from the current LLI entry, until | |
75 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
da1b6c05 | 76 | * will then move to the next LLI entry. Unsupported by PL080S. |
e8689e63 | 77 | */ |
730404ac | 78 | #include <linux/amba/bus.h> |
e8689e63 LW |
79 | #include <linux/amba/pl08x.h> |
80 | #include <linux/debugfs.h> | |
0c38d701 VK |
81 | #include <linux/delay.h> |
82 | #include <linux/device.h> | |
83 | #include <linux/dmaengine.h> | |
84 | #include <linux/dmapool.h> | |
8516f52f | 85 | #include <linux/dma-mapping.h> |
0c38d701 VK |
86 | #include <linux/init.h> |
87 | #include <linux/interrupt.h> | |
88 | #include <linux/module.h> | |
b7b6018b | 89 | #include <linux/pm_runtime.h> |
e8689e63 | 90 | #include <linux/seq_file.h> |
0c38d701 | 91 | #include <linux/slab.h> |
3a95b9fb | 92 | #include <linux/amba/pl080.h> |
e8689e63 | 93 | |
d2ebfb33 | 94 | #include "dmaengine.h" |
01d8dc64 | 95 | #include "virt-dma.h" |
d2ebfb33 | 96 | |
e8689e63 LW |
97 | #define DRIVER_NAME "pl08xdmac" |
98 | ||
7703eac9 | 99 | static struct amba_driver pl08x_amba_driver; |
b23f204c | 100 | struct pl08x_driver_data; |
7703eac9 | 101 | |
e8689e63 | 102 | /** |
94ae8522 | 103 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
e8689e63 | 104 | * @channels: the number of channels available in this variant |
94ae8522 | 105 | * @dualmaster: whether this version supports dual AHB masters or not. |
affa115e LW |
106 | * @nomadik: whether the channels have Nomadik security extension bits |
107 | * that need to be checked for permission before use and some registers are | |
108 | * missing | |
da1b6c05 TF |
109 | * @pl080s: whether this version is a PL080S, which has separate register and |
110 | * LLI word for transfer size. | |
e8689e63 LW |
111 | */ |
112 | struct vendor_data { | |
d86ccea7 | 113 | u8 config_offset; |
e8689e63 LW |
114 | u8 channels; |
115 | bool dualmaster; | |
affa115e | 116 | bool nomadik; |
da1b6c05 | 117 | bool pl080s; |
e8689e63 LW |
118 | }; |
119 | ||
b23f204c RK |
120 | /** |
121 | * struct pl08x_bus_data - information of source or destination | |
122 | * busses for a transfer | |
123 | * @addr: current address | |
124 | * @maxwidth: the maximum width of a transfer on this bus | |
125 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | |
126 | */ | |
127 | struct pl08x_bus_data { | |
128 | dma_addr_t addr; | |
129 | u8 maxwidth; | |
130 | u8 buswidth; | |
131 | }; | |
132 | ||
133 | /** | |
134 | * struct pl08x_phy_chan - holder for the physical channels | |
135 | * @id: physical index to this channel | |
136 | * @lock: a lock to use when altering an instance of this struct | |
b23f204c RK |
137 | * @serving: the virtual channel currently being served by this physical |
138 | * channel | |
ad0de2ac RK |
139 | * @locked: channel unavailable for the system, e.g. dedicated to secure |
140 | * world | |
b23f204c RK |
141 | */ |
142 | struct pl08x_phy_chan { | |
143 | unsigned int id; | |
144 | void __iomem *base; | |
d86ccea7 | 145 | void __iomem *reg_config; |
b23f204c | 146 | spinlock_t lock; |
b23f204c | 147 | struct pl08x_dma_chan *serving; |
ad0de2ac | 148 | bool locked; |
b23f204c RK |
149 | }; |
150 | ||
151 | /** | |
152 | * struct pl08x_sg - structure containing data per sg | |
153 | * @src_addr: src address of sg | |
154 | * @dst_addr: dst address of sg | |
155 | * @len: transfer len in bytes | |
156 | * @node: node for txd's dsg_list | |
157 | */ | |
158 | struct pl08x_sg { | |
159 | dma_addr_t src_addr; | |
160 | dma_addr_t dst_addr; | |
161 | size_t len; | |
162 | struct list_head node; | |
163 | }; | |
164 | ||
165 | /** | |
166 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | |
01d8dc64 | 167 | * @vd: virtual DMA descriptor |
b23f204c | 168 | * @dsg_list: list of children sg's |
b23f204c RK |
169 | * @llis_bus: DMA memory address (physical) start for the LLIs |
170 | * @llis_va: virtual memory address start for the LLIs | |
171 | * @cctl: control reg values for current txd | |
172 | * @ccfg: config reg values for current txd | |
18536134 RK |
173 | * @done: this marks completed descriptors, which should not have their |
174 | * mux released. | |
b23f204c RK |
175 | */ |
176 | struct pl08x_txd { | |
01d8dc64 | 177 | struct virt_dma_desc vd; |
b23f204c | 178 | struct list_head dsg_list; |
b23f204c | 179 | dma_addr_t llis_bus; |
ba6785ff | 180 | u32 *llis_va; |
b23f204c RK |
181 | /* Default cctl value for LLIs */ |
182 | u32 cctl; | |
183 | /* | |
184 | * Settings to be put into the physical channel when we | |
185 | * trigger this txd. Other registers are in llis_va[0]. | |
186 | */ | |
187 | u32 ccfg; | |
18536134 | 188 | bool done; |
b23f204c RK |
189 | }; |
190 | ||
191 | /** | |
192 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel | |
193 | * states | |
194 | * @PL08X_CHAN_IDLE: the channel is idle | |
195 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | |
196 | * channel and is running a transfer on it | |
197 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport | |
198 | * channel, but the transfer is currently paused | |
199 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport | |
200 | * channel to become available (only pertains to memcpy channels) | |
201 | */ | |
202 | enum pl08x_dma_chan_state { | |
203 | PL08X_CHAN_IDLE, | |
204 | PL08X_CHAN_RUNNING, | |
205 | PL08X_CHAN_PAUSED, | |
206 | PL08X_CHAN_WAITING, | |
207 | }; | |
208 | ||
209 | /** | |
210 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | |
01d8dc64 | 211 | * @vc: wrappped virtual channel |
b23f204c | 212 | * @phychan: the physical channel utilized by this channel, if there is one |
b23f204c RK |
213 | * @name: name of channel |
214 | * @cd: channel platform data | |
215 | * @runtime_addr: address for RX/TX according to the runtime config | |
b23f204c RK |
216 | * @at: active transaction on this channel |
217 | * @lock: a lock for this channel data | |
218 | * @host: a pointer to the host (internal use) | |
219 | * @state: whether the channel is idle, paused, running etc | |
220 | * @slave: whether this channel is a device (slave) or for memcpy | |
ad0de2ac | 221 | * @signal: the physical DMA request signal which this channel is using |
5e2479bd | 222 | * @mux_use: count of descriptors using this DMA request signal setting |
b23f204c RK |
223 | */ |
224 | struct pl08x_dma_chan { | |
01d8dc64 | 225 | struct virt_dma_chan vc; |
b23f204c | 226 | struct pl08x_phy_chan *phychan; |
550ec36f | 227 | const char *name; |
b23f204c | 228 | const struct pl08x_channel_data *cd; |
ed91c13d | 229 | struct dma_slave_config cfg; |
b23f204c | 230 | struct pl08x_txd *at; |
b23f204c RK |
231 | struct pl08x_driver_data *host; |
232 | enum pl08x_dma_chan_state state; | |
233 | bool slave; | |
ad0de2ac | 234 | int signal; |
5e2479bd | 235 | unsigned mux_use; |
b23f204c RK |
236 | }; |
237 | ||
e8689e63 LW |
238 | /** |
239 | * struct pl08x_driver_data - the local state holder for the PL08x | |
240 | * @slave: slave engine for this instance | |
241 | * @memcpy: memcpy engine for this instance | |
242 | * @base: virtual memory base (remapped) for the PL08x | |
243 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
244 | * @vd: vendor data for this PL08x variant | |
245 | * @pd: platform data passed in from the platform/machine | |
246 | * @phy_chans: array of data for the physical channels | |
247 | * @pool: a pool for the LLI descriptors | |
3e27ee84 VK |
248 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
249 | * fetches | |
30749cb4 | 250 | * @mem_buses: set to indicate memory transfers on AHB2. |
e8689e63 LW |
251 | * @lock: a spinlock for this struct |
252 | */ | |
253 | struct pl08x_driver_data { | |
254 | struct dma_device slave; | |
255 | struct dma_device memcpy; | |
256 | void __iomem *base; | |
257 | struct amba_device *adev; | |
f96ca9ec | 258 | const struct vendor_data *vd; |
e8689e63 LW |
259 | struct pl08x_platform_data *pd; |
260 | struct pl08x_phy_chan *phy_chans; | |
261 | struct dma_pool *pool; | |
30749cb4 RKAL |
262 | u8 lli_buses; |
263 | u8 mem_buses; | |
ba6785ff | 264 | u8 lli_words; |
e8689e63 LW |
265 | }; |
266 | ||
267 | /* | |
268 | * PL08X specific defines | |
269 | */ | |
270 | ||
ba6785ff TF |
271 | /* The order of words in an LLI. */ |
272 | #define PL080_LLI_SRC 0 | |
273 | #define PL080_LLI_DST 1 | |
274 | #define PL080_LLI_LLI 2 | |
275 | #define PL080_LLI_CCTL 3 | |
da1b6c05 | 276 | #define PL080S_LLI_CCTL2 4 |
ba6785ff TF |
277 | |
278 | /* Total words in an LLI. */ | |
279 | #define PL080_LLI_WORDS 4 | |
da1b6c05 | 280 | #define PL080S_LLI_WORDS 8 |
e8689e63 | 281 | |
ba6785ff TF |
282 | /* |
283 | * Number of LLIs in each LLI buffer allocated for one transfer | |
284 | * (maximum times we call dma_pool_alloc on this pool without freeing) | |
285 | */ | |
286 | #define MAX_NUM_TSFR_LLIS 512 | |
e8689e63 LW |
287 | #define PL08X_ALIGN 8 |
288 | ||
289 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
290 | { | |
01d8dc64 | 291 | return container_of(chan, struct pl08x_dma_chan, vc.chan); |
e8689e63 LW |
292 | } |
293 | ||
501e67e8 RKAL |
294 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
295 | { | |
01d8dc64 | 296 | return container_of(tx, struct pl08x_txd, vd.tx); |
501e67e8 RKAL |
297 | } |
298 | ||
6b16c8b1 RK |
299 | /* |
300 | * Mux handling. | |
301 | * | |
302 | * This gives us the DMA request input to the PL08x primecell which the | |
303 | * peripheral described by the channel data will be routed to, possibly | |
304 | * via a board/SoC specific external MUX. One important point to note | |
305 | * here is that this does not depend on the physical channel. | |
306 | */ | |
ad0de2ac | 307 | static int pl08x_request_mux(struct pl08x_dma_chan *plchan) |
6b16c8b1 RK |
308 | { |
309 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
310 | int ret; | |
311 | ||
d7cabeed MB |
312 | if (plchan->mux_use++ == 0 && pd->get_xfer_signal) { |
313 | ret = pd->get_xfer_signal(plchan->cd); | |
5e2479bd RK |
314 | if (ret < 0) { |
315 | plchan->mux_use = 0; | |
6b16c8b1 | 316 | return ret; |
5e2479bd | 317 | } |
6b16c8b1 | 318 | |
ad0de2ac | 319 | plchan->signal = ret; |
6b16c8b1 RK |
320 | } |
321 | return 0; | |
322 | } | |
323 | ||
324 | static void pl08x_release_mux(struct pl08x_dma_chan *plchan) | |
325 | { | |
326 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
327 | ||
5e2479bd RK |
328 | if (plchan->signal >= 0) { |
329 | WARN_ON(plchan->mux_use == 0); | |
330 | ||
d7cabeed MB |
331 | if (--plchan->mux_use == 0 && pd->put_xfer_signal) { |
332 | pd->put_xfer_signal(plchan->cd, plchan->signal); | |
5e2479bd RK |
333 | plchan->signal = -1; |
334 | } | |
6b16c8b1 RK |
335 | } |
336 | } | |
337 | ||
e8689e63 LW |
338 | /* |
339 | * Physical channel handling | |
340 | */ | |
341 | ||
342 | /* Whether a certain channel is busy or not */ | |
343 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
344 | { | |
345 | unsigned int val; | |
346 | ||
d86ccea7 | 347 | val = readl(ch->reg_config); |
e8689e63 LW |
348 | return val & PL080_CONFIG_ACTIVE; |
349 | } | |
350 | ||
ba6785ff TF |
351 | static void pl08x_write_lli(struct pl08x_driver_data *pl08x, |
352 | struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg) | |
353 | { | |
da1b6c05 TF |
354 | if (pl08x->vd->pl080s) |
355 | dev_vdbg(&pl08x->adev->dev, | |
356 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
357 | "clli=0x%08x, cctl=0x%08x, cctl2=0x%08x, ccfg=0x%08x\n", | |
358 | phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST], | |
359 | lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], | |
360 | lli[PL080S_LLI_CCTL2], ccfg); | |
361 | else | |
362 | dev_vdbg(&pl08x->adev->dev, | |
363 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
364 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", | |
365 | phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST], | |
366 | lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg); | |
ba6785ff TF |
367 | |
368 | writel_relaxed(lli[PL080_LLI_SRC], phychan->base + PL080_CH_SRC_ADDR); | |
369 | writel_relaxed(lli[PL080_LLI_DST], phychan->base + PL080_CH_DST_ADDR); | |
370 | writel_relaxed(lli[PL080_LLI_LLI], phychan->base + PL080_CH_LLI); | |
371 | writel_relaxed(lli[PL080_LLI_CCTL], phychan->base + PL080_CH_CONTROL); | |
372 | ||
da1b6c05 TF |
373 | if (pl08x->vd->pl080s) |
374 | writel_relaxed(lli[PL080S_LLI_CCTL2], | |
375 | phychan->base + PL080S_CH_CONTROL2); | |
376 | ||
ba6785ff TF |
377 | writel(ccfg, phychan->reg_config); |
378 | } | |
379 | ||
e8689e63 LW |
380 | /* |
381 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 382 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
383 | * been set when the LLIs were constructed. Poke them into the hardware |
384 | * and start the transfer. | |
e8689e63 | 385 | */ |
eab82533 | 386 | static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) |
e8689e63 | 387 | { |
c885bee4 | 388 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 389 | struct pl08x_phy_chan *phychan = plchan->phychan; |
879f127b RK |
390 | struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc); |
391 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
09b3c323 | 392 | u32 val; |
c885bee4 | 393 | |
879f127b | 394 | list_del(&txd->vd.node); |
eab82533 | 395 | |
c885bee4 | 396 | plchan->at = txd; |
e8689e63 | 397 | |
c885bee4 RKAL |
398 | /* Wait for channel inactive */ |
399 | while (pl08x_phy_channel_busy(phychan)) | |
400 | cpu_relax(); | |
e8689e63 | 401 | |
ba6785ff | 402 | pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg); |
c885bee4 RKAL |
403 | |
404 | /* Enable the DMA channel */ | |
405 | /* Do not access config register until channel shows as disabled */ | |
406 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 407 | cpu_relax(); |
e8689e63 | 408 | |
c885bee4 | 409 | /* Do not access config register until channel shows as inactive */ |
d86ccea7 | 410 | val = readl(phychan->reg_config); |
e8689e63 | 411 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
d86ccea7 | 412 | val = readl(phychan->reg_config); |
e8689e63 | 413 | |
d86ccea7 | 414 | writel(val | PL080_CONFIG_ENABLE, phychan->reg_config); |
e8689e63 LW |
415 | } |
416 | ||
417 | /* | |
81796616 | 418 | * Pause the channel by setting the HALT bit. |
e8689e63 | 419 | * |
81796616 RKAL |
420 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
421 | * the FIFO can only drain if the peripheral is still requesting data. | |
422 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 423 | * |
81796616 RKAL |
424 | * For P->M transfers, disable the peripheral first to stop it filling |
425 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
426 | */ |
427 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
428 | { | |
429 | u32 val; | |
81796616 | 430 | int timeout; |
e8689e63 LW |
431 | |
432 | /* Set the HALT bit and wait for the FIFO to drain */ | |
d86ccea7 | 433 | val = readl(ch->reg_config); |
e8689e63 | 434 | val |= PL080_CONFIG_HALT; |
d86ccea7 | 435 | writel(val, ch->reg_config); |
e8689e63 LW |
436 | |
437 | /* Wait for channel inactive */ | |
81796616 RKAL |
438 | for (timeout = 1000; timeout; timeout--) { |
439 | if (!pl08x_phy_channel_busy(ch)) | |
440 | break; | |
441 | udelay(1); | |
442 | } | |
443 | if (pl08x_phy_channel_busy(ch)) | |
444 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
445 | } |
446 | ||
447 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
448 | { | |
449 | u32 val; | |
450 | ||
451 | /* Clear the HALT bit */ | |
d86ccea7 | 452 | val = readl(ch->reg_config); |
e8689e63 | 453 | val &= ~PL080_CONFIG_HALT; |
d86ccea7 | 454 | writel(val, ch->reg_config); |
e8689e63 LW |
455 | } |
456 | ||
fb526210 RKAL |
457 | /* |
458 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
459 | * clears any pending interrupt status. This should not be used for | |
460 | * an on-going transfer, but as a method of shutting down a channel | |
461 | * (eg, when it's no longer used) or terminating a transfer. | |
462 | */ | |
463 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
464 | struct pl08x_phy_chan *ch) | |
e8689e63 | 465 | { |
d86ccea7 | 466 | u32 val = readl(ch->reg_config); |
e8689e63 | 467 | |
fb526210 RKAL |
468 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
469 | PL080_CONFIG_TC_IRQ_MASK); | |
e8689e63 | 470 | |
d86ccea7 | 471 | writel(val, ch->reg_config); |
fb526210 RKAL |
472 | |
473 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); | |
474 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
475 | } |
476 | ||
477 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
478 | { | |
479 | /* The source width defines the number of bytes */ | |
480 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
481 | ||
482 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
483 | case PL080_WIDTH_8BIT: | |
484 | break; | |
485 | case PL080_WIDTH_16BIT: | |
486 | bytes *= 2; | |
487 | break; | |
488 | case PL080_WIDTH_32BIT: | |
489 | bytes *= 4; | |
490 | break; | |
491 | } | |
492 | return bytes; | |
493 | } | |
494 | ||
da1b6c05 TF |
495 | static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1) |
496 | { | |
497 | /* The source width defines the number of bytes */ | |
498 | u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK; | |
499 | ||
500 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
501 | case PL080_WIDTH_8BIT: | |
502 | break; | |
503 | case PL080_WIDTH_16BIT: | |
504 | bytes *= 2; | |
505 | break; | |
506 | case PL080_WIDTH_32BIT: | |
507 | bytes *= 4; | |
508 | break; | |
509 | } | |
510 | return bytes; | |
511 | } | |
512 | ||
e8689e63 LW |
513 | /* The channel should be paused when calling this */ |
514 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
515 | { | |
ba6785ff TF |
516 | struct pl08x_driver_data *pl08x = plchan->host; |
517 | const u32 *llis_va, *llis_va_limit; | |
e8689e63 | 518 | struct pl08x_phy_chan *ch; |
68a7faa2 | 519 | dma_addr_t llis_bus; |
e8689e63 | 520 | struct pl08x_txd *txd; |
ba6785ff | 521 | u32 llis_max_words; |
68a7faa2 | 522 | size_t bytes; |
68a7faa2 | 523 | u32 clli; |
e8689e63 | 524 | |
e8689e63 LW |
525 | ch = plchan->phychan; |
526 | txd = plchan->at; | |
527 | ||
68a7faa2 TF |
528 | if (!ch || !txd) |
529 | return 0; | |
530 | ||
e8689e63 | 531 | /* |
db9f136a RKAL |
532 | * Follow the LLIs to get the number of remaining |
533 | * bytes in the currently active transaction. | |
e8689e63 | 534 | */ |
68a7faa2 | 535 | clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 536 | |
68a7faa2 | 537 | /* First get the remaining bytes in the active transfer */ |
da1b6c05 TF |
538 | if (pl08x->vd->pl080s) |
539 | bytes = get_bytes_in_cctl_pl080s( | |
540 | readl(ch->base + PL080_CH_CONTROL), | |
541 | readl(ch->base + PL080S_CH_CONTROL2)); | |
542 | else | |
543 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); | |
e8689e63 | 544 | |
68a7faa2 TF |
545 | if (!clli) |
546 | return bytes; | |
db9f136a | 547 | |
68a7faa2 TF |
548 | llis_va = txd->llis_va; |
549 | llis_bus = txd->llis_bus; | |
550 | ||
ba6785ff | 551 | llis_max_words = pl08x->lli_words * MAX_NUM_TSFR_LLIS; |
68a7faa2 | 552 | BUG_ON(clli < llis_bus || clli >= llis_bus + |
ba6785ff | 553 | sizeof(u32) * llis_max_words); |
e8689e63 | 554 | |
68a7faa2 TF |
555 | /* |
556 | * Locate the next LLI - as this is an array, | |
557 | * it's simple maths to find. | |
558 | */ | |
ba6785ff | 559 | llis_va += (clli - llis_bus) / sizeof(u32); |
68a7faa2 | 560 | |
ba6785ff TF |
561 | llis_va_limit = llis_va + llis_max_words; |
562 | ||
563 | for (; llis_va < llis_va_limit; llis_va += pl08x->lli_words) { | |
da1b6c05 TF |
564 | if (pl08x->vd->pl080s) |
565 | bytes += get_bytes_in_cctl_pl080s( | |
566 | llis_va[PL080_LLI_CCTL], | |
567 | llis_va[PL080S_LLI_CCTL2]); | |
568 | else | |
569 | bytes += get_bytes_in_cctl(llis_va[PL080_LLI_CCTL]); | |
68a7faa2 TF |
570 | |
571 | /* | |
572 | * A LLI pointer of 0 terminates the LLI list | |
573 | */ | |
ba6785ff | 574 | if (!llis_va[PL080_LLI_LLI]) |
68a7faa2 | 575 | break; |
e8689e63 LW |
576 | } |
577 | ||
e8689e63 LW |
578 | return bytes; |
579 | } | |
580 | ||
581 | /* | |
582 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
583 | * |
584 | * Try to locate a physical channel to be used for this transfer. If all | |
585 | * are taken return NULL and the requester will have to cope by using | |
586 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
587 | */ |
588 | static struct pl08x_phy_chan * | |
589 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
590 | struct pl08x_dma_chan *virt_chan) | |
591 | { | |
592 | struct pl08x_phy_chan *ch = NULL; | |
593 | unsigned long flags; | |
594 | int i; | |
595 | ||
e8689e63 LW |
596 | for (i = 0; i < pl08x->vd->channels; i++) { |
597 | ch = &pl08x->phy_chans[i]; | |
598 | ||
599 | spin_lock_irqsave(&ch->lock, flags); | |
600 | ||
affa115e | 601 | if (!ch->locked && !ch->serving) { |
e8689e63 | 602 | ch->serving = virt_chan; |
e8689e63 LW |
603 | spin_unlock_irqrestore(&ch->lock, flags); |
604 | break; | |
605 | } | |
606 | ||
607 | spin_unlock_irqrestore(&ch->lock, flags); | |
608 | } | |
609 | ||
610 | if (i == pl08x->vd->channels) { | |
611 | /* No physical channel available, cope with it */ | |
612 | return NULL; | |
613 | } | |
614 | ||
615 | return ch; | |
616 | } | |
617 | ||
a5a488db | 618 | /* Mark the physical channel as free. Note, this write is atomic. */ |
e8689e63 LW |
619 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, |
620 | struct pl08x_phy_chan *ch) | |
621 | { | |
a5a488db RK |
622 | ch->serving = NULL; |
623 | } | |
e8689e63 | 624 | |
a5a488db RK |
625 | /* |
626 | * Try to allocate a physical channel. When successful, assign it to | |
627 | * this virtual channel, and initiate the next descriptor. The | |
628 | * virtual channel lock must be held at this point. | |
629 | */ | |
630 | static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan) | |
631 | { | |
632 | struct pl08x_driver_data *pl08x = plchan->host; | |
633 | struct pl08x_phy_chan *ch; | |
fb526210 | 634 | |
a5a488db RK |
635 | ch = pl08x_get_phy_channel(pl08x, plchan); |
636 | if (!ch) { | |
637 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
638 | plchan->state = PL08X_CHAN_WAITING; | |
639 | return; | |
640 | } | |
e8689e63 | 641 | |
a5a488db RK |
642 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n", |
643 | ch->id, plchan->name); | |
644 | ||
645 | plchan->phychan = ch; | |
646 | plchan->state = PL08X_CHAN_RUNNING; | |
647 | pl08x_start_next_txd(plchan); | |
648 | } | |
649 | ||
650 | static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch, | |
651 | struct pl08x_dma_chan *plchan) | |
652 | { | |
653 | struct pl08x_driver_data *pl08x = plchan->host; | |
654 | ||
655 | dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n", | |
656 | ch->id, plchan->name); | |
657 | ||
658 | /* | |
659 | * We do this without taking the lock; we're really only concerned | |
660 | * about whether this pointer is NULL or not, and we're guaranteed | |
661 | * that this will only be called when it _already_ is non-NULL. | |
662 | */ | |
663 | ch->serving = plchan; | |
664 | plchan->phychan = ch; | |
665 | plchan->state = PL08X_CHAN_RUNNING; | |
666 | pl08x_start_next_txd(plchan); | |
667 | } | |
668 | ||
669 | /* | |
670 | * Free a physical DMA channel, potentially reallocating it to another | |
671 | * virtual channel if we have any pending. | |
672 | */ | |
673 | static void pl08x_phy_free(struct pl08x_dma_chan *plchan) | |
674 | { | |
675 | struct pl08x_driver_data *pl08x = plchan->host; | |
676 | struct pl08x_dma_chan *p, *next; | |
677 | ||
678 | retry: | |
679 | next = NULL; | |
680 | ||
681 | /* Find a waiting virtual channel for the next transfer. */ | |
01d8dc64 | 682 | list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node) |
a5a488db RK |
683 | if (p->state == PL08X_CHAN_WAITING) { |
684 | next = p; | |
685 | break; | |
686 | } | |
687 | ||
688 | if (!next) { | |
01d8dc64 | 689 | list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node) |
a5a488db RK |
690 | if (p->state == PL08X_CHAN_WAITING) { |
691 | next = p; | |
692 | break; | |
693 | } | |
694 | } | |
695 | ||
696 | /* Ensure that the physical channel is stopped */ | |
697 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); | |
698 | ||
699 | if (next) { | |
700 | bool success; | |
701 | ||
702 | /* | |
703 | * Eww. We know this isn't going to deadlock | |
704 | * but lockdep probably doesn't. | |
705 | */ | |
083be28a | 706 | spin_lock(&next->vc.lock); |
a5a488db RK |
707 | /* Re-check the state now that we have the lock */ |
708 | success = next->state == PL08X_CHAN_WAITING; | |
709 | if (success) | |
710 | pl08x_phy_reassign_start(plchan->phychan, next); | |
083be28a | 711 | spin_unlock(&next->vc.lock); |
a5a488db RK |
712 | |
713 | /* If the state changed, try to find another channel */ | |
714 | if (!success) | |
715 | goto retry; | |
716 | } else { | |
717 | /* No more jobs, so free up the physical channel */ | |
718 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
719 | } | |
720 | ||
721 | plchan->phychan = NULL; | |
722 | plchan->state = PL08X_CHAN_IDLE; | |
e8689e63 LW |
723 | } |
724 | ||
725 | /* | |
726 | * LLI handling | |
727 | */ | |
728 | ||
729 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
730 | { | |
731 | switch (coded) { | |
732 | case PL080_WIDTH_8BIT: | |
733 | return 1; | |
734 | case PL080_WIDTH_16BIT: | |
735 | return 2; | |
736 | case PL080_WIDTH_32BIT: | |
737 | return 4; | |
738 | default: | |
739 | break; | |
740 | } | |
741 | BUG(); | |
742 | return 0; | |
743 | } | |
744 | ||
745 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 746 | size_t tsize) |
e8689e63 LW |
747 | { |
748 | u32 retbits = cctl; | |
749 | ||
e8b5e11d | 750 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
751 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
752 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
753 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
754 | ||
755 | /* Then set the bits according to the parameters */ | |
756 | switch (srcwidth) { | |
757 | case 1: | |
758 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
759 | break; | |
760 | case 2: | |
761 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
762 | break; | |
763 | case 4: | |
764 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
765 | break; | |
766 | default: | |
767 | BUG(); | |
768 | break; | |
769 | } | |
770 | ||
771 | switch (dstwidth) { | |
772 | case 1: | |
773 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
774 | break; | |
775 | case 2: | |
776 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
777 | break; | |
778 | case 4: | |
779 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
780 | break; | |
781 | default: | |
782 | BUG(); | |
783 | break; | |
784 | } | |
785 | ||
786 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
787 | return retbits; | |
788 | } | |
789 | ||
542361f8 RKAL |
790 | struct pl08x_lli_build_data { |
791 | struct pl08x_txd *txd; | |
542361f8 RKAL |
792 | struct pl08x_bus_data srcbus; |
793 | struct pl08x_bus_data dstbus; | |
794 | size_t remainder; | |
25c94f7f | 795 | u32 lli_bus; |
542361f8 RKAL |
796 | }; |
797 | ||
e8689e63 | 798 | /* |
0532e6fc VK |
799 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
800 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
801 | * masters address with width requirements of transfer (by sending few byte by | |
802 | * byte data), slave is still not aligned, then its width will be reduced to | |
803 | * BYTE. | |
804 | * - prefers the destination bus if both available | |
036f05fd | 805 | * - prefers bus with fixed address (i.e. peripheral) |
e8689e63 | 806 | */ |
542361f8 RKAL |
807 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
808 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) | |
e8689e63 LW |
809 | { |
810 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
542361f8 RKAL |
811 | *mbus = &bd->dstbus; |
812 | *sbus = &bd->srcbus; | |
036f05fd VK |
813 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
814 | *mbus = &bd->srcbus; | |
815 | *sbus = &bd->dstbus; | |
e8689e63 | 816 | } else { |
036f05fd | 817 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
542361f8 RKAL |
818 | *mbus = &bd->dstbus; |
819 | *sbus = &bd->srcbus; | |
036f05fd | 820 | } else { |
542361f8 RKAL |
821 | *mbus = &bd->srcbus; |
822 | *sbus = &bd->dstbus; | |
e8689e63 LW |
823 | } |
824 | } | |
825 | } | |
826 | ||
827 | /* | |
94ae8522 | 828 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 829 | */ |
ba6785ff TF |
830 | static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x, |
831 | struct pl08x_lli_build_data *bd, | |
da1b6c05 | 832 | int num_llis, int len, u32 cctl, u32 cctl2) |
e8689e63 | 833 | { |
ba6785ff TF |
834 | u32 offset = num_llis * pl08x->lli_words; |
835 | u32 *llis_va = bd->txd->llis_va + offset; | |
542361f8 | 836 | dma_addr_t llis_bus = bd->txd->llis_bus; |
e8689e63 LW |
837 | |
838 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
839 | ||
ba6785ff TF |
840 | /* Advance the offset to next LLI. */ |
841 | offset += pl08x->lli_words; | |
842 | ||
843 | llis_va[PL080_LLI_SRC] = bd->srcbus.addr; | |
844 | llis_va[PL080_LLI_DST] = bd->dstbus.addr; | |
845 | llis_va[PL080_LLI_LLI] = (llis_bus + sizeof(u32) * offset); | |
846 | llis_va[PL080_LLI_LLI] |= bd->lli_bus; | |
847 | llis_va[PL080_LLI_CCTL] = cctl; | |
da1b6c05 TF |
848 | if (pl08x->vd->pl080s) |
849 | llis_va[PL080S_LLI_CCTL2] = cctl2; | |
e8689e63 LW |
850 | |
851 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 | 852 | bd->srcbus.addr += len; |
e8689e63 | 853 | if (cctl & PL080_CONTROL_DST_INCR) |
542361f8 | 854 | bd->dstbus.addr += len; |
e8689e63 | 855 | |
542361f8 | 856 | BUG_ON(bd->remainder < len); |
cace6585 | 857 | |
542361f8 | 858 | bd->remainder -= len; |
e8689e63 LW |
859 | } |
860 | ||
ba6785ff TF |
861 | static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x, |
862 | struct pl08x_lli_build_data *bd, u32 *cctl, u32 len, | |
863 | int num_llis, size_t *total_bytes) | |
e8689e63 | 864 | { |
03af500f | 865 | *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); |
da1b6c05 | 866 | pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl, len); |
03af500f | 867 | (*total_bytes) += len; |
e8689e63 LW |
868 | } |
869 | ||
48924e42 TF |
870 | #ifdef VERBOSE_DEBUG |
871 | static void pl08x_dump_lli(struct pl08x_driver_data *pl08x, | |
872 | const u32 *llis_va, int num_llis) | |
873 | { | |
874 | int i; | |
875 | ||
da1b6c05 | 876 | if (pl08x->vd->pl080s) { |
48924e42 | 877 | dev_vdbg(&pl08x->adev->dev, |
da1b6c05 TF |
878 | "%-3s %-9s %-10s %-10s %-10s %-10s %s\n", |
879 | "lli", "", "csrc", "cdst", "clli", "cctl", "cctl2"); | |
880 | for (i = 0; i < num_llis; i++) { | |
881 | dev_vdbg(&pl08x->adev->dev, | |
882 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
883 | i, llis_va, llis_va[PL080_LLI_SRC], | |
884 | llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI], | |
885 | llis_va[PL080_LLI_CCTL], | |
886 | llis_va[PL080S_LLI_CCTL2]); | |
887 | llis_va += pl08x->lli_words; | |
888 | } | |
889 | } else { | |
890 | dev_vdbg(&pl08x->adev->dev, | |
891 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
892 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
893 | for (i = 0; i < num_llis; i++) { | |
894 | dev_vdbg(&pl08x->adev->dev, | |
895 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
896 | i, llis_va, llis_va[PL080_LLI_SRC], | |
897 | llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI], | |
898 | llis_va[PL080_LLI_CCTL]); | |
899 | llis_va += pl08x->lli_words; | |
900 | } | |
48924e42 TF |
901 | } |
902 | } | |
903 | #else | |
904 | static inline void pl08x_dump_lli(struct pl08x_driver_data *pl08x, | |
905 | const u32 *llis_va, int num_llis) {} | |
906 | #endif | |
907 | ||
e8689e63 LW |
908 | /* |
909 | * This fills in the table of LLIs for the transfer descriptor | |
910 | * Note that we assume we never have to change the burst sizes | |
911 | * Return 0 for error | |
912 | */ | |
913 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
914 | struct pl08x_txd *txd) | |
915 | { | |
e8689e63 | 916 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 917 | struct pl08x_lli_build_data bd; |
e8689e63 | 918 | int num_llis = 0; |
03af500f | 919 | u32 cctl, early_bytes = 0; |
b7f69d9d | 920 | size_t max_bytes_per_lli, total_bytes; |
ba6785ff | 921 | u32 *llis_va, *last_lli; |
b7f69d9d | 922 | struct pl08x_sg *dsg; |
e8689e63 | 923 | |
3e27ee84 | 924 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
925 | if (!txd->llis_va) { |
926 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
927 | return 0; | |
928 | } | |
929 | ||
542361f8 | 930 | bd.txd = txd; |
25c94f7f | 931 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
b7f69d9d | 932 | cctl = txd->cctl; |
542361f8 | 933 | |
e8689e63 | 934 | /* Find maximum width of the source bus */ |
542361f8 | 935 | bd.srcbus.maxwidth = |
e8689e63 LW |
936 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
937 | PL080_CONTROL_SWIDTH_SHIFT); | |
938 | ||
939 | /* Find maximum width of the destination bus */ | |
542361f8 | 940 | bd.dstbus.maxwidth = |
e8689e63 LW |
941 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
942 | PL080_CONTROL_DWIDTH_SHIFT); | |
943 | ||
b7f69d9d VK |
944 | list_for_each_entry(dsg, &txd->dsg_list, node) { |
945 | total_bytes = 0; | |
946 | cctl = txd->cctl; | |
e8689e63 | 947 | |
b7f69d9d VK |
948 | bd.srcbus.addr = dsg->src_addr; |
949 | bd.dstbus.addr = dsg->dst_addr; | |
950 | bd.remainder = dsg->len; | |
951 | bd.srcbus.buswidth = bd.srcbus.maxwidth; | |
952 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 | 953 | |
b7f69d9d | 954 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
e8689e63 | 955 | |
b7f69d9d VK |
956 | dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n", |
957 | bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", | |
958 | bd.srcbus.buswidth, | |
959 | bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
960 | bd.dstbus.buswidth, | |
961 | bd.remainder); | |
962 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", | |
963 | mbus == &bd.srcbus ? "src" : "dst", | |
964 | sbus == &bd.srcbus ? "src" : "dst"); | |
fc74eb79 | 965 | |
b7f69d9d VK |
966 | /* |
967 | * Zero length is only allowed if all these requirements are | |
968 | * met: | |
969 | * - flow controller is peripheral. | |
970 | * - src.addr is aligned to src.width | |
971 | * - dst.addr is aligned to dst.width | |
972 | * | |
973 | * sg_len == 1 should be true, as there can be two cases here: | |
974 | * | |
975 | * - Memory addresses are contiguous and are not scattered. | |
976 | * Here, Only one sg will be passed by user driver, with | |
977 | * memory address and zero length. We pass this to controller | |
978 | * and after the transfer it will receive the last burst | |
979 | * request from peripheral and so transfer finishes. | |
980 | * | |
981 | * - Memory addresses are scattered and are not contiguous. | |
982 | * Here, Obviously as DMA controller doesn't know when a lli's | |
983 | * transfer gets over, it can't load next lli. So in this | |
984 | * case, there has to be an assumption that only one lli is | |
985 | * supported. Thus, we can't have scattered addresses. | |
986 | */ | |
987 | if (!bd.remainder) { | |
988 | u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> | |
989 | PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
990 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && | |
0a235657 | 991 | (fc <= PL080_FLOW_SRC2DST_SRC))) { |
b7f69d9d VK |
992 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", |
993 | __func__); | |
994 | return 0; | |
995 | } | |
0a235657 | 996 | |
b7f69d9d | 997 | if ((bd.srcbus.addr % bd.srcbus.buswidth) || |
880db3ff | 998 | (bd.dstbus.addr % bd.dstbus.buswidth)) { |
b7f69d9d VK |
999 | dev_err(&pl08x->adev->dev, |
1000 | "%s src & dst address must be aligned to src" | |
1001 | " & dst width if peripheral is flow controller", | |
1002 | __func__); | |
1003 | return 0; | |
1004 | } | |
03af500f | 1005 | |
b7f69d9d VK |
1006 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
1007 | bd.dstbus.buswidth, 0); | |
ba6785ff | 1008 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
da1b6c05 | 1009 | 0, cctl, 0); |
b7f69d9d VK |
1010 | break; |
1011 | } | |
e8689e63 LW |
1012 | |
1013 | /* | |
b7f69d9d VK |
1014 | * Send byte by byte for following cases |
1015 | * - Less than a bus width available | |
1016 | * - until master bus is aligned | |
e8689e63 | 1017 | */ |
b7f69d9d VK |
1018 | if (bd.remainder < mbus->buswidth) |
1019 | early_bytes = bd.remainder; | |
1020 | else if ((mbus->addr) % (mbus->buswidth)) { | |
1021 | early_bytes = mbus->buswidth - (mbus->addr) % | |
1022 | (mbus->buswidth); | |
1023 | if ((bd.remainder - early_bytes) < mbus->buswidth) | |
1024 | early_bytes = bd.remainder; | |
1025 | } | |
e8689e63 | 1026 | |
b7f69d9d VK |
1027 | if (early_bytes) { |
1028 | dev_vdbg(&pl08x->adev->dev, | |
1029 | "%s byte width LLIs (remain 0x%08x)\n", | |
1030 | __func__, bd.remainder); | |
ba6785ff TF |
1031 | prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes, |
1032 | num_llis++, &total_bytes); | |
e8689e63 LW |
1033 | } |
1034 | ||
b7f69d9d VK |
1035 | if (bd.remainder) { |
1036 | /* | |
1037 | * Master now aligned | |
1038 | * - if slave is not then we must set its width down | |
1039 | */ | |
1040 | if (sbus->addr % sbus->buswidth) { | |
1041 | dev_dbg(&pl08x->adev->dev, | |
1042 | "%s set down bus width to one byte\n", | |
1043 | __func__); | |
fa6a940b | 1044 | |
b7f69d9d VK |
1045 | sbus->buswidth = 1; |
1046 | } | |
e8689e63 LW |
1047 | |
1048 | /* | |
b7f69d9d VK |
1049 | * Bytes transferred = tsize * src width, not |
1050 | * MIN(buswidths) | |
e8689e63 | 1051 | */ |
b7f69d9d VK |
1052 | max_bytes_per_lli = bd.srcbus.buswidth * |
1053 | PL080_CONTROL_TRANSFER_SIZE_MASK; | |
1054 | dev_vdbg(&pl08x->adev->dev, | |
1055 | "%s max bytes per lli = %zu\n", | |
1056 | __func__, max_bytes_per_lli); | |
e8689e63 LW |
1057 | |
1058 | /* | |
b7f69d9d VK |
1059 | * Make largest possible LLIs until less than one bus |
1060 | * width left | |
e8689e63 | 1061 | */ |
b7f69d9d VK |
1062 | while (bd.remainder > (mbus->buswidth - 1)) { |
1063 | size_t lli_len, tsize, width; | |
e8689e63 | 1064 | |
b7f69d9d VK |
1065 | /* |
1066 | * If enough left try to send max possible, | |
1067 | * otherwise try to send the remainder | |
1068 | */ | |
1069 | lli_len = min(bd.remainder, max_bytes_per_lli); | |
16a2e7d3 | 1070 | |
b7f69d9d VK |
1071 | /* |
1072 | * Check against maximum bus alignment: | |
1073 | * Calculate actual transfer size in relation to | |
1074 | * bus width an get a maximum remainder of the | |
1075 | * highest bus width - 1 | |
1076 | */ | |
1077 | width = max(mbus->buswidth, sbus->buswidth); | |
1078 | lli_len = (lli_len / width) * width; | |
1079 | tsize = lli_len / bd.srcbus.buswidth; | |
1080 | ||
1081 | dev_vdbg(&pl08x->adev->dev, | |
1082 | "%s fill lli with single lli chunk of " | |
1083 | "size 0x%08zx (remainder 0x%08zx)\n", | |
1084 | __func__, lli_len, bd.remainder); | |
1085 | ||
1086 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, | |
16a2e7d3 | 1087 | bd.dstbus.buswidth, tsize); |
ba6785ff | 1088 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
da1b6c05 | 1089 | lli_len, cctl, tsize); |
b7f69d9d VK |
1090 | total_bytes += lli_len; |
1091 | } | |
e8689e63 | 1092 | |
b7f69d9d VK |
1093 | /* |
1094 | * Send any odd bytes | |
1095 | */ | |
1096 | if (bd.remainder) { | |
1097 | dev_vdbg(&pl08x->adev->dev, | |
1098 | "%s align with boundary, send odd bytes (remain %zu)\n", | |
1099 | __func__, bd.remainder); | |
ba6785ff TF |
1100 | prep_byte_width_lli(pl08x, &bd, &cctl, |
1101 | bd.remainder, num_llis++, &total_bytes); | |
b7f69d9d | 1102 | } |
e8689e63 | 1103 | } |
16a2e7d3 | 1104 | |
b7f69d9d VK |
1105 | if (total_bytes != dsg->len) { |
1106 | dev_err(&pl08x->adev->dev, | |
1107 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", | |
1108 | __func__, total_bytes, dsg->len); | |
1109 | return 0; | |
1110 | } | |
e8689e63 | 1111 | |
b7f69d9d VK |
1112 | if (num_llis >= MAX_NUM_TSFR_LLIS) { |
1113 | dev_err(&pl08x->adev->dev, | |
1114 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
ba6785ff | 1115 | __func__, MAX_NUM_TSFR_LLIS); |
b7f69d9d VK |
1116 | return 0; |
1117 | } | |
e8689e63 | 1118 | } |
b58b6b5b RKAL |
1119 | |
1120 | llis_va = txd->llis_va; | |
ba6785ff | 1121 | last_lli = llis_va + (num_llis - 1) * pl08x->lli_words; |
94ae8522 | 1122 | /* The final LLI terminates the LLI. */ |
ba6785ff | 1123 | last_lli[PL080_LLI_LLI] = 0; |
94ae8522 | 1124 | /* The final LLI element shall also fire an interrupt. */ |
ba6785ff | 1125 | last_lli[PL080_LLI_CCTL] |= PL080_CONTROL_TC_IRQ_EN; |
e8689e63 | 1126 | |
48924e42 | 1127 | pl08x_dump_lli(pl08x, llis_va, num_llis); |
e8689e63 LW |
1128 | |
1129 | return num_llis; | |
1130 | } | |
1131 | ||
e8689e63 LW |
1132 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, |
1133 | struct pl08x_txd *txd) | |
1134 | { | |
b7f69d9d VK |
1135 | struct pl08x_sg *dsg, *_dsg; |
1136 | ||
c1205646 VK |
1137 | if (txd->llis_va) |
1138 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); | |
e8689e63 | 1139 | |
b7f69d9d VK |
1140 | list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) { |
1141 | list_del(&dsg->node); | |
1142 | kfree(dsg); | |
1143 | } | |
1144 | ||
e8689e63 LW |
1145 | kfree(txd); |
1146 | } | |
1147 | ||
18536134 RK |
1148 | static void pl08x_unmap_buffers(struct pl08x_txd *txd) |
1149 | { | |
1150 | struct device *dev = txd->vd.tx.chan->device->dev; | |
1151 | struct pl08x_sg *dsg; | |
1152 | ||
1153 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
1154 | if (txd->vd.tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
1155 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1156 | dma_unmap_single(dev, dsg->src_addr, dsg->len, | |
1157 | DMA_TO_DEVICE); | |
1158 | else { | |
1159 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1160 | dma_unmap_page(dev, dsg->src_addr, dsg->len, | |
1161 | DMA_TO_DEVICE); | |
1162 | } | |
1163 | } | |
1164 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
1165 | if (txd->vd.tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
1166 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1167 | dma_unmap_single(dev, dsg->dst_addr, dsg->len, | |
1168 | DMA_FROM_DEVICE); | |
1169 | else | |
1170 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1171 | dma_unmap_page(dev, dsg->dst_addr, dsg->len, | |
1172 | DMA_FROM_DEVICE); | |
1173 | } | |
1174 | } | |
1175 | ||
1176 | static void pl08x_desc_free(struct virt_dma_desc *vd) | |
1177 | { | |
1178 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1179 | struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan); | |
18536134 RK |
1180 | |
1181 | if (!plchan->slave) | |
1182 | pl08x_unmap_buffers(txd); | |
1183 | ||
1184 | if (!txd->done) | |
1185 | pl08x_release_mux(plchan); | |
1186 | ||
18536134 | 1187 | pl08x_free_txd(plchan->host, txd); |
18536134 RK |
1188 | } |
1189 | ||
e8689e63 LW |
1190 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, |
1191 | struct pl08x_dma_chan *plchan) | |
1192 | { | |
ea160561 | 1193 | LIST_HEAD(head); |
e8689e63 | 1194 | |
879f127b | 1195 | vchan_get_all_descriptors(&plchan->vc, &head); |
91998261 | 1196 | vchan_dma_desc_free_list(&plchan->vc, &head); |
e8689e63 LW |
1197 | } |
1198 | ||
1199 | /* | |
1200 | * The DMA ENGINE API | |
1201 | */ | |
1202 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
1203 | { | |
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
1208 | { | |
a068682c RK |
1209 | /* Ensure all queued descriptors are freed */ |
1210 | vchan_free_chan_resources(to_virt_chan(chan)); | |
e8689e63 LW |
1211 | } |
1212 | ||
e8689e63 LW |
1213 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( |
1214 | struct dma_chan *chan, unsigned long flags) | |
1215 | { | |
1216 | struct dma_async_tx_descriptor *retval = NULL; | |
1217 | ||
1218 | return retval; | |
1219 | } | |
1220 | ||
1221 | /* | |
94ae8522 RKAL |
1222 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
1223 | * If slaves are relying on interrupts to signal completion this function | |
1224 | * must not be called with interrupts disabled. | |
e8689e63 | 1225 | */ |
3e27ee84 VK |
1226 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
1227 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
1228 | { |
1229 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
06e885b7 RK |
1230 | struct virt_dma_desc *vd; |
1231 | unsigned long flags; | |
e8689e63 | 1232 | enum dma_status ret; |
06e885b7 | 1233 | size_t bytes = 0; |
e8689e63 | 1234 | |
96a2af41 RKAL |
1235 | ret = dma_cookie_status(chan, cookie, txstate); |
1236 | if (ret == DMA_SUCCESS) | |
e8689e63 | 1237 | return ret; |
e8689e63 | 1238 | |
06e885b7 RK |
1239 | /* |
1240 | * There's no point calculating the residue if there's | |
1241 | * no txstate to store the value. | |
1242 | */ | |
1243 | if (!txstate) { | |
1244 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1245 | ret = DMA_PAUSED; | |
1246 | return ret; | |
1247 | } | |
1248 | ||
1249 | spin_lock_irqsave(&plchan->vc.lock, flags); | |
1250 | ret = dma_cookie_status(chan, cookie, txstate); | |
1251 | if (ret != DMA_SUCCESS) { | |
1252 | vd = vchan_find_desc(&plchan->vc, cookie); | |
1253 | if (vd) { | |
1254 | /* On the issued list, so hasn't been processed yet */ | |
1255 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1256 | struct pl08x_sg *dsg; | |
1257 | ||
1258 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1259 | bytes += dsg->len; | |
1260 | } else { | |
1261 | bytes = pl08x_getbytes_chan(plchan); | |
1262 | } | |
1263 | } | |
1264 | spin_unlock_irqrestore(&plchan->vc.lock, flags); | |
1265 | ||
e8689e63 LW |
1266 | /* |
1267 | * This cookie not complete yet | |
96a2af41 | 1268 | * Get number of bytes left in the active transactions and queue |
e8689e63 | 1269 | */ |
06e885b7 | 1270 | dma_set_residue(txstate, bytes); |
e8689e63 | 1271 | |
06e885b7 RK |
1272 | if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS) |
1273 | ret = DMA_PAUSED; | |
e8689e63 LW |
1274 | |
1275 | /* Whether waiting or running, we're in progress */ | |
06e885b7 | 1276 | return ret; |
e8689e63 LW |
1277 | } |
1278 | ||
1279 | /* PrimeCell DMA extension */ | |
1280 | struct burst_table { | |
760596c6 | 1281 | u32 burstwords; |
e8689e63 LW |
1282 | u32 reg; |
1283 | }; | |
1284 | ||
1285 | static const struct burst_table burst_sizes[] = { | |
1286 | { | |
1287 | .burstwords = 256, | |
760596c6 | 1288 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
1289 | }, |
1290 | { | |
1291 | .burstwords = 128, | |
760596c6 | 1292 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
1293 | }, |
1294 | { | |
1295 | .burstwords = 64, | |
760596c6 | 1296 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
1297 | }, |
1298 | { | |
1299 | .burstwords = 32, | |
760596c6 | 1300 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
1301 | }, |
1302 | { | |
1303 | .burstwords = 16, | |
760596c6 | 1304 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
1305 | }, |
1306 | { | |
1307 | .burstwords = 8, | |
760596c6 | 1308 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1309 | }, |
1310 | { | |
1311 | .burstwords = 4, | |
760596c6 | 1312 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1313 | }, |
1314 | { | |
760596c6 RKAL |
1315 | .burstwords = 0, |
1316 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1317 | }, |
1318 | }; | |
1319 | ||
121c8476 RKAL |
1320 | /* |
1321 | * Given the source and destination available bus masks, select which | |
1322 | * will be routed to each port. We try to have source and destination | |
1323 | * on separate ports, but always respect the allowable settings. | |
1324 | */ | |
1325 | static u32 pl08x_select_bus(u8 src, u8 dst) | |
1326 | { | |
1327 | u32 cctl = 0; | |
1328 | ||
1329 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1330 | cctl |= PL080_CONTROL_DST_AHB2; | |
1331 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1332 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1333 | ||
1334 | return cctl; | |
1335 | } | |
1336 | ||
f14c426c RKAL |
1337 | static u32 pl08x_cctl(u32 cctl) |
1338 | { | |
1339 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1340 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1341 | PL080_CONTROL_PROT_MASK); | |
1342 | ||
1343 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1344 | return cctl | PL080_CONTROL_PROT_SYS; | |
1345 | } | |
1346 | ||
aa88cdaa RKAL |
1347 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1348 | { | |
1349 | switch (width) { | |
1350 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1351 | return PL080_WIDTH_8BIT; | |
1352 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1353 | return PL080_WIDTH_16BIT; | |
1354 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1355 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1356 | default: |
1357 | return ~0; | |
aa88cdaa | 1358 | } |
aa88cdaa RKAL |
1359 | } |
1360 | ||
760596c6 RKAL |
1361 | static u32 pl08x_burst(u32 maxburst) |
1362 | { | |
1363 | int i; | |
1364 | ||
1365 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1366 | if (burst_sizes[i].burstwords <= maxburst) | |
1367 | break; | |
1368 | ||
1369 | return burst_sizes[i].reg; | |
1370 | } | |
1371 | ||
9862ba17 RK |
1372 | static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan, |
1373 | enum dma_slave_buswidth addr_width, u32 maxburst) | |
1374 | { | |
1375 | u32 width, burst, cctl = 0; | |
1376 | ||
1377 | width = pl08x_width(addr_width); | |
1378 | if (width == ~0) | |
1379 | return ~0; | |
1380 | ||
1381 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; | |
1382 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1383 | ||
1384 | /* | |
1385 | * If this channel will only request single transfers, set this | |
1386 | * down to ONE element. Also select one element if no maxburst | |
1387 | * is specified. | |
1388 | */ | |
1389 | if (plchan->cd->single) | |
1390 | maxburst = 1; | |
1391 | ||
1392 | burst = pl08x_burst(maxburst); | |
1393 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1394 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
1395 | ||
1396 | return pl08x_cctl(cctl); | |
1397 | } | |
1398 | ||
f0fd9446 RKAL |
1399 | static int dma_set_runtime_config(struct dma_chan *chan, |
1400 | struct dma_slave_config *config) | |
e8689e63 LW |
1401 | { |
1402 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
da1b6c05 | 1403 | struct pl08x_driver_data *pl08x = plchan->host; |
b7f75865 RKAL |
1404 | |
1405 | if (!plchan->slave) | |
1406 | return -EINVAL; | |
e8689e63 | 1407 | |
dc8d5f8d RK |
1408 | /* Reject definitely invalid configurations */ |
1409 | if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || | |
1410 | config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
f0fd9446 | 1411 | return -EINVAL; |
e8689e63 | 1412 | |
da1b6c05 TF |
1413 | if (config->device_fc && pl08x->vd->pl080s) { |
1414 | dev_err(&pl08x->adev->dev, | |
1415 | "%s: PL080S does not support peripheral flow control\n", | |
1416 | __func__); | |
1417 | return -EINVAL; | |
1418 | } | |
1419 | ||
ed91c13d RK |
1420 | plchan->cfg = *config; |
1421 | ||
f0fd9446 | 1422 | return 0; |
e8689e63 LW |
1423 | } |
1424 | ||
1425 | /* | |
1426 | * Slave transactions callback to the slave device to allow | |
1427 | * synchronization of slave DMA signals with the DMAC enable | |
1428 | */ | |
1429 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1430 | { | |
1431 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1432 | unsigned long flags; |
1433 | ||
083be28a | 1434 | spin_lock_irqsave(&plchan->vc.lock, flags); |
879f127b | 1435 | if (vchan_issue_pending(&plchan->vc)) { |
a5a488db RK |
1436 | if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING) |
1437 | pl08x_phy_alloc_and_start(plchan); | |
e8689e63 | 1438 | } |
083be28a | 1439 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1440 | } |
1441 | ||
879f127b | 1442 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan) |
ac3cd20d | 1443 | { |
b201c111 | 1444 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d RKAL |
1445 | |
1446 | if (txd) { | |
b7f69d9d | 1447 | INIT_LIST_HEAD(&txd->dsg_list); |
4983a04f RKAL |
1448 | |
1449 | /* Always enable error and terminal interrupts */ | |
1450 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1451 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1452 | } |
1453 | return txd; | |
1454 | } | |
1455 | ||
e8689e63 LW |
1456 | /* |
1457 | * Initialize a descriptor to be used by memcpy submit | |
1458 | */ | |
1459 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1460 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1461 | size_t len, unsigned long flags) | |
1462 | { | |
1463 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1464 | struct pl08x_driver_data *pl08x = plchan->host; | |
1465 | struct pl08x_txd *txd; | |
b7f69d9d | 1466 | struct pl08x_sg *dsg; |
e8689e63 LW |
1467 | int ret; |
1468 | ||
879f127b | 1469 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1470 | if (!txd) { |
1471 | dev_err(&pl08x->adev->dev, | |
1472 | "%s no memory for descriptor\n", __func__); | |
1473 | return NULL; | |
1474 | } | |
1475 | ||
b7f69d9d VK |
1476 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); |
1477 | if (!dsg) { | |
1478 | pl08x_free_txd(pl08x, txd); | |
1479 | dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n", | |
1480 | __func__); | |
1481 | return NULL; | |
1482 | } | |
1483 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1484 | ||
b7f69d9d VK |
1485 | dsg->src_addr = src; |
1486 | dsg->dst_addr = dest; | |
1487 | dsg->len = len; | |
e8689e63 LW |
1488 | |
1489 | /* Set platform data for m2m */ | |
4983a04f | 1490 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
dc8d5f8d | 1491 | txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy & |
c7da9a56 | 1492 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); |
4983a04f | 1493 | |
e8689e63 | 1494 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1495 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1496 | |
c7da9a56 | 1497 | if (pl08x->vd->dualmaster) |
121c8476 RKAL |
1498 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
1499 | pl08x->mem_buses); | |
e8689e63 | 1500 | |
aa4afb75 RK |
1501 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1502 | if (!ret) { | |
1503 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 1504 | return NULL; |
aa4afb75 | 1505 | } |
e8689e63 | 1506 | |
879f127b | 1507 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1508 | } |
1509 | ||
3e2a037c | 1510 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 | 1511 | struct dma_chan *chan, struct scatterlist *sgl, |
db8196df | 1512 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1513 | unsigned long flags, void *context) |
e8689e63 LW |
1514 | { |
1515 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1516 | struct pl08x_driver_data *pl08x = plchan->host; | |
1517 | struct pl08x_txd *txd; | |
b7f69d9d VK |
1518 | struct pl08x_sg *dsg; |
1519 | struct scatterlist *sg; | |
dc8d5f8d | 1520 | enum dma_slave_buswidth addr_width; |
b7f69d9d | 1521 | dma_addr_t slave_addr; |
0a235657 | 1522 | int ret, tmp; |
409ec8db | 1523 | u8 src_buses, dst_buses; |
dc8d5f8d | 1524 | u32 maxburst, cctl; |
e8689e63 | 1525 | |
e8689e63 | 1526 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", |
fdaf9c4b | 1527 | __func__, sg_dma_len(sgl), plchan->name); |
e8689e63 | 1528 | |
879f127b | 1529 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1530 | if (!txd) { |
1531 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1532 | return NULL; | |
1533 | } | |
1534 | ||
e8689e63 LW |
1535 | /* |
1536 | * Set up addresses, the PrimeCell configured address | |
1537 | * will take precedence since this may configure the | |
1538 | * channel target address dynamically at runtime. | |
1539 | */ | |
db8196df | 1540 | if (direction == DMA_MEM_TO_DEV) { |
dc8d5f8d | 1541 | cctl = PL080_CONTROL_SRC_INCR; |
ed91c13d | 1542 | slave_addr = plchan->cfg.dst_addr; |
dc8d5f8d RK |
1543 | addr_width = plchan->cfg.dst_addr_width; |
1544 | maxburst = plchan->cfg.dst_maxburst; | |
409ec8db RK |
1545 | src_buses = pl08x->mem_buses; |
1546 | dst_buses = plchan->cd->periph_buses; | |
db8196df | 1547 | } else if (direction == DMA_DEV_TO_MEM) { |
dc8d5f8d | 1548 | cctl = PL080_CONTROL_DST_INCR; |
ed91c13d | 1549 | slave_addr = plchan->cfg.src_addr; |
dc8d5f8d RK |
1550 | addr_width = plchan->cfg.src_addr_width; |
1551 | maxburst = plchan->cfg.src_maxburst; | |
409ec8db RK |
1552 | src_buses = plchan->cd->periph_buses; |
1553 | dst_buses = pl08x->mem_buses; | |
e8689e63 | 1554 | } else { |
b7f69d9d | 1555 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1556 | dev_err(&pl08x->adev->dev, |
1557 | "%s direction unsupported\n", __func__); | |
1558 | return NULL; | |
1559 | } | |
e8689e63 | 1560 | |
dc8d5f8d | 1561 | cctl |= pl08x_get_cctl(plchan, addr_width, maxburst); |
800d683e RK |
1562 | if (cctl == ~0) { |
1563 | pl08x_free_txd(pl08x, txd); | |
1564 | dev_err(&pl08x->adev->dev, | |
1565 | "DMA slave configuration botched?\n"); | |
1566 | return NULL; | |
1567 | } | |
1568 | ||
409ec8db RK |
1569 | txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses); |
1570 | ||
95442b22 | 1571 | if (plchan->cfg.device_fc) |
db8196df | 1572 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : |
0a235657 VK |
1573 | PL080_FLOW_PER2MEM_PER; |
1574 | else | |
db8196df | 1575 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER : |
0a235657 VK |
1576 | PL080_FLOW_PER2MEM; |
1577 | ||
1578 | txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1579 | ||
c48d4963 RK |
1580 | ret = pl08x_request_mux(plchan); |
1581 | if (ret < 0) { | |
1582 | pl08x_free_txd(pl08x, txd); | |
1583 | dev_dbg(&pl08x->adev->dev, | |
1584 | "unable to mux for transfer on %s due to platform restrictions\n", | |
1585 | plchan->name); | |
1586 | return NULL; | |
1587 | } | |
1588 | ||
1589 | dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n", | |
1590 | plchan->signal, plchan->name); | |
1591 | ||
1592 | /* Assign the flow control signal to this channel */ | |
1593 | if (direction == DMA_MEM_TO_DEV) | |
1594 | txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
1595 | else | |
1596 | txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
1597 | ||
b7f69d9d VK |
1598 | for_each_sg(sgl, sg, sg_len, tmp) { |
1599 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); | |
1600 | if (!dsg) { | |
c48d4963 | 1601 | pl08x_release_mux(plchan); |
b7f69d9d VK |
1602 | pl08x_free_txd(pl08x, txd); |
1603 | dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n", | |
1604 | __func__); | |
1605 | return NULL; | |
1606 | } | |
1607 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1608 | ||
1609 | dsg->len = sg_dma_len(sg); | |
db8196df | 1610 | if (direction == DMA_MEM_TO_DEV) { |
cbb796cc | 1611 | dsg->src_addr = sg_dma_address(sg); |
b7f69d9d VK |
1612 | dsg->dst_addr = slave_addr; |
1613 | } else { | |
1614 | dsg->src_addr = slave_addr; | |
cbb796cc | 1615 | dsg->dst_addr = sg_dma_address(sg); |
b7f69d9d VK |
1616 | } |
1617 | } | |
1618 | ||
aa4afb75 RK |
1619 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1620 | if (!ret) { | |
1621 | pl08x_release_mux(plchan); | |
1622 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 1623 | return NULL; |
aa4afb75 | 1624 | } |
e8689e63 | 1625 | |
879f127b | 1626 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1627 | } |
1628 | ||
1629 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1630 | unsigned long arg) | |
1631 | { | |
1632 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1633 | struct pl08x_driver_data *pl08x = plchan->host; | |
1634 | unsigned long flags; | |
1635 | int ret = 0; | |
1636 | ||
1637 | /* Controls applicable to inactive channels */ | |
1638 | if (cmd == DMA_SLAVE_CONFIG) { | |
f0fd9446 RKAL |
1639 | return dma_set_runtime_config(chan, |
1640 | (struct dma_slave_config *)arg); | |
e8689e63 LW |
1641 | } |
1642 | ||
1643 | /* | |
1644 | * Anything succeeds on channels with no physical allocation and | |
1645 | * no queued transfers. | |
1646 | */ | |
083be28a | 1647 | spin_lock_irqsave(&plchan->vc.lock, flags); |
e8689e63 | 1648 | if (!plchan->phychan && !plchan->at) { |
083be28a | 1649 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1650 | return 0; |
1651 | } | |
1652 | ||
1653 | switch (cmd) { | |
1654 | case DMA_TERMINATE_ALL: | |
1655 | plchan->state = PL08X_CHAN_IDLE; | |
1656 | ||
1657 | if (plchan->phychan) { | |
e8689e63 LW |
1658 | /* |
1659 | * Mark physical channel as free and free any slave | |
1660 | * signal | |
1661 | */ | |
a5a488db | 1662 | pl08x_phy_free(plchan); |
e8689e63 | 1663 | } |
e8689e63 LW |
1664 | /* Dequeue jobs and free LLIs */ |
1665 | if (plchan->at) { | |
18536134 | 1666 | pl08x_desc_free(&plchan->at->vd); |
e8689e63 LW |
1667 | plchan->at = NULL; |
1668 | } | |
1669 | /* Dequeue jobs not yet fired as well */ | |
1670 | pl08x_free_txd_list(pl08x, plchan); | |
1671 | break; | |
1672 | case DMA_PAUSE: | |
1673 | pl08x_pause_phy_chan(plchan->phychan); | |
1674 | plchan->state = PL08X_CHAN_PAUSED; | |
1675 | break; | |
1676 | case DMA_RESUME: | |
1677 | pl08x_resume_phy_chan(plchan->phychan); | |
1678 | plchan->state = PL08X_CHAN_RUNNING; | |
1679 | break; | |
1680 | default: | |
1681 | /* Unknown command */ | |
1682 | ret = -ENXIO; | |
1683 | break; | |
1684 | } | |
1685 | ||
083be28a | 1686 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1687 | |
1688 | return ret; | |
1689 | } | |
1690 | ||
1691 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1692 | { | |
7703eac9 | 1693 | struct pl08x_dma_chan *plchan; |
e8689e63 LW |
1694 | char *name = chan_id; |
1695 | ||
7703eac9 RKAL |
1696 | /* Reject channels for devices not bound to this driver */ |
1697 | if (chan->device->dev->driver != &pl08x_amba_driver.drv) | |
1698 | return false; | |
1699 | ||
1700 | plchan = to_pl08x_chan(chan); | |
1701 | ||
e8689e63 LW |
1702 | /* Check that the channel is not taken! */ |
1703 | if (!strcmp(plchan->name, name)) | |
1704 | return true; | |
1705 | ||
1706 | return false; | |
1707 | } | |
1708 | ||
1709 | /* | |
1710 | * Just check that the device is there and active | |
94ae8522 RKAL |
1711 | * TODO: turn this bit on/off depending on the number of physical channels |
1712 | * actually used, if it is zero... well shut it off. That will save some | |
1713 | * power. Cut the clock at the same time. | |
e8689e63 LW |
1714 | */ |
1715 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1716 | { | |
affa115e LW |
1717 | /* The Nomadik variant does not have the config register */ |
1718 | if (pl08x->vd->nomadik) | |
1719 | return; | |
48a59ef3 | 1720 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
e8689e63 LW |
1721 | } |
1722 | ||
e8689e63 LW |
1723 | static irqreturn_t pl08x_irq(int irq, void *dev) |
1724 | { | |
1725 | struct pl08x_driver_data *pl08x = dev; | |
28da2836 VK |
1726 | u32 mask = 0, err, tc, i; |
1727 | ||
1728 | /* check & clear - ERR & TC interrupts */ | |
1729 | err = readl(pl08x->base + PL080_ERR_STATUS); | |
1730 | if (err) { | |
1731 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", | |
1732 | __func__, err); | |
1733 | writel(err, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 | 1734 | } |
d29bf019 | 1735 | tc = readl(pl08x->base + PL080_TC_STATUS); |
28da2836 VK |
1736 | if (tc) |
1737 | writel(tc, pl08x->base + PL080_TC_CLEAR); | |
1738 | ||
1739 | if (!err && !tc) | |
1740 | return IRQ_NONE; | |
1741 | ||
e8689e63 | 1742 | for (i = 0; i < pl08x->vd->channels; i++) { |
28da2836 | 1743 | if (((1 << i) & err) || ((1 << i) & tc)) { |
e8689e63 LW |
1744 | /* Locate physical channel */ |
1745 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1746 | struct pl08x_dma_chan *plchan = phychan->serving; | |
a936e793 | 1747 | struct pl08x_txd *tx; |
e8689e63 | 1748 | |
28da2836 VK |
1749 | if (!plchan) { |
1750 | dev_err(&pl08x->adev->dev, | |
1751 | "%s Error TC interrupt on unused channel: 0x%08x\n", | |
1752 | __func__, i); | |
1753 | continue; | |
1754 | } | |
1755 | ||
083be28a | 1756 | spin_lock(&plchan->vc.lock); |
a936e793 RK |
1757 | tx = plchan->at; |
1758 | if (tx) { | |
1759 | plchan->at = NULL; | |
c48d4963 RK |
1760 | /* |
1761 | * This descriptor is done, release its mux | |
1762 | * reservation. | |
1763 | */ | |
1764 | pl08x_release_mux(plchan); | |
18536134 RK |
1765 | tx->done = true; |
1766 | vchan_cookie_complete(&tx->vd); | |
c33b644c | 1767 | |
a5a488db RK |
1768 | /* |
1769 | * And start the next descriptor (if any), | |
1770 | * otherwise free this channel. | |
1771 | */ | |
879f127b | 1772 | if (vchan_next_desc(&plchan->vc)) |
c33b644c | 1773 | pl08x_start_next_txd(plchan); |
a5a488db RK |
1774 | else |
1775 | pl08x_phy_free(plchan); | |
a936e793 | 1776 | } |
083be28a | 1777 | spin_unlock(&plchan->vc.lock); |
a936e793 | 1778 | |
e8689e63 LW |
1779 | mask |= (1 << i); |
1780 | } | |
1781 | } | |
e8689e63 LW |
1782 | |
1783 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1784 | } | |
1785 | ||
121c8476 RKAL |
1786 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
1787 | { | |
121c8476 RKAL |
1788 | chan->slave = true; |
1789 | chan->name = chan->cd->bus_id; | |
ed91c13d RK |
1790 | chan->cfg.src_addr = chan->cd->addr; |
1791 | chan->cfg.dst_addr = chan->cd->addr; | |
121c8476 RKAL |
1792 | } |
1793 | ||
e8689e63 LW |
1794 | /* |
1795 | * Initialise the DMAC memcpy/slave channels. | |
1796 | * Make a local wrapper to hold required data | |
1797 | */ | |
1798 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 1799 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
1800 | { |
1801 | struct pl08x_dma_chan *chan; | |
1802 | int i; | |
1803 | ||
1804 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 1805 | |
e8689e63 LW |
1806 | /* |
1807 | * Register as many many memcpy as we have physical channels, | |
1808 | * we won't always be able to use all but the code will have | |
1809 | * to cope with that situation. | |
1810 | */ | |
1811 | for (i = 0; i < channels; i++) { | |
b201c111 | 1812 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
e8689e63 LW |
1813 | if (!chan) { |
1814 | dev_err(&pl08x->adev->dev, | |
1815 | "%s no memory for channel\n", __func__); | |
1816 | return -ENOMEM; | |
1817 | } | |
1818 | ||
1819 | chan->host = pl08x; | |
1820 | chan->state = PL08X_CHAN_IDLE; | |
ad0de2ac | 1821 | chan->signal = -1; |
e8689e63 LW |
1822 | |
1823 | if (slave) { | |
e8689e63 | 1824 | chan->cd = &pl08x->pd->slave_channels[i]; |
121c8476 | 1825 | pl08x_dma_slave_init(chan); |
e8689e63 LW |
1826 | } else { |
1827 | chan->cd = &pl08x->pd->memcpy_channel; | |
1828 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1829 | if (!chan->name) { | |
1830 | kfree(chan); | |
1831 | return -ENOMEM; | |
1832 | } | |
1833 | } | |
175a5e61 | 1834 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
1835 | "initialize virtual channel \"%s\"\n", |
1836 | chan->name); | |
1837 | ||
18536134 | 1838 | chan->vc.desc_free = pl08x_desc_free; |
083be28a | 1839 | vchan_init(&chan->vc, dmadev); |
e8689e63 LW |
1840 | } |
1841 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1842 | i, slave ? "slave" : "memcpy"); | |
1843 | return i; | |
1844 | } | |
1845 | ||
1846 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1847 | { | |
1848 | struct pl08x_dma_chan *chan = NULL; | |
1849 | struct pl08x_dma_chan *next; | |
1850 | ||
1851 | list_for_each_entry_safe(chan, | |
01d8dc64 RK |
1852 | next, &dmadev->channels, vc.chan.device_node) { |
1853 | list_del(&chan->vc.chan.device_node); | |
e8689e63 LW |
1854 | kfree(chan); |
1855 | } | |
1856 | } | |
1857 | ||
1858 | #ifdef CONFIG_DEBUG_FS | |
1859 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1860 | { | |
1861 | switch (state) { | |
1862 | case PL08X_CHAN_IDLE: | |
1863 | return "idle"; | |
1864 | case PL08X_CHAN_RUNNING: | |
1865 | return "running"; | |
1866 | case PL08X_CHAN_PAUSED: | |
1867 | return "paused"; | |
1868 | case PL08X_CHAN_WAITING: | |
1869 | return "waiting"; | |
1870 | default: | |
1871 | break; | |
1872 | } | |
1873 | return "UNKNOWN STATE"; | |
1874 | } | |
1875 | ||
1876 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1877 | { | |
1878 | struct pl08x_driver_data *pl08x = s->private; | |
1879 | struct pl08x_dma_chan *chan; | |
1880 | struct pl08x_phy_chan *ch; | |
1881 | unsigned long flags; | |
1882 | int i; | |
1883 | ||
1884 | seq_printf(s, "PL08x physical channels:\n"); | |
1885 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1886 | seq_printf(s, "--------\t-----\n"); | |
1887 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1888 | struct pl08x_dma_chan *virt_chan; | |
1889 | ||
1890 | ch = &pl08x->phy_chans[i]; | |
1891 | ||
1892 | spin_lock_irqsave(&ch->lock, flags); | |
1893 | virt_chan = ch->serving; | |
1894 | ||
affa115e LW |
1895 | seq_printf(s, "%d\t\t%s%s\n", |
1896 | ch->id, | |
1897 | virt_chan ? virt_chan->name : "(none)", | |
1898 | ch->locked ? " LOCKED" : ""); | |
e8689e63 LW |
1899 | |
1900 | spin_unlock_irqrestore(&ch->lock, flags); | |
1901 | } | |
1902 | ||
1903 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1904 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1905 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1906 | list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) { |
3e2a037c | 1907 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1908 | pl08x_state_str(chan->state)); |
1909 | } | |
1910 | ||
1911 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1912 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1913 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1914 | list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) { |
3e2a037c | 1915 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1916 | pl08x_state_str(chan->state)); |
1917 | } | |
1918 | ||
1919 | return 0; | |
1920 | } | |
1921 | ||
1922 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1923 | { | |
1924 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1925 | } | |
1926 | ||
1927 | static const struct file_operations pl08x_debugfs_operations = { | |
1928 | .open = pl08x_debugfs_open, | |
1929 | .read = seq_read, | |
1930 | .llseek = seq_lseek, | |
1931 | .release = single_release, | |
1932 | }; | |
1933 | ||
1934 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1935 | { | |
1936 | /* Expose a simple debugfs interface to view all clocks */ | |
3e27ee84 VK |
1937 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
1938 | S_IFREG | S_IRUGO, NULL, pl08x, | |
1939 | &pl08x_debugfs_operations); | |
e8689e63 LW |
1940 | } |
1941 | ||
1942 | #else | |
1943 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1944 | { | |
1945 | } | |
1946 | #endif | |
1947 | ||
aa25afad | 1948 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
1949 | { |
1950 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1951 | const struct vendor_data *vd = id->data; |
ba6785ff | 1952 | u32 tsfr_size; |
e8689e63 LW |
1953 | int ret = 0; |
1954 | int i; | |
1955 | ||
1956 | ret = amba_request_regions(adev, NULL); | |
1957 | if (ret) | |
1958 | return ret; | |
1959 | ||
1960 | /* Create the driver state holder */ | |
b201c111 | 1961 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
1962 | if (!pl08x) { |
1963 | ret = -ENOMEM; | |
1964 | goto out_no_pl08x; | |
1965 | } | |
1966 | ||
1967 | /* Initialize memcpy engine */ | |
1968 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1969 | pl08x->memcpy.dev = &adev->dev; | |
1970 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1971 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1972 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1973 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1974 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1975 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1976 | pl08x->memcpy.device_control = pl08x_control; | |
1977 | ||
1978 | /* Initialize slave engine */ | |
1979 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1980 | pl08x->slave.dev = &adev->dev; | |
1981 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1982 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1983 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1984 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1985 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1986 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1987 | pl08x->slave.device_control = pl08x_control; | |
1988 | ||
1989 | /* Get the platform data */ | |
1990 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1991 | if (!pl08x->pd) { | |
1992 | dev_err(&adev->dev, "no platform data supplied\n"); | |
983d7beb | 1993 | ret = -EINVAL; |
e8689e63 LW |
1994 | goto out_no_platdata; |
1995 | } | |
1996 | ||
1997 | /* Assign useful pointers to the driver state */ | |
1998 | pl08x->adev = adev; | |
1999 | pl08x->vd = vd; | |
2000 | ||
30749cb4 RKAL |
2001 | /* By default, AHB1 only. If dualmaster, from platform */ |
2002 | pl08x->lli_buses = PL08X_AHB1; | |
2003 | pl08x->mem_buses = PL08X_AHB1; | |
2004 | if (pl08x->vd->dualmaster) { | |
2005 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
2006 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
2007 | } | |
2008 | ||
da1b6c05 TF |
2009 | if (vd->pl080s) |
2010 | pl08x->lli_words = PL080S_LLI_WORDS; | |
2011 | else | |
2012 | pl08x->lli_words = PL080_LLI_WORDS; | |
ba6785ff TF |
2013 | tsfr_size = MAX_NUM_TSFR_LLIS * pl08x->lli_words * sizeof(u32); |
2014 | ||
e8689e63 LW |
2015 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
2016 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
ba6785ff | 2017 | tsfr_size, PL08X_ALIGN, 0); |
e8689e63 LW |
2018 | if (!pl08x->pool) { |
2019 | ret = -ENOMEM; | |
2020 | goto out_no_lli_pool; | |
2021 | } | |
2022 | ||
e8689e63 LW |
2023 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); |
2024 | if (!pl08x->base) { | |
2025 | ret = -ENOMEM; | |
2026 | goto out_no_ioremap; | |
2027 | } | |
2028 | ||
2029 | /* Turn on the PL08x */ | |
2030 | pl08x_ensure_on(pl08x); | |
2031 | ||
94ae8522 | 2032 | /* Attach the interrupt handler */ |
e8689e63 LW |
2033 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
2034 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
2035 | ||
2036 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 2037 | DRIVER_NAME, pl08x); |
e8689e63 LW |
2038 | if (ret) { |
2039 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
2040 | __func__, adev->irq[0]); | |
2041 | goto out_no_irq; | |
2042 | } | |
2043 | ||
2044 | /* Initialize physical channels */ | |
affa115e | 2045 | pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
2046 | GFP_KERNEL); |
2047 | if (!pl08x->phy_chans) { | |
2048 | dev_err(&adev->dev, "%s failed to allocate " | |
2049 | "physical channel holders\n", | |
2050 | __func__); | |
983d7beb | 2051 | ret = -ENOMEM; |
e8689e63 LW |
2052 | goto out_no_phychans; |
2053 | } | |
2054 | ||
2055 | for (i = 0; i < vd->channels; i++) { | |
2056 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
2057 | ||
2058 | ch->id = i; | |
2059 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
d86ccea7 | 2060 | ch->reg_config = ch->base + vd->config_offset; |
e8689e63 | 2061 | spin_lock_init(&ch->lock); |
affa115e LW |
2062 | |
2063 | /* | |
2064 | * Nomadik variants can have channels that are locked | |
2065 | * down for the secure world only. Lock up these channels | |
2066 | * by perpetually serving a dummy virtual channel. | |
2067 | */ | |
2068 | if (vd->nomadik) { | |
2069 | u32 val; | |
2070 | ||
d86ccea7 | 2071 | val = readl(ch->reg_config); |
affa115e LW |
2072 | if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { |
2073 | dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i); | |
2074 | ch->locked = true; | |
2075 | } | |
2076 | } | |
2077 | ||
175a5e61 VK |
2078 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
2079 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
2080 | } |
2081 | ||
2082 | /* Register as many memcpy channels as there are physical channels */ | |
2083 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
2084 | pl08x->vd->channels, false); | |
2085 | if (ret <= 0) { | |
2086 | dev_warn(&pl08x->adev->dev, | |
2087 | "%s failed to enumerate memcpy channels - %d\n", | |
2088 | __func__, ret); | |
2089 | goto out_no_memcpy; | |
2090 | } | |
2091 | pl08x->memcpy.chancnt = ret; | |
2092 | ||
2093 | /* Register slave channels */ | |
2094 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
3e27ee84 | 2095 | pl08x->pd->num_slave_channels, true); |
e8689e63 LW |
2096 | if (ret <= 0) { |
2097 | dev_warn(&pl08x->adev->dev, | |
2098 | "%s failed to enumerate slave channels - %d\n", | |
2099 | __func__, ret); | |
2100 | goto out_no_slave; | |
2101 | } | |
2102 | pl08x->slave.chancnt = ret; | |
2103 | ||
2104 | ret = dma_async_device_register(&pl08x->memcpy); | |
2105 | if (ret) { | |
2106 | dev_warn(&pl08x->adev->dev, | |
2107 | "%s failed to register memcpy as an async device - %d\n", | |
2108 | __func__, ret); | |
2109 | goto out_no_memcpy_reg; | |
2110 | } | |
2111 | ||
2112 | ret = dma_async_device_register(&pl08x->slave); | |
2113 | if (ret) { | |
2114 | dev_warn(&pl08x->adev->dev, | |
2115 | "%s failed to register slave as an async device - %d\n", | |
2116 | __func__, ret); | |
2117 | goto out_no_slave_reg; | |
2118 | } | |
2119 | ||
2120 | amba_set_drvdata(adev, pl08x); | |
2121 | init_pl08x_debugfs(pl08x); | |
da1b6c05 TF |
2122 | dev_info(&pl08x->adev->dev, "DMA: PL%03x%s rev%u at 0x%08llx irq %d\n", |
2123 | amba_part(adev), pl08x->vd->pl080s ? "s" : "", amba_rev(adev), | |
b05cd8f4 | 2124 | (unsigned long long)adev->res.start, adev->irq[0]); |
b7b6018b | 2125 | |
e8689e63 LW |
2126 | return 0; |
2127 | ||
2128 | out_no_slave_reg: | |
2129 | dma_async_device_unregister(&pl08x->memcpy); | |
2130 | out_no_memcpy_reg: | |
2131 | pl08x_free_virtual_channels(&pl08x->slave); | |
2132 | out_no_slave: | |
2133 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2134 | out_no_memcpy: | |
2135 | kfree(pl08x->phy_chans); | |
2136 | out_no_phychans: | |
2137 | free_irq(adev->irq[0], pl08x); | |
2138 | out_no_irq: | |
2139 | iounmap(pl08x->base); | |
2140 | out_no_ioremap: | |
2141 | dma_pool_destroy(pl08x->pool); | |
2142 | out_no_lli_pool: | |
2143 | out_no_platdata: | |
2144 | kfree(pl08x); | |
2145 | out_no_pl08x: | |
2146 | amba_release_regions(adev); | |
2147 | return ret; | |
2148 | } | |
2149 | ||
2150 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2151 | static struct vendor_data vendor_pl080 = { | |
d86ccea7 | 2152 | .config_offset = PL080_CH_CONFIG, |
e8689e63 LW |
2153 | .channels = 8, |
2154 | .dualmaster = true, | |
2155 | }; | |
2156 | ||
affa115e | 2157 | static struct vendor_data vendor_nomadik = { |
d86ccea7 | 2158 | .config_offset = PL080_CH_CONFIG, |
affa115e LW |
2159 | .channels = 8, |
2160 | .dualmaster = true, | |
2161 | .nomadik = true, | |
2162 | }; | |
2163 | ||
da1b6c05 TF |
2164 | static struct vendor_data vendor_pl080s = { |
2165 | .config_offset = PL080S_CH_CONFIG, | |
2166 | .channels = 8, | |
2167 | .pl080s = true, | |
2168 | }; | |
2169 | ||
e8689e63 | 2170 | static struct vendor_data vendor_pl081 = { |
d86ccea7 | 2171 | .config_offset = PL080_CH_CONFIG, |
e8689e63 LW |
2172 | .channels = 2, |
2173 | .dualmaster = false, | |
2174 | }; | |
2175 | ||
2176 | static struct amba_id pl08x_ids[] = { | |
da1b6c05 TF |
2177 | /* Samsung PL080S variant */ |
2178 | { | |
2179 | .id = 0x0a141080, | |
2180 | .mask = 0xffffffff, | |
2181 | .data = &vendor_pl080s, | |
2182 | }, | |
e8689e63 LW |
2183 | /* PL080 */ |
2184 | { | |
2185 | .id = 0x00041080, | |
2186 | .mask = 0x000fffff, | |
2187 | .data = &vendor_pl080, | |
2188 | }, | |
2189 | /* PL081 */ | |
2190 | { | |
2191 | .id = 0x00041081, | |
2192 | .mask = 0x000fffff, | |
2193 | .data = &vendor_pl081, | |
2194 | }, | |
2195 | /* Nomadik 8815 PL080 variant */ | |
2196 | { | |
affa115e | 2197 | .id = 0x00280080, |
e8689e63 | 2198 | .mask = 0x00ffffff, |
affa115e | 2199 | .data = &vendor_nomadik, |
e8689e63 LW |
2200 | }, |
2201 | { 0, 0 }, | |
2202 | }; | |
2203 | ||
037566df DM |
2204 | MODULE_DEVICE_TABLE(amba, pl08x_ids); |
2205 | ||
e8689e63 LW |
2206 | static struct amba_driver pl08x_amba_driver = { |
2207 | .drv.name = DRIVER_NAME, | |
2208 | .id_table = pl08x_ids, | |
2209 | .probe = pl08x_probe, | |
2210 | }; | |
2211 | ||
2212 | static int __init pl08x_init(void) | |
2213 | { | |
2214 | int retval; | |
2215 | retval = amba_driver_register(&pl08x_amba_driver); | |
2216 | if (retval) | |
2217 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2218 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2219 | retval); |
2220 | return retval; | |
2221 | } | |
2222 | subsys_initcall(pl08x_init); |