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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
94ae8522 RKAL |
22 | * The full GNU General Public License is in this distribution in the file |
23 | * called COPYING. | |
e8689e63 LW |
24 | * |
25 | * Documentation: ARM DDI 0196G == PL080 | |
94ae8522 | 26 | * Documentation: ARM DDI 0218E == PL081 |
da1b6c05 | 27 | * Documentation: S3C6410 User's Manual == PL080S |
e8689e63 | 28 | * |
94ae8522 RKAL |
29 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
30 | * channel. | |
e8689e63 LW |
31 | * |
32 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
33 | * has only two channels. So on these DMA controllers the number of channels | |
34 | * and the number of incoming DMA signals are two totally different things. | |
35 | * It is usually not possible to theoretically handle all physical signals, | |
36 | * so a multiplexing scheme with possible denial of use is necessary. | |
37 | * | |
38 | * The PL080 has a dual bus master, PL081 has a single master. | |
39 | * | |
da1b6c05 TF |
40 | * PL080S is a version modified by Samsung and used in S3C64xx SoCs. |
41 | * It differs in following aspects: | |
42 | * - CH_CONFIG register at different offset, | |
43 | * - separate CH_CONTROL2 register for transfer size, | |
44 | * - bigger maximum transfer size, | |
45 | * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word, | |
46 | * - no support for peripheral flow control. | |
47 | * | |
e8689e63 LW |
48 | * Memory to peripheral transfer may be visualized as |
49 | * Get data from memory to DMAC | |
50 | * Until no data left | |
51 | * On burst request from peripheral | |
52 | * Destination burst from DMAC to peripheral | |
53 | * Clear burst request | |
54 | * Raise terminal count interrupt | |
55 | * | |
56 | * For peripherals with a FIFO: | |
57 | * Source burst size == half the depth of the peripheral FIFO | |
58 | * Destination burst size == the depth of the peripheral FIFO | |
59 | * | |
60 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
61 | * signals, the DMA controller will simply facilitate its AHB master.) | |
62 | * | |
63 | * ASSUMES default (little) endianness for DMA transfers | |
64 | * | |
9dc2c200 RKAL |
65 | * The PL08x has two flow control settings: |
66 | * - DMAC flow control: the transfer size defines the number of transfers | |
67 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
68 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
69 | * to both the BREQ and SREQ signals (contrary to documented), | |
70 | * transferring data if either is active. The LBREQ and LSREQ signals | |
71 | * are ignored. | |
72 | * | |
73 | * - Peripheral flow control: the transfer size is ignored (and should be | |
74 | * zero). The data is transferred from the current LLI entry, until | |
75 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
da1b6c05 | 76 | * will then move to the next LLI entry. Unsupported by PL080S. |
e8689e63 | 77 | */ |
730404ac | 78 | #include <linux/amba/bus.h> |
e8689e63 LW |
79 | #include <linux/amba/pl08x.h> |
80 | #include <linux/debugfs.h> | |
0c38d701 VK |
81 | #include <linux/delay.h> |
82 | #include <linux/device.h> | |
83 | #include <linux/dmaengine.h> | |
84 | #include <linux/dmapool.h> | |
8516f52f | 85 | #include <linux/dma-mapping.h> |
0c38d701 VK |
86 | #include <linux/init.h> |
87 | #include <linux/interrupt.h> | |
88 | #include <linux/module.h> | |
b7b6018b | 89 | #include <linux/pm_runtime.h> |
e8689e63 | 90 | #include <linux/seq_file.h> |
0c38d701 | 91 | #include <linux/slab.h> |
3a95b9fb | 92 | #include <linux/amba/pl080.h> |
e8689e63 | 93 | |
d2ebfb33 | 94 | #include "dmaengine.h" |
01d8dc64 | 95 | #include "virt-dma.h" |
d2ebfb33 | 96 | |
e8689e63 LW |
97 | #define DRIVER_NAME "pl08xdmac" |
98 | ||
7703eac9 | 99 | static struct amba_driver pl08x_amba_driver; |
b23f204c | 100 | struct pl08x_driver_data; |
7703eac9 | 101 | |
e8689e63 | 102 | /** |
94ae8522 | 103 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
e8689e63 | 104 | * @channels: the number of channels available in this variant |
94ae8522 | 105 | * @dualmaster: whether this version supports dual AHB masters or not. |
affa115e LW |
106 | * @nomadik: whether the channels have Nomadik security extension bits |
107 | * that need to be checked for permission before use and some registers are | |
108 | * missing | |
da1b6c05 TF |
109 | * @pl080s: whether this version is a PL080S, which has separate register and |
110 | * LLI word for transfer size. | |
e8689e63 LW |
111 | */ |
112 | struct vendor_data { | |
d86ccea7 | 113 | u8 config_offset; |
e8689e63 LW |
114 | u8 channels; |
115 | bool dualmaster; | |
affa115e | 116 | bool nomadik; |
da1b6c05 | 117 | bool pl080s; |
5110e51d | 118 | u32 max_transfer_size; |
e8689e63 LW |
119 | }; |
120 | ||
b23f204c RK |
121 | /** |
122 | * struct pl08x_bus_data - information of source or destination | |
123 | * busses for a transfer | |
124 | * @addr: current address | |
125 | * @maxwidth: the maximum width of a transfer on this bus | |
126 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | |
127 | */ | |
128 | struct pl08x_bus_data { | |
129 | dma_addr_t addr; | |
130 | u8 maxwidth; | |
131 | u8 buswidth; | |
132 | }; | |
133 | ||
134 | /** | |
135 | * struct pl08x_phy_chan - holder for the physical channels | |
136 | * @id: physical index to this channel | |
137 | * @lock: a lock to use when altering an instance of this struct | |
b23f204c RK |
138 | * @serving: the virtual channel currently being served by this physical |
139 | * channel | |
ad0de2ac RK |
140 | * @locked: channel unavailable for the system, e.g. dedicated to secure |
141 | * world | |
b23f204c RK |
142 | */ |
143 | struct pl08x_phy_chan { | |
144 | unsigned int id; | |
145 | void __iomem *base; | |
d86ccea7 | 146 | void __iomem *reg_config; |
b23f204c | 147 | spinlock_t lock; |
b23f204c | 148 | struct pl08x_dma_chan *serving; |
ad0de2ac | 149 | bool locked; |
b23f204c RK |
150 | }; |
151 | ||
152 | /** | |
153 | * struct pl08x_sg - structure containing data per sg | |
154 | * @src_addr: src address of sg | |
155 | * @dst_addr: dst address of sg | |
156 | * @len: transfer len in bytes | |
157 | * @node: node for txd's dsg_list | |
158 | */ | |
159 | struct pl08x_sg { | |
160 | dma_addr_t src_addr; | |
161 | dma_addr_t dst_addr; | |
162 | size_t len; | |
163 | struct list_head node; | |
164 | }; | |
165 | ||
166 | /** | |
167 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | |
01d8dc64 | 168 | * @vd: virtual DMA descriptor |
b23f204c | 169 | * @dsg_list: list of children sg's |
b23f204c RK |
170 | * @llis_bus: DMA memory address (physical) start for the LLIs |
171 | * @llis_va: virtual memory address start for the LLIs | |
172 | * @cctl: control reg values for current txd | |
173 | * @ccfg: config reg values for current txd | |
18536134 RK |
174 | * @done: this marks completed descriptors, which should not have their |
175 | * mux released. | |
b23f204c RK |
176 | */ |
177 | struct pl08x_txd { | |
01d8dc64 | 178 | struct virt_dma_desc vd; |
b23f204c | 179 | struct list_head dsg_list; |
b23f204c | 180 | dma_addr_t llis_bus; |
ba6785ff | 181 | u32 *llis_va; |
b23f204c RK |
182 | /* Default cctl value for LLIs */ |
183 | u32 cctl; | |
184 | /* | |
185 | * Settings to be put into the physical channel when we | |
186 | * trigger this txd. Other registers are in llis_va[0]. | |
187 | */ | |
188 | u32 ccfg; | |
18536134 | 189 | bool done; |
b23f204c RK |
190 | }; |
191 | ||
192 | /** | |
193 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel | |
194 | * states | |
195 | * @PL08X_CHAN_IDLE: the channel is idle | |
196 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | |
197 | * channel and is running a transfer on it | |
198 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport | |
199 | * channel, but the transfer is currently paused | |
200 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport | |
201 | * channel to become available (only pertains to memcpy channels) | |
202 | */ | |
203 | enum pl08x_dma_chan_state { | |
204 | PL08X_CHAN_IDLE, | |
205 | PL08X_CHAN_RUNNING, | |
206 | PL08X_CHAN_PAUSED, | |
207 | PL08X_CHAN_WAITING, | |
208 | }; | |
209 | ||
210 | /** | |
211 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | |
01d8dc64 | 212 | * @vc: wrappped virtual channel |
b23f204c | 213 | * @phychan: the physical channel utilized by this channel, if there is one |
b23f204c RK |
214 | * @name: name of channel |
215 | * @cd: channel platform data | |
216 | * @runtime_addr: address for RX/TX according to the runtime config | |
b23f204c RK |
217 | * @at: active transaction on this channel |
218 | * @lock: a lock for this channel data | |
219 | * @host: a pointer to the host (internal use) | |
220 | * @state: whether the channel is idle, paused, running etc | |
221 | * @slave: whether this channel is a device (slave) or for memcpy | |
ad0de2ac | 222 | * @signal: the physical DMA request signal which this channel is using |
5e2479bd | 223 | * @mux_use: count of descriptors using this DMA request signal setting |
b23f204c RK |
224 | */ |
225 | struct pl08x_dma_chan { | |
01d8dc64 | 226 | struct virt_dma_chan vc; |
b23f204c | 227 | struct pl08x_phy_chan *phychan; |
550ec36f | 228 | const char *name; |
b23f204c | 229 | const struct pl08x_channel_data *cd; |
ed91c13d | 230 | struct dma_slave_config cfg; |
b23f204c | 231 | struct pl08x_txd *at; |
b23f204c RK |
232 | struct pl08x_driver_data *host; |
233 | enum pl08x_dma_chan_state state; | |
234 | bool slave; | |
ad0de2ac | 235 | int signal; |
5e2479bd | 236 | unsigned mux_use; |
b23f204c RK |
237 | }; |
238 | ||
e8689e63 LW |
239 | /** |
240 | * struct pl08x_driver_data - the local state holder for the PL08x | |
241 | * @slave: slave engine for this instance | |
242 | * @memcpy: memcpy engine for this instance | |
243 | * @base: virtual memory base (remapped) for the PL08x | |
244 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
245 | * @vd: vendor data for this PL08x variant | |
246 | * @pd: platform data passed in from the platform/machine | |
247 | * @phy_chans: array of data for the physical channels | |
248 | * @pool: a pool for the LLI descriptors | |
3e27ee84 VK |
249 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
250 | * fetches | |
30749cb4 | 251 | * @mem_buses: set to indicate memory transfers on AHB2. |
e8689e63 LW |
252 | * @lock: a spinlock for this struct |
253 | */ | |
254 | struct pl08x_driver_data { | |
255 | struct dma_device slave; | |
256 | struct dma_device memcpy; | |
257 | void __iomem *base; | |
258 | struct amba_device *adev; | |
f96ca9ec | 259 | const struct vendor_data *vd; |
e8689e63 LW |
260 | struct pl08x_platform_data *pd; |
261 | struct pl08x_phy_chan *phy_chans; | |
262 | struct dma_pool *pool; | |
30749cb4 RKAL |
263 | u8 lli_buses; |
264 | u8 mem_buses; | |
ba6785ff | 265 | u8 lli_words; |
e8689e63 LW |
266 | }; |
267 | ||
268 | /* | |
269 | * PL08X specific defines | |
270 | */ | |
271 | ||
ba6785ff TF |
272 | /* The order of words in an LLI. */ |
273 | #define PL080_LLI_SRC 0 | |
274 | #define PL080_LLI_DST 1 | |
275 | #define PL080_LLI_LLI 2 | |
276 | #define PL080_LLI_CCTL 3 | |
da1b6c05 | 277 | #define PL080S_LLI_CCTL2 4 |
ba6785ff TF |
278 | |
279 | /* Total words in an LLI. */ | |
280 | #define PL080_LLI_WORDS 4 | |
da1b6c05 | 281 | #define PL080S_LLI_WORDS 8 |
e8689e63 | 282 | |
ba6785ff TF |
283 | /* |
284 | * Number of LLIs in each LLI buffer allocated for one transfer | |
285 | * (maximum times we call dma_pool_alloc on this pool without freeing) | |
286 | */ | |
287 | #define MAX_NUM_TSFR_LLIS 512 | |
e8689e63 LW |
288 | #define PL08X_ALIGN 8 |
289 | ||
290 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
291 | { | |
01d8dc64 | 292 | return container_of(chan, struct pl08x_dma_chan, vc.chan); |
e8689e63 LW |
293 | } |
294 | ||
501e67e8 RKAL |
295 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
296 | { | |
01d8dc64 | 297 | return container_of(tx, struct pl08x_txd, vd.tx); |
501e67e8 RKAL |
298 | } |
299 | ||
6b16c8b1 RK |
300 | /* |
301 | * Mux handling. | |
302 | * | |
303 | * This gives us the DMA request input to the PL08x primecell which the | |
304 | * peripheral described by the channel data will be routed to, possibly | |
305 | * via a board/SoC specific external MUX. One important point to note | |
306 | * here is that this does not depend on the physical channel. | |
307 | */ | |
ad0de2ac | 308 | static int pl08x_request_mux(struct pl08x_dma_chan *plchan) |
6b16c8b1 RK |
309 | { |
310 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
311 | int ret; | |
312 | ||
d7cabeed MB |
313 | if (plchan->mux_use++ == 0 && pd->get_xfer_signal) { |
314 | ret = pd->get_xfer_signal(plchan->cd); | |
5e2479bd RK |
315 | if (ret < 0) { |
316 | plchan->mux_use = 0; | |
6b16c8b1 | 317 | return ret; |
5e2479bd | 318 | } |
6b16c8b1 | 319 | |
ad0de2ac | 320 | plchan->signal = ret; |
6b16c8b1 RK |
321 | } |
322 | return 0; | |
323 | } | |
324 | ||
325 | static void pl08x_release_mux(struct pl08x_dma_chan *plchan) | |
326 | { | |
327 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
328 | ||
5e2479bd RK |
329 | if (plchan->signal >= 0) { |
330 | WARN_ON(plchan->mux_use == 0); | |
331 | ||
d7cabeed MB |
332 | if (--plchan->mux_use == 0 && pd->put_xfer_signal) { |
333 | pd->put_xfer_signal(plchan->cd, plchan->signal); | |
5e2479bd RK |
334 | plchan->signal = -1; |
335 | } | |
6b16c8b1 RK |
336 | } |
337 | } | |
338 | ||
e8689e63 LW |
339 | /* |
340 | * Physical channel handling | |
341 | */ | |
342 | ||
343 | /* Whether a certain channel is busy or not */ | |
344 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
345 | { | |
346 | unsigned int val; | |
347 | ||
d86ccea7 | 348 | val = readl(ch->reg_config); |
e8689e63 LW |
349 | return val & PL080_CONFIG_ACTIVE; |
350 | } | |
351 | ||
ba6785ff TF |
352 | static void pl08x_write_lli(struct pl08x_driver_data *pl08x, |
353 | struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg) | |
354 | { | |
da1b6c05 TF |
355 | if (pl08x->vd->pl080s) |
356 | dev_vdbg(&pl08x->adev->dev, | |
357 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
358 | "clli=0x%08x, cctl=0x%08x, cctl2=0x%08x, ccfg=0x%08x\n", | |
359 | phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST], | |
360 | lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], | |
361 | lli[PL080S_LLI_CCTL2], ccfg); | |
362 | else | |
363 | dev_vdbg(&pl08x->adev->dev, | |
364 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
365 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", | |
366 | phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST], | |
367 | lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg); | |
ba6785ff TF |
368 | |
369 | writel_relaxed(lli[PL080_LLI_SRC], phychan->base + PL080_CH_SRC_ADDR); | |
370 | writel_relaxed(lli[PL080_LLI_DST], phychan->base + PL080_CH_DST_ADDR); | |
371 | writel_relaxed(lli[PL080_LLI_LLI], phychan->base + PL080_CH_LLI); | |
372 | writel_relaxed(lli[PL080_LLI_CCTL], phychan->base + PL080_CH_CONTROL); | |
373 | ||
da1b6c05 TF |
374 | if (pl08x->vd->pl080s) |
375 | writel_relaxed(lli[PL080S_LLI_CCTL2], | |
376 | phychan->base + PL080S_CH_CONTROL2); | |
377 | ||
ba6785ff TF |
378 | writel(ccfg, phychan->reg_config); |
379 | } | |
380 | ||
e8689e63 LW |
381 | /* |
382 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 383 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
384 | * been set when the LLIs were constructed. Poke them into the hardware |
385 | * and start the transfer. | |
e8689e63 | 386 | */ |
eab82533 | 387 | static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) |
e8689e63 | 388 | { |
c885bee4 | 389 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 390 | struct pl08x_phy_chan *phychan = plchan->phychan; |
879f127b RK |
391 | struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc); |
392 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
09b3c323 | 393 | u32 val; |
c885bee4 | 394 | |
879f127b | 395 | list_del(&txd->vd.node); |
eab82533 | 396 | |
c885bee4 | 397 | plchan->at = txd; |
e8689e63 | 398 | |
c885bee4 RKAL |
399 | /* Wait for channel inactive */ |
400 | while (pl08x_phy_channel_busy(phychan)) | |
401 | cpu_relax(); | |
e8689e63 | 402 | |
ba6785ff | 403 | pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg); |
c885bee4 RKAL |
404 | |
405 | /* Enable the DMA channel */ | |
406 | /* Do not access config register until channel shows as disabled */ | |
407 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 408 | cpu_relax(); |
e8689e63 | 409 | |
c885bee4 | 410 | /* Do not access config register until channel shows as inactive */ |
d86ccea7 | 411 | val = readl(phychan->reg_config); |
e8689e63 | 412 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
d86ccea7 | 413 | val = readl(phychan->reg_config); |
e8689e63 | 414 | |
d86ccea7 | 415 | writel(val | PL080_CONFIG_ENABLE, phychan->reg_config); |
e8689e63 LW |
416 | } |
417 | ||
418 | /* | |
81796616 | 419 | * Pause the channel by setting the HALT bit. |
e8689e63 | 420 | * |
81796616 RKAL |
421 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
422 | * the FIFO can only drain if the peripheral is still requesting data. | |
423 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 424 | * |
81796616 RKAL |
425 | * For P->M transfers, disable the peripheral first to stop it filling |
426 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
427 | */ |
428 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
429 | { | |
430 | u32 val; | |
81796616 | 431 | int timeout; |
e8689e63 LW |
432 | |
433 | /* Set the HALT bit and wait for the FIFO to drain */ | |
d86ccea7 | 434 | val = readl(ch->reg_config); |
e8689e63 | 435 | val |= PL080_CONFIG_HALT; |
d86ccea7 | 436 | writel(val, ch->reg_config); |
e8689e63 LW |
437 | |
438 | /* Wait for channel inactive */ | |
81796616 RKAL |
439 | for (timeout = 1000; timeout; timeout--) { |
440 | if (!pl08x_phy_channel_busy(ch)) | |
441 | break; | |
442 | udelay(1); | |
443 | } | |
444 | if (pl08x_phy_channel_busy(ch)) | |
445 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
446 | } |
447 | ||
448 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
449 | { | |
450 | u32 val; | |
451 | ||
452 | /* Clear the HALT bit */ | |
d86ccea7 | 453 | val = readl(ch->reg_config); |
e8689e63 | 454 | val &= ~PL080_CONFIG_HALT; |
d86ccea7 | 455 | writel(val, ch->reg_config); |
e8689e63 LW |
456 | } |
457 | ||
fb526210 RKAL |
458 | /* |
459 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
460 | * clears any pending interrupt status. This should not be used for | |
461 | * an on-going transfer, but as a method of shutting down a channel | |
462 | * (eg, when it's no longer used) or terminating a transfer. | |
463 | */ | |
464 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
465 | struct pl08x_phy_chan *ch) | |
e8689e63 | 466 | { |
d86ccea7 | 467 | u32 val = readl(ch->reg_config); |
e8689e63 | 468 | |
fb526210 RKAL |
469 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
470 | PL080_CONFIG_TC_IRQ_MASK); | |
e8689e63 | 471 | |
d86ccea7 | 472 | writel(val, ch->reg_config); |
fb526210 RKAL |
473 | |
474 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); | |
475 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
476 | } |
477 | ||
478 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
479 | { | |
480 | /* The source width defines the number of bytes */ | |
481 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
482 | ||
f3287a52 AB |
483 | cctl &= PL080_CONTROL_SWIDTH_MASK; |
484 | ||
e8689e63 LW |
485 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { |
486 | case PL080_WIDTH_8BIT: | |
487 | break; | |
488 | case PL080_WIDTH_16BIT: | |
489 | bytes *= 2; | |
490 | break; | |
491 | case PL080_WIDTH_32BIT: | |
492 | bytes *= 4; | |
493 | break; | |
494 | } | |
495 | return bytes; | |
496 | } | |
497 | ||
da1b6c05 TF |
498 | static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1) |
499 | { | |
500 | /* The source width defines the number of bytes */ | |
501 | u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK; | |
502 | ||
f3287a52 AB |
503 | cctl &= PL080_CONTROL_SWIDTH_MASK; |
504 | ||
da1b6c05 TF |
505 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { |
506 | case PL080_WIDTH_8BIT: | |
507 | break; | |
508 | case PL080_WIDTH_16BIT: | |
509 | bytes *= 2; | |
510 | break; | |
511 | case PL080_WIDTH_32BIT: | |
512 | bytes *= 4; | |
513 | break; | |
514 | } | |
515 | return bytes; | |
516 | } | |
517 | ||
e8689e63 LW |
518 | /* The channel should be paused when calling this */ |
519 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
520 | { | |
ba6785ff TF |
521 | struct pl08x_driver_data *pl08x = plchan->host; |
522 | const u32 *llis_va, *llis_va_limit; | |
e8689e63 | 523 | struct pl08x_phy_chan *ch; |
68a7faa2 | 524 | dma_addr_t llis_bus; |
e8689e63 | 525 | struct pl08x_txd *txd; |
ba6785ff | 526 | u32 llis_max_words; |
68a7faa2 | 527 | size_t bytes; |
68a7faa2 | 528 | u32 clli; |
e8689e63 | 529 | |
e8689e63 LW |
530 | ch = plchan->phychan; |
531 | txd = plchan->at; | |
532 | ||
68a7faa2 TF |
533 | if (!ch || !txd) |
534 | return 0; | |
535 | ||
e8689e63 | 536 | /* |
db9f136a RKAL |
537 | * Follow the LLIs to get the number of remaining |
538 | * bytes in the currently active transaction. | |
e8689e63 | 539 | */ |
68a7faa2 | 540 | clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 541 | |
68a7faa2 | 542 | /* First get the remaining bytes in the active transfer */ |
da1b6c05 TF |
543 | if (pl08x->vd->pl080s) |
544 | bytes = get_bytes_in_cctl_pl080s( | |
545 | readl(ch->base + PL080_CH_CONTROL), | |
546 | readl(ch->base + PL080S_CH_CONTROL2)); | |
547 | else | |
548 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); | |
e8689e63 | 549 | |
68a7faa2 TF |
550 | if (!clli) |
551 | return bytes; | |
db9f136a | 552 | |
68a7faa2 TF |
553 | llis_va = txd->llis_va; |
554 | llis_bus = txd->llis_bus; | |
555 | ||
ba6785ff | 556 | llis_max_words = pl08x->lli_words * MAX_NUM_TSFR_LLIS; |
68a7faa2 | 557 | BUG_ON(clli < llis_bus || clli >= llis_bus + |
ba6785ff | 558 | sizeof(u32) * llis_max_words); |
e8689e63 | 559 | |
68a7faa2 TF |
560 | /* |
561 | * Locate the next LLI - as this is an array, | |
562 | * it's simple maths to find. | |
563 | */ | |
ba6785ff | 564 | llis_va += (clli - llis_bus) / sizeof(u32); |
68a7faa2 | 565 | |
ba6785ff TF |
566 | llis_va_limit = llis_va + llis_max_words; |
567 | ||
568 | for (; llis_va < llis_va_limit; llis_va += pl08x->lli_words) { | |
da1b6c05 TF |
569 | if (pl08x->vd->pl080s) |
570 | bytes += get_bytes_in_cctl_pl080s( | |
571 | llis_va[PL080_LLI_CCTL], | |
572 | llis_va[PL080S_LLI_CCTL2]); | |
573 | else | |
574 | bytes += get_bytes_in_cctl(llis_va[PL080_LLI_CCTL]); | |
68a7faa2 TF |
575 | |
576 | /* | |
577 | * A LLI pointer of 0 terminates the LLI list | |
578 | */ | |
ba6785ff | 579 | if (!llis_va[PL080_LLI_LLI]) |
68a7faa2 | 580 | break; |
e8689e63 LW |
581 | } |
582 | ||
e8689e63 LW |
583 | return bytes; |
584 | } | |
585 | ||
586 | /* | |
587 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
588 | * |
589 | * Try to locate a physical channel to be used for this transfer. If all | |
590 | * are taken return NULL and the requester will have to cope by using | |
591 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
592 | */ |
593 | static struct pl08x_phy_chan * | |
594 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
595 | struct pl08x_dma_chan *virt_chan) | |
596 | { | |
597 | struct pl08x_phy_chan *ch = NULL; | |
598 | unsigned long flags; | |
599 | int i; | |
600 | ||
e8689e63 LW |
601 | for (i = 0; i < pl08x->vd->channels; i++) { |
602 | ch = &pl08x->phy_chans[i]; | |
603 | ||
604 | spin_lock_irqsave(&ch->lock, flags); | |
605 | ||
affa115e | 606 | if (!ch->locked && !ch->serving) { |
e8689e63 | 607 | ch->serving = virt_chan; |
e8689e63 LW |
608 | spin_unlock_irqrestore(&ch->lock, flags); |
609 | break; | |
610 | } | |
611 | ||
612 | spin_unlock_irqrestore(&ch->lock, flags); | |
613 | } | |
614 | ||
615 | if (i == pl08x->vd->channels) { | |
616 | /* No physical channel available, cope with it */ | |
617 | return NULL; | |
618 | } | |
619 | ||
620 | return ch; | |
621 | } | |
622 | ||
a5a488db | 623 | /* Mark the physical channel as free. Note, this write is atomic. */ |
e8689e63 LW |
624 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, |
625 | struct pl08x_phy_chan *ch) | |
626 | { | |
a5a488db RK |
627 | ch->serving = NULL; |
628 | } | |
e8689e63 | 629 | |
a5a488db RK |
630 | /* |
631 | * Try to allocate a physical channel. When successful, assign it to | |
632 | * this virtual channel, and initiate the next descriptor. The | |
633 | * virtual channel lock must be held at this point. | |
634 | */ | |
635 | static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan) | |
636 | { | |
637 | struct pl08x_driver_data *pl08x = plchan->host; | |
638 | struct pl08x_phy_chan *ch; | |
fb526210 | 639 | |
a5a488db RK |
640 | ch = pl08x_get_phy_channel(pl08x, plchan); |
641 | if (!ch) { | |
642 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
643 | plchan->state = PL08X_CHAN_WAITING; | |
644 | return; | |
645 | } | |
e8689e63 | 646 | |
a5a488db RK |
647 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n", |
648 | ch->id, plchan->name); | |
649 | ||
650 | plchan->phychan = ch; | |
651 | plchan->state = PL08X_CHAN_RUNNING; | |
652 | pl08x_start_next_txd(plchan); | |
653 | } | |
654 | ||
655 | static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch, | |
656 | struct pl08x_dma_chan *plchan) | |
657 | { | |
658 | struct pl08x_driver_data *pl08x = plchan->host; | |
659 | ||
660 | dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n", | |
661 | ch->id, plchan->name); | |
662 | ||
663 | /* | |
664 | * We do this without taking the lock; we're really only concerned | |
665 | * about whether this pointer is NULL or not, and we're guaranteed | |
666 | * that this will only be called when it _already_ is non-NULL. | |
667 | */ | |
668 | ch->serving = plchan; | |
669 | plchan->phychan = ch; | |
670 | plchan->state = PL08X_CHAN_RUNNING; | |
671 | pl08x_start_next_txd(plchan); | |
672 | } | |
673 | ||
674 | /* | |
675 | * Free a physical DMA channel, potentially reallocating it to another | |
676 | * virtual channel if we have any pending. | |
677 | */ | |
678 | static void pl08x_phy_free(struct pl08x_dma_chan *plchan) | |
679 | { | |
680 | struct pl08x_driver_data *pl08x = plchan->host; | |
681 | struct pl08x_dma_chan *p, *next; | |
682 | ||
683 | retry: | |
684 | next = NULL; | |
685 | ||
686 | /* Find a waiting virtual channel for the next transfer. */ | |
01d8dc64 | 687 | list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node) |
a5a488db RK |
688 | if (p->state == PL08X_CHAN_WAITING) { |
689 | next = p; | |
690 | break; | |
691 | } | |
692 | ||
693 | if (!next) { | |
01d8dc64 | 694 | list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node) |
a5a488db RK |
695 | if (p->state == PL08X_CHAN_WAITING) { |
696 | next = p; | |
697 | break; | |
698 | } | |
699 | } | |
700 | ||
701 | /* Ensure that the physical channel is stopped */ | |
702 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); | |
703 | ||
704 | if (next) { | |
705 | bool success; | |
706 | ||
707 | /* | |
708 | * Eww. We know this isn't going to deadlock | |
709 | * but lockdep probably doesn't. | |
710 | */ | |
083be28a | 711 | spin_lock(&next->vc.lock); |
a5a488db RK |
712 | /* Re-check the state now that we have the lock */ |
713 | success = next->state == PL08X_CHAN_WAITING; | |
714 | if (success) | |
715 | pl08x_phy_reassign_start(plchan->phychan, next); | |
083be28a | 716 | spin_unlock(&next->vc.lock); |
a5a488db RK |
717 | |
718 | /* If the state changed, try to find another channel */ | |
719 | if (!success) | |
720 | goto retry; | |
721 | } else { | |
722 | /* No more jobs, so free up the physical channel */ | |
723 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
724 | } | |
725 | ||
726 | plchan->phychan = NULL; | |
727 | plchan->state = PL08X_CHAN_IDLE; | |
e8689e63 LW |
728 | } |
729 | ||
730 | /* | |
731 | * LLI handling | |
732 | */ | |
733 | ||
734 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
735 | { | |
736 | switch (coded) { | |
737 | case PL080_WIDTH_8BIT: | |
738 | return 1; | |
739 | case PL080_WIDTH_16BIT: | |
740 | return 2; | |
741 | case PL080_WIDTH_32BIT: | |
742 | return 4; | |
743 | default: | |
744 | break; | |
745 | } | |
746 | BUG(); | |
747 | return 0; | |
748 | } | |
749 | ||
750 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 751 | size_t tsize) |
e8689e63 LW |
752 | { |
753 | u32 retbits = cctl; | |
754 | ||
e8b5e11d | 755 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
756 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
757 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
758 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
759 | ||
760 | /* Then set the bits according to the parameters */ | |
761 | switch (srcwidth) { | |
762 | case 1: | |
763 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
764 | break; | |
765 | case 2: | |
766 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
767 | break; | |
768 | case 4: | |
769 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
770 | break; | |
771 | default: | |
772 | BUG(); | |
773 | break; | |
774 | } | |
775 | ||
776 | switch (dstwidth) { | |
777 | case 1: | |
778 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
779 | break; | |
780 | case 2: | |
781 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
782 | break; | |
783 | case 4: | |
784 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
785 | break; | |
786 | default: | |
787 | BUG(); | |
788 | break; | |
789 | } | |
790 | ||
5110e51d | 791 | tsize &= PL080_CONTROL_TRANSFER_SIZE_MASK; |
e8689e63 LW |
792 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; |
793 | return retbits; | |
794 | } | |
795 | ||
542361f8 RKAL |
796 | struct pl08x_lli_build_data { |
797 | struct pl08x_txd *txd; | |
542361f8 RKAL |
798 | struct pl08x_bus_data srcbus; |
799 | struct pl08x_bus_data dstbus; | |
800 | size_t remainder; | |
25c94f7f | 801 | u32 lli_bus; |
542361f8 RKAL |
802 | }; |
803 | ||
e8689e63 | 804 | /* |
0532e6fc VK |
805 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
806 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
807 | * masters address with width requirements of transfer (by sending few byte by | |
808 | * byte data), slave is still not aligned, then its width will be reduced to | |
809 | * BYTE. | |
810 | * - prefers the destination bus if both available | |
036f05fd | 811 | * - prefers bus with fixed address (i.e. peripheral) |
e8689e63 | 812 | */ |
542361f8 RKAL |
813 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
814 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) | |
e8689e63 LW |
815 | { |
816 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
542361f8 RKAL |
817 | *mbus = &bd->dstbus; |
818 | *sbus = &bd->srcbus; | |
036f05fd VK |
819 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
820 | *mbus = &bd->srcbus; | |
821 | *sbus = &bd->dstbus; | |
e8689e63 | 822 | } else { |
036f05fd | 823 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
542361f8 RKAL |
824 | *mbus = &bd->dstbus; |
825 | *sbus = &bd->srcbus; | |
036f05fd | 826 | } else { |
542361f8 RKAL |
827 | *mbus = &bd->srcbus; |
828 | *sbus = &bd->dstbus; | |
e8689e63 LW |
829 | } |
830 | } | |
831 | } | |
832 | ||
833 | /* | |
94ae8522 | 834 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 835 | */ |
ba6785ff TF |
836 | static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x, |
837 | struct pl08x_lli_build_data *bd, | |
da1b6c05 | 838 | int num_llis, int len, u32 cctl, u32 cctl2) |
e8689e63 | 839 | { |
ba6785ff TF |
840 | u32 offset = num_llis * pl08x->lli_words; |
841 | u32 *llis_va = bd->txd->llis_va + offset; | |
542361f8 | 842 | dma_addr_t llis_bus = bd->txd->llis_bus; |
e8689e63 LW |
843 | |
844 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
845 | ||
ba6785ff TF |
846 | /* Advance the offset to next LLI. */ |
847 | offset += pl08x->lli_words; | |
848 | ||
849 | llis_va[PL080_LLI_SRC] = bd->srcbus.addr; | |
850 | llis_va[PL080_LLI_DST] = bd->dstbus.addr; | |
851 | llis_va[PL080_LLI_LLI] = (llis_bus + sizeof(u32) * offset); | |
852 | llis_va[PL080_LLI_LLI] |= bd->lli_bus; | |
853 | llis_va[PL080_LLI_CCTL] = cctl; | |
da1b6c05 TF |
854 | if (pl08x->vd->pl080s) |
855 | llis_va[PL080S_LLI_CCTL2] = cctl2; | |
e8689e63 LW |
856 | |
857 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 | 858 | bd->srcbus.addr += len; |
e8689e63 | 859 | if (cctl & PL080_CONTROL_DST_INCR) |
542361f8 | 860 | bd->dstbus.addr += len; |
e8689e63 | 861 | |
542361f8 | 862 | BUG_ON(bd->remainder < len); |
cace6585 | 863 | |
542361f8 | 864 | bd->remainder -= len; |
e8689e63 LW |
865 | } |
866 | ||
ba6785ff TF |
867 | static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x, |
868 | struct pl08x_lli_build_data *bd, u32 *cctl, u32 len, | |
869 | int num_llis, size_t *total_bytes) | |
e8689e63 | 870 | { |
03af500f | 871 | *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); |
da1b6c05 | 872 | pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl, len); |
03af500f | 873 | (*total_bytes) += len; |
e8689e63 LW |
874 | } |
875 | ||
48924e42 TF |
876 | #ifdef VERBOSE_DEBUG |
877 | static void pl08x_dump_lli(struct pl08x_driver_data *pl08x, | |
878 | const u32 *llis_va, int num_llis) | |
879 | { | |
880 | int i; | |
881 | ||
da1b6c05 | 882 | if (pl08x->vd->pl080s) { |
48924e42 | 883 | dev_vdbg(&pl08x->adev->dev, |
da1b6c05 TF |
884 | "%-3s %-9s %-10s %-10s %-10s %-10s %s\n", |
885 | "lli", "", "csrc", "cdst", "clli", "cctl", "cctl2"); | |
886 | for (i = 0; i < num_llis; i++) { | |
887 | dev_vdbg(&pl08x->adev->dev, | |
888 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
889 | i, llis_va, llis_va[PL080_LLI_SRC], | |
890 | llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI], | |
891 | llis_va[PL080_LLI_CCTL], | |
892 | llis_va[PL080S_LLI_CCTL2]); | |
893 | llis_va += pl08x->lli_words; | |
894 | } | |
895 | } else { | |
896 | dev_vdbg(&pl08x->adev->dev, | |
897 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
898 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
899 | for (i = 0; i < num_llis; i++) { | |
900 | dev_vdbg(&pl08x->adev->dev, | |
901 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
902 | i, llis_va, llis_va[PL080_LLI_SRC], | |
903 | llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI], | |
904 | llis_va[PL080_LLI_CCTL]); | |
905 | llis_va += pl08x->lli_words; | |
906 | } | |
48924e42 TF |
907 | } |
908 | } | |
909 | #else | |
910 | static inline void pl08x_dump_lli(struct pl08x_driver_data *pl08x, | |
911 | const u32 *llis_va, int num_llis) {} | |
912 | #endif | |
913 | ||
e8689e63 LW |
914 | /* |
915 | * This fills in the table of LLIs for the transfer descriptor | |
916 | * Note that we assume we never have to change the burst sizes | |
917 | * Return 0 for error | |
918 | */ | |
919 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
920 | struct pl08x_txd *txd) | |
921 | { | |
e8689e63 | 922 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 923 | struct pl08x_lli_build_data bd; |
e8689e63 | 924 | int num_llis = 0; |
03af500f | 925 | u32 cctl, early_bytes = 0; |
b7f69d9d | 926 | size_t max_bytes_per_lli, total_bytes; |
ba6785ff | 927 | u32 *llis_va, *last_lli; |
b7f69d9d | 928 | struct pl08x_sg *dsg; |
e8689e63 | 929 | |
3e27ee84 | 930 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
931 | if (!txd->llis_va) { |
932 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
933 | return 0; | |
934 | } | |
935 | ||
542361f8 | 936 | bd.txd = txd; |
25c94f7f | 937 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
b7f69d9d | 938 | cctl = txd->cctl; |
542361f8 | 939 | |
e8689e63 | 940 | /* Find maximum width of the source bus */ |
542361f8 | 941 | bd.srcbus.maxwidth = |
e8689e63 LW |
942 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
943 | PL080_CONTROL_SWIDTH_SHIFT); | |
944 | ||
945 | /* Find maximum width of the destination bus */ | |
542361f8 | 946 | bd.dstbus.maxwidth = |
e8689e63 LW |
947 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
948 | PL080_CONTROL_DWIDTH_SHIFT); | |
949 | ||
b7f69d9d VK |
950 | list_for_each_entry(dsg, &txd->dsg_list, node) { |
951 | total_bytes = 0; | |
952 | cctl = txd->cctl; | |
e8689e63 | 953 | |
b7f69d9d VK |
954 | bd.srcbus.addr = dsg->src_addr; |
955 | bd.dstbus.addr = dsg->dst_addr; | |
956 | bd.remainder = dsg->len; | |
957 | bd.srcbus.buswidth = bd.srcbus.maxwidth; | |
958 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 | 959 | |
b7f69d9d | 960 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
e8689e63 | 961 | |
b7f69d9d VK |
962 | dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n", |
963 | bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", | |
964 | bd.srcbus.buswidth, | |
965 | bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
966 | bd.dstbus.buswidth, | |
967 | bd.remainder); | |
968 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", | |
969 | mbus == &bd.srcbus ? "src" : "dst", | |
970 | sbus == &bd.srcbus ? "src" : "dst"); | |
fc74eb79 | 971 | |
b7f69d9d VK |
972 | /* |
973 | * Zero length is only allowed if all these requirements are | |
974 | * met: | |
975 | * - flow controller is peripheral. | |
976 | * - src.addr is aligned to src.width | |
977 | * - dst.addr is aligned to dst.width | |
978 | * | |
979 | * sg_len == 1 should be true, as there can be two cases here: | |
980 | * | |
981 | * - Memory addresses are contiguous and are not scattered. | |
982 | * Here, Only one sg will be passed by user driver, with | |
983 | * memory address and zero length. We pass this to controller | |
984 | * and after the transfer it will receive the last burst | |
985 | * request from peripheral and so transfer finishes. | |
986 | * | |
987 | * - Memory addresses are scattered and are not contiguous. | |
988 | * Here, Obviously as DMA controller doesn't know when a lli's | |
989 | * transfer gets over, it can't load next lli. So in this | |
990 | * case, there has to be an assumption that only one lli is | |
991 | * supported. Thus, we can't have scattered addresses. | |
992 | */ | |
993 | if (!bd.remainder) { | |
994 | u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> | |
995 | PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
996 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && | |
0a235657 | 997 | (fc <= PL080_FLOW_SRC2DST_SRC))) { |
b7f69d9d VK |
998 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", |
999 | __func__); | |
1000 | return 0; | |
1001 | } | |
0a235657 | 1002 | |
b7f69d9d | 1003 | if ((bd.srcbus.addr % bd.srcbus.buswidth) || |
880db3ff | 1004 | (bd.dstbus.addr % bd.dstbus.buswidth)) { |
b7f69d9d VK |
1005 | dev_err(&pl08x->adev->dev, |
1006 | "%s src & dst address must be aligned to src" | |
1007 | " & dst width if peripheral is flow controller", | |
1008 | __func__); | |
1009 | return 0; | |
1010 | } | |
03af500f | 1011 | |
b7f69d9d VK |
1012 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
1013 | bd.dstbus.buswidth, 0); | |
ba6785ff | 1014 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
da1b6c05 | 1015 | 0, cctl, 0); |
b7f69d9d VK |
1016 | break; |
1017 | } | |
e8689e63 LW |
1018 | |
1019 | /* | |
b7f69d9d VK |
1020 | * Send byte by byte for following cases |
1021 | * - Less than a bus width available | |
1022 | * - until master bus is aligned | |
e8689e63 | 1023 | */ |
b7f69d9d VK |
1024 | if (bd.remainder < mbus->buswidth) |
1025 | early_bytes = bd.remainder; | |
1026 | else if ((mbus->addr) % (mbus->buswidth)) { | |
1027 | early_bytes = mbus->buswidth - (mbus->addr) % | |
1028 | (mbus->buswidth); | |
1029 | if ((bd.remainder - early_bytes) < mbus->buswidth) | |
1030 | early_bytes = bd.remainder; | |
1031 | } | |
e8689e63 | 1032 | |
b7f69d9d VK |
1033 | if (early_bytes) { |
1034 | dev_vdbg(&pl08x->adev->dev, | |
1035 | "%s byte width LLIs (remain 0x%08x)\n", | |
1036 | __func__, bd.remainder); | |
ba6785ff TF |
1037 | prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes, |
1038 | num_llis++, &total_bytes); | |
e8689e63 LW |
1039 | } |
1040 | ||
b7f69d9d VK |
1041 | if (bd.remainder) { |
1042 | /* | |
1043 | * Master now aligned | |
1044 | * - if slave is not then we must set its width down | |
1045 | */ | |
1046 | if (sbus->addr % sbus->buswidth) { | |
1047 | dev_dbg(&pl08x->adev->dev, | |
1048 | "%s set down bus width to one byte\n", | |
1049 | __func__); | |
fa6a940b | 1050 | |
b7f69d9d VK |
1051 | sbus->buswidth = 1; |
1052 | } | |
e8689e63 LW |
1053 | |
1054 | /* | |
b7f69d9d VK |
1055 | * Bytes transferred = tsize * src width, not |
1056 | * MIN(buswidths) | |
e8689e63 | 1057 | */ |
b7f69d9d | 1058 | max_bytes_per_lli = bd.srcbus.buswidth * |
5110e51d | 1059 | pl08x->vd->max_transfer_size; |
b7f69d9d VK |
1060 | dev_vdbg(&pl08x->adev->dev, |
1061 | "%s max bytes per lli = %zu\n", | |
1062 | __func__, max_bytes_per_lli); | |
e8689e63 LW |
1063 | |
1064 | /* | |
b7f69d9d VK |
1065 | * Make largest possible LLIs until less than one bus |
1066 | * width left | |
e8689e63 | 1067 | */ |
b7f69d9d VK |
1068 | while (bd.remainder > (mbus->buswidth - 1)) { |
1069 | size_t lli_len, tsize, width; | |
e8689e63 | 1070 | |
b7f69d9d VK |
1071 | /* |
1072 | * If enough left try to send max possible, | |
1073 | * otherwise try to send the remainder | |
1074 | */ | |
1075 | lli_len = min(bd.remainder, max_bytes_per_lli); | |
16a2e7d3 | 1076 | |
b7f69d9d VK |
1077 | /* |
1078 | * Check against maximum bus alignment: | |
1079 | * Calculate actual transfer size in relation to | |
1080 | * bus width an get a maximum remainder of the | |
1081 | * highest bus width - 1 | |
1082 | */ | |
1083 | width = max(mbus->buswidth, sbus->buswidth); | |
1084 | lli_len = (lli_len / width) * width; | |
1085 | tsize = lli_len / bd.srcbus.buswidth; | |
1086 | ||
1087 | dev_vdbg(&pl08x->adev->dev, | |
1088 | "%s fill lli with single lli chunk of " | |
1089 | "size 0x%08zx (remainder 0x%08zx)\n", | |
1090 | __func__, lli_len, bd.remainder); | |
1091 | ||
1092 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, | |
16a2e7d3 | 1093 | bd.dstbus.buswidth, tsize); |
ba6785ff | 1094 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
da1b6c05 | 1095 | lli_len, cctl, tsize); |
b7f69d9d VK |
1096 | total_bytes += lli_len; |
1097 | } | |
e8689e63 | 1098 | |
b7f69d9d VK |
1099 | /* |
1100 | * Send any odd bytes | |
1101 | */ | |
1102 | if (bd.remainder) { | |
1103 | dev_vdbg(&pl08x->adev->dev, | |
1104 | "%s align with boundary, send odd bytes (remain %zu)\n", | |
1105 | __func__, bd.remainder); | |
ba6785ff TF |
1106 | prep_byte_width_lli(pl08x, &bd, &cctl, |
1107 | bd.remainder, num_llis++, &total_bytes); | |
b7f69d9d | 1108 | } |
e8689e63 | 1109 | } |
16a2e7d3 | 1110 | |
b7f69d9d VK |
1111 | if (total_bytes != dsg->len) { |
1112 | dev_err(&pl08x->adev->dev, | |
1113 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", | |
1114 | __func__, total_bytes, dsg->len); | |
1115 | return 0; | |
1116 | } | |
e8689e63 | 1117 | |
b7f69d9d VK |
1118 | if (num_llis >= MAX_NUM_TSFR_LLIS) { |
1119 | dev_err(&pl08x->adev->dev, | |
1120 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
ba6785ff | 1121 | __func__, MAX_NUM_TSFR_LLIS); |
b7f69d9d VK |
1122 | return 0; |
1123 | } | |
e8689e63 | 1124 | } |
b58b6b5b RKAL |
1125 | |
1126 | llis_va = txd->llis_va; | |
ba6785ff | 1127 | last_lli = llis_va + (num_llis - 1) * pl08x->lli_words; |
94ae8522 | 1128 | /* The final LLI terminates the LLI. */ |
ba6785ff | 1129 | last_lli[PL080_LLI_LLI] = 0; |
94ae8522 | 1130 | /* The final LLI element shall also fire an interrupt. */ |
ba6785ff | 1131 | last_lli[PL080_LLI_CCTL] |= PL080_CONTROL_TC_IRQ_EN; |
e8689e63 | 1132 | |
48924e42 | 1133 | pl08x_dump_lli(pl08x, llis_va, num_llis); |
e8689e63 LW |
1134 | |
1135 | return num_llis; | |
1136 | } | |
1137 | ||
e8689e63 LW |
1138 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, |
1139 | struct pl08x_txd *txd) | |
1140 | { | |
b7f69d9d VK |
1141 | struct pl08x_sg *dsg, *_dsg; |
1142 | ||
c1205646 VK |
1143 | if (txd->llis_va) |
1144 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); | |
e8689e63 | 1145 | |
b7f69d9d VK |
1146 | list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) { |
1147 | list_del(&dsg->node); | |
1148 | kfree(dsg); | |
1149 | } | |
1150 | ||
e8689e63 LW |
1151 | kfree(txd); |
1152 | } | |
1153 | ||
18536134 RK |
1154 | static void pl08x_unmap_buffers(struct pl08x_txd *txd) |
1155 | { | |
1156 | struct device *dev = txd->vd.tx.chan->device->dev; | |
1157 | struct pl08x_sg *dsg; | |
1158 | ||
1159 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
1160 | if (txd->vd.tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
1161 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1162 | dma_unmap_single(dev, dsg->src_addr, dsg->len, | |
1163 | DMA_TO_DEVICE); | |
1164 | else { | |
1165 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1166 | dma_unmap_page(dev, dsg->src_addr, dsg->len, | |
1167 | DMA_TO_DEVICE); | |
1168 | } | |
1169 | } | |
1170 | if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
1171 | if (txd->vd.tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
1172 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1173 | dma_unmap_single(dev, dsg->dst_addr, dsg->len, | |
1174 | DMA_FROM_DEVICE); | |
1175 | else | |
1176 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1177 | dma_unmap_page(dev, dsg->dst_addr, dsg->len, | |
1178 | DMA_FROM_DEVICE); | |
1179 | } | |
1180 | } | |
1181 | ||
1182 | static void pl08x_desc_free(struct virt_dma_desc *vd) | |
1183 | { | |
1184 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1185 | struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan); | |
18536134 RK |
1186 | |
1187 | if (!plchan->slave) | |
1188 | pl08x_unmap_buffers(txd); | |
1189 | ||
1190 | if (!txd->done) | |
1191 | pl08x_release_mux(plchan); | |
1192 | ||
18536134 | 1193 | pl08x_free_txd(plchan->host, txd); |
18536134 RK |
1194 | } |
1195 | ||
e8689e63 LW |
1196 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, |
1197 | struct pl08x_dma_chan *plchan) | |
1198 | { | |
ea160561 | 1199 | LIST_HEAD(head); |
e8689e63 | 1200 | |
879f127b | 1201 | vchan_get_all_descriptors(&plchan->vc, &head); |
91998261 | 1202 | vchan_dma_desc_free_list(&plchan->vc, &head); |
e8689e63 LW |
1203 | } |
1204 | ||
1205 | /* | |
1206 | * The DMA ENGINE API | |
1207 | */ | |
1208 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
1209 | { | |
1210 | return 0; | |
1211 | } | |
1212 | ||
1213 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
1214 | { | |
a068682c RK |
1215 | /* Ensure all queued descriptors are freed */ |
1216 | vchan_free_chan_resources(to_virt_chan(chan)); | |
e8689e63 LW |
1217 | } |
1218 | ||
e8689e63 LW |
1219 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( |
1220 | struct dma_chan *chan, unsigned long flags) | |
1221 | { | |
1222 | struct dma_async_tx_descriptor *retval = NULL; | |
1223 | ||
1224 | return retval; | |
1225 | } | |
1226 | ||
1227 | /* | |
94ae8522 RKAL |
1228 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
1229 | * If slaves are relying on interrupts to signal completion this function | |
1230 | * must not be called with interrupts disabled. | |
e8689e63 | 1231 | */ |
3e27ee84 VK |
1232 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
1233 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
1234 | { |
1235 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
06e885b7 RK |
1236 | struct virt_dma_desc *vd; |
1237 | unsigned long flags; | |
e8689e63 | 1238 | enum dma_status ret; |
06e885b7 | 1239 | size_t bytes = 0; |
e8689e63 | 1240 | |
96a2af41 RKAL |
1241 | ret = dma_cookie_status(chan, cookie, txstate); |
1242 | if (ret == DMA_SUCCESS) | |
e8689e63 | 1243 | return ret; |
e8689e63 | 1244 | |
06e885b7 RK |
1245 | /* |
1246 | * There's no point calculating the residue if there's | |
1247 | * no txstate to store the value. | |
1248 | */ | |
1249 | if (!txstate) { | |
1250 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1251 | ret = DMA_PAUSED; | |
1252 | return ret; | |
1253 | } | |
1254 | ||
1255 | spin_lock_irqsave(&plchan->vc.lock, flags); | |
1256 | ret = dma_cookie_status(chan, cookie, txstate); | |
1257 | if (ret != DMA_SUCCESS) { | |
1258 | vd = vchan_find_desc(&plchan->vc, cookie); | |
1259 | if (vd) { | |
1260 | /* On the issued list, so hasn't been processed yet */ | |
1261 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1262 | struct pl08x_sg *dsg; | |
1263 | ||
1264 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1265 | bytes += dsg->len; | |
1266 | } else { | |
1267 | bytes = pl08x_getbytes_chan(plchan); | |
1268 | } | |
1269 | } | |
1270 | spin_unlock_irqrestore(&plchan->vc.lock, flags); | |
1271 | ||
e8689e63 LW |
1272 | /* |
1273 | * This cookie not complete yet | |
96a2af41 | 1274 | * Get number of bytes left in the active transactions and queue |
e8689e63 | 1275 | */ |
06e885b7 | 1276 | dma_set_residue(txstate, bytes); |
e8689e63 | 1277 | |
06e885b7 RK |
1278 | if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS) |
1279 | ret = DMA_PAUSED; | |
e8689e63 LW |
1280 | |
1281 | /* Whether waiting or running, we're in progress */ | |
06e885b7 | 1282 | return ret; |
e8689e63 LW |
1283 | } |
1284 | ||
1285 | /* PrimeCell DMA extension */ | |
1286 | struct burst_table { | |
760596c6 | 1287 | u32 burstwords; |
e8689e63 LW |
1288 | u32 reg; |
1289 | }; | |
1290 | ||
1291 | static const struct burst_table burst_sizes[] = { | |
1292 | { | |
1293 | .burstwords = 256, | |
760596c6 | 1294 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
1295 | }, |
1296 | { | |
1297 | .burstwords = 128, | |
760596c6 | 1298 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
1299 | }, |
1300 | { | |
1301 | .burstwords = 64, | |
760596c6 | 1302 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
1303 | }, |
1304 | { | |
1305 | .burstwords = 32, | |
760596c6 | 1306 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
1307 | }, |
1308 | { | |
1309 | .burstwords = 16, | |
760596c6 | 1310 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
1311 | }, |
1312 | { | |
1313 | .burstwords = 8, | |
760596c6 | 1314 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1315 | }, |
1316 | { | |
1317 | .burstwords = 4, | |
760596c6 | 1318 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1319 | }, |
1320 | { | |
760596c6 RKAL |
1321 | .burstwords = 0, |
1322 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1323 | }, |
1324 | }; | |
1325 | ||
121c8476 RKAL |
1326 | /* |
1327 | * Given the source and destination available bus masks, select which | |
1328 | * will be routed to each port. We try to have source and destination | |
1329 | * on separate ports, but always respect the allowable settings. | |
1330 | */ | |
1331 | static u32 pl08x_select_bus(u8 src, u8 dst) | |
1332 | { | |
1333 | u32 cctl = 0; | |
1334 | ||
1335 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1336 | cctl |= PL080_CONTROL_DST_AHB2; | |
1337 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1338 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1339 | ||
1340 | return cctl; | |
1341 | } | |
1342 | ||
f14c426c RKAL |
1343 | static u32 pl08x_cctl(u32 cctl) |
1344 | { | |
1345 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1346 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1347 | PL080_CONTROL_PROT_MASK); | |
1348 | ||
1349 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1350 | return cctl | PL080_CONTROL_PROT_SYS; | |
1351 | } | |
1352 | ||
aa88cdaa RKAL |
1353 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1354 | { | |
1355 | switch (width) { | |
1356 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1357 | return PL080_WIDTH_8BIT; | |
1358 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1359 | return PL080_WIDTH_16BIT; | |
1360 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1361 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1362 | default: |
1363 | return ~0; | |
aa88cdaa | 1364 | } |
aa88cdaa RKAL |
1365 | } |
1366 | ||
760596c6 RKAL |
1367 | static u32 pl08x_burst(u32 maxburst) |
1368 | { | |
1369 | int i; | |
1370 | ||
1371 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1372 | if (burst_sizes[i].burstwords <= maxburst) | |
1373 | break; | |
1374 | ||
1375 | return burst_sizes[i].reg; | |
1376 | } | |
1377 | ||
9862ba17 RK |
1378 | static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan, |
1379 | enum dma_slave_buswidth addr_width, u32 maxburst) | |
1380 | { | |
1381 | u32 width, burst, cctl = 0; | |
1382 | ||
1383 | width = pl08x_width(addr_width); | |
1384 | if (width == ~0) | |
1385 | return ~0; | |
1386 | ||
1387 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; | |
1388 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1389 | ||
1390 | /* | |
1391 | * If this channel will only request single transfers, set this | |
1392 | * down to ONE element. Also select one element if no maxburst | |
1393 | * is specified. | |
1394 | */ | |
1395 | if (plchan->cd->single) | |
1396 | maxburst = 1; | |
1397 | ||
1398 | burst = pl08x_burst(maxburst); | |
1399 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1400 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
1401 | ||
1402 | return pl08x_cctl(cctl); | |
1403 | } | |
1404 | ||
f0fd9446 RKAL |
1405 | static int dma_set_runtime_config(struct dma_chan *chan, |
1406 | struct dma_slave_config *config) | |
e8689e63 LW |
1407 | { |
1408 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
da1b6c05 | 1409 | struct pl08x_driver_data *pl08x = plchan->host; |
b7f75865 RKAL |
1410 | |
1411 | if (!plchan->slave) | |
1412 | return -EINVAL; | |
e8689e63 | 1413 | |
dc8d5f8d RK |
1414 | /* Reject definitely invalid configurations */ |
1415 | if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || | |
1416 | config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
f0fd9446 | 1417 | return -EINVAL; |
e8689e63 | 1418 | |
da1b6c05 TF |
1419 | if (config->device_fc && pl08x->vd->pl080s) { |
1420 | dev_err(&pl08x->adev->dev, | |
1421 | "%s: PL080S does not support peripheral flow control\n", | |
1422 | __func__); | |
1423 | return -EINVAL; | |
1424 | } | |
1425 | ||
ed91c13d RK |
1426 | plchan->cfg = *config; |
1427 | ||
f0fd9446 | 1428 | return 0; |
e8689e63 LW |
1429 | } |
1430 | ||
1431 | /* | |
1432 | * Slave transactions callback to the slave device to allow | |
1433 | * synchronization of slave DMA signals with the DMAC enable | |
1434 | */ | |
1435 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1436 | { | |
1437 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1438 | unsigned long flags; |
1439 | ||
083be28a | 1440 | spin_lock_irqsave(&plchan->vc.lock, flags); |
879f127b | 1441 | if (vchan_issue_pending(&plchan->vc)) { |
a5a488db RK |
1442 | if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING) |
1443 | pl08x_phy_alloc_and_start(plchan); | |
e8689e63 | 1444 | } |
083be28a | 1445 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1446 | } |
1447 | ||
879f127b | 1448 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan) |
ac3cd20d | 1449 | { |
b201c111 | 1450 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d RKAL |
1451 | |
1452 | if (txd) { | |
b7f69d9d | 1453 | INIT_LIST_HEAD(&txd->dsg_list); |
4983a04f RKAL |
1454 | |
1455 | /* Always enable error and terminal interrupts */ | |
1456 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1457 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1458 | } |
1459 | return txd; | |
1460 | } | |
1461 | ||
e8689e63 LW |
1462 | /* |
1463 | * Initialize a descriptor to be used by memcpy submit | |
1464 | */ | |
1465 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1466 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1467 | size_t len, unsigned long flags) | |
1468 | { | |
1469 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1470 | struct pl08x_driver_data *pl08x = plchan->host; | |
1471 | struct pl08x_txd *txd; | |
b7f69d9d | 1472 | struct pl08x_sg *dsg; |
e8689e63 LW |
1473 | int ret; |
1474 | ||
879f127b | 1475 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1476 | if (!txd) { |
1477 | dev_err(&pl08x->adev->dev, | |
1478 | "%s no memory for descriptor\n", __func__); | |
1479 | return NULL; | |
1480 | } | |
1481 | ||
b7f69d9d VK |
1482 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); |
1483 | if (!dsg) { | |
1484 | pl08x_free_txd(pl08x, txd); | |
1485 | dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n", | |
1486 | __func__); | |
1487 | return NULL; | |
1488 | } | |
1489 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1490 | ||
b7f69d9d VK |
1491 | dsg->src_addr = src; |
1492 | dsg->dst_addr = dest; | |
1493 | dsg->len = len; | |
e8689e63 LW |
1494 | |
1495 | /* Set platform data for m2m */ | |
4983a04f | 1496 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
dc8d5f8d | 1497 | txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy & |
c7da9a56 | 1498 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); |
4983a04f | 1499 | |
e8689e63 | 1500 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1501 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1502 | |
c7da9a56 | 1503 | if (pl08x->vd->dualmaster) |
121c8476 RKAL |
1504 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
1505 | pl08x->mem_buses); | |
e8689e63 | 1506 | |
aa4afb75 RK |
1507 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1508 | if (!ret) { | |
1509 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 1510 | return NULL; |
aa4afb75 | 1511 | } |
e8689e63 | 1512 | |
879f127b | 1513 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1514 | } |
1515 | ||
3e2a037c | 1516 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 | 1517 | struct dma_chan *chan, struct scatterlist *sgl, |
db8196df | 1518 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1519 | unsigned long flags, void *context) |
e8689e63 LW |
1520 | { |
1521 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1522 | struct pl08x_driver_data *pl08x = plchan->host; | |
1523 | struct pl08x_txd *txd; | |
b7f69d9d VK |
1524 | struct pl08x_sg *dsg; |
1525 | struct scatterlist *sg; | |
dc8d5f8d | 1526 | enum dma_slave_buswidth addr_width; |
b7f69d9d | 1527 | dma_addr_t slave_addr; |
0a235657 | 1528 | int ret, tmp; |
409ec8db | 1529 | u8 src_buses, dst_buses; |
dc8d5f8d | 1530 | u32 maxburst, cctl; |
e8689e63 | 1531 | |
e8689e63 | 1532 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", |
fdaf9c4b | 1533 | __func__, sg_dma_len(sgl), plchan->name); |
e8689e63 | 1534 | |
879f127b | 1535 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1536 | if (!txd) { |
1537 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1538 | return NULL; | |
1539 | } | |
1540 | ||
e8689e63 LW |
1541 | /* |
1542 | * Set up addresses, the PrimeCell configured address | |
1543 | * will take precedence since this may configure the | |
1544 | * channel target address dynamically at runtime. | |
1545 | */ | |
db8196df | 1546 | if (direction == DMA_MEM_TO_DEV) { |
dc8d5f8d | 1547 | cctl = PL080_CONTROL_SRC_INCR; |
ed91c13d | 1548 | slave_addr = plchan->cfg.dst_addr; |
dc8d5f8d RK |
1549 | addr_width = plchan->cfg.dst_addr_width; |
1550 | maxburst = plchan->cfg.dst_maxburst; | |
409ec8db RK |
1551 | src_buses = pl08x->mem_buses; |
1552 | dst_buses = plchan->cd->periph_buses; | |
db8196df | 1553 | } else if (direction == DMA_DEV_TO_MEM) { |
dc8d5f8d | 1554 | cctl = PL080_CONTROL_DST_INCR; |
ed91c13d | 1555 | slave_addr = plchan->cfg.src_addr; |
dc8d5f8d RK |
1556 | addr_width = plchan->cfg.src_addr_width; |
1557 | maxburst = plchan->cfg.src_maxburst; | |
409ec8db RK |
1558 | src_buses = plchan->cd->periph_buses; |
1559 | dst_buses = pl08x->mem_buses; | |
e8689e63 | 1560 | } else { |
b7f69d9d | 1561 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1562 | dev_err(&pl08x->adev->dev, |
1563 | "%s direction unsupported\n", __func__); | |
1564 | return NULL; | |
1565 | } | |
e8689e63 | 1566 | |
dc8d5f8d | 1567 | cctl |= pl08x_get_cctl(plchan, addr_width, maxburst); |
800d683e RK |
1568 | if (cctl == ~0) { |
1569 | pl08x_free_txd(pl08x, txd); | |
1570 | dev_err(&pl08x->adev->dev, | |
1571 | "DMA slave configuration botched?\n"); | |
1572 | return NULL; | |
1573 | } | |
1574 | ||
409ec8db RK |
1575 | txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses); |
1576 | ||
95442b22 | 1577 | if (plchan->cfg.device_fc) |
db8196df | 1578 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : |
0a235657 VK |
1579 | PL080_FLOW_PER2MEM_PER; |
1580 | else | |
db8196df | 1581 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER : |
0a235657 VK |
1582 | PL080_FLOW_PER2MEM; |
1583 | ||
1584 | txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1585 | ||
c48d4963 RK |
1586 | ret = pl08x_request_mux(plchan); |
1587 | if (ret < 0) { | |
1588 | pl08x_free_txd(pl08x, txd); | |
1589 | dev_dbg(&pl08x->adev->dev, | |
1590 | "unable to mux for transfer on %s due to platform restrictions\n", | |
1591 | plchan->name); | |
1592 | return NULL; | |
1593 | } | |
1594 | ||
1595 | dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n", | |
1596 | plchan->signal, plchan->name); | |
1597 | ||
1598 | /* Assign the flow control signal to this channel */ | |
1599 | if (direction == DMA_MEM_TO_DEV) | |
1600 | txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
1601 | else | |
1602 | txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
1603 | ||
b7f69d9d VK |
1604 | for_each_sg(sgl, sg, sg_len, tmp) { |
1605 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); | |
1606 | if (!dsg) { | |
c48d4963 | 1607 | pl08x_release_mux(plchan); |
b7f69d9d VK |
1608 | pl08x_free_txd(pl08x, txd); |
1609 | dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n", | |
1610 | __func__); | |
1611 | return NULL; | |
1612 | } | |
1613 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1614 | ||
1615 | dsg->len = sg_dma_len(sg); | |
db8196df | 1616 | if (direction == DMA_MEM_TO_DEV) { |
cbb796cc | 1617 | dsg->src_addr = sg_dma_address(sg); |
b7f69d9d VK |
1618 | dsg->dst_addr = slave_addr; |
1619 | } else { | |
1620 | dsg->src_addr = slave_addr; | |
cbb796cc | 1621 | dsg->dst_addr = sg_dma_address(sg); |
b7f69d9d VK |
1622 | } |
1623 | } | |
1624 | ||
aa4afb75 RK |
1625 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1626 | if (!ret) { | |
1627 | pl08x_release_mux(plchan); | |
1628 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 1629 | return NULL; |
aa4afb75 | 1630 | } |
e8689e63 | 1631 | |
879f127b | 1632 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1633 | } |
1634 | ||
1635 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1636 | unsigned long arg) | |
1637 | { | |
1638 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1639 | struct pl08x_driver_data *pl08x = plchan->host; | |
1640 | unsigned long flags; | |
1641 | int ret = 0; | |
1642 | ||
1643 | /* Controls applicable to inactive channels */ | |
1644 | if (cmd == DMA_SLAVE_CONFIG) { | |
f0fd9446 RKAL |
1645 | return dma_set_runtime_config(chan, |
1646 | (struct dma_slave_config *)arg); | |
e8689e63 LW |
1647 | } |
1648 | ||
1649 | /* | |
1650 | * Anything succeeds on channels with no physical allocation and | |
1651 | * no queued transfers. | |
1652 | */ | |
083be28a | 1653 | spin_lock_irqsave(&plchan->vc.lock, flags); |
e8689e63 | 1654 | if (!plchan->phychan && !plchan->at) { |
083be28a | 1655 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1656 | return 0; |
1657 | } | |
1658 | ||
1659 | switch (cmd) { | |
1660 | case DMA_TERMINATE_ALL: | |
1661 | plchan->state = PL08X_CHAN_IDLE; | |
1662 | ||
1663 | if (plchan->phychan) { | |
e8689e63 LW |
1664 | /* |
1665 | * Mark physical channel as free and free any slave | |
1666 | * signal | |
1667 | */ | |
a5a488db | 1668 | pl08x_phy_free(plchan); |
e8689e63 | 1669 | } |
e8689e63 LW |
1670 | /* Dequeue jobs and free LLIs */ |
1671 | if (plchan->at) { | |
18536134 | 1672 | pl08x_desc_free(&plchan->at->vd); |
e8689e63 LW |
1673 | plchan->at = NULL; |
1674 | } | |
1675 | /* Dequeue jobs not yet fired as well */ | |
1676 | pl08x_free_txd_list(pl08x, plchan); | |
1677 | break; | |
1678 | case DMA_PAUSE: | |
1679 | pl08x_pause_phy_chan(plchan->phychan); | |
1680 | plchan->state = PL08X_CHAN_PAUSED; | |
1681 | break; | |
1682 | case DMA_RESUME: | |
1683 | pl08x_resume_phy_chan(plchan->phychan); | |
1684 | plchan->state = PL08X_CHAN_RUNNING; | |
1685 | break; | |
1686 | default: | |
1687 | /* Unknown command */ | |
1688 | ret = -ENXIO; | |
1689 | break; | |
1690 | } | |
1691 | ||
083be28a | 1692 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1693 | |
1694 | return ret; | |
1695 | } | |
1696 | ||
1697 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1698 | { | |
7703eac9 | 1699 | struct pl08x_dma_chan *plchan; |
e8689e63 LW |
1700 | char *name = chan_id; |
1701 | ||
7703eac9 RKAL |
1702 | /* Reject channels for devices not bound to this driver */ |
1703 | if (chan->device->dev->driver != &pl08x_amba_driver.drv) | |
1704 | return false; | |
1705 | ||
1706 | plchan = to_pl08x_chan(chan); | |
1707 | ||
e8689e63 LW |
1708 | /* Check that the channel is not taken! */ |
1709 | if (!strcmp(plchan->name, name)) | |
1710 | return true; | |
1711 | ||
1712 | return false; | |
1713 | } | |
1714 | ||
1715 | /* | |
1716 | * Just check that the device is there and active | |
94ae8522 RKAL |
1717 | * TODO: turn this bit on/off depending on the number of physical channels |
1718 | * actually used, if it is zero... well shut it off. That will save some | |
1719 | * power. Cut the clock at the same time. | |
e8689e63 LW |
1720 | */ |
1721 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1722 | { | |
affa115e LW |
1723 | /* The Nomadik variant does not have the config register */ |
1724 | if (pl08x->vd->nomadik) | |
1725 | return; | |
48a59ef3 | 1726 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
e8689e63 LW |
1727 | } |
1728 | ||
e8689e63 LW |
1729 | static irqreturn_t pl08x_irq(int irq, void *dev) |
1730 | { | |
1731 | struct pl08x_driver_data *pl08x = dev; | |
28da2836 VK |
1732 | u32 mask = 0, err, tc, i; |
1733 | ||
1734 | /* check & clear - ERR & TC interrupts */ | |
1735 | err = readl(pl08x->base + PL080_ERR_STATUS); | |
1736 | if (err) { | |
1737 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", | |
1738 | __func__, err); | |
1739 | writel(err, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 | 1740 | } |
d29bf019 | 1741 | tc = readl(pl08x->base + PL080_TC_STATUS); |
28da2836 VK |
1742 | if (tc) |
1743 | writel(tc, pl08x->base + PL080_TC_CLEAR); | |
1744 | ||
1745 | if (!err && !tc) | |
1746 | return IRQ_NONE; | |
1747 | ||
e8689e63 | 1748 | for (i = 0; i < pl08x->vd->channels; i++) { |
28da2836 | 1749 | if (((1 << i) & err) || ((1 << i) & tc)) { |
e8689e63 LW |
1750 | /* Locate physical channel */ |
1751 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1752 | struct pl08x_dma_chan *plchan = phychan->serving; | |
a936e793 | 1753 | struct pl08x_txd *tx; |
e8689e63 | 1754 | |
28da2836 VK |
1755 | if (!plchan) { |
1756 | dev_err(&pl08x->adev->dev, | |
1757 | "%s Error TC interrupt on unused channel: 0x%08x\n", | |
1758 | __func__, i); | |
1759 | continue; | |
1760 | } | |
1761 | ||
083be28a | 1762 | spin_lock(&plchan->vc.lock); |
a936e793 RK |
1763 | tx = plchan->at; |
1764 | if (tx) { | |
1765 | plchan->at = NULL; | |
c48d4963 RK |
1766 | /* |
1767 | * This descriptor is done, release its mux | |
1768 | * reservation. | |
1769 | */ | |
1770 | pl08x_release_mux(plchan); | |
18536134 RK |
1771 | tx->done = true; |
1772 | vchan_cookie_complete(&tx->vd); | |
c33b644c | 1773 | |
a5a488db RK |
1774 | /* |
1775 | * And start the next descriptor (if any), | |
1776 | * otherwise free this channel. | |
1777 | */ | |
879f127b | 1778 | if (vchan_next_desc(&plchan->vc)) |
c33b644c | 1779 | pl08x_start_next_txd(plchan); |
a5a488db RK |
1780 | else |
1781 | pl08x_phy_free(plchan); | |
a936e793 | 1782 | } |
083be28a | 1783 | spin_unlock(&plchan->vc.lock); |
a936e793 | 1784 | |
e8689e63 LW |
1785 | mask |= (1 << i); |
1786 | } | |
1787 | } | |
e8689e63 LW |
1788 | |
1789 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1790 | } | |
1791 | ||
121c8476 RKAL |
1792 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
1793 | { | |
121c8476 RKAL |
1794 | chan->slave = true; |
1795 | chan->name = chan->cd->bus_id; | |
ed91c13d RK |
1796 | chan->cfg.src_addr = chan->cd->addr; |
1797 | chan->cfg.dst_addr = chan->cd->addr; | |
121c8476 RKAL |
1798 | } |
1799 | ||
e8689e63 LW |
1800 | /* |
1801 | * Initialise the DMAC memcpy/slave channels. | |
1802 | * Make a local wrapper to hold required data | |
1803 | */ | |
1804 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 1805 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
1806 | { |
1807 | struct pl08x_dma_chan *chan; | |
1808 | int i; | |
1809 | ||
1810 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 1811 | |
e8689e63 LW |
1812 | /* |
1813 | * Register as many many memcpy as we have physical channels, | |
1814 | * we won't always be able to use all but the code will have | |
1815 | * to cope with that situation. | |
1816 | */ | |
1817 | for (i = 0; i < channels; i++) { | |
b201c111 | 1818 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
e8689e63 LW |
1819 | if (!chan) { |
1820 | dev_err(&pl08x->adev->dev, | |
1821 | "%s no memory for channel\n", __func__); | |
1822 | return -ENOMEM; | |
1823 | } | |
1824 | ||
1825 | chan->host = pl08x; | |
1826 | chan->state = PL08X_CHAN_IDLE; | |
ad0de2ac | 1827 | chan->signal = -1; |
e8689e63 LW |
1828 | |
1829 | if (slave) { | |
e8689e63 | 1830 | chan->cd = &pl08x->pd->slave_channels[i]; |
121c8476 | 1831 | pl08x_dma_slave_init(chan); |
e8689e63 LW |
1832 | } else { |
1833 | chan->cd = &pl08x->pd->memcpy_channel; | |
1834 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1835 | if (!chan->name) { | |
1836 | kfree(chan); | |
1837 | return -ENOMEM; | |
1838 | } | |
1839 | } | |
175a5e61 | 1840 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
1841 | "initialize virtual channel \"%s\"\n", |
1842 | chan->name); | |
1843 | ||
18536134 | 1844 | chan->vc.desc_free = pl08x_desc_free; |
083be28a | 1845 | vchan_init(&chan->vc, dmadev); |
e8689e63 LW |
1846 | } |
1847 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1848 | i, slave ? "slave" : "memcpy"); | |
1849 | return i; | |
1850 | } | |
1851 | ||
1852 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1853 | { | |
1854 | struct pl08x_dma_chan *chan = NULL; | |
1855 | struct pl08x_dma_chan *next; | |
1856 | ||
1857 | list_for_each_entry_safe(chan, | |
01d8dc64 RK |
1858 | next, &dmadev->channels, vc.chan.device_node) { |
1859 | list_del(&chan->vc.chan.device_node); | |
e8689e63 LW |
1860 | kfree(chan); |
1861 | } | |
1862 | } | |
1863 | ||
1864 | #ifdef CONFIG_DEBUG_FS | |
1865 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1866 | { | |
1867 | switch (state) { | |
1868 | case PL08X_CHAN_IDLE: | |
1869 | return "idle"; | |
1870 | case PL08X_CHAN_RUNNING: | |
1871 | return "running"; | |
1872 | case PL08X_CHAN_PAUSED: | |
1873 | return "paused"; | |
1874 | case PL08X_CHAN_WAITING: | |
1875 | return "waiting"; | |
1876 | default: | |
1877 | break; | |
1878 | } | |
1879 | return "UNKNOWN STATE"; | |
1880 | } | |
1881 | ||
1882 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1883 | { | |
1884 | struct pl08x_driver_data *pl08x = s->private; | |
1885 | struct pl08x_dma_chan *chan; | |
1886 | struct pl08x_phy_chan *ch; | |
1887 | unsigned long flags; | |
1888 | int i; | |
1889 | ||
1890 | seq_printf(s, "PL08x physical channels:\n"); | |
1891 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1892 | seq_printf(s, "--------\t-----\n"); | |
1893 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1894 | struct pl08x_dma_chan *virt_chan; | |
1895 | ||
1896 | ch = &pl08x->phy_chans[i]; | |
1897 | ||
1898 | spin_lock_irqsave(&ch->lock, flags); | |
1899 | virt_chan = ch->serving; | |
1900 | ||
affa115e LW |
1901 | seq_printf(s, "%d\t\t%s%s\n", |
1902 | ch->id, | |
1903 | virt_chan ? virt_chan->name : "(none)", | |
1904 | ch->locked ? " LOCKED" : ""); | |
e8689e63 LW |
1905 | |
1906 | spin_unlock_irqrestore(&ch->lock, flags); | |
1907 | } | |
1908 | ||
1909 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1910 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1911 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1912 | list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) { |
3e2a037c | 1913 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1914 | pl08x_state_str(chan->state)); |
1915 | } | |
1916 | ||
1917 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1918 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1919 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 1920 | list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) { |
3e2a037c | 1921 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1922 | pl08x_state_str(chan->state)); |
1923 | } | |
1924 | ||
1925 | return 0; | |
1926 | } | |
1927 | ||
1928 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1929 | { | |
1930 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1931 | } | |
1932 | ||
1933 | static const struct file_operations pl08x_debugfs_operations = { | |
1934 | .open = pl08x_debugfs_open, | |
1935 | .read = seq_read, | |
1936 | .llseek = seq_lseek, | |
1937 | .release = single_release, | |
1938 | }; | |
1939 | ||
1940 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1941 | { | |
1942 | /* Expose a simple debugfs interface to view all clocks */ | |
3e27ee84 VK |
1943 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
1944 | S_IFREG | S_IRUGO, NULL, pl08x, | |
1945 | &pl08x_debugfs_operations); | |
e8689e63 LW |
1946 | } |
1947 | ||
1948 | #else | |
1949 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1950 | { | |
1951 | } | |
1952 | #endif | |
1953 | ||
aa25afad | 1954 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
1955 | { |
1956 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1957 | const struct vendor_data *vd = id->data; |
ba6785ff | 1958 | u32 tsfr_size; |
e8689e63 LW |
1959 | int ret = 0; |
1960 | int i; | |
1961 | ||
1962 | ret = amba_request_regions(adev, NULL); | |
1963 | if (ret) | |
1964 | return ret; | |
1965 | ||
1966 | /* Create the driver state holder */ | |
b201c111 | 1967 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
1968 | if (!pl08x) { |
1969 | ret = -ENOMEM; | |
1970 | goto out_no_pl08x; | |
1971 | } | |
1972 | ||
1973 | /* Initialize memcpy engine */ | |
1974 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1975 | pl08x->memcpy.dev = &adev->dev; | |
1976 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1977 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1978 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1979 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1980 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1981 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1982 | pl08x->memcpy.device_control = pl08x_control; | |
1983 | ||
1984 | /* Initialize slave engine */ | |
1985 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1986 | pl08x->slave.dev = &adev->dev; | |
1987 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1988 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1989 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1990 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1991 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1992 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1993 | pl08x->slave.device_control = pl08x_control; | |
1994 | ||
1995 | /* Get the platform data */ | |
1996 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1997 | if (!pl08x->pd) { | |
1998 | dev_err(&adev->dev, "no platform data supplied\n"); | |
983d7beb | 1999 | ret = -EINVAL; |
e8689e63 LW |
2000 | goto out_no_platdata; |
2001 | } | |
2002 | ||
2003 | /* Assign useful pointers to the driver state */ | |
2004 | pl08x->adev = adev; | |
2005 | pl08x->vd = vd; | |
2006 | ||
30749cb4 RKAL |
2007 | /* By default, AHB1 only. If dualmaster, from platform */ |
2008 | pl08x->lli_buses = PL08X_AHB1; | |
2009 | pl08x->mem_buses = PL08X_AHB1; | |
2010 | if (pl08x->vd->dualmaster) { | |
2011 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
2012 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
2013 | } | |
2014 | ||
da1b6c05 TF |
2015 | if (vd->pl080s) |
2016 | pl08x->lli_words = PL080S_LLI_WORDS; | |
2017 | else | |
2018 | pl08x->lli_words = PL080_LLI_WORDS; | |
ba6785ff TF |
2019 | tsfr_size = MAX_NUM_TSFR_LLIS * pl08x->lli_words * sizeof(u32); |
2020 | ||
e8689e63 LW |
2021 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
2022 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
ba6785ff | 2023 | tsfr_size, PL08X_ALIGN, 0); |
e8689e63 LW |
2024 | if (!pl08x->pool) { |
2025 | ret = -ENOMEM; | |
2026 | goto out_no_lli_pool; | |
2027 | } | |
2028 | ||
e8689e63 LW |
2029 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); |
2030 | if (!pl08x->base) { | |
2031 | ret = -ENOMEM; | |
2032 | goto out_no_ioremap; | |
2033 | } | |
2034 | ||
2035 | /* Turn on the PL08x */ | |
2036 | pl08x_ensure_on(pl08x); | |
2037 | ||
94ae8522 | 2038 | /* Attach the interrupt handler */ |
e8689e63 LW |
2039 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
2040 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
2041 | ||
2042 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 2043 | DRIVER_NAME, pl08x); |
e8689e63 LW |
2044 | if (ret) { |
2045 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
2046 | __func__, adev->irq[0]); | |
2047 | goto out_no_irq; | |
2048 | } | |
2049 | ||
2050 | /* Initialize physical channels */ | |
affa115e | 2051 | pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
2052 | GFP_KERNEL); |
2053 | if (!pl08x->phy_chans) { | |
2054 | dev_err(&adev->dev, "%s failed to allocate " | |
2055 | "physical channel holders\n", | |
2056 | __func__); | |
983d7beb | 2057 | ret = -ENOMEM; |
e8689e63 LW |
2058 | goto out_no_phychans; |
2059 | } | |
2060 | ||
2061 | for (i = 0; i < vd->channels; i++) { | |
2062 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
2063 | ||
2064 | ch->id = i; | |
2065 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
d86ccea7 | 2066 | ch->reg_config = ch->base + vd->config_offset; |
e8689e63 | 2067 | spin_lock_init(&ch->lock); |
affa115e LW |
2068 | |
2069 | /* | |
2070 | * Nomadik variants can have channels that are locked | |
2071 | * down for the secure world only. Lock up these channels | |
2072 | * by perpetually serving a dummy virtual channel. | |
2073 | */ | |
2074 | if (vd->nomadik) { | |
2075 | u32 val; | |
2076 | ||
d86ccea7 | 2077 | val = readl(ch->reg_config); |
affa115e LW |
2078 | if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { |
2079 | dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i); | |
2080 | ch->locked = true; | |
2081 | } | |
2082 | } | |
2083 | ||
175a5e61 VK |
2084 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
2085 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
2086 | } |
2087 | ||
2088 | /* Register as many memcpy channels as there are physical channels */ | |
2089 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
2090 | pl08x->vd->channels, false); | |
2091 | if (ret <= 0) { | |
2092 | dev_warn(&pl08x->adev->dev, | |
2093 | "%s failed to enumerate memcpy channels - %d\n", | |
2094 | __func__, ret); | |
2095 | goto out_no_memcpy; | |
2096 | } | |
2097 | pl08x->memcpy.chancnt = ret; | |
2098 | ||
2099 | /* Register slave channels */ | |
2100 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
3e27ee84 | 2101 | pl08x->pd->num_slave_channels, true); |
e8689e63 LW |
2102 | if (ret <= 0) { |
2103 | dev_warn(&pl08x->adev->dev, | |
2104 | "%s failed to enumerate slave channels - %d\n", | |
2105 | __func__, ret); | |
2106 | goto out_no_slave; | |
2107 | } | |
2108 | pl08x->slave.chancnt = ret; | |
2109 | ||
2110 | ret = dma_async_device_register(&pl08x->memcpy); | |
2111 | if (ret) { | |
2112 | dev_warn(&pl08x->adev->dev, | |
2113 | "%s failed to register memcpy as an async device - %d\n", | |
2114 | __func__, ret); | |
2115 | goto out_no_memcpy_reg; | |
2116 | } | |
2117 | ||
2118 | ret = dma_async_device_register(&pl08x->slave); | |
2119 | if (ret) { | |
2120 | dev_warn(&pl08x->adev->dev, | |
2121 | "%s failed to register slave as an async device - %d\n", | |
2122 | __func__, ret); | |
2123 | goto out_no_slave_reg; | |
2124 | } | |
2125 | ||
2126 | amba_set_drvdata(adev, pl08x); | |
2127 | init_pl08x_debugfs(pl08x); | |
da1b6c05 TF |
2128 | dev_info(&pl08x->adev->dev, "DMA: PL%03x%s rev%u at 0x%08llx irq %d\n", |
2129 | amba_part(adev), pl08x->vd->pl080s ? "s" : "", amba_rev(adev), | |
b05cd8f4 | 2130 | (unsigned long long)adev->res.start, adev->irq[0]); |
b7b6018b | 2131 | |
e8689e63 LW |
2132 | return 0; |
2133 | ||
2134 | out_no_slave_reg: | |
2135 | dma_async_device_unregister(&pl08x->memcpy); | |
2136 | out_no_memcpy_reg: | |
2137 | pl08x_free_virtual_channels(&pl08x->slave); | |
2138 | out_no_slave: | |
2139 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2140 | out_no_memcpy: | |
2141 | kfree(pl08x->phy_chans); | |
2142 | out_no_phychans: | |
2143 | free_irq(adev->irq[0], pl08x); | |
2144 | out_no_irq: | |
2145 | iounmap(pl08x->base); | |
2146 | out_no_ioremap: | |
2147 | dma_pool_destroy(pl08x->pool); | |
2148 | out_no_lli_pool: | |
2149 | out_no_platdata: | |
2150 | kfree(pl08x); | |
2151 | out_no_pl08x: | |
2152 | amba_release_regions(adev); | |
2153 | return ret; | |
2154 | } | |
2155 | ||
2156 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2157 | static struct vendor_data vendor_pl080 = { | |
d86ccea7 | 2158 | .config_offset = PL080_CH_CONFIG, |
e8689e63 LW |
2159 | .channels = 8, |
2160 | .dualmaster = true, | |
5110e51d | 2161 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
e8689e63 LW |
2162 | }; |
2163 | ||
affa115e | 2164 | static struct vendor_data vendor_nomadik = { |
d86ccea7 | 2165 | .config_offset = PL080_CH_CONFIG, |
affa115e LW |
2166 | .channels = 8, |
2167 | .dualmaster = true, | |
2168 | .nomadik = true, | |
5110e51d | 2169 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
affa115e LW |
2170 | }; |
2171 | ||
da1b6c05 TF |
2172 | static struct vendor_data vendor_pl080s = { |
2173 | .config_offset = PL080S_CH_CONFIG, | |
2174 | .channels = 8, | |
2175 | .pl080s = true, | |
5110e51d | 2176 | .max_transfer_size = PL080S_CONTROL_TRANSFER_SIZE_MASK, |
da1b6c05 TF |
2177 | }; |
2178 | ||
e8689e63 | 2179 | static struct vendor_data vendor_pl081 = { |
d86ccea7 | 2180 | .config_offset = PL080_CH_CONFIG, |
e8689e63 LW |
2181 | .channels = 2, |
2182 | .dualmaster = false, | |
5110e51d | 2183 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
e8689e63 LW |
2184 | }; |
2185 | ||
2186 | static struct amba_id pl08x_ids[] = { | |
da1b6c05 TF |
2187 | /* Samsung PL080S variant */ |
2188 | { | |
2189 | .id = 0x0a141080, | |
2190 | .mask = 0xffffffff, | |
2191 | .data = &vendor_pl080s, | |
2192 | }, | |
e8689e63 LW |
2193 | /* PL080 */ |
2194 | { | |
2195 | .id = 0x00041080, | |
2196 | .mask = 0x000fffff, | |
2197 | .data = &vendor_pl080, | |
2198 | }, | |
2199 | /* PL081 */ | |
2200 | { | |
2201 | .id = 0x00041081, | |
2202 | .mask = 0x000fffff, | |
2203 | .data = &vendor_pl081, | |
2204 | }, | |
2205 | /* Nomadik 8815 PL080 variant */ | |
2206 | { | |
affa115e | 2207 | .id = 0x00280080, |
e8689e63 | 2208 | .mask = 0x00ffffff, |
affa115e | 2209 | .data = &vendor_nomadik, |
e8689e63 LW |
2210 | }, |
2211 | { 0, 0 }, | |
2212 | }; | |
2213 | ||
037566df DM |
2214 | MODULE_DEVICE_TABLE(amba, pl08x_ids); |
2215 | ||
e8689e63 LW |
2216 | static struct amba_driver pl08x_amba_driver = { |
2217 | .drv.name = DRIVER_NAME, | |
2218 | .id_table = pl08x_ids, | |
2219 | .probe = pl08x_probe, | |
2220 | }; | |
2221 | ||
2222 | static int __init pl08x_init(void) | |
2223 | { | |
2224 | int retval; | |
2225 | retval = amba_driver_register(&pl08x_amba_driver); | |
2226 | if (retval) | |
2227 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2228 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2229 | retval); |
2230 | return retval; | |
2231 | } | |
2232 | subsys_initcall(pl08x_init); |