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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
94ae8522 RKAL |
22 | * The full GNU General Public License is in this distribution in the file |
23 | * called COPYING. | |
e8689e63 LW |
24 | * |
25 | * Documentation: ARM DDI 0196G == PL080 | |
94ae8522 | 26 | * Documentation: ARM DDI 0218E == PL081 |
e8689e63 | 27 | * |
94ae8522 RKAL |
28 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
29 | * channel. | |
e8689e63 LW |
30 | * |
31 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
32 | * has only two channels. So on these DMA controllers the number of channels | |
33 | * and the number of incoming DMA signals are two totally different things. | |
34 | * It is usually not possible to theoretically handle all physical signals, | |
35 | * so a multiplexing scheme with possible denial of use is necessary. | |
36 | * | |
37 | * The PL080 has a dual bus master, PL081 has a single master. | |
38 | * | |
39 | * Memory to peripheral transfer may be visualized as | |
40 | * Get data from memory to DMAC | |
41 | * Until no data left | |
42 | * On burst request from peripheral | |
43 | * Destination burst from DMAC to peripheral | |
44 | * Clear burst request | |
45 | * Raise terminal count interrupt | |
46 | * | |
47 | * For peripherals with a FIFO: | |
48 | * Source burst size == half the depth of the peripheral FIFO | |
49 | * Destination burst size == the depth of the peripheral FIFO | |
50 | * | |
51 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
52 | * signals, the DMA controller will simply facilitate its AHB master.) | |
53 | * | |
54 | * ASSUMES default (little) endianness for DMA transfers | |
55 | * | |
9dc2c200 RKAL |
56 | * The PL08x has two flow control settings: |
57 | * - DMAC flow control: the transfer size defines the number of transfers | |
58 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
59 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
60 | * to both the BREQ and SREQ signals (contrary to documented), | |
61 | * transferring data if either is active. The LBREQ and LSREQ signals | |
62 | * are ignored. | |
63 | * | |
64 | * - Peripheral flow control: the transfer size is ignored (and should be | |
65 | * zero). The data is transferred from the current LLI entry, until | |
66 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
67 | * will then move to the next LLI entry. | |
68 | * | |
e8689e63 LW |
69 | * Global TODO: |
70 | * - Break out common code from arch/arm/mach-s3c64xx and share | |
71 | */ | |
730404ac | 72 | #include <linux/amba/bus.h> |
e8689e63 LW |
73 | #include <linux/amba/pl08x.h> |
74 | #include <linux/debugfs.h> | |
0c38d701 VK |
75 | #include <linux/delay.h> |
76 | #include <linux/device.h> | |
77 | #include <linux/dmaengine.h> | |
78 | #include <linux/dmapool.h> | |
8516f52f | 79 | #include <linux/dma-mapping.h> |
0c38d701 VK |
80 | #include <linux/init.h> |
81 | #include <linux/interrupt.h> | |
82 | #include <linux/module.h> | |
b7b6018b | 83 | #include <linux/pm_runtime.h> |
e8689e63 | 84 | #include <linux/seq_file.h> |
0c38d701 | 85 | #include <linux/slab.h> |
e8689e63 | 86 | #include <asm/hardware/pl080.h> |
e8689e63 | 87 | |
d2ebfb33 RKAL |
88 | #include "dmaengine.h" |
89 | ||
e8689e63 LW |
90 | #define DRIVER_NAME "pl08xdmac" |
91 | ||
7703eac9 RKAL |
92 | static struct amba_driver pl08x_amba_driver; |
93 | ||
e8689e63 | 94 | /** |
94ae8522 | 95 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
e8689e63 | 96 | * @channels: the number of channels available in this variant |
94ae8522 | 97 | * @dualmaster: whether this version supports dual AHB masters or not. |
e8689e63 LW |
98 | */ |
99 | struct vendor_data { | |
e8689e63 LW |
100 | u8 channels; |
101 | bool dualmaster; | |
102 | }; | |
103 | ||
104 | /* | |
105 | * PL08X private data structures | |
e8b5e11d | 106 | * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit, |
e25761d7 RKAL |
107 | * start & end do not - their bus bit info is in cctl. Also note that these |
108 | * are fixed 32-bit quantities. | |
e8689e63 | 109 | */ |
7cb72ad9 | 110 | struct pl08x_lli { |
e25761d7 RKAL |
111 | u32 src; |
112 | u32 dst; | |
bfddfb45 | 113 | u32 lli; |
e8689e63 LW |
114 | u32 cctl; |
115 | }; | |
116 | ||
117 | /** | |
118 | * struct pl08x_driver_data - the local state holder for the PL08x | |
119 | * @slave: slave engine for this instance | |
120 | * @memcpy: memcpy engine for this instance | |
121 | * @base: virtual memory base (remapped) for the PL08x | |
122 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
123 | * @vd: vendor data for this PL08x variant | |
124 | * @pd: platform data passed in from the platform/machine | |
125 | * @phy_chans: array of data for the physical channels | |
126 | * @pool: a pool for the LLI descriptors | |
127 | * @pool_ctr: counter of LLIs in the pool | |
3e27ee84 VK |
128 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
129 | * fetches | |
30749cb4 | 130 | * @mem_buses: set to indicate memory transfers on AHB2. |
e8689e63 LW |
131 | * @lock: a spinlock for this struct |
132 | */ | |
133 | struct pl08x_driver_data { | |
134 | struct dma_device slave; | |
135 | struct dma_device memcpy; | |
136 | void __iomem *base; | |
137 | struct amba_device *adev; | |
f96ca9ec | 138 | const struct vendor_data *vd; |
e8689e63 LW |
139 | struct pl08x_platform_data *pd; |
140 | struct pl08x_phy_chan *phy_chans; | |
141 | struct dma_pool *pool; | |
142 | int pool_ctr; | |
30749cb4 RKAL |
143 | u8 lli_buses; |
144 | u8 mem_buses; | |
e8689e63 LW |
145 | spinlock_t lock; |
146 | }; | |
147 | ||
148 | /* | |
149 | * PL08X specific defines | |
150 | */ | |
151 | ||
e8689e63 LW |
152 | /* Size (bytes) of each LLI buffer allocated for one transfer */ |
153 | # define PL08X_LLI_TSFR_SIZE 0x2000 | |
154 | ||
e8b5e11d | 155 | /* Maximum times we call dma_pool_alloc on this pool without freeing */ |
7cb72ad9 | 156 | #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli)) |
e8689e63 LW |
157 | #define PL08X_ALIGN 8 |
158 | ||
159 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
160 | { | |
161 | return container_of(chan, struct pl08x_dma_chan, chan); | |
162 | } | |
163 | ||
501e67e8 RKAL |
164 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
165 | { | |
166 | return container_of(tx, struct pl08x_txd, tx); | |
167 | } | |
168 | ||
e8689e63 LW |
169 | /* |
170 | * Physical channel handling | |
171 | */ | |
172 | ||
173 | /* Whether a certain channel is busy or not */ | |
174 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
175 | { | |
176 | unsigned int val; | |
177 | ||
178 | val = readl(ch->base + PL080_CH_CONFIG); | |
179 | return val & PL080_CONFIG_ACTIVE; | |
180 | } | |
181 | ||
182 | /* | |
183 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 184 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
185 | * been set when the LLIs were constructed. Poke them into the hardware |
186 | * and start the transfer. | |
e8689e63 | 187 | */ |
c885bee4 RKAL |
188 | static void pl08x_start_txd(struct pl08x_dma_chan *plchan, |
189 | struct pl08x_txd *txd) | |
e8689e63 | 190 | { |
c885bee4 | 191 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 192 | struct pl08x_phy_chan *phychan = plchan->phychan; |
19524d77 | 193 | struct pl08x_lli *lli = &txd->llis_va[0]; |
09b3c323 | 194 | u32 val; |
c885bee4 RKAL |
195 | |
196 | plchan->at = txd; | |
e8689e63 | 197 | |
c885bee4 RKAL |
198 | /* Wait for channel inactive */ |
199 | while (pl08x_phy_channel_busy(phychan)) | |
200 | cpu_relax(); | |
e8689e63 | 201 | |
c885bee4 RKAL |
202 | dev_vdbg(&pl08x->adev->dev, |
203 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
19524d77 RKAL |
204 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", |
205 | phychan->id, lli->src, lli->dst, lli->lli, lli->cctl, | |
09b3c323 | 206 | txd->ccfg); |
19524d77 RKAL |
207 | |
208 | writel(lli->src, phychan->base + PL080_CH_SRC_ADDR); | |
209 | writel(lli->dst, phychan->base + PL080_CH_DST_ADDR); | |
210 | writel(lli->lli, phychan->base + PL080_CH_LLI); | |
211 | writel(lli->cctl, phychan->base + PL080_CH_CONTROL); | |
09b3c323 | 212 | writel(txd->ccfg, phychan->base + PL080_CH_CONFIG); |
c885bee4 RKAL |
213 | |
214 | /* Enable the DMA channel */ | |
215 | /* Do not access config register until channel shows as disabled */ | |
216 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 217 | cpu_relax(); |
e8689e63 | 218 | |
c885bee4 RKAL |
219 | /* Do not access config register until channel shows as inactive */ |
220 | val = readl(phychan->base + PL080_CH_CONFIG); | |
e8689e63 | 221 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
c885bee4 | 222 | val = readl(phychan->base + PL080_CH_CONFIG); |
e8689e63 | 223 | |
c885bee4 | 224 | writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG); |
e8689e63 LW |
225 | } |
226 | ||
227 | /* | |
81796616 | 228 | * Pause the channel by setting the HALT bit. |
e8689e63 | 229 | * |
81796616 RKAL |
230 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
231 | * the FIFO can only drain if the peripheral is still requesting data. | |
232 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 233 | * |
81796616 RKAL |
234 | * For P->M transfers, disable the peripheral first to stop it filling |
235 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
236 | */ |
237 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
238 | { | |
239 | u32 val; | |
81796616 | 240 | int timeout; |
e8689e63 LW |
241 | |
242 | /* Set the HALT bit and wait for the FIFO to drain */ | |
243 | val = readl(ch->base + PL080_CH_CONFIG); | |
244 | val |= PL080_CONFIG_HALT; | |
245 | writel(val, ch->base + PL080_CH_CONFIG); | |
246 | ||
247 | /* Wait for channel inactive */ | |
81796616 RKAL |
248 | for (timeout = 1000; timeout; timeout--) { |
249 | if (!pl08x_phy_channel_busy(ch)) | |
250 | break; | |
251 | udelay(1); | |
252 | } | |
253 | if (pl08x_phy_channel_busy(ch)) | |
254 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
255 | } |
256 | ||
257 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
258 | { | |
259 | u32 val; | |
260 | ||
261 | /* Clear the HALT bit */ | |
262 | val = readl(ch->base + PL080_CH_CONFIG); | |
263 | val &= ~PL080_CONFIG_HALT; | |
264 | writel(val, ch->base + PL080_CH_CONFIG); | |
265 | } | |
266 | ||
fb526210 RKAL |
267 | /* |
268 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
269 | * clears any pending interrupt status. This should not be used for | |
270 | * an on-going transfer, but as a method of shutting down a channel | |
271 | * (eg, when it's no longer used) or terminating a transfer. | |
272 | */ | |
273 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
274 | struct pl08x_phy_chan *ch) | |
e8689e63 | 275 | { |
fb526210 | 276 | u32 val = readl(ch->base + PL080_CH_CONFIG); |
e8689e63 | 277 | |
fb526210 RKAL |
278 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
279 | PL080_CONFIG_TC_IRQ_MASK); | |
e8689e63 | 280 | |
e8689e63 | 281 | writel(val, ch->base + PL080_CH_CONFIG); |
fb526210 RKAL |
282 | |
283 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); | |
284 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
285 | } |
286 | ||
287 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
288 | { | |
289 | /* The source width defines the number of bytes */ | |
290 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
291 | ||
292 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
293 | case PL080_WIDTH_8BIT: | |
294 | break; | |
295 | case PL080_WIDTH_16BIT: | |
296 | bytes *= 2; | |
297 | break; | |
298 | case PL080_WIDTH_32BIT: | |
299 | bytes *= 4; | |
300 | break; | |
301 | } | |
302 | return bytes; | |
303 | } | |
304 | ||
305 | /* The channel should be paused when calling this */ | |
306 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
307 | { | |
308 | struct pl08x_phy_chan *ch; | |
e8689e63 LW |
309 | struct pl08x_txd *txd; |
310 | unsigned long flags; | |
cace6585 | 311 | size_t bytes = 0; |
e8689e63 LW |
312 | |
313 | spin_lock_irqsave(&plchan->lock, flags); | |
e8689e63 LW |
314 | ch = plchan->phychan; |
315 | txd = plchan->at; | |
316 | ||
317 | /* | |
db9f136a RKAL |
318 | * Follow the LLIs to get the number of remaining |
319 | * bytes in the currently active transaction. | |
e8689e63 LW |
320 | */ |
321 | if (ch && txd) { | |
4c0df6a3 | 322 | u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 323 | |
db9f136a | 324 | /* First get the remaining bytes in the active transfer */ |
e8689e63 LW |
325 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); |
326 | ||
327 | if (clli) { | |
db9f136a RKAL |
328 | struct pl08x_lli *llis_va = txd->llis_va; |
329 | dma_addr_t llis_bus = txd->llis_bus; | |
330 | int index; | |
331 | ||
332 | BUG_ON(clli < llis_bus || clli >= llis_bus + | |
333 | sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS); | |
e8689e63 | 334 | |
db9f136a RKAL |
335 | /* |
336 | * Locate the next LLI - as this is an array, | |
337 | * it's simple maths to find. | |
338 | */ | |
339 | index = (clli - llis_bus) / sizeof(struct pl08x_lli); | |
340 | ||
341 | for (; index < MAX_NUM_TSFR_LLIS; index++) { | |
342 | bytes += get_bytes_in_cctl(llis_va[index].cctl); | |
e8689e63 | 343 | |
e8689e63 | 344 | /* |
e8b5e11d | 345 | * A LLI pointer of 0 terminates the LLI list |
e8689e63 | 346 | */ |
db9f136a RKAL |
347 | if (!llis_va[index].lli) |
348 | break; | |
e8689e63 LW |
349 | } |
350 | } | |
351 | } | |
352 | ||
353 | /* Sum up all queued transactions */ | |
15c17232 | 354 | if (!list_empty(&plchan->pend_list)) { |
db9f136a | 355 | struct pl08x_txd *txdi; |
15c17232 | 356 | list_for_each_entry(txdi, &plchan->pend_list, node) { |
b7f69d9d VK |
357 | struct pl08x_sg *dsg; |
358 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
359 | bytes += dsg->len; | |
e8689e63 | 360 | } |
e8689e63 LW |
361 | } |
362 | ||
363 | spin_unlock_irqrestore(&plchan->lock, flags); | |
364 | ||
365 | return bytes; | |
366 | } | |
367 | ||
368 | /* | |
369 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
370 | * |
371 | * Try to locate a physical channel to be used for this transfer. If all | |
372 | * are taken return NULL and the requester will have to cope by using | |
373 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
374 | */ |
375 | static struct pl08x_phy_chan * | |
376 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
377 | struct pl08x_dma_chan *virt_chan) | |
378 | { | |
379 | struct pl08x_phy_chan *ch = NULL; | |
380 | unsigned long flags; | |
381 | int i; | |
382 | ||
e8689e63 LW |
383 | for (i = 0; i < pl08x->vd->channels; i++) { |
384 | ch = &pl08x->phy_chans[i]; | |
385 | ||
386 | spin_lock_irqsave(&ch->lock, flags); | |
387 | ||
388 | if (!ch->serving) { | |
389 | ch->serving = virt_chan; | |
390 | ch->signal = -1; | |
391 | spin_unlock_irqrestore(&ch->lock, flags); | |
392 | break; | |
393 | } | |
394 | ||
395 | spin_unlock_irqrestore(&ch->lock, flags); | |
396 | } | |
397 | ||
398 | if (i == pl08x->vd->channels) { | |
399 | /* No physical channel available, cope with it */ | |
400 | return NULL; | |
401 | } | |
402 | ||
b7b6018b | 403 | pm_runtime_get_sync(&pl08x->adev->dev); |
e8689e63 LW |
404 | return ch; |
405 | } | |
406 | ||
407 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, | |
408 | struct pl08x_phy_chan *ch) | |
409 | { | |
410 | unsigned long flags; | |
411 | ||
fb526210 RKAL |
412 | spin_lock_irqsave(&ch->lock, flags); |
413 | ||
e8689e63 | 414 | /* Stop the channel and clear its interrupts */ |
fb526210 | 415 | pl08x_terminate_phy_chan(pl08x, ch); |
e8689e63 | 416 | |
b7b6018b VK |
417 | pm_runtime_put(&pl08x->adev->dev); |
418 | ||
e8689e63 | 419 | /* Mark it as free */ |
e8689e63 LW |
420 | ch->serving = NULL; |
421 | spin_unlock_irqrestore(&ch->lock, flags); | |
422 | } | |
423 | ||
424 | /* | |
425 | * LLI handling | |
426 | */ | |
427 | ||
428 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
429 | { | |
430 | switch (coded) { | |
431 | case PL080_WIDTH_8BIT: | |
432 | return 1; | |
433 | case PL080_WIDTH_16BIT: | |
434 | return 2; | |
435 | case PL080_WIDTH_32BIT: | |
436 | return 4; | |
437 | default: | |
438 | break; | |
439 | } | |
440 | BUG(); | |
441 | return 0; | |
442 | } | |
443 | ||
444 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 445 | size_t tsize) |
e8689e63 LW |
446 | { |
447 | u32 retbits = cctl; | |
448 | ||
e8b5e11d | 449 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
450 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
451 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
452 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
453 | ||
454 | /* Then set the bits according to the parameters */ | |
455 | switch (srcwidth) { | |
456 | case 1: | |
457 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
458 | break; | |
459 | case 2: | |
460 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
461 | break; | |
462 | case 4: | |
463 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
464 | break; | |
465 | default: | |
466 | BUG(); | |
467 | break; | |
468 | } | |
469 | ||
470 | switch (dstwidth) { | |
471 | case 1: | |
472 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
473 | break; | |
474 | case 2: | |
475 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
476 | break; | |
477 | case 4: | |
478 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
479 | break; | |
480 | default: | |
481 | BUG(); | |
482 | break; | |
483 | } | |
484 | ||
485 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
486 | return retbits; | |
487 | } | |
488 | ||
542361f8 RKAL |
489 | struct pl08x_lli_build_data { |
490 | struct pl08x_txd *txd; | |
542361f8 RKAL |
491 | struct pl08x_bus_data srcbus; |
492 | struct pl08x_bus_data dstbus; | |
493 | size_t remainder; | |
25c94f7f | 494 | u32 lli_bus; |
542361f8 RKAL |
495 | }; |
496 | ||
e8689e63 | 497 | /* |
0532e6fc VK |
498 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
499 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
500 | * masters address with width requirements of transfer (by sending few byte by | |
501 | * byte data), slave is still not aligned, then its width will be reduced to | |
502 | * BYTE. | |
503 | * - prefers the destination bus if both available | |
036f05fd | 504 | * - prefers bus with fixed address (i.e. peripheral) |
e8689e63 | 505 | */ |
542361f8 RKAL |
506 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
507 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) | |
e8689e63 LW |
508 | { |
509 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
542361f8 RKAL |
510 | *mbus = &bd->dstbus; |
511 | *sbus = &bd->srcbus; | |
036f05fd VK |
512 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
513 | *mbus = &bd->srcbus; | |
514 | *sbus = &bd->dstbus; | |
e8689e63 | 515 | } else { |
036f05fd | 516 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
542361f8 RKAL |
517 | *mbus = &bd->dstbus; |
518 | *sbus = &bd->srcbus; | |
036f05fd | 519 | } else { |
542361f8 RKAL |
520 | *mbus = &bd->srcbus; |
521 | *sbus = &bd->dstbus; | |
e8689e63 LW |
522 | } |
523 | } | |
524 | } | |
525 | ||
526 | /* | |
94ae8522 | 527 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 528 | */ |
542361f8 RKAL |
529 | static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd, |
530 | int num_llis, int len, u32 cctl) | |
e8689e63 | 531 | { |
542361f8 RKAL |
532 | struct pl08x_lli *llis_va = bd->txd->llis_va; |
533 | dma_addr_t llis_bus = bd->txd->llis_bus; | |
e8689e63 LW |
534 | |
535 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
536 | ||
30749cb4 | 537 | llis_va[num_llis].cctl = cctl; |
542361f8 RKAL |
538 | llis_va[num_llis].src = bd->srcbus.addr; |
539 | llis_va[num_llis].dst = bd->dstbus.addr; | |
3e27ee84 VK |
540 | llis_va[num_llis].lli = llis_bus + (num_llis + 1) * |
541 | sizeof(struct pl08x_lli); | |
25c94f7f | 542 | llis_va[num_llis].lli |= bd->lli_bus; |
e8689e63 LW |
543 | |
544 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 | 545 | bd->srcbus.addr += len; |
e8689e63 | 546 | if (cctl & PL080_CONTROL_DST_INCR) |
542361f8 | 547 | bd->dstbus.addr += len; |
e8689e63 | 548 | |
542361f8 | 549 | BUG_ON(bd->remainder < len); |
cace6585 | 550 | |
542361f8 | 551 | bd->remainder -= len; |
e8689e63 LW |
552 | } |
553 | ||
03af500f VK |
554 | static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd, |
555 | u32 *cctl, u32 len, int num_llis, size_t *total_bytes) | |
e8689e63 | 556 | { |
03af500f VK |
557 | *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); |
558 | pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl); | |
559 | (*total_bytes) += len; | |
e8689e63 LW |
560 | } |
561 | ||
562 | /* | |
563 | * This fills in the table of LLIs for the transfer descriptor | |
564 | * Note that we assume we never have to change the burst sizes | |
565 | * Return 0 for error | |
566 | */ | |
567 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
568 | struct pl08x_txd *txd) | |
569 | { | |
e8689e63 | 570 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 571 | struct pl08x_lli_build_data bd; |
e8689e63 | 572 | int num_llis = 0; |
03af500f | 573 | u32 cctl, early_bytes = 0; |
b7f69d9d | 574 | size_t max_bytes_per_lli, total_bytes; |
7cb72ad9 | 575 | struct pl08x_lli *llis_va; |
b7f69d9d | 576 | struct pl08x_sg *dsg; |
e8689e63 | 577 | |
3e27ee84 | 578 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
579 | if (!txd->llis_va) { |
580 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
581 | return 0; | |
582 | } | |
583 | ||
584 | pl08x->pool_ctr++; | |
585 | ||
542361f8 | 586 | bd.txd = txd; |
25c94f7f | 587 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
b7f69d9d | 588 | cctl = txd->cctl; |
542361f8 | 589 | |
e8689e63 | 590 | /* Find maximum width of the source bus */ |
542361f8 | 591 | bd.srcbus.maxwidth = |
e8689e63 LW |
592 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
593 | PL080_CONTROL_SWIDTH_SHIFT); | |
594 | ||
595 | /* Find maximum width of the destination bus */ | |
542361f8 | 596 | bd.dstbus.maxwidth = |
e8689e63 LW |
597 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
598 | PL080_CONTROL_DWIDTH_SHIFT); | |
599 | ||
b7f69d9d VK |
600 | list_for_each_entry(dsg, &txd->dsg_list, node) { |
601 | total_bytes = 0; | |
602 | cctl = txd->cctl; | |
e8689e63 | 603 | |
b7f69d9d VK |
604 | bd.srcbus.addr = dsg->src_addr; |
605 | bd.dstbus.addr = dsg->dst_addr; | |
606 | bd.remainder = dsg->len; | |
607 | bd.srcbus.buswidth = bd.srcbus.maxwidth; | |
608 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 | 609 | |
b7f69d9d | 610 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
e8689e63 | 611 | |
b7f69d9d VK |
612 | dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n", |
613 | bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", | |
614 | bd.srcbus.buswidth, | |
615 | bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
616 | bd.dstbus.buswidth, | |
617 | bd.remainder); | |
618 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", | |
619 | mbus == &bd.srcbus ? "src" : "dst", | |
620 | sbus == &bd.srcbus ? "src" : "dst"); | |
fc74eb79 | 621 | |
b7f69d9d VK |
622 | /* |
623 | * Zero length is only allowed if all these requirements are | |
624 | * met: | |
625 | * - flow controller is peripheral. | |
626 | * - src.addr is aligned to src.width | |
627 | * - dst.addr is aligned to dst.width | |
628 | * | |
629 | * sg_len == 1 should be true, as there can be two cases here: | |
630 | * | |
631 | * - Memory addresses are contiguous and are not scattered. | |
632 | * Here, Only one sg will be passed by user driver, with | |
633 | * memory address and zero length. We pass this to controller | |
634 | * and after the transfer it will receive the last burst | |
635 | * request from peripheral and so transfer finishes. | |
636 | * | |
637 | * - Memory addresses are scattered and are not contiguous. | |
638 | * Here, Obviously as DMA controller doesn't know when a lli's | |
639 | * transfer gets over, it can't load next lli. So in this | |
640 | * case, there has to be an assumption that only one lli is | |
641 | * supported. Thus, we can't have scattered addresses. | |
642 | */ | |
643 | if (!bd.remainder) { | |
644 | u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> | |
645 | PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
646 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && | |
0a235657 | 647 | (fc <= PL080_FLOW_SRC2DST_SRC))) { |
b7f69d9d VK |
648 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", |
649 | __func__); | |
650 | return 0; | |
651 | } | |
0a235657 | 652 | |
b7f69d9d | 653 | if ((bd.srcbus.addr % bd.srcbus.buswidth) || |
880db3ff | 654 | (bd.dstbus.addr % bd.dstbus.buswidth)) { |
b7f69d9d VK |
655 | dev_err(&pl08x->adev->dev, |
656 | "%s src & dst address must be aligned to src" | |
657 | " & dst width if peripheral is flow controller", | |
658 | __func__); | |
659 | return 0; | |
660 | } | |
03af500f | 661 | |
b7f69d9d VK |
662 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
663 | bd.dstbus.buswidth, 0); | |
664 | pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl); | |
665 | break; | |
666 | } | |
e8689e63 LW |
667 | |
668 | /* | |
b7f69d9d VK |
669 | * Send byte by byte for following cases |
670 | * - Less than a bus width available | |
671 | * - until master bus is aligned | |
e8689e63 | 672 | */ |
b7f69d9d VK |
673 | if (bd.remainder < mbus->buswidth) |
674 | early_bytes = bd.remainder; | |
675 | else if ((mbus->addr) % (mbus->buswidth)) { | |
676 | early_bytes = mbus->buswidth - (mbus->addr) % | |
677 | (mbus->buswidth); | |
678 | if ((bd.remainder - early_bytes) < mbus->buswidth) | |
679 | early_bytes = bd.remainder; | |
680 | } | |
e8689e63 | 681 | |
b7f69d9d VK |
682 | if (early_bytes) { |
683 | dev_vdbg(&pl08x->adev->dev, | |
684 | "%s byte width LLIs (remain 0x%08x)\n", | |
685 | __func__, bd.remainder); | |
686 | prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++, | |
687 | &total_bytes); | |
e8689e63 LW |
688 | } |
689 | ||
b7f69d9d VK |
690 | if (bd.remainder) { |
691 | /* | |
692 | * Master now aligned | |
693 | * - if slave is not then we must set its width down | |
694 | */ | |
695 | if (sbus->addr % sbus->buswidth) { | |
696 | dev_dbg(&pl08x->adev->dev, | |
697 | "%s set down bus width to one byte\n", | |
698 | __func__); | |
fa6a940b | 699 | |
b7f69d9d VK |
700 | sbus->buswidth = 1; |
701 | } | |
e8689e63 LW |
702 | |
703 | /* | |
b7f69d9d VK |
704 | * Bytes transferred = tsize * src width, not |
705 | * MIN(buswidths) | |
e8689e63 | 706 | */ |
b7f69d9d VK |
707 | max_bytes_per_lli = bd.srcbus.buswidth * |
708 | PL080_CONTROL_TRANSFER_SIZE_MASK; | |
709 | dev_vdbg(&pl08x->adev->dev, | |
710 | "%s max bytes per lli = %zu\n", | |
711 | __func__, max_bytes_per_lli); | |
e8689e63 LW |
712 | |
713 | /* | |
b7f69d9d VK |
714 | * Make largest possible LLIs until less than one bus |
715 | * width left | |
e8689e63 | 716 | */ |
b7f69d9d VK |
717 | while (bd.remainder > (mbus->buswidth - 1)) { |
718 | size_t lli_len, tsize, width; | |
e8689e63 | 719 | |
b7f69d9d VK |
720 | /* |
721 | * If enough left try to send max possible, | |
722 | * otherwise try to send the remainder | |
723 | */ | |
724 | lli_len = min(bd.remainder, max_bytes_per_lli); | |
16a2e7d3 | 725 | |
b7f69d9d VK |
726 | /* |
727 | * Check against maximum bus alignment: | |
728 | * Calculate actual transfer size in relation to | |
729 | * bus width an get a maximum remainder of the | |
730 | * highest bus width - 1 | |
731 | */ | |
732 | width = max(mbus->buswidth, sbus->buswidth); | |
733 | lli_len = (lli_len / width) * width; | |
734 | tsize = lli_len / bd.srcbus.buswidth; | |
735 | ||
736 | dev_vdbg(&pl08x->adev->dev, | |
737 | "%s fill lli with single lli chunk of " | |
738 | "size 0x%08zx (remainder 0x%08zx)\n", | |
739 | __func__, lli_len, bd.remainder); | |
740 | ||
741 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, | |
16a2e7d3 | 742 | bd.dstbus.buswidth, tsize); |
b7f69d9d VK |
743 | pl08x_fill_lli_for_desc(&bd, num_llis++, |
744 | lli_len, cctl); | |
745 | total_bytes += lli_len; | |
746 | } | |
e8689e63 | 747 | |
b7f69d9d VK |
748 | /* |
749 | * Send any odd bytes | |
750 | */ | |
751 | if (bd.remainder) { | |
752 | dev_vdbg(&pl08x->adev->dev, | |
753 | "%s align with boundary, send odd bytes (remain %zu)\n", | |
754 | __func__, bd.remainder); | |
755 | prep_byte_width_lli(&bd, &cctl, bd.remainder, | |
756 | num_llis++, &total_bytes); | |
757 | } | |
e8689e63 | 758 | } |
16a2e7d3 | 759 | |
b7f69d9d VK |
760 | if (total_bytes != dsg->len) { |
761 | dev_err(&pl08x->adev->dev, | |
762 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", | |
763 | __func__, total_bytes, dsg->len); | |
764 | return 0; | |
765 | } | |
e8689e63 | 766 | |
b7f69d9d VK |
767 | if (num_llis >= MAX_NUM_TSFR_LLIS) { |
768 | dev_err(&pl08x->adev->dev, | |
769 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
770 | __func__, (u32) MAX_NUM_TSFR_LLIS); | |
771 | return 0; | |
772 | } | |
e8689e63 | 773 | } |
b58b6b5b RKAL |
774 | |
775 | llis_va = txd->llis_va; | |
94ae8522 | 776 | /* The final LLI terminates the LLI. */ |
bfddfb45 | 777 | llis_va[num_llis - 1].lli = 0; |
94ae8522 | 778 | /* The final LLI element shall also fire an interrupt. */ |
b58b6b5b | 779 | llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN; |
e8689e63 | 780 | |
e8689e63 LW |
781 | #ifdef VERBOSE_DEBUG |
782 | { | |
783 | int i; | |
784 | ||
fc74eb79 RKAL |
785 | dev_vdbg(&pl08x->adev->dev, |
786 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
787 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
e8689e63 LW |
788 | for (i = 0; i < num_llis; i++) { |
789 | dev_vdbg(&pl08x->adev->dev, | |
fc74eb79 RKAL |
790 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
791 | i, &llis_va[i], llis_va[i].src, | |
792 | llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl | |
e8689e63 LW |
793 | ); |
794 | } | |
795 | } | |
796 | #endif | |
797 | ||
798 | return num_llis; | |
799 | } | |
800 | ||
801 | /* You should call this with the struct pl08x lock held */ | |
802 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, | |
803 | struct pl08x_txd *txd) | |
804 | { | |
b7f69d9d VK |
805 | struct pl08x_sg *dsg, *_dsg; |
806 | ||
e8689e63 | 807 | /* Free the LLI */ |
c1205646 VK |
808 | if (txd->llis_va) |
809 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); | |
e8689e63 LW |
810 | |
811 | pl08x->pool_ctr--; | |
812 | ||
b7f69d9d VK |
813 | list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) { |
814 | list_del(&dsg->node); | |
815 | kfree(dsg); | |
816 | } | |
817 | ||
e8689e63 LW |
818 | kfree(txd); |
819 | } | |
820 | ||
821 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, | |
822 | struct pl08x_dma_chan *plchan) | |
823 | { | |
824 | struct pl08x_txd *txdi = NULL; | |
825 | struct pl08x_txd *next; | |
826 | ||
15c17232 | 827 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 | 828 | list_for_each_entry_safe(txdi, |
15c17232 | 829 | next, &plchan->pend_list, node) { |
e8689e63 LW |
830 | list_del(&txdi->node); |
831 | pl08x_free_txd(pl08x, txdi); | |
832 | } | |
e8689e63 LW |
833 | } |
834 | } | |
835 | ||
836 | /* | |
837 | * The DMA ENGINE API | |
838 | */ | |
839 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
840 | { | |
841 | return 0; | |
842 | } | |
843 | ||
844 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
845 | { | |
846 | } | |
847 | ||
848 | /* | |
849 | * This should be called with the channel plchan->lock held | |
850 | */ | |
851 | static int prep_phy_channel(struct pl08x_dma_chan *plchan, | |
852 | struct pl08x_txd *txd) | |
853 | { | |
854 | struct pl08x_driver_data *pl08x = plchan->host; | |
855 | struct pl08x_phy_chan *ch; | |
856 | int ret; | |
857 | ||
858 | /* Check if we already have a channel */ | |
8f0d30f9 VK |
859 | if (plchan->phychan) { |
860 | ch = plchan->phychan; | |
861 | goto got_channel; | |
862 | } | |
e8689e63 LW |
863 | |
864 | ch = pl08x_get_phy_channel(pl08x, plchan); | |
865 | if (!ch) { | |
866 | /* No physical channel available, cope with it */ | |
867 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
868 | return -EBUSY; | |
869 | } | |
870 | ||
871 | /* | |
872 | * OK we have a physical channel: for memcpy() this is all we | |
873 | * need, but for slaves the physical signals may be muxed! | |
874 | * Can the platform allow us to use this channel? | |
875 | */ | |
16ca8105 | 876 | if (plchan->slave && pl08x->pd->get_signal) { |
e8689e63 LW |
877 | ret = pl08x->pd->get_signal(plchan); |
878 | if (ret < 0) { | |
879 | dev_dbg(&pl08x->adev->dev, | |
880 | "unable to use physical channel %d for transfer on %s due to platform restrictions\n", | |
881 | ch->id, plchan->name); | |
882 | /* Release physical channel & return */ | |
883 | pl08x_put_phy_channel(pl08x, ch); | |
884 | return -EBUSY; | |
885 | } | |
886 | ch->signal = ret; | |
887 | } | |
888 | ||
8f0d30f9 | 889 | plchan->phychan = ch; |
e8689e63 LW |
890 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n", |
891 | ch->id, | |
892 | ch->signal, | |
893 | plchan->name); | |
894 | ||
8f0d30f9 VK |
895 | got_channel: |
896 | /* Assign the flow control signal to this channel */ | |
897 | if (txd->direction == DMA_MEM_TO_DEV) | |
898 | txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
899 | else if (txd->direction == DMA_DEV_TO_MEM) | |
900 | txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
901 | ||
8087aacd | 902 | plchan->phychan_hold++; |
e8689e63 LW |
903 | |
904 | return 0; | |
905 | } | |
906 | ||
8c8cc2b1 RKAL |
907 | static void release_phy_channel(struct pl08x_dma_chan *plchan) |
908 | { | |
909 | struct pl08x_driver_data *pl08x = plchan->host; | |
910 | ||
911 | if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) { | |
912 | pl08x->pd->put_signal(plchan); | |
913 | plchan->phychan->signal = -1; | |
914 | } | |
915 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
916 | plchan->phychan = NULL; | |
917 | } | |
918 | ||
e8689e63 LW |
919 | static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) |
920 | { | |
921 | struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan); | |
501e67e8 | 922 | struct pl08x_txd *txd = to_pl08x_txd(tx); |
c370e594 | 923 | unsigned long flags; |
884485e1 | 924 | dma_cookie_t cookie; |
c370e594 RKAL |
925 | |
926 | spin_lock_irqsave(&plchan->lock, flags); | |
884485e1 | 927 | cookie = dma_cookie_assign(tx); |
501e67e8 RKAL |
928 | |
929 | /* Put this onto the pending list */ | |
930 | list_add_tail(&txd->node, &plchan->pend_list); | |
931 | ||
932 | /* | |
933 | * If there was no physical channel available for this memcpy, | |
934 | * stack the request up and indicate that the channel is waiting | |
935 | * for a free physical channel. | |
936 | */ | |
937 | if (!plchan->slave && !plchan->phychan) { | |
938 | /* Do this memcpy whenever there is a channel ready */ | |
939 | plchan->state = PL08X_CHAN_WAITING; | |
940 | plchan->waiting = txd; | |
8087aacd RKAL |
941 | } else { |
942 | plchan->phychan_hold--; | |
501e67e8 RKAL |
943 | } |
944 | ||
c370e594 | 945 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 | 946 | |
884485e1 | 947 | return cookie; |
e8689e63 LW |
948 | } |
949 | ||
950 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( | |
951 | struct dma_chan *chan, unsigned long flags) | |
952 | { | |
953 | struct dma_async_tx_descriptor *retval = NULL; | |
954 | ||
955 | return retval; | |
956 | } | |
957 | ||
958 | /* | |
94ae8522 RKAL |
959 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
960 | * If slaves are relying on interrupts to signal completion this function | |
961 | * must not be called with interrupts disabled. | |
e8689e63 | 962 | */ |
3e27ee84 VK |
963 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
964 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
965 | { |
966 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
967 | dma_cookie_t last_used; | |
968 | dma_cookie_t last_complete; | |
969 | enum dma_status ret; | |
970 | u32 bytesleft = 0; | |
971 | ||
91aa5fad | 972 | last_used = plchan->chan.cookie; |
4d4e58de | 973 | last_complete = plchan->chan.completed_cookie; |
e8689e63 LW |
974 | |
975 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
976 | if (ret == DMA_SUCCESS) { | |
977 | dma_set_tx_state(txstate, last_complete, last_used, 0); | |
978 | return ret; | |
979 | } | |
980 | ||
e8689e63 LW |
981 | /* |
982 | * This cookie not complete yet | |
983 | */ | |
91aa5fad | 984 | last_used = plchan->chan.cookie; |
4d4e58de | 985 | last_complete = plchan->chan.completed_cookie; |
e8689e63 LW |
986 | |
987 | /* Get number of bytes left in the active transactions and queue */ | |
988 | bytesleft = pl08x_getbytes_chan(plchan); | |
989 | ||
990 | dma_set_tx_state(txstate, last_complete, last_used, | |
991 | bytesleft); | |
992 | ||
993 | if (plchan->state == PL08X_CHAN_PAUSED) | |
994 | return DMA_PAUSED; | |
995 | ||
996 | /* Whether waiting or running, we're in progress */ | |
997 | return DMA_IN_PROGRESS; | |
998 | } | |
999 | ||
1000 | /* PrimeCell DMA extension */ | |
1001 | struct burst_table { | |
760596c6 | 1002 | u32 burstwords; |
e8689e63 LW |
1003 | u32 reg; |
1004 | }; | |
1005 | ||
1006 | static const struct burst_table burst_sizes[] = { | |
1007 | { | |
1008 | .burstwords = 256, | |
760596c6 | 1009 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
1010 | }, |
1011 | { | |
1012 | .burstwords = 128, | |
760596c6 | 1013 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
1014 | }, |
1015 | { | |
1016 | .burstwords = 64, | |
760596c6 | 1017 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
1018 | }, |
1019 | { | |
1020 | .burstwords = 32, | |
760596c6 | 1021 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
1022 | }, |
1023 | { | |
1024 | .burstwords = 16, | |
760596c6 | 1025 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
1026 | }, |
1027 | { | |
1028 | .burstwords = 8, | |
760596c6 | 1029 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1030 | }, |
1031 | { | |
1032 | .burstwords = 4, | |
760596c6 | 1033 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1034 | }, |
1035 | { | |
760596c6 RKAL |
1036 | .burstwords = 0, |
1037 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1038 | }, |
1039 | }; | |
1040 | ||
121c8476 RKAL |
1041 | /* |
1042 | * Given the source and destination available bus masks, select which | |
1043 | * will be routed to each port. We try to have source and destination | |
1044 | * on separate ports, but always respect the allowable settings. | |
1045 | */ | |
1046 | static u32 pl08x_select_bus(u8 src, u8 dst) | |
1047 | { | |
1048 | u32 cctl = 0; | |
1049 | ||
1050 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1051 | cctl |= PL080_CONTROL_DST_AHB2; | |
1052 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1053 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1054 | ||
1055 | return cctl; | |
1056 | } | |
1057 | ||
f14c426c RKAL |
1058 | static u32 pl08x_cctl(u32 cctl) |
1059 | { | |
1060 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1061 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1062 | PL080_CONTROL_PROT_MASK); | |
1063 | ||
1064 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1065 | return cctl | PL080_CONTROL_PROT_SYS; | |
1066 | } | |
1067 | ||
aa88cdaa RKAL |
1068 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1069 | { | |
1070 | switch (width) { | |
1071 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1072 | return PL080_WIDTH_8BIT; | |
1073 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1074 | return PL080_WIDTH_16BIT; | |
1075 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1076 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1077 | default: |
1078 | return ~0; | |
aa88cdaa | 1079 | } |
aa88cdaa RKAL |
1080 | } |
1081 | ||
760596c6 RKAL |
1082 | static u32 pl08x_burst(u32 maxburst) |
1083 | { | |
1084 | int i; | |
1085 | ||
1086 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1087 | if (burst_sizes[i].burstwords <= maxburst) | |
1088 | break; | |
1089 | ||
1090 | return burst_sizes[i].reg; | |
1091 | } | |
1092 | ||
f0fd9446 RKAL |
1093 | static int dma_set_runtime_config(struct dma_chan *chan, |
1094 | struct dma_slave_config *config) | |
e8689e63 LW |
1095 | { |
1096 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1097 | struct pl08x_driver_data *pl08x = plchan->host; | |
e8689e63 | 1098 | enum dma_slave_buswidth addr_width; |
760596c6 | 1099 | u32 width, burst, maxburst; |
e8689e63 | 1100 | u32 cctl = 0; |
b7f75865 RKAL |
1101 | |
1102 | if (!plchan->slave) | |
1103 | return -EINVAL; | |
e8689e63 LW |
1104 | |
1105 | /* Transfer direction */ | |
1106 | plchan->runtime_direction = config->direction; | |
db8196df | 1107 | if (config->direction == DMA_MEM_TO_DEV) { |
e8689e63 LW |
1108 | addr_width = config->dst_addr_width; |
1109 | maxburst = config->dst_maxburst; | |
db8196df | 1110 | } else if (config->direction == DMA_DEV_TO_MEM) { |
e8689e63 LW |
1111 | addr_width = config->src_addr_width; |
1112 | maxburst = config->src_maxburst; | |
1113 | } else { | |
1114 | dev_err(&pl08x->adev->dev, | |
1115 | "bad runtime_config: alien transfer direction\n"); | |
f0fd9446 | 1116 | return -EINVAL; |
e8689e63 LW |
1117 | } |
1118 | ||
aa88cdaa RKAL |
1119 | width = pl08x_width(addr_width); |
1120 | if (width == ~0) { | |
e8689e63 LW |
1121 | dev_err(&pl08x->adev->dev, |
1122 | "bad runtime_config: alien address width\n"); | |
f0fd9446 | 1123 | return -EINVAL; |
e8689e63 LW |
1124 | } |
1125 | ||
aa88cdaa RKAL |
1126 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; |
1127 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1128 | ||
e8689e63 | 1129 | /* |
4440aacf RKAL |
1130 | * If this channel will only request single transfers, set this |
1131 | * down to ONE element. Also select one element if no maxburst | |
1132 | * is specified. | |
e8689e63 | 1133 | */ |
760596c6 RKAL |
1134 | if (plchan->cd->single) |
1135 | maxburst = 1; | |
1136 | ||
1137 | burst = pl08x_burst(maxburst); | |
1138 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1139 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
e8689e63 | 1140 | |
8c9f7aa3 VK |
1141 | plchan->device_fc = config->device_fc; |
1142 | ||
db8196df | 1143 | if (plchan->runtime_direction == DMA_DEV_TO_MEM) { |
b207b4d0 | 1144 | plchan->src_addr = config->src_addr; |
121c8476 RKAL |
1145 | plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR | |
1146 | pl08x_select_bus(plchan->cd->periph_buses, | |
1147 | pl08x->mem_buses); | |
b207b4d0 RKAL |
1148 | } else { |
1149 | plchan->dst_addr = config->dst_addr; | |
121c8476 RKAL |
1150 | plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR | |
1151 | pl08x_select_bus(pl08x->mem_buses, | |
1152 | plchan->cd->periph_buses); | |
b207b4d0 | 1153 | } |
f0fd9446 | 1154 | |
e8689e63 LW |
1155 | dev_dbg(&pl08x->adev->dev, |
1156 | "configured channel %s (%s) for %s, data width %d, " | |
4983a04f | 1157 | "maxburst %d words, LE, CCTL=0x%08x\n", |
e8689e63 | 1158 | dma_chan_name(chan), plchan->name, |
db8196df | 1159 | (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX", |
e8689e63 LW |
1160 | addr_width, |
1161 | maxburst, | |
4983a04f | 1162 | cctl); |
f0fd9446 RKAL |
1163 | |
1164 | return 0; | |
e8689e63 LW |
1165 | } |
1166 | ||
1167 | /* | |
1168 | * Slave transactions callback to the slave device to allow | |
1169 | * synchronization of slave DMA signals with the DMAC enable | |
1170 | */ | |
1171 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1172 | { | |
1173 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1174 | unsigned long flags; |
1175 | ||
1176 | spin_lock_irqsave(&plchan->lock, flags); | |
9c0bb43b RKAL |
1177 | /* Something is already active, or we're waiting for a channel... */ |
1178 | if (plchan->at || plchan->state == PL08X_CHAN_WAITING) { | |
1179 | spin_unlock_irqrestore(&plchan->lock, flags); | |
e8689e63 | 1180 | return; |
9c0bb43b | 1181 | } |
e8689e63 LW |
1182 | |
1183 | /* Take the first element in the queue and execute it */ | |
15c17232 | 1184 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 LW |
1185 | struct pl08x_txd *next; |
1186 | ||
15c17232 | 1187 | next = list_first_entry(&plchan->pend_list, |
e8689e63 LW |
1188 | struct pl08x_txd, |
1189 | node); | |
1190 | list_del(&next->node); | |
e8689e63 LW |
1191 | plchan->state = PL08X_CHAN_RUNNING; |
1192 | ||
c885bee4 | 1193 | pl08x_start_txd(plchan, next); |
e8689e63 LW |
1194 | } |
1195 | ||
1196 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1197 | } | |
1198 | ||
1199 | static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan, | |
1200 | struct pl08x_txd *txd) | |
1201 | { | |
e8689e63 | 1202 | struct pl08x_driver_data *pl08x = plchan->host; |
c370e594 RKAL |
1203 | unsigned long flags; |
1204 | int num_llis, ret; | |
e8689e63 LW |
1205 | |
1206 | num_llis = pl08x_fill_llis_for_desc(pl08x, txd); | |
dafa7317 | 1207 | if (!num_llis) { |
57001a60 VK |
1208 | spin_lock_irqsave(&plchan->lock, flags); |
1209 | pl08x_free_txd(pl08x, txd); | |
1210 | spin_unlock_irqrestore(&plchan->lock, flags); | |
e8689e63 | 1211 | return -EINVAL; |
dafa7317 | 1212 | } |
e8689e63 | 1213 | |
c370e594 | 1214 | spin_lock_irqsave(&plchan->lock, flags); |
e8689e63 | 1215 | |
e8689e63 LW |
1216 | /* |
1217 | * See if we already have a physical channel allocated, | |
1218 | * else this is the time to try to get one. | |
1219 | */ | |
1220 | ret = prep_phy_channel(plchan, txd); | |
1221 | if (ret) { | |
1222 | /* | |
501e67e8 RKAL |
1223 | * No physical channel was available. |
1224 | * | |
1225 | * memcpy transfers can be sorted out at submission time. | |
1226 | * | |
1227 | * Slave transfers may have been denied due to platform | |
1228 | * channel muxing restrictions. Since there is no guarantee | |
1229 | * that this will ever be resolved, and the signal must be | |
1230 | * acquired AFTER acquiring the physical channel, we will let | |
1231 | * them be NACK:ed with -EBUSY here. The drivers can retry | |
1232 | * the prep() call if they are eager on doing this using DMA. | |
e8689e63 LW |
1233 | */ |
1234 | if (plchan->slave) { | |
1235 | pl08x_free_txd_list(pl08x, plchan); | |
501e67e8 | 1236 | pl08x_free_txd(pl08x, txd); |
c370e594 | 1237 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 LW |
1238 | return -EBUSY; |
1239 | } | |
e8689e63 LW |
1240 | } else |
1241 | /* | |
94ae8522 RKAL |
1242 | * Else we're all set, paused and ready to roll, status |
1243 | * will switch to PL08X_CHAN_RUNNING when we call | |
1244 | * issue_pending(). If there is something running on the | |
1245 | * channel already we don't change its state. | |
e8689e63 LW |
1246 | */ |
1247 | if (plchan->state == PL08X_CHAN_IDLE) | |
1248 | plchan->state = PL08X_CHAN_PAUSED; | |
1249 | ||
c370e594 | 1250 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 LW |
1251 | |
1252 | return 0; | |
1253 | } | |
1254 | ||
c0428794 RKAL |
1255 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan, |
1256 | unsigned long flags) | |
ac3cd20d | 1257 | { |
b201c111 | 1258 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d RKAL |
1259 | |
1260 | if (txd) { | |
1261 | dma_async_tx_descriptor_init(&txd->tx, &plchan->chan); | |
c0428794 | 1262 | txd->tx.flags = flags; |
ac3cd20d RKAL |
1263 | txd->tx.tx_submit = pl08x_tx_submit; |
1264 | INIT_LIST_HEAD(&txd->node); | |
b7f69d9d | 1265 | INIT_LIST_HEAD(&txd->dsg_list); |
4983a04f RKAL |
1266 | |
1267 | /* Always enable error and terminal interrupts */ | |
1268 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1269 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1270 | } |
1271 | return txd; | |
1272 | } | |
1273 | ||
e8689e63 LW |
1274 | /* |
1275 | * Initialize a descriptor to be used by memcpy submit | |
1276 | */ | |
1277 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1278 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1279 | size_t len, unsigned long flags) | |
1280 | { | |
1281 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1282 | struct pl08x_driver_data *pl08x = plchan->host; | |
1283 | struct pl08x_txd *txd; | |
b7f69d9d | 1284 | struct pl08x_sg *dsg; |
e8689e63 LW |
1285 | int ret; |
1286 | ||
c0428794 | 1287 | txd = pl08x_get_txd(plchan, flags); |
e8689e63 LW |
1288 | if (!txd) { |
1289 | dev_err(&pl08x->adev->dev, | |
1290 | "%s no memory for descriptor\n", __func__); | |
1291 | return NULL; | |
1292 | } | |
1293 | ||
b7f69d9d VK |
1294 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); |
1295 | if (!dsg) { | |
1296 | pl08x_free_txd(pl08x, txd); | |
1297 | dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n", | |
1298 | __func__); | |
1299 | return NULL; | |
1300 | } | |
1301 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1302 | ||
e8689e63 | 1303 | txd->direction = DMA_NONE; |
b7f69d9d VK |
1304 | dsg->src_addr = src; |
1305 | dsg->dst_addr = dest; | |
1306 | dsg->len = len; | |
e8689e63 LW |
1307 | |
1308 | /* Set platform data for m2m */ | |
4983a04f | 1309 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
c7da9a56 RKAL |
1310 | txd->cctl = pl08x->pd->memcpy_channel.cctl & |
1311 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); | |
4983a04f | 1312 | |
e8689e63 | 1313 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1314 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1315 | |
c7da9a56 | 1316 | if (pl08x->vd->dualmaster) |
121c8476 RKAL |
1317 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
1318 | pl08x->mem_buses); | |
e8689e63 | 1319 | |
e8689e63 LW |
1320 | ret = pl08x_prep_channel_resources(plchan, txd); |
1321 | if (ret) | |
1322 | return NULL; | |
e8689e63 LW |
1323 | |
1324 | return &txd->tx; | |
1325 | } | |
1326 | ||
3e2a037c | 1327 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 | 1328 | struct dma_chan *chan, struct scatterlist *sgl, |
db8196df | 1329 | unsigned int sg_len, enum dma_transfer_direction direction, |
e8689e63 LW |
1330 | unsigned long flags) |
1331 | { | |
1332 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1333 | struct pl08x_driver_data *pl08x = plchan->host; | |
1334 | struct pl08x_txd *txd; | |
b7f69d9d VK |
1335 | struct pl08x_sg *dsg; |
1336 | struct scatterlist *sg; | |
1337 | dma_addr_t slave_addr; | |
0a235657 | 1338 | int ret, tmp; |
e8689e63 | 1339 | |
e8689e63 | 1340 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", |
b7f69d9d | 1341 | __func__, sgl->length, plchan->name); |
e8689e63 | 1342 | |
c0428794 | 1343 | txd = pl08x_get_txd(plchan, flags); |
e8689e63 LW |
1344 | if (!txd) { |
1345 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1346 | return NULL; | |
1347 | } | |
1348 | ||
e8689e63 LW |
1349 | if (direction != plchan->runtime_direction) |
1350 | dev_err(&pl08x->adev->dev, "%s DMA setup does not match " | |
1351 | "the direction configured for the PrimeCell\n", | |
1352 | __func__); | |
1353 | ||
1354 | /* | |
1355 | * Set up addresses, the PrimeCell configured address | |
1356 | * will take precedence since this may configure the | |
1357 | * channel target address dynamically at runtime. | |
1358 | */ | |
1359 | txd->direction = direction; | |
c7da9a56 | 1360 | |
db8196df | 1361 | if (direction == DMA_MEM_TO_DEV) { |
121c8476 | 1362 | txd->cctl = plchan->dst_cctl; |
b7f69d9d | 1363 | slave_addr = plchan->dst_addr; |
db8196df | 1364 | } else if (direction == DMA_DEV_TO_MEM) { |
121c8476 | 1365 | txd->cctl = plchan->src_cctl; |
b7f69d9d | 1366 | slave_addr = plchan->src_addr; |
e8689e63 | 1367 | } else { |
b7f69d9d | 1368 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1369 | dev_err(&pl08x->adev->dev, |
1370 | "%s direction unsupported\n", __func__); | |
1371 | return NULL; | |
1372 | } | |
e8689e63 | 1373 | |
8c9f7aa3 | 1374 | if (plchan->device_fc) |
db8196df | 1375 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : |
0a235657 VK |
1376 | PL080_FLOW_PER2MEM_PER; |
1377 | else | |
db8196df | 1378 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER : |
0a235657 VK |
1379 | PL080_FLOW_PER2MEM; |
1380 | ||
1381 | txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1382 | ||
b7f69d9d VK |
1383 | for_each_sg(sgl, sg, sg_len, tmp) { |
1384 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); | |
1385 | if (!dsg) { | |
1386 | pl08x_free_txd(pl08x, txd); | |
1387 | dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n", | |
1388 | __func__); | |
1389 | return NULL; | |
1390 | } | |
1391 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1392 | ||
1393 | dsg->len = sg_dma_len(sg); | |
db8196df | 1394 | if (direction == DMA_MEM_TO_DEV) { |
b7f69d9d VK |
1395 | dsg->src_addr = sg_phys(sg); |
1396 | dsg->dst_addr = slave_addr; | |
1397 | } else { | |
1398 | dsg->src_addr = slave_addr; | |
1399 | dsg->dst_addr = sg_phys(sg); | |
1400 | } | |
1401 | } | |
1402 | ||
e8689e63 LW |
1403 | ret = pl08x_prep_channel_resources(plchan, txd); |
1404 | if (ret) | |
1405 | return NULL; | |
e8689e63 LW |
1406 | |
1407 | return &txd->tx; | |
1408 | } | |
1409 | ||
1410 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1411 | unsigned long arg) | |
1412 | { | |
1413 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1414 | struct pl08x_driver_data *pl08x = plchan->host; | |
1415 | unsigned long flags; | |
1416 | int ret = 0; | |
1417 | ||
1418 | /* Controls applicable to inactive channels */ | |
1419 | if (cmd == DMA_SLAVE_CONFIG) { | |
f0fd9446 RKAL |
1420 | return dma_set_runtime_config(chan, |
1421 | (struct dma_slave_config *)arg); | |
e8689e63 LW |
1422 | } |
1423 | ||
1424 | /* | |
1425 | * Anything succeeds on channels with no physical allocation and | |
1426 | * no queued transfers. | |
1427 | */ | |
1428 | spin_lock_irqsave(&plchan->lock, flags); | |
1429 | if (!plchan->phychan && !plchan->at) { | |
1430 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1431 | return 0; | |
1432 | } | |
1433 | ||
1434 | switch (cmd) { | |
1435 | case DMA_TERMINATE_ALL: | |
1436 | plchan->state = PL08X_CHAN_IDLE; | |
1437 | ||
1438 | if (plchan->phychan) { | |
fb526210 | 1439 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); |
e8689e63 LW |
1440 | |
1441 | /* | |
1442 | * Mark physical channel as free and free any slave | |
1443 | * signal | |
1444 | */ | |
8c8cc2b1 | 1445 | release_phy_channel(plchan); |
e8689e63 | 1446 | } |
e8689e63 LW |
1447 | /* Dequeue jobs and free LLIs */ |
1448 | if (plchan->at) { | |
1449 | pl08x_free_txd(pl08x, plchan->at); | |
1450 | plchan->at = NULL; | |
1451 | } | |
1452 | /* Dequeue jobs not yet fired as well */ | |
1453 | pl08x_free_txd_list(pl08x, plchan); | |
1454 | break; | |
1455 | case DMA_PAUSE: | |
1456 | pl08x_pause_phy_chan(plchan->phychan); | |
1457 | plchan->state = PL08X_CHAN_PAUSED; | |
1458 | break; | |
1459 | case DMA_RESUME: | |
1460 | pl08x_resume_phy_chan(plchan->phychan); | |
1461 | plchan->state = PL08X_CHAN_RUNNING; | |
1462 | break; | |
1463 | default: | |
1464 | /* Unknown command */ | |
1465 | ret = -ENXIO; | |
1466 | break; | |
1467 | } | |
1468 | ||
1469 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1470 | ||
1471 | return ret; | |
1472 | } | |
1473 | ||
1474 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1475 | { | |
7703eac9 | 1476 | struct pl08x_dma_chan *plchan; |
e8689e63 LW |
1477 | char *name = chan_id; |
1478 | ||
7703eac9 RKAL |
1479 | /* Reject channels for devices not bound to this driver */ |
1480 | if (chan->device->dev->driver != &pl08x_amba_driver.drv) | |
1481 | return false; | |
1482 | ||
1483 | plchan = to_pl08x_chan(chan); | |
1484 | ||
e8689e63 LW |
1485 | /* Check that the channel is not taken! */ |
1486 | if (!strcmp(plchan->name, name)) | |
1487 | return true; | |
1488 | ||
1489 | return false; | |
1490 | } | |
1491 | ||
1492 | /* | |
1493 | * Just check that the device is there and active | |
94ae8522 RKAL |
1494 | * TODO: turn this bit on/off depending on the number of physical channels |
1495 | * actually used, if it is zero... well shut it off. That will save some | |
1496 | * power. Cut the clock at the same time. | |
e8689e63 LW |
1497 | */ |
1498 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1499 | { | |
48a59ef3 | 1500 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
e8689e63 LW |
1501 | } |
1502 | ||
3d992e1a RKAL |
1503 | static void pl08x_unmap_buffers(struct pl08x_txd *txd) |
1504 | { | |
1505 | struct device *dev = txd->tx.chan->device->dev; | |
b7f69d9d | 1506 | struct pl08x_sg *dsg; |
3d992e1a RKAL |
1507 | |
1508 | if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
1509 | if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
b7f69d9d VK |
1510 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1511 | dma_unmap_single(dev, dsg->src_addr, dsg->len, | |
1512 | DMA_TO_DEVICE); | |
1513 | else { | |
1514 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1515 | dma_unmap_page(dev, dsg->src_addr, dsg->len, | |
1516 | DMA_TO_DEVICE); | |
1517 | } | |
3d992e1a RKAL |
1518 | } |
1519 | if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
1520 | if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
b7f69d9d VK |
1521 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1522 | dma_unmap_single(dev, dsg->dst_addr, dsg->len, | |
1523 | DMA_FROM_DEVICE); | |
3d992e1a | 1524 | else |
b7f69d9d VK |
1525 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1526 | dma_unmap_page(dev, dsg->dst_addr, dsg->len, | |
1527 | DMA_FROM_DEVICE); | |
3d992e1a RKAL |
1528 | } |
1529 | } | |
1530 | ||
e8689e63 LW |
1531 | static void pl08x_tasklet(unsigned long data) |
1532 | { | |
1533 | struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data; | |
e8689e63 | 1534 | struct pl08x_driver_data *pl08x = plchan->host; |
858c21c0 | 1535 | struct pl08x_txd *txd; |
bf072af4 | 1536 | unsigned long flags; |
e8689e63 | 1537 | |
bf072af4 | 1538 | spin_lock_irqsave(&plchan->lock, flags); |
e8689e63 | 1539 | |
858c21c0 RKAL |
1540 | txd = plchan->at; |
1541 | plchan->at = NULL; | |
e8689e63 | 1542 | |
858c21c0 | 1543 | if (txd) { |
94ae8522 | 1544 | /* Update last completed */ |
f7fbce07 | 1545 | dma_cookie_complete(&txd->tx); |
e8689e63 | 1546 | } |
8087aacd | 1547 | |
94ae8522 | 1548 | /* If a new descriptor is queued, set it up plchan->at is NULL here */ |
15c17232 | 1549 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 LW |
1550 | struct pl08x_txd *next; |
1551 | ||
15c17232 | 1552 | next = list_first_entry(&plchan->pend_list, |
e8689e63 LW |
1553 | struct pl08x_txd, |
1554 | node); | |
1555 | list_del(&next->node); | |
c885bee4 RKAL |
1556 | |
1557 | pl08x_start_txd(plchan, next); | |
8087aacd RKAL |
1558 | } else if (plchan->phychan_hold) { |
1559 | /* | |
1560 | * This channel is still in use - we have a new txd being | |
1561 | * prepared and will soon be queued. Don't give up the | |
1562 | * physical channel. | |
1563 | */ | |
e8689e63 LW |
1564 | } else { |
1565 | struct pl08x_dma_chan *waiting = NULL; | |
1566 | ||
1567 | /* | |
1568 | * No more jobs, so free up the physical channel | |
1569 | * Free any allocated signal on slave transfers too | |
1570 | */ | |
8c8cc2b1 | 1571 | release_phy_channel(plchan); |
e8689e63 LW |
1572 | plchan->state = PL08X_CHAN_IDLE; |
1573 | ||
1574 | /* | |
94ae8522 RKAL |
1575 | * And NOW before anyone else can grab that free:d up |
1576 | * physical channel, see if there is some memcpy pending | |
1577 | * that seriously needs to start because of being stacked | |
1578 | * up while we were choking the physical channels with data. | |
e8689e63 LW |
1579 | */ |
1580 | list_for_each_entry(waiting, &pl08x->memcpy.channels, | |
1581 | chan.device_node) { | |
3e27ee84 VK |
1582 | if (waiting->state == PL08X_CHAN_WAITING && |
1583 | waiting->waiting != NULL) { | |
e8689e63 LW |
1584 | int ret; |
1585 | ||
1586 | /* This should REALLY not fail now */ | |
1587 | ret = prep_phy_channel(waiting, | |
1588 | waiting->waiting); | |
1589 | BUG_ON(ret); | |
8087aacd | 1590 | waiting->phychan_hold--; |
e8689e63 LW |
1591 | waiting->state = PL08X_CHAN_RUNNING; |
1592 | waiting->waiting = NULL; | |
1593 | pl08x_issue_pending(&waiting->chan); | |
1594 | break; | |
1595 | } | |
1596 | } | |
1597 | } | |
1598 | ||
bf072af4 | 1599 | spin_unlock_irqrestore(&plchan->lock, flags); |
858c21c0 | 1600 | |
3d992e1a RKAL |
1601 | if (txd) { |
1602 | dma_async_tx_callback callback = txd->tx.callback; | |
1603 | void *callback_param = txd->tx.callback_param; | |
1604 | ||
1605 | /* Don't try to unmap buffers on slave channels */ | |
1606 | if (!plchan->slave) | |
1607 | pl08x_unmap_buffers(txd); | |
1608 | ||
1609 | /* Free the descriptor */ | |
1610 | spin_lock_irqsave(&plchan->lock, flags); | |
1611 | pl08x_free_txd(pl08x, txd); | |
1612 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1613 | ||
1614 | /* Callback to signal completion */ | |
1615 | if (callback) | |
1616 | callback(callback_param); | |
1617 | } | |
e8689e63 LW |
1618 | } |
1619 | ||
1620 | static irqreturn_t pl08x_irq(int irq, void *dev) | |
1621 | { | |
1622 | struct pl08x_driver_data *pl08x = dev; | |
28da2836 VK |
1623 | u32 mask = 0, err, tc, i; |
1624 | ||
1625 | /* check & clear - ERR & TC interrupts */ | |
1626 | err = readl(pl08x->base + PL080_ERR_STATUS); | |
1627 | if (err) { | |
1628 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", | |
1629 | __func__, err); | |
1630 | writel(err, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 | 1631 | } |
28da2836 VK |
1632 | tc = readl(pl08x->base + PL080_INT_STATUS); |
1633 | if (tc) | |
1634 | writel(tc, pl08x->base + PL080_TC_CLEAR); | |
1635 | ||
1636 | if (!err && !tc) | |
1637 | return IRQ_NONE; | |
1638 | ||
e8689e63 | 1639 | for (i = 0; i < pl08x->vd->channels; i++) { |
28da2836 | 1640 | if (((1 << i) & err) || ((1 << i) & tc)) { |
e8689e63 LW |
1641 | /* Locate physical channel */ |
1642 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1643 | struct pl08x_dma_chan *plchan = phychan->serving; | |
1644 | ||
28da2836 VK |
1645 | if (!plchan) { |
1646 | dev_err(&pl08x->adev->dev, | |
1647 | "%s Error TC interrupt on unused channel: 0x%08x\n", | |
1648 | __func__, i); | |
1649 | continue; | |
1650 | } | |
1651 | ||
e8689e63 LW |
1652 | /* Schedule tasklet on this channel */ |
1653 | tasklet_schedule(&plchan->tasklet); | |
e8689e63 LW |
1654 | mask |= (1 << i); |
1655 | } | |
1656 | } | |
e8689e63 LW |
1657 | |
1658 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1659 | } | |
1660 | ||
121c8476 RKAL |
1661 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
1662 | { | |
1663 | u32 cctl = pl08x_cctl(chan->cd->cctl); | |
1664 | ||
1665 | chan->slave = true; | |
1666 | chan->name = chan->cd->bus_id; | |
1667 | chan->src_addr = chan->cd->addr; | |
1668 | chan->dst_addr = chan->cd->addr; | |
1669 | chan->src_cctl = cctl | PL080_CONTROL_DST_INCR | | |
1670 | pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses); | |
1671 | chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR | | |
1672 | pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses); | |
1673 | } | |
1674 | ||
e8689e63 LW |
1675 | /* |
1676 | * Initialise the DMAC memcpy/slave channels. | |
1677 | * Make a local wrapper to hold required data | |
1678 | */ | |
1679 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 1680 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
1681 | { |
1682 | struct pl08x_dma_chan *chan; | |
1683 | int i; | |
1684 | ||
1685 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 1686 | |
e8689e63 LW |
1687 | /* |
1688 | * Register as many many memcpy as we have physical channels, | |
1689 | * we won't always be able to use all but the code will have | |
1690 | * to cope with that situation. | |
1691 | */ | |
1692 | for (i = 0; i < channels; i++) { | |
b201c111 | 1693 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
e8689e63 LW |
1694 | if (!chan) { |
1695 | dev_err(&pl08x->adev->dev, | |
1696 | "%s no memory for channel\n", __func__); | |
1697 | return -ENOMEM; | |
1698 | } | |
1699 | ||
1700 | chan->host = pl08x; | |
1701 | chan->state = PL08X_CHAN_IDLE; | |
1702 | ||
1703 | if (slave) { | |
e8689e63 | 1704 | chan->cd = &pl08x->pd->slave_channels[i]; |
121c8476 | 1705 | pl08x_dma_slave_init(chan); |
e8689e63 LW |
1706 | } else { |
1707 | chan->cd = &pl08x->pd->memcpy_channel; | |
1708 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1709 | if (!chan->name) { | |
1710 | kfree(chan); | |
1711 | return -ENOMEM; | |
1712 | } | |
1713 | } | |
b58b6b5b RKAL |
1714 | if (chan->cd->circular_buffer) { |
1715 | dev_err(&pl08x->adev->dev, | |
1716 | "channel %s: circular buffers not supported\n", | |
1717 | chan->name); | |
1718 | kfree(chan); | |
1719 | continue; | |
1720 | } | |
175a5e61 | 1721 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
1722 | "initialize virtual channel \"%s\"\n", |
1723 | chan->name); | |
1724 | ||
1725 | chan->chan.device = dmadev; | |
91aa5fad | 1726 | chan->chan.cookie = 0; |
4d4e58de | 1727 | chan->chan.completed_cookie = 0; |
e8689e63 LW |
1728 | |
1729 | spin_lock_init(&chan->lock); | |
15c17232 | 1730 | INIT_LIST_HEAD(&chan->pend_list); |
e8689e63 LW |
1731 | tasklet_init(&chan->tasklet, pl08x_tasklet, |
1732 | (unsigned long) chan); | |
1733 | ||
1734 | list_add_tail(&chan->chan.device_node, &dmadev->channels); | |
1735 | } | |
1736 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1737 | i, slave ? "slave" : "memcpy"); | |
1738 | return i; | |
1739 | } | |
1740 | ||
1741 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1742 | { | |
1743 | struct pl08x_dma_chan *chan = NULL; | |
1744 | struct pl08x_dma_chan *next; | |
1745 | ||
1746 | list_for_each_entry_safe(chan, | |
1747 | next, &dmadev->channels, chan.device_node) { | |
1748 | list_del(&chan->chan.device_node); | |
1749 | kfree(chan); | |
1750 | } | |
1751 | } | |
1752 | ||
1753 | #ifdef CONFIG_DEBUG_FS | |
1754 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1755 | { | |
1756 | switch (state) { | |
1757 | case PL08X_CHAN_IDLE: | |
1758 | return "idle"; | |
1759 | case PL08X_CHAN_RUNNING: | |
1760 | return "running"; | |
1761 | case PL08X_CHAN_PAUSED: | |
1762 | return "paused"; | |
1763 | case PL08X_CHAN_WAITING: | |
1764 | return "waiting"; | |
1765 | default: | |
1766 | break; | |
1767 | } | |
1768 | return "UNKNOWN STATE"; | |
1769 | } | |
1770 | ||
1771 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1772 | { | |
1773 | struct pl08x_driver_data *pl08x = s->private; | |
1774 | struct pl08x_dma_chan *chan; | |
1775 | struct pl08x_phy_chan *ch; | |
1776 | unsigned long flags; | |
1777 | int i; | |
1778 | ||
1779 | seq_printf(s, "PL08x physical channels:\n"); | |
1780 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1781 | seq_printf(s, "--------\t-----\n"); | |
1782 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1783 | struct pl08x_dma_chan *virt_chan; | |
1784 | ||
1785 | ch = &pl08x->phy_chans[i]; | |
1786 | ||
1787 | spin_lock_irqsave(&ch->lock, flags); | |
1788 | virt_chan = ch->serving; | |
1789 | ||
1790 | seq_printf(s, "%d\t\t%s\n", | |
1791 | ch->id, virt_chan ? virt_chan->name : "(none)"); | |
1792 | ||
1793 | spin_unlock_irqrestore(&ch->lock, flags); | |
1794 | } | |
1795 | ||
1796 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1797 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1798 | seq_printf(s, "--------\t------\n"); | |
1799 | list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) { | |
3e2a037c | 1800 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1801 | pl08x_state_str(chan->state)); |
1802 | } | |
1803 | ||
1804 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1805 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1806 | seq_printf(s, "--------\t------\n"); | |
1807 | list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) { | |
3e2a037c | 1808 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1809 | pl08x_state_str(chan->state)); |
1810 | } | |
1811 | ||
1812 | return 0; | |
1813 | } | |
1814 | ||
1815 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1816 | { | |
1817 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1818 | } | |
1819 | ||
1820 | static const struct file_operations pl08x_debugfs_operations = { | |
1821 | .open = pl08x_debugfs_open, | |
1822 | .read = seq_read, | |
1823 | .llseek = seq_lseek, | |
1824 | .release = single_release, | |
1825 | }; | |
1826 | ||
1827 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1828 | { | |
1829 | /* Expose a simple debugfs interface to view all clocks */ | |
3e27ee84 VK |
1830 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
1831 | S_IFREG | S_IRUGO, NULL, pl08x, | |
1832 | &pl08x_debugfs_operations); | |
e8689e63 LW |
1833 | } |
1834 | ||
1835 | #else | |
1836 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1837 | { | |
1838 | } | |
1839 | #endif | |
1840 | ||
aa25afad | 1841 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
1842 | { |
1843 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1844 | const struct vendor_data *vd = id->data; |
e8689e63 LW |
1845 | int ret = 0; |
1846 | int i; | |
1847 | ||
1848 | ret = amba_request_regions(adev, NULL); | |
1849 | if (ret) | |
1850 | return ret; | |
1851 | ||
1852 | /* Create the driver state holder */ | |
b201c111 | 1853 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
1854 | if (!pl08x) { |
1855 | ret = -ENOMEM; | |
1856 | goto out_no_pl08x; | |
1857 | } | |
1858 | ||
b7b6018b VK |
1859 | pm_runtime_set_active(&adev->dev); |
1860 | pm_runtime_enable(&adev->dev); | |
1861 | ||
e8689e63 LW |
1862 | /* Initialize memcpy engine */ |
1863 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1864 | pl08x->memcpy.dev = &adev->dev; | |
1865 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1866 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1867 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1868 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1869 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1870 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1871 | pl08x->memcpy.device_control = pl08x_control; | |
1872 | ||
1873 | /* Initialize slave engine */ | |
1874 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1875 | pl08x->slave.dev = &adev->dev; | |
1876 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1877 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1878 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1879 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1880 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1881 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1882 | pl08x->slave.device_control = pl08x_control; | |
1883 | ||
1884 | /* Get the platform data */ | |
1885 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1886 | if (!pl08x->pd) { | |
1887 | dev_err(&adev->dev, "no platform data supplied\n"); | |
1888 | goto out_no_platdata; | |
1889 | } | |
1890 | ||
1891 | /* Assign useful pointers to the driver state */ | |
1892 | pl08x->adev = adev; | |
1893 | pl08x->vd = vd; | |
1894 | ||
30749cb4 RKAL |
1895 | /* By default, AHB1 only. If dualmaster, from platform */ |
1896 | pl08x->lli_buses = PL08X_AHB1; | |
1897 | pl08x->mem_buses = PL08X_AHB1; | |
1898 | if (pl08x->vd->dualmaster) { | |
1899 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
1900 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
1901 | } | |
1902 | ||
e8689e63 LW |
1903 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
1904 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
1905 | PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0); | |
1906 | if (!pl08x->pool) { | |
1907 | ret = -ENOMEM; | |
1908 | goto out_no_lli_pool; | |
1909 | } | |
1910 | ||
1911 | spin_lock_init(&pl08x->lock); | |
1912 | ||
1913 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); | |
1914 | if (!pl08x->base) { | |
1915 | ret = -ENOMEM; | |
1916 | goto out_no_ioremap; | |
1917 | } | |
1918 | ||
1919 | /* Turn on the PL08x */ | |
1920 | pl08x_ensure_on(pl08x); | |
1921 | ||
94ae8522 | 1922 | /* Attach the interrupt handler */ |
e8689e63 LW |
1923 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
1924 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
1925 | ||
1926 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 1927 | DRIVER_NAME, pl08x); |
e8689e63 LW |
1928 | if (ret) { |
1929 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
1930 | __func__, adev->irq[0]); | |
1931 | goto out_no_irq; | |
1932 | } | |
1933 | ||
1934 | /* Initialize physical channels */ | |
b201c111 | 1935 | pl08x->phy_chans = kmalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
1936 | GFP_KERNEL); |
1937 | if (!pl08x->phy_chans) { | |
1938 | dev_err(&adev->dev, "%s failed to allocate " | |
1939 | "physical channel holders\n", | |
1940 | __func__); | |
1941 | goto out_no_phychans; | |
1942 | } | |
1943 | ||
1944 | for (i = 0; i < vd->channels; i++) { | |
1945 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
1946 | ||
1947 | ch->id = i; | |
1948 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
1949 | spin_lock_init(&ch->lock); | |
1950 | ch->serving = NULL; | |
1951 | ch->signal = -1; | |
175a5e61 VK |
1952 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
1953 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
1954 | } |
1955 | ||
1956 | /* Register as many memcpy channels as there are physical channels */ | |
1957 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
1958 | pl08x->vd->channels, false); | |
1959 | if (ret <= 0) { | |
1960 | dev_warn(&pl08x->adev->dev, | |
1961 | "%s failed to enumerate memcpy channels - %d\n", | |
1962 | __func__, ret); | |
1963 | goto out_no_memcpy; | |
1964 | } | |
1965 | pl08x->memcpy.chancnt = ret; | |
1966 | ||
1967 | /* Register slave channels */ | |
1968 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
3e27ee84 | 1969 | pl08x->pd->num_slave_channels, true); |
e8689e63 LW |
1970 | if (ret <= 0) { |
1971 | dev_warn(&pl08x->adev->dev, | |
1972 | "%s failed to enumerate slave channels - %d\n", | |
1973 | __func__, ret); | |
1974 | goto out_no_slave; | |
1975 | } | |
1976 | pl08x->slave.chancnt = ret; | |
1977 | ||
1978 | ret = dma_async_device_register(&pl08x->memcpy); | |
1979 | if (ret) { | |
1980 | dev_warn(&pl08x->adev->dev, | |
1981 | "%s failed to register memcpy as an async device - %d\n", | |
1982 | __func__, ret); | |
1983 | goto out_no_memcpy_reg; | |
1984 | } | |
1985 | ||
1986 | ret = dma_async_device_register(&pl08x->slave); | |
1987 | if (ret) { | |
1988 | dev_warn(&pl08x->adev->dev, | |
1989 | "%s failed to register slave as an async device - %d\n", | |
1990 | __func__, ret); | |
1991 | goto out_no_slave_reg; | |
1992 | } | |
1993 | ||
1994 | amba_set_drvdata(adev, pl08x); | |
1995 | init_pl08x_debugfs(pl08x); | |
b05cd8f4 RKAL |
1996 | dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n", |
1997 | amba_part(adev), amba_rev(adev), | |
1998 | (unsigned long long)adev->res.start, adev->irq[0]); | |
b7b6018b VK |
1999 | |
2000 | pm_runtime_put(&adev->dev); | |
e8689e63 LW |
2001 | return 0; |
2002 | ||
2003 | out_no_slave_reg: | |
2004 | dma_async_device_unregister(&pl08x->memcpy); | |
2005 | out_no_memcpy_reg: | |
2006 | pl08x_free_virtual_channels(&pl08x->slave); | |
2007 | out_no_slave: | |
2008 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2009 | out_no_memcpy: | |
2010 | kfree(pl08x->phy_chans); | |
2011 | out_no_phychans: | |
2012 | free_irq(adev->irq[0], pl08x); | |
2013 | out_no_irq: | |
2014 | iounmap(pl08x->base); | |
2015 | out_no_ioremap: | |
2016 | dma_pool_destroy(pl08x->pool); | |
2017 | out_no_lli_pool: | |
2018 | out_no_platdata: | |
b7b6018b VK |
2019 | pm_runtime_put(&adev->dev); |
2020 | pm_runtime_disable(&adev->dev); | |
2021 | ||
e8689e63 LW |
2022 | kfree(pl08x); |
2023 | out_no_pl08x: | |
2024 | amba_release_regions(adev); | |
2025 | return ret; | |
2026 | } | |
2027 | ||
2028 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2029 | static struct vendor_data vendor_pl080 = { | |
e8689e63 LW |
2030 | .channels = 8, |
2031 | .dualmaster = true, | |
2032 | }; | |
2033 | ||
2034 | static struct vendor_data vendor_pl081 = { | |
e8689e63 LW |
2035 | .channels = 2, |
2036 | .dualmaster = false, | |
2037 | }; | |
2038 | ||
2039 | static struct amba_id pl08x_ids[] = { | |
2040 | /* PL080 */ | |
2041 | { | |
2042 | .id = 0x00041080, | |
2043 | .mask = 0x000fffff, | |
2044 | .data = &vendor_pl080, | |
2045 | }, | |
2046 | /* PL081 */ | |
2047 | { | |
2048 | .id = 0x00041081, | |
2049 | .mask = 0x000fffff, | |
2050 | .data = &vendor_pl081, | |
2051 | }, | |
2052 | /* Nomadik 8815 PL080 variant */ | |
2053 | { | |
2054 | .id = 0x00280880, | |
2055 | .mask = 0x00ffffff, | |
2056 | .data = &vendor_pl080, | |
2057 | }, | |
2058 | { 0, 0 }, | |
2059 | }; | |
2060 | ||
037566df DM |
2061 | MODULE_DEVICE_TABLE(amba, pl08x_ids); |
2062 | ||
e8689e63 LW |
2063 | static struct amba_driver pl08x_amba_driver = { |
2064 | .drv.name = DRIVER_NAME, | |
2065 | .id_table = pl08x_ids, | |
2066 | .probe = pl08x_probe, | |
2067 | }; | |
2068 | ||
2069 | static int __init pl08x_init(void) | |
2070 | { | |
2071 | int retval; | |
2072 | retval = amba_driver_register(&pl08x_amba_driver); | |
2073 | if (retval) | |
2074 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2075 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2076 | retval); |
2077 | return retval; | |
2078 | } | |
2079 | subsys_initcall(pl08x_init); |