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Commit | Line | Data |
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dc78baa2 NF |
1 | /* |
2 | * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) | |
3 | * | |
4 | * Copyright (C) 2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * | |
9102d871 NF |
12 | * This supports the Atmel AHB DMA Controller found in several Atmel SoCs. |
13 | * The only Atmel DMA Controller that is not covered by this driver is the one | |
14 | * found on AT91SAM9263. | |
dc78baa2 NF |
15 | */ |
16 | ||
62971b29 | 17 | #include <dt-bindings/dma/at91.h> |
dc78baa2 NF |
18 | #include <linux/clk.h> |
19 | #include <linux/dmaengine.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
c5115953 NF |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
bbe89c8e | 28 | #include <linux/of_dma.h> |
dc78baa2 NF |
29 | |
30 | #include "at_hdmac_regs.h" | |
d2ebfb33 | 31 | #include "dmaengine.h" |
dc78baa2 NF |
32 | |
33 | /* | |
34 | * Glossary | |
35 | * -------- | |
36 | * | |
37 | * at_hdmac : Name of the ATmel AHB DMA Controller | |
38 | * at_dma_ / atdma : ATmel DMA controller entity related | |
39 | * atc_ / atchan : ATmel DMA Channel entity related | |
40 | */ | |
41 | ||
42 | #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) | |
ae14d4b5 NF |
43 | #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ |
44 | |ATC_DIF(AT_DMA_MEM_IF)) | |
dc78baa2 NF |
45 | |
46 | /* | |
47 | * Initial number of descriptors to allocate for each channel. This could | |
48 | * be increased during dma usage. | |
49 | */ | |
50 | static unsigned int init_nr_desc_per_channel = 64; | |
51 | module_param(init_nr_desc_per_channel, uint, 0644); | |
52 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
53 | "initial descriptors per channel (default: 64)"); | |
54 | ||
55 | ||
56 | /* prototypes */ | |
57 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); | |
d48de6f1 | 58 | static void atc_issue_pending(struct dma_chan *chan); |
dc78baa2 NF |
59 | |
60 | ||
61 | /*----------------------------------------------------------------------*/ | |
62 | ||
63 | static struct at_desc *atc_first_active(struct at_dma_chan *atchan) | |
64 | { | |
65 | return list_first_entry(&atchan->active_list, | |
66 | struct at_desc, desc_node); | |
67 | } | |
68 | ||
69 | static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) | |
70 | { | |
71 | return list_first_entry(&atchan->queue, | |
72 | struct at_desc, desc_node); | |
73 | } | |
74 | ||
75 | /** | |
421f91d2 | 76 | * atc_alloc_descriptor - allocate and return an initialized descriptor |
dc78baa2 NF |
77 | * @chan: the channel to allocate descriptors for |
78 | * @gfp_flags: GFP allocation flags | |
79 | * | |
80 | * Note: The ack-bit is positioned in the descriptor flag at creation time | |
81 | * to make initial allocation more convenient. This bit will be cleared | |
82 | * and control will be given to client at usage time (during | |
83 | * preparation functions). | |
84 | */ | |
85 | static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, | |
86 | gfp_t gfp_flags) | |
87 | { | |
88 | struct at_desc *desc = NULL; | |
89 | struct at_dma *atdma = to_at_dma(chan->device); | |
90 | dma_addr_t phys; | |
91 | ||
92 | desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); | |
93 | if (desc) { | |
94 | memset(desc, 0, sizeof(struct at_desc)); | |
285a3c71 | 95 | INIT_LIST_HEAD(&desc->tx_list); |
dc78baa2 NF |
96 | dma_async_tx_descriptor_init(&desc->txd, chan); |
97 | /* txd.flags will be overwritten in prep functions */ | |
98 | desc->txd.flags = DMA_CTRL_ACK; | |
99 | desc->txd.tx_submit = atc_tx_submit; | |
100 | desc->txd.phys = phys; | |
101 | } | |
102 | ||
103 | return desc; | |
104 | } | |
105 | ||
106 | /** | |
af901ca1 | 107 | * atc_desc_get - get an unused descriptor from free_list |
dc78baa2 NF |
108 | * @atchan: channel we want a new descriptor for |
109 | */ | |
110 | static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) | |
111 | { | |
112 | struct at_desc *desc, *_desc; | |
113 | struct at_desc *ret = NULL; | |
d8cb04b0 | 114 | unsigned long flags; |
dc78baa2 NF |
115 | unsigned int i = 0; |
116 | LIST_HEAD(tmp_list); | |
117 | ||
d8cb04b0 | 118 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
119 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { |
120 | i++; | |
121 | if (async_tx_test_ack(&desc->txd)) { | |
122 | list_del(&desc->desc_node); | |
123 | ret = desc; | |
124 | break; | |
125 | } | |
126 | dev_dbg(chan2dev(&atchan->chan_common), | |
127 | "desc %p not ACKed\n", desc); | |
128 | } | |
d8cb04b0 | 129 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
130 | dev_vdbg(chan2dev(&atchan->chan_common), |
131 | "scanned %u descriptors on freelist\n", i); | |
132 | ||
133 | /* no more descriptor available in initial pool: create one more */ | |
134 | if (!ret) { | |
135 | ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); | |
136 | if (ret) { | |
d8cb04b0 | 137 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 138 | atchan->descs_allocated++; |
d8cb04b0 | 139 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
140 | } else { |
141 | dev_err(chan2dev(&atchan->chan_common), | |
142 | "not enough descriptors available\n"); | |
143 | } | |
144 | } | |
145 | ||
146 | return ret; | |
147 | } | |
148 | ||
149 | /** | |
150 | * atc_desc_put - move a descriptor, including any children, to the free list | |
151 | * @atchan: channel we work on | |
152 | * @desc: descriptor, at the head of a chain, to move to free list | |
153 | */ | |
154 | static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) | |
155 | { | |
156 | if (desc) { | |
157 | struct at_desc *child; | |
d8cb04b0 | 158 | unsigned long flags; |
dc78baa2 | 159 | |
d8cb04b0 | 160 | spin_lock_irqsave(&atchan->lock, flags); |
285a3c71 | 161 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
162 | dev_vdbg(chan2dev(&atchan->chan_common), |
163 | "moving child desc %p to freelist\n", | |
164 | child); | |
285a3c71 | 165 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
166 | dev_vdbg(chan2dev(&atchan->chan_common), |
167 | "moving desc %p to freelist\n", desc); | |
168 | list_add(&desc->desc_node, &atchan->free_list); | |
d8cb04b0 | 169 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
170 | } |
171 | } | |
172 | ||
53830cc7 | 173 | /** |
d73111c6 MI |
174 | * atc_desc_chain - build chain adding a descriptor |
175 | * @first: address of first descriptor of the chain | |
176 | * @prev: address of previous descriptor of the chain | |
53830cc7 NF |
177 | * @desc: descriptor to queue |
178 | * | |
179 | * Called from prep_* functions | |
180 | */ | |
181 | static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, | |
182 | struct at_desc *desc) | |
183 | { | |
184 | if (!(*first)) { | |
185 | *first = desc; | |
186 | } else { | |
187 | /* inform the HW lli about chaining */ | |
188 | (*prev)->lli.dscr = desc->txd.phys; | |
189 | /* insert the link descriptor to the LD ring */ | |
190 | list_add_tail(&desc->desc_node, | |
191 | &(*first)->tx_list); | |
192 | } | |
193 | *prev = desc; | |
194 | } | |
195 | ||
dc78baa2 NF |
196 | /** |
197 | * atc_dostart - starts the DMA engine for real | |
198 | * @atchan: the channel we want to start | |
199 | * @first: first descriptor in the list we want to begin with | |
200 | * | |
201 | * Called with atchan->lock held and bh disabled | |
202 | */ | |
203 | static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) | |
204 | { | |
205 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
206 | ||
207 | /* ASSERT: channel is idle */ | |
208 | if (atc_chan_is_enabled(atchan)) { | |
209 | dev_err(chan2dev(&atchan->chan_common), | |
210 | "BUG: Attempted to start non-idle channel\n"); | |
211 | dev_err(chan2dev(&atchan->chan_common), | |
212 | " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", | |
213 | channel_readl(atchan, SADDR), | |
214 | channel_readl(atchan, DADDR), | |
215 | channel_readl(atchan, CTRLA), | |
216 | channel_readl(atchan, CTRLB), | |
217 | channel_readl(atchan, DSCR)); | |
218 | ||
219 | /* The tasklet will hopefully advance the queue... */ | |
220 | return; | |
221 | } | |
222 | ||
223 | vdbg_dump_regs(atchan); | |
224 | ||
dc78baa2 NF |
225 | channel_writel(atchan, SADDR, 0); |
226 | channel_writel(atchan, DADDR, 0); | |
227 | channel_writel(atchan, CTRLA, 0); | |
228 | channel_writel(atchan, CTRLB, 0); | |
229 | channel_writel(atchan, DSCR, first->txd.phys); | |
230 | dma_writel(atdma, CHER, atchan->mask); | |
231 | ||
232 | vdbg_dump_regs(atchan); | |
233 | } | |
234 | ||
d48de6f1 ES |
235 | /* |
236 | * atc_get_current_descriptors - | |
237 | * locate the descriptor which equal to physical address in DSCR | |
238 | * @atchan: the channel we want to start | |
239 | * @dscr_addr: physical descriptor address in DSCR | |
240 | */ | |
241 | static struct at_desc *atc_get_current_descriptors(struct at_dma_chan *atchan, | |
242 | u32 dscr_addr) | |
243 | { | |
244 | struct at_desc *desc, *_desc, *child, *desc_cur = NULL; | |
245 | ||
246 | list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { | |
247 | if (desc->lli.dscr == dscr_addr) { | |
248 | desc_cur = desc; | |
249 | break; | |
250 | } | |
251 | ||
252 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
253 | if (child->lli.dscr == dscr_addr) { | |
254 | desc_cur = child; | |
255 | break; | |
256 | } | |
257 | } | |
258 | } | |
259 | ||
260 | return desc_cur; | |
261 | } | |
262 | ||
263 | /* | |
264 | * atc_get_bytes_left - | |
265 | * Get the number of bytes residue in dma buffer, | |
266 | * @chan: the channel we want to start | |
267 | */ | |
268 | static int atc_get_bytes_left(struct dma_chan *chan) | |
269 | { | |
270 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
271 | struct at_dma *atdma = to_at_dma(chan->device); | |
272 | int chan_id = atchan->chan_common.chan_id; | |
273 | struct at_desc *desc_first = atc_first_active(atchan); | |
274 | struct at_desc *desc_cur; | |
275 | int ret = 0, count = 0; | |
276 | ||
277 | /* | |
278 | * Initialize necessary values in the first time. | |
279 | * remain_desc record remain desc length. | |
280 | */ | |
281 | if (atchan->remain_desc == 0) | |
282 | /* First descriptor embedds the transaction length */ | |
283 | atchan->remain_desc = desc_first->len; | |
284 | ||
285 | /* | |
286 | * This happens when current descriptor transfer complete. | |
287 | * The residual buffer size should reduce current descriptor length. | |
288 | */ | |
289 | if (unlikely(test_bit(ATC_IS_BTC, &atchan->status))) { | |
290 | clear_bit(ATC_IS_BTC, &atchan->status); | |
291 | desc_cur = atc_get_current_descriptors(atchan, | |
292 | channel_readl(atchan, DSCR)); | |
293 | if (!desc_cur) { | |
294 | ret = -EINVAL; | |
295 | goto out; | |
296 | } | |
297 | atchan->remain_desc -= (desc_cur->lli.ctrla & ATC_BTSIZE_MAX) | |
298 | << (desc_first->tx_width); | |
299 | if (atchan->remain_desc < 0) { | |
300 | ret = -EINVAL; | |
301 | goto out; | |
c3dbc60c | 302 | } else { |
d48de6f1 | 303 | ret = atchan->remain_desc; |
c3dbc60c | 304 | } |
d48de6f1 ES |
305 | } else { |
306 | /* | |
307 | * Get residual bytes when current | |
308 | * descriptor transfer in progress. | |
309 | */ | |
310 | count = (channel_readl(atchan, CTRLA) & ATC_BTSIZE_MAX) | |
311 | << (desc_first->tx_width); | |
312 | ret = atchan->remain_desc - count; | |
313 | } | |
314 | /* | |
315 | * Check fifo empty. | |
316 | */ | |
317 | if (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id))) | |
318 | atc_issue_pending(chan); | |
319 | ||
320 | out: | |
321 | return ret; | |
322 | } | |
323 | ||
dc78baa2 NF |
324 | /** |
325 | * atc_chain_complete - finish work for one transaction chain | |
326 | * @atchan: channel we work on | |
327 | * @desc: descriptor at the head of the chain we want do complete | |
328 | * | |
329 | * Called with atchan->lock held and bh disabled */ | |
330 | static void | |
331 | atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) | |
332 | { | |
dc78baa2 NF |
333 | struct dma_async_tx_descriptor *txd = &desc->txd; |
334 | ||
335 | dev_vdbg(chan2dev(&atchan->chan_common), | |
336 | "descriptor %u complete\n", txd->cookie); | |
337 | ||
d4116052 VK |
338 | /* mark the descriptor as complete for non cyclic cases only */ |
339 | if (!atc_chan_is_cyclic(atchan)) | |
340 | dma_cookie_complete(txd); | |
dc78baa2 NF |
341 | |
342 | /* move children to free_list */ | |
285a3c71 | 343 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
344 | /* move myself to free_list */ |
345 | list_move(&desc->desc_node, &atchan->free_list); | |
346 | ||
ebcf9b80 | 347 | /* unmap dma addresses (not on slave channels) */ |
657a77fa AN |
348 | if (!atchan->chan_common.private) { |
349 | struct device *parent = chan2parent(&atchan->chan_common); | |
350 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
351 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
352 | dma_unmap_single(parent, | |
353 | desc->lli.daddr, | |
354 | desc->len, DMA_FROM_DEVICE); | |
355 | else | |
356 | dma_unmap_page(parent, | |
357 | desc->lli.daddr, | |
358 | desc->len, DMA_FROM_DEVICE); | |
359 | } | |
360 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
361 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
362 | dma_unmap_single(parent, | |
363 | desc->lli.saddr, | |
364 | desc->len, DMA_TO_DEVICE); | |
365 | else | |
366 | dma_unmap_page(parent, | |
367 | desc->lli.saddr, | |
368 | desc->len, DMA_TO_DEVICE); | |
369 | } | |
dc78baa2 NF |
370 | } |
371 | ||
53830cc7 NF |
372 | /* for cyclic transfers, |
373 | * no need to replay callback function while stopping */ | |
3c477482 | 374 | if (!atc_chan_is_cyclic(atchan)) { |
53830cc7 NF |
375 | dma_async_tx_callback callback = txd->callback; |
376 | void *param = txd->callback_param; | |
377 | ||
378 | /* | |
379 | * The API requires that no submissions are done from a | |
380 | * callback, so we don't need to drop the lock here | |
381 | */ | |
382 | if (callback) | |
383 | callback(param); | |
384 | } | |
dc78baa2 NF |
385 | |
386 | dma_run_dependencies(txd); | |
387 | } | |
388 | ||
389 | /** | |
390 | * atc_complete_all - finish work for all transactions | |
391 | * @atchan: channel to complete transactions for | |
392 | * | |
393 | * Eventually submit queued descriptors if any | |
394 | * | |
395 | * Assume channel is idle while calling this function | |
396 | * Called with atchan->lock held and bh disabled | |
397 | */ | |
398 | static void atc_complete_all(struct at_dma_chan *atchan) | |
399 | { | |
400 | struct at_desc *desc, *_desc; | |
401 | LIST_HEAD(list); | |
402 | ||
403 | dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); | |
404 | ||
dc78baa2 NF |
405 | /* |
406 | * Submit queued descriptors ASAP, i.e. before we go through | |
407 | * the completed ones. | |
408 | */ | |
409 | if (!list_empty(&atchan->queue)) | |
410 | atc_dostart(atchan, atc_first_queued(atchan)); | |
411 | /* empty active_list now it is completed */ | |
412 | list_splice_init(&atchan->active_list, &list); | |
413 | /* empty queue list by moving descriptors (if any) to active_list */ | |
414 | list_splice_init(&atchan->queue, &atchan->active_list); | |
415 | ||
416 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
417 | atc_chain_complete(atchan, desc); | |
418 | } | |
419 | ||
dc78baa2 NF |
420 | /** |
421 | * atc_advance_work - at the end of a transaction, move forward | |
422 | * @atchan: channel where the transaction ended | |
423 | * | |
424 | * Called with atchan->lock held and bh disabled | |
425 | */ | |
426 | static void atc_advance_work(struct at_dma_chan *atchan) | |
427 | { | |
428 | dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); | |
429 | ||
d202f051 LD |
430 | if (atc_chan_is_enabled(atchan)) |
431 | return; | |
432 | ||
dc78baa2 NF |
433 | if (list_empty(&atchan->active_list) || |
434 | list_is_singular(&atchan->active_list)) { | |
435 | atc_complete_all(atchan); | |
436 | } else { | |
437 | atc_chain_complete(atchan, atc_first_active(atchan)); | |
438 | /* advance work */ | |
439 | atc_dostart(atchan, atc_first_active(atchan)); | |
440 | } | |
441 | } | |
442 | ||
443 | ||
444 | /** | |
445 | * atc_handle_error - handle errors reported by DMA controller | |
446 | * @atchan: channel where error occurs | |
447 | * | |
448 | * Called with atchan->lock held and bh disabled | |
449 | */ | |
450 | static void atc_handle_error(struct at_dma_chan *atchan) | |
451 | { | |
452 | struct at_desc *bad_desc; | |
453 | struct at_desc *child; | |
454 | ||
455 | /* | |
456 | * The descriptor currently at the head of the active list is | |
457 | * broked. Since we don't have any way to report errors, we'll | |
458 | * just have to scream loudly and try to carry on. | |
459 | */ | |
460 | bad_desc = atc_first_active(atchan); | |
461 | list_del_init(&bad_desc->desc_node); | |
462 | ||
463 | /* As we are stopped, take advantage to push queued descriptors | |
464 | * in active_list */ | |
465 | list_splice_init(&atchan->queue, atchan->active_list.prev); | |
466 | ||
467 | /* Try to restart the controller */ | |
468 | if (!list_empty(&atchan->active_list)) | |
469 | atc_dostart(atchan, atc_first_active(atchan)); | |
470 | ||
471 | /* | |
472 | * KERN_CRITICAL may seem harsh, but since this only happens | |
473 | * when someone submits a bad physical address in a | |
474 | * descriptor, we should consider ourselves lucky that the | |
475 | * controller flagged an error instead of scribbling over | |
476 | * random memory locations. | |
477 | */ | |
478 | dev_crit(chan2dev(&atchan->chan_common), | |
479 | "Bad descriptor submitted for DMA!\n"); | |
480 | dev_crit(chan2dev(&atchan->chan_common), | |
481 | " cookie: %d\n", bad_desc->txd.cookie); | |
482 | atc_dump_lli(atchan, &bad_desc->lli); | |
285a3c71 | 483 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
dc78baa2 NF |
484 | atc_dump_lli(atchan, &child->lli); |
485 | ||
486 | /* Pretend the descriptor completed successfully */ | |
487 | atc_chain_complete(atchan, bad_desc); | |
488 | } | |
489 | ||
53830cc7 NF |
490 | /** |
491 | * atc_handle_cyclic - at the end of a period, run callback function | |
492 | * @atchan: channel used for cyclic operations | |
493 | * | |
494 | * Called with atchan->lock held and bh disabled | |
495 | */ | |
496 | static void atc_handle_cyclic(struct at_dma_chan *atchan) | |
497 | { | |
498 | struct at_desc *first = atc_first_active(atchan); | |
499 | struct dma_async_tx_descriptor *txd = &first->txd; | |
500 | dma_async_tx_callback callback = txd->callback; | |
501 | void *param = txd->callback_param; | |
502 | ||
503 | dev_vdbg(chan2dev(&atchan->chan_common), | |
504 | "new cyclic period llp 0x%08x\n", | |
505 | channel_readl(atchan, DSCR)); | |
506 | ||
507 | if (callback) | |
508 | callback(param); | |
509 | } | |
dc78baa2 NF |
510 | |
511 | /*-- IRQ & Tasklet ---------------------------------------------------*/ | |
512 | ||
513 | static void atc_tasklet(unsigned long data) | |
514 | { | |
515 | struct at_dma_chan *atchan = (struct at_dma_chan *)data; | |
d8cb04b0 | 516 | unsigned long flags; |
dc78baa2 | 517 | |
d8cb04b0 | 518 | spin_lock_irqsave(&atchan->lock, flags); |
53830cc7 | 519 | if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) |
dc78baa2 | 520 | atc_handle_error(atchan); |
3c477482 | 521 | else if (atc_chan_is_cyclic(atchan)) |
53830cc7 | 522 | atc_handle_cyclic(atchan); |
dc78baa2 NF |
523 | else |
524 | atc_advance_work(atchan); | |
525 | ||
d8cb04b0 | 526 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
527 | } |
528 | ||
529 | static irqreturn_t at_dma_interrupt(int irq, void *dev_id) | |
530 | { | |
531 | struct at_dma *atdma = (struct at_dma *)dev_id; | |
532 | struct at_dma_chan *atchan; | |
533 | int i; | |
534 | u32 status, pending, imr; | |
535 | int ret = IRQ_NONE; | |
536 | ||
537 | do { | |
538 | imr = dma_readl(atdma, EBCIMR); | |
539 | status = dma_readl(atdma, EBCISR); | |
540 | pending = status & imr; | |
541 | ||
542 | if (!pending) | |
543 | break; | |
544 | ||
545 | dev_vdbg(atdma->dma_common.dev, | |
546 | "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", | |
547 | status, imr, pending); | |
548 | ||
549 | for (i = 0; i < atdma->dma_common.chancnt; i++) { | |
550 | atchan = &atdma->chan[i]; | |
9b3aa589 | 551 | if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { |
dc78baa2 NF |
552 | if (pending & AT_DMA_ERR(i)) { |
553 | /* Disable channel on AHB error */ | |
23b5e3ad NF |
554 | dma_writel(atdma, CHDR, |
555 | AT_DMA_RES(i) | atchan->mask); | |
dc78baa2 | 556 | /* Give information to tasklet */ |
53830cc7 | 557 | set_bit(ATC_IS_ERROR, &atchan->status); |
dc78baa2 | 558 | } |
d48de6f1 ES |
559 | if (pending & AT_DMA_BTC(i)) |
560 | set_bit(ATC_IS_BTC, &atchan->status); | |
dc78baa2 NF |
561 | tasklet_schedule(&atchan->tasklet); |
562 | ret = IRQ_HANDLED; | |
563 | } | |
564 | } | |
565 | ||
566 | } while (pending); | |
567 | ||
568 | return ret; | |
569 | } | |
570 | ||
571 | ||
572 | /*-- DMA Engine API --------------------------------------------------*/ | |
573 | ||
574 | /** | |
575 | * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine | |
576 | * @desc: descriptor at the head of the transaction chain | |
577 | * | |
578 | * Queue chain if DMA engine is working already | |
579 | * | |
580 | * Cookie increment and adding to active_list or queue must be atomic | |
581 | */ | |
582 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) | |
583 | { | |
584 | struct at_desc *desc = txd_to_at_desc(tx); | |
585 | struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); | |
586 | dma_cookie_t cookie; | |
d8cb04b0 | 587 | unsigned long flags; |
dc78baa2 | 588 | |
d8cb04b0 | 589 | spin_lock_irqsave(&atchan->lock, flags); |
884485e1 | 590 | cookie = dma_cookie_assign(tx); |
dc78baa2 NF |
591 | |
592 | if (list_empty(&atchan->active_list)) { | |
593 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", | |
594 | desc->txd.cookie); | |
595 | atc_dostart(atchan, desc); | |
596 | list_add_tail(&desc->desc_node, &atchan->active_list); | |
597 | } else { | |
598 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", | |
599 | desc->txd.cookie); | |
600 | list_add_tail(&desc->desc_node, &atchan->queue); | |
601 | } | |
602 | ||
d8cb04b0 | 603 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
604 | |
605 | return cookie; | |
606 | } | |
607 | ||
608 | /** | |
609 | * atc_prep_dma_memcpy - prepare a memcpy operation | |
610 | * @chan: the channel to prepare operation on | |
611 | * @dest: operation virtual destination address | |
612 | * @src: operation virtual source address | |
613 | * @len: operation length | |
614 | * @flags: tx descriptor status flags | |
615 | */ | |
616 | static struct dma_async_tx_descriptor * | |
617 | atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
618 | size_t len, unsigned long flags) | |
619 | { | |
620 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
621 | struct at_desc *desc = NULL; | |
622 | struct at_desc *first = NULL; | |
623 | struct at_desc *prev = NULL; | |
624 | size_t xfer_count; | |
625 | size_t offset; | |
626 | unsigned int src_width; | |
627 | unsigned int dst_width; | |
628 | u32 ctrla; | |
629 | u32 ctrlb; | |
630 | ||
631 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", | |
632 | dest, src, len, flags); | |
633 | ||
634 | if (unlikely(!len)) { | |
635 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
636 | return NULL; | |
637 | } | |
638 | ||
9b3aa589 | 639 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
dc78baa2 NF |
640 | | ATC_SRC_ADDR_MODE_INCR |
641 | | ATC_DST_ADDR_MODE_INCR | |
642 | | ATC_FC_MEM2MEM; | |
643 | ||
644 | /* | |
645 | * We can be a lot more clever here, but this should take care | |
646 | * of the most common optimization. | |
647 | */ | |
648 | if (!((src | dest | len) & 3)) { | |
b409ebfb | 649 | ctrla = ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; |
dc78baa2 NF |
650 | src_width = dst_width = 2; |
651 | } else if (!((src | dest | len) & 1)) { | |
b409ebfb | 652 | ctrla = ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; |
dc78baa2 NF |
653 | src_width = dst_width = 1; |
654 | } else { | |
b409ebfb | 655 | ctrla = ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; |
dc78baa2 NF |
656 | src_width = dst_width = 0; |
657 | } | |
658 | ||
659 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
660 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
661 | ATC_BTSIZE_MAX); | |
662 | ||
663 | desc = atc_desc_get(atchan); | |
664 | if (!desc) | |
665 | goto err_desc_get; | |
666 | ||
667 | desc->lli.saddr = src + offset; | |
668 | desc->lli.daddr = dest + offset; | |
669 | desc->lli.ctrla = ctrla | xfer_count; | |
670 | desc->lli.ctrlb = ctrlb; | |
671 | ||
672 | desc->txd.cookie = 0; | |
dc78baa2 | 673 | |
e257e156 | 674 | atc_desc_chain(&first, &prev, desc); |
dc78baa2 NF |
675 | } |
676 | ||
677 | /* First descriptor of the chain embedds additional information */ | |
678 | first->txd.cookie = -EBUSY; | |
679 | first->len = len; | |
d088c33b | 680 | first->tx_width = src_width; |
dc78baa2 NF |
681 | |
682 | /* set end-of-link to the last link descriptor of list*/ | |
683 | set_desc_eol(desc); | |
684 | ||
568f7f0c | 685 | first->txd.flags = flags; /* client is in control of this ack */ |
dc78baa2 NF |
686 | |
687 | return &first->txd; | |
688 | ||
689 | err_desc_get: | |
690 | atc_desc_put(atchan, first); | |
691 | return NULL; | |
692 | } | |
693 | ||
808347f6 NF |
694 | |
695 | /** | |
696 | * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
697 | * @chan: DMA channel | |
698 | * @sgl: scatterlist to transfer to/from | |
699 | * @sg_len: number of entries in @scatterlist | |
700 | * @direction: DMA direction | |
701 | * @flags: tx descriptor status flags | |
185ecb5f | 702 | * @context: transaction context (ignored) |
808347f6 NF |
703 | */ |
704 | static struct dma_async_tx_descriptor * | |
705 | atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 706 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 707 | unsigned long flags, void *context) |
808347f6 NF |
708 | { |
709 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
710 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 711 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
808347f6 NF |
712 | struct at_desc *first = NULL; |
713 | struct at_desc *prev = NULL; | |
714 | u32 ctrla; | |
715 | u32 ctrlb; | |
716 | dma_addr_t reg; | |
717 | unsigned int reg_width; | |
718 | unsigned int mem_width; | |
719 | unsigned int i; | |
720 | struct scatterlist *sg; | |
721 | size_t total_len = 0; | |
722 | ||
cc52a10a NF |
723 | dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", |
724 | sg_len, | |
db8196df | 725 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
808347f6 NF |
726 | flags); |
727 | ||
728 | if (unlikely(!atslave || !sg_len)) { | |
c618a9be | 729 | dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n"); |
808347f6 NF |
730 | return NULL; |
731 | } | |
732 | ||
1dd1ea8e NF |
733 | ctrla = ATC_SCSIZE(sconfig->src_maxburst) |
734 | | ATC_DCSIZE(sconfig->dst_maxburst); | |
ae14d4b5 | 735 | ctrlb = ATC_IEN; |
808347f6 NF |
736 | |
737 | switch (direction) { | |
db8196df | 738 | case DMA_MEM_TO_DEV: |
beeaa103 | 739 | reg_width = convert_buswidth(sconfig->dst_addr_width); |
808347f6 NF |
740 | ctrla |= ATC_DST_WIDTH(reg_width); |
741 | ctrlb |= ATC_DST_ADDR_MODE_FIXED | |
742 | | ATC_SRC_ADDR_MODE_INCR | |
ae14d4b5 | 743 | | ATC_FC_MEM2PER |
bbe89c8e | 744 | | ATC_SIF(atchan->mem_if) | ATC_DIF(atchan->per_if); |
beeaa103 | 745 | reg = sconfig->dst_addr; |
808347f6 NF |
746 | for_each_sg(sgl, sg, sg_len, i) { |
747 | struct at_desc *desc; | |
748 | u32 len; | |
749 | u32 mem; | |
750 | ||
751 | desc = atc_desc_get(atchan); | |
752 | if (!desc) | |
753 | goto err_desc_get; | |
754 | ||
0f70e8ce | 755 | mem = sg_dma_address(sg); |
808347f6 | 756 | len = sg_dma_len(sg); |
c4567976 NF |
757 | if (unlikely(!len)) { |
758 | dev_dbg(chan2dev(chan), | |
759 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
760 | goto err; | |
761 | } | |
808347f6 NF |
762 | mem_width = 2; |
763 | if (unlikely(mem & 3 || len & 3)) | |
764 | mem_width = 0; | |
765 | ||
766 | desc->lli.saddr = mem; | |
767 | desc->lli.daddr = reg; | |
768 | desc->lli.ctrla = ctrla | |
769 | | ATC_SRC_WIDTH(mem_width) | |
770 | | len >> mem_width; | |
771 | desc->lli.ctrlb = ctrlb; | |
772 | ||
e257e156 | 773 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
774 | total_len += len; |
775 | } | |
776 | break; | |
db8196df | 777 | case DMA_DEV_TO_MEM: |
beeaa103 | 778 | reg_width = convert_buswidth(sconfig->src_addr_width); |
808347f6 NF |
779 | ctrla |= ATC_SRC_WIDTH(reg_width); |
780 | ctrlb |= ATC_DST_ADDR_MODE_INCR | |
781 | | ATC_SRC_ADDR_MODE_FIXED | |
ae14d4b5 | 782 | | ATC_FC_PER2MEM |
bbe89c8e | 783 | | ATC_SIF(atchan->per_if) | ATC_DIF(atchan->mem_if); |
808347f6 | 784 | |
beeaa103 | 785 | reg = sconfig->src_addr; |
808347f6 NF |
786 | for_each_sg(sgl, sg, sg_len, i) { |
787 | struct at_desc *desc; | |
788 | u32 len; | |
789 | u32 mem; | |
790 | ||
791 | desc = atc_desc_get(atchan); | |
792 | if (!desc) | |
793 | goto err_desc_get; | |
794 | ||
0f70e8ce | 795 | mem = sg_dma_address(sg); |
808347f6 | 796 | len = sg_dma_len(sg); |
c4567976 NF |
797 | if (unlikely(!len)) { |
798 | dev_dbg(chan2dev(chan), | |
799 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
800 | goto err; | |
801 | } | |
808347f6 NF |
802 | mem_width = 2; |
803 | if (unlikely(mem & 3 || len & 3)) | |
804 | mem_width = 0; | |
805 | ||
806 | desc->lli.saddr = reg; | |
807 | desc->lli.daddr = mem; | |
808 | desc->lli.ctrla = ctrla | |
809 | | ATC_DST_WIDTH(mem_width) | |
59a609d9 | 810 | | len >> reg_width; |
808347f6 NF |
811 | desc->lli.ctrlb = ctrlb; |
812 | ||
e257e156 | 813 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
814 | total_len += len; |
815 | } | |
816 | break; | |
817 | default: | |
818 | return NULL; | |
819 | } | |
820 | ||
821 | /* set end-of-link to the last link descriptor of list*/ | |
822 | set_desc_eol(prev); | |
823 | ||
824 | /* First descriptor of the chain embedds additional information */ | |
825 | first->txd.cookie = -EBUSY; | |
826 | first->len = total_len; | |
d088c33b | 827 | first->tx_width = reg_width; |
808347f6 | 828 | |
568f7f0c NF |
829 | /* first link descriptor of list is responsible of flags */ |
830 | first->txd.flags = flags; /* client is in control of this ack */ | |
808347f6 NF |
831 | |
832 | return &first->txd; | |
833 | ||
834 | err_desc_get: | |
835 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
c4567976 | 836 | err: |
808347f6 NF |
837 | atc_desc_put(atchan, first); |
838 | return NULL; | |
839 | } | |
840 | ||
53830cc7 NF |
841 | /** |
842 | * atc_dma_cyclic_check_values | |
843 | * Check for too big/unaligned periods and unaligned DMA buffer | |
844 | */ | |
845 | static int | |
846 | atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, | |
0e7264cc | 847 | size_t period_len) |
53830cc7 NF |
848 | { |
849 | if (period_len > (ATC_BTSIZE_MAX << reg_width)) | |
850 | goto err_out; | |
851 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
852 | goto err_out; | |
853 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
854 | goto err_out; | |
53830cc7 NF |
855 | |
856 | return 0; | |
857 | ||
858 | err_out: | |
859 | return -EINVAL; | |
860 | } | |
861 | ||
862 | /** | |
d73111c6 | 863 | * atc_dma_cyclic_fill_desc - Fill one period descriptor |
53830cc7 NF |
864 | */ |
865 | static int | |
beeaa103 | 866 | atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc, |
53830cc7 | 867 | unsigned int period_index, dma_addr_t buf_addr, |
beeaa103 NF |
868 | unsigned int reg_width, size_t period_len, |
869 | enum dma_transfer_direction direction) | |
53830cc7 | 870 | { |
beeaa103 | 871 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
beeaa103 NF |
872 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
873 | u32 ctrla; | |
53830cc7 NF |
874 | |
875 | /* prepare common CRTLA value */ | |
1dd1ea8e NF |
876 | ctrla = ATC_SCSIZE(sconfig->src_maxburst) |
877 | | ATC_DCSIZE(sconfig->dst_maxburst) | |
53830cc7 NF |
878 | | ATC_DST_WIDTH(reg_width) |
879 | | ATC_SRC_WIDTH(reg_width) | |
880 | | period_len >> reg_width; | |
881 | ||
882 | switch (direction) { | |
db8196df | 883 | case DMA_MEM_TO_DEV: |
53830cc7 | 884 | desc->lli.saddr = buf_addr + (period_len * period_index); |
beeaa103 | 885 | desc->lli.daddr = sconfig->dst_addr; |
53830cc7 | 886 | desc->lli.ctrla = ctrla; |
ae14d4b5 | 887 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED |
53830cc7 | 888 | | ATC_SRC_ADDR_MODE_INCR |
ae14d4b5 | 889 | | ATC_FC_MEM2PER |
bbe89c8e LD |
890 | | ATC_SIF(atchan->mem_if) |
891 | | ATC_DIF(atchan->per_if); | |
53830cc7 NF |
892 | break; |
893 | ||
db8196df | 894 | case DMA_DEV_TO_MEM: |
beeaa103 | 895 | desc->lli.saddr = sconfig->src_addr; |
53830cc7 NF |
896 | desc->lli.daddr = buf_addr + (period_len * period_index); |
897 | desc->lli.ctrla = ctrla; | |
ae14d4b5 | 898 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR |
53830cc7 | 899 | | ATC_SRC_ADDR_MODE_FIXED |
ae14d4b5 | 900 | | ATC_FC_PER2MEM |
bbe89c8e LD |
901 | | ATC_SIF(atchan->per_if) |
902 | | ATC_DIF(atchan->mem_if); | |
53830cc7 NF |
903 | break; |
904 | ||
905 | default: | |
906 | return -EINVAL; | |
907 | } | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
912 | /** | |
913 | * atc_prep_dma_cyclic - prepare the cyclic DMA transfer | |
914 | * @chan: the DMA channel to prepare | |
915 | * @buf_addr: physical DMA address where the buffer starts | |
916 | * @buf_len: total number of bytes for the entire buffer | |
917 | * @period_len: number of bytes for each period | |
918 | * @direction: transfer direction, to or from device | |
ec8b5e48 | 919 | * @flags: tx descriptor status flags |
185ecb5f | 920 | * @context: transfer context (ignored) |
53830cc7 NF |
921 | */ |
922 | static struct dma_async_tx_descriptor * | |
923 | atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 924 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 925 | unsigned long flags, void *context) |
53830cc7 NF |
926 | { |
927 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
928 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 929 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
53830cc7 NF |
930 | struct at_desc *first = NULL; |
931 | struct at_desc *prev = NULL; | |
932 | unsigned long was_cyclic; | |
beeaa103 | 933 | unsigned int reg_width; |
53830cc7 NF |
934 | unsigned int periods = buf_len / period_len; |
935 | unsigned int i; | |
936 | ||
937 | dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", | |
db8196df | 938 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
53830cc7 NF |
939 | buf_addr, |
940 | periods, buf_len, period_len); | |
941 | ||
942 | if (unlikely(!atslave || !buf_len || !period_len)) { | |
943 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); | |
944 | return NULL; | |
945 | } | |
946 | ||
947 | was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); | |
948 | if (was_cyclic) { | |
949 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); | |
950 | return NULL; | |
951 | } | |
952 | ||
0e7264cc AS |
953 | if (unlikely(!is_slave_direction(direction))) |
954 | goto err_out; | |
955 | ||
beeaa103 NF |
956 | if (sconfig->direction == DMA_MEM_TO_DEV) |
957 | reg_width = convert_buswidth(sconfig->dst_addr_width); | |
958 | else | |
959 | reg_width = convert_buswidth(sconfig->src_addr_width); | |
960 | ||
53830cc7 | 961 | /* Check for too big/unaligned periods and unaligned DMA buffer */ |
0e7264cc | 962 | if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len)) |
53830cc7 NF |
963 | goto err_out; |
964 | ||
965 | /* build cyclic linked list */ | |
966 | for (i = 0; i < periods; i++) { | |
967 | struct at_desc *desc; | |
968 | ||
969 | desc = atc_desc_get(atchan); | |
970 | if (!desc) | |
971 | goto err_desc_get; | |
972 | ||
beeaa103 NF |
973 | if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr, |
974 | reg_width, period_len, direction)) | |
53830cc7 NF |
975 | goto err_desc_get; |
976 | ||
977 | atc_desc_chain(&first, &prev, desc); | |
978 | } | |
979 | ||
980 | /* lets make a cyclic list */ | |
981 | prev->lli.dscr = first->txd.phys; | |
982 | ||
983 | /* First descriptor of the chain embedds additional information */ | |
984 | first->txd.cookie = -EBUSY; | |
985 | first->len = buf_len; | |
d088c33b | 986 | first->tx_width = reg_width; |
53830cc7 NF |
987 | |
988 | return &first->txd; | |
989 | ||
990 | err_desc_get: | |
991 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
992 | atc_desc_put(atchan, first); | |
993 | err_out: | |
994 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
995 | return NULL; | |
996 | } | |
997 | ||
beeaa103 NF |
998 | static int set_runtime_config(struct dma_chan *chan, |
999 | struct dma_slave_config *sconfig) | |
1000 | { | |
1001 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1002 | ||
1003 | /* Check if it is chan is configured for slave transfers */ | |
1004 | if (!chan->private) | |
1005 | return -EINVAL; | |
1006 | ||
1007 | memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig)); | |
1008 | ||
1009 | convert_burst(&atchan->dma_sconfig.src_maxburst); | |
1010 | convert_burst(&atchan->dma_sconfig.dst_maxburst); | |
1011 | ||
1012 | return 0; | |
1013 | } | |
1014 | ||
53830cc7 | 1015 | |
05827630 LW |
1016 | static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
1017 | unsigned long arg) | |
808347f6 NF |
1018 | { |
1019 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1020 | struct at_dma *atdma = to_at_dma(chan->device); | |
23b5e3ad | 1021 | int chan_id = atchan->chan_common.chan_id; |
d8cb04b0 | 1022 | unsigned long flags; |
23b5e3ad | 1023 | |
808347f6 NF |
1024 | LIST_HEAD(list); |
1025 | ||
23b5e3ad | 1026 | dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd); |
c3635c78 | 1027 | |
23b5e3ad | 1028 | if (cmd == DMA_PAUSE) { |
d8cb04b0 | 1029 | spin_lock_irqsave(&atchan->lock, flags); |
808347f6 | 1030 | |
23b5e3ad | 1031 | dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); |
23b5e3ad | 1032 | set_bit(ATC_IS_PAUSED, &atchan->status); |
808347f6 | 1033 | |
d8cb04b0 | 1034 | spin_unlock_irqrestore(&atchan->lock, flags); |
23b5e3ad | 1035 | } else if (cmd == DMA_RESUME) { |
3c477482 | 1036 | if (!atc_chan_is_paused(atchan)) |
23b5e3ad | 1037 | return 0; |
808347f6 | 1038 | |
d8cb04b0 | 1039 | spin_lock_irqsave(&atchan->lock, flags); |
808347f6 | 1040 | |
23b5e3ad NF |
1041 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); |
1042 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
c3635c78 | 1043 | |
d8cb04b0 | 1044 | spin_unlock_irqrestore(&atchan->lock, flags); |
23b5e3ad NF |
1045 | } else if (cmd == DMA_TERMINATE_ALL) { |
1046 | struct at_desc *desc, *_desc; | |
1047 | /* | |
1048 | * This is only called when something went wrong elsewhere, so | |
1049 | * we don't really care about the data. Just disable the | |
1050 | * channel. We still have to poll the channel enable bit due | |
1051 | * to AHB/HSB limitations. | |
1052 | */ | |
d8cb04b0 | 1053 | spin_lock_irqsave(&atchan->lock, flags); |
23b5e3ad NF |
1054 | |
1055 | /* disabling channel: must also remove suspend state */ | |
1056 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); | |
1057 | ||
1058 | /* confirm that this channel is disabled */ | |
1059 | while (dma_readl(atdma, CHSR) & atchan->mask) | |
1060 | cpu_relax(); | |
1061 | ||
1062 | /* active_list entries will end up before queued entries */ | |
1063 | list_splice_init(&atchan->queue, &list); | |
1064 | list_splice_init(&atchan->active_list, &list); | |
1065 | ||
1066 | /* Flush all pending and queued descriptors */ | |
1067 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1068 | atc_chain_complete(atchan, desc); | |
1069 | ||
1070 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
1071 | /* if channel dedicated to cyclic operations, free it */ | |
1072 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
1073 | ||
d8cb04b0 | 1074 | spin_unlock_irqrestore(&atchan->lock, flags); |
beeaa103 NF |
1075 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1076 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
23b5e3ad NF |
1077 | } else { |
1078 | return -ENXIO; | |
1079 | } | |
b0ebeb9c | 1080 | |
c3635c78 | 1081 | return 0; |
808347f6 NF |
1082 | } |
1083 | ||
dc78baa2 | 1084 | /** |
07934481 | 1085 | * atc_tx_status - poll for transaction completion |
dc78baa2 NF |
1086 | * @chan: DMA channel |
1087 | * @cookie: transaction identifier to check status of | |
07934481 | 1088 | * @txstate: if not %NULL updated with transaction state |
dc78baa2 | 1089 | * |
07934481 | 1090 | * If @txstate is passed in, upon return it reflect the driver |
dc78baa2 NF |
1091 | * internal state and can be used with dma_async_is_complete() to check |
1092 | * the status of multiple cookies without re-checking hardware state. | |
1093 | */ | |
1094 | static enum dma_status | |
07934481 | 1095 | atc_tx_status(struct dma_chan *chan, |
dc78baa2 | 1096 | dma_cookie_t cookie, |
07934481 | 1097 | struct dma_tx_state *txstate) |
dc78baa2 NF |
1098 | { |
1099 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1100 | unsigned long flags; |
dc78baa2 | 1101 | enum dma_status ret; |
d48de6f1 | 1102 | int bytes = 0; |
dc78baa2 | 1103 | |
96a2af41 | 1104 | ret = dma_cookie_status(chan, cookie, txstate); |
d48de6f1 ES |
1105 | if (ret == DMA_SUCCESS) |
1106 | return ret; | |
1107 | /* | |
1108 | * There's no point calculating the residue if there's | |
1109 | * no txstate to store the value. | |
1110 | */ | |
1111 | if (!txstate) | |
1112 | return DMA_ERROR; | |
dc78baa2 | 1113 | |
d48de6f1 | 1114 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 1115 | |
d48de6f1 ES |
1116 | /* Get number of bytes left in the active transactions */ |
1117 | bytes = atc_get_bytes_left(chan); | |
96a2af41 | 1118 | |
d8cb04b0 | 1119 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 | 1120 | |
d48de6f1 ES |
1121 | if (unlikely(bytes < 0)) { |
1122 | dev_vdbg(chan2dev(chan), "get residual bytes error\n"); | |
1123 | return DMA_ERROR; | |
c3dbc60c | 1124 | } else { |
d48de6f1 | 1125 | dma_set_residue(txstate, bytes); |
c3dbc60c | 1126 | } |
23b5e3ad | 1127 | |
d48de6f1 ES |
1128 | dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n", |
1129 | ret, cookie, bytes); | |
dc78baa2 NF |
1130 | |
1131 | return ret; | |
1132 | } | |
1133 | ||
1134 | /** | |
1135 | * atc_issue_pending - try to finish work | |
1136 | * @chan: target DMA channel | |
1137 | */ | |
1138 | static void atc_issue_pending(struct dma_chan *chan) | |
1139 | { | |
1140 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1141 | unsigned long flags; |
dc78baa2 NF |
1142 | |
1143 | dev_vdbg(chan2dev(chan), "issue_pending\n"); | |
1144 | ||
53830cc7 | 1145 | /* Not needed for cyclic transfers */ |
3c477482 | 1146 | if (atc_chan_is_cyclic(atchan)) |
53830cc7 NF |
1147 | return; |
1148 | ||
d8cb04b0 | 1149 | spin_lock_irqsave(&atchan->lock, flags); |
d202f051 | 1150 | atc_advance_work(atchan); |
d8cb04b0 | 1151 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1152 | } |
1153 | ||
1154 | /** | |
1155 | * atc_alloc_chan_resources - allocate resources for DMA channel | |
1156 | * @chan: allocate descriptor resources for this channel | |
1157 | * @client: current client requesting the channel be ready for requests | |
1158 | * | |
1159 | * return - the number of allocated descriptors | |
1160 | */ | |
1161 | static int atc_alloc_chan_resources(struct dma_chan *chan) | |
1162 | { | |
1163 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1164 | struct at_dma *atdma = to_at_dma(chan->device); | |
1165 | struct at_desc *desc; | |
808347f6 | 1166 | struct at_dma_slave *atslave; |
d8cb04b0 | 1167 | unsigned long flags; |
dc78baa2 | 1168 | int i; |
808347f6 | 1169 | u32 cfg; |
dc78baa2 NF |
1170 | LIST_HEAD(tmp_list); |
1171 | ||
1172 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); | |
1173 | ||
1174 | /* ASSERT: channel is idle */ | |
1175 | if (atc_chan_is_enabled(atchan)) { | |
1176 | dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); | |
1177 | return -EIO; | |
1178 | } | |
1179 | ||
808347f6 NF |
1180 | cfg = ATC_DEFAULT_CFG; |
1181 | ||
1182 | atslave = chan->private; | |
1183 | if (atslave) { | |
1184 | /* | |
1185 | * We need controller-specific data to set up slave | |
1186 | * transfers. | |
1187 | */ | |
1188 | BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); | |
1189 | ||
ea7e7906 | 1190 | /* if cfg configuration specified take it instead of default */ |
808347f6 NF |
1191 | if (atslave->cfg) |
1192 | cfg = atslave->cfg; | |
1193 | } | |
1194 | ||
1195 | /* have we already been set up? | |
1196 | * reconfigure channel but no need to reallocate descriptors */ | |
dc78baa2 NF |
1197 | if (!list_empty(&atchan->free_list)) |
1198 | return atchan->descs_allocated; | |
1199 | ||
1200 | /* Allocate initial pool of descriptors */ | |
1201 | for (i = 0; i < init_nr_desc_per_channel; i++) { | |
1202 | desc = atc_alloc_descriptor(chan, GFP_KERNEL); | |
1203 | if (!desc) { | |
1204 | dev_err(atdma->dma_common.dev, | |
1205 | "Only %d initial descriptors\n", i); | |
1206 | break; | |
1207 | } | |
1208 | list_add_tail(&desc->desc_node, &tmp_list); | |
1209 | } | |
1210 | ||
d8cb04b0 | 1211 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 1212 | atchan->descs_allocated = i; |
d48de6f1 | 1213 | atchan->remain_desc = 0; |
dc78baa2 | 1214 | list_splice(&tmp_list, &atchan->free_list); |
d3ee98cd | 1215 | dma_cookie_init(chan); |
d8cb04b0 | 1216 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1217 | |
1218 | /* channel parameters */ | |
808347f6 | 1219 | channel_writel(atchan, CFG, cfg); |
dc78baa2 NF |
1220 | |
1221 | dev_dbg(chan2dev(chan), | |
1222 | "alloc_chan_resources: allocated %d descriptors\n", | |
1223 | atchan->descs_allocated); | |
1224 | ||
1225 | return atchan->descs_allocated; | |
1226 | } | |
1227 | ||
1228 | /** | |
1229 | * atc_free_chan_resources - free all channel resources | |
1230 | * @chan: DMA channel | |
1231 | */ | |
1232 | static void atc_free_chan_resources(struct dma_chan *chan) | |
1233 | { | |
1234 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1235 | struct at_dma *atdma = to_at_dma(chan->device); | |
1236 | struct at_desc *desc, *_desc; | |
1237 | LIST_HEAD(list); | |
1238 | ||
1239 | dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", | |
1240 | atchan->descs_allocated); | |
1241 | ||
1242 | /* ASSERT: channel is idle */ | |
1243 | BUG_ON(!list_empty(&atchan->active_list)); | |
1244 | BUG_ON(!list_empty(&atchan->queue)); | |
1245 | BUG_ON(atc_chan_is_enabled(atchan)); | |
1246 | ||
1247 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { | |
1248 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); | |
1249 | list_del(&desc->desc_node); | |
1250 | /* free link descriptor */ | |
1251 | dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); | |
1252 | } | |
1253 | list_splice_init(&atchan->free_list, &list); | |
1254 | atchan->descs_allocated = 0; | |
53830cc7 | 1255 | atchan->status = 0; |
d48de6f1 | 1256 | atchan->remain_desc = 0; |
dc78baa2 NF |
1257 | |
1258 | dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); | |
1259 | } | |
1260 | ||
bbe89c8e LD |
1261 | #ifdef CONFIG_OF |
1262 | static bool at_dma_filter(struct dma_chan *chan, void *slave) | |
1263 | { | |
1264 | struct at_dma_slave *atslave = slave; | |
1265 | ||
1266 | if (atslave->dma_dev == chan->device->dev) { | |
1267 | chan->private = atslave; | |
1268 | return true; | |
1269 | } else { | |
1270 | return false; | |
1271 | } | |
1272 | } | |
1273 | ||
1274 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1275 | struct of_dma *of_dma) | |
1276 | { | |
1277 | struct dma_chan *chan; | |
1278 | struct at_dma_chan *atchan; | |
1279 | struct at_dma_slave *atslave; | |
1280 | dma_cap_mask_t mask; | |
1281 | unsigned int per_id; | |
1282 | struct platform_device *dmac_pdev; | |
1283 | ||
1284 | if (dma_spec->args_count != 2) | |
1285 | return NULL; | |
1286 | ||
1287 | dmac_pdev = of_find_device_by_node(dma_spec->np); | |
1288 | ||
1289 | dma_cap_zero(mask); | |
1290 | dma_cap_set(DMA_SLAVE, mask); | |
1291 | ||
1292 | atslave = devm_kzalloc(&dmac_pdev->dev, sizeof(*atslave), GFP_KERNEL); | |
1293 | if (!atslave) | |
1294 | return NULL; | |
62971b29 LD |
1295 | |
1296 | atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW; | |
bbe89c8e LD |
1297 | /* |
1298 | * We can fill both SRC_PER and DST_PER, one of these fields will be | |
1299 | * ignored depending on DMA transfer direction. | |
1300 | */ | |
62971b29 LD |
1301 | per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK; |
1302 | atslave->cfg |= ATC_DST_PER_MSB(per_id) | ATC_DST_PER(per_id) | |
6c22770f | 1303 | | ATC_SRC_PER_MSB(per_id) | ATC_SRC_PER(per_id); |
62971b29 LD |
1304 | /* |
1305 | * We have to translate the value we get from the device tree since | |
1306 | * the half FIFO configuration value had to be 0 to keep backward | |
1307 | * compatibility. | |
1308 | */ | |
1309 | switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) { | |
1310 | case AT91_DMA_CFG_FIFOCFG_ALAP: | |
1311 | atslave->cfg |= ATC_FIFOCFG_LARGESTBURST; | |
1312 | break; | |
1313 | case AT91_DMA_CFG_FIFOCFG_ASAP: | |
1314 | atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE; | |
1315 | break; | |
1316 | case AT91_DMA_CFG_FIFOCFG_HALF: | |
1317 | default: | |
1318 | atslave->cfg |= ATC_FIFOCFG_HALFFIFO; | |
1319 | } | |
bbe89c8e LD |
1320 | atslave->dma_dev = &dmac_pdev->dev; |
1321 | ||
1322 | chan = dma_request_channel(mask, at_dma_filter, atslave); | |
1323 | if (!chan) | |
1324 | return NULL; | |
1325 | ||
1326 | atchan = to_at_dma_chan(chan); | |
1327 | atchan->per_if = dma_spec->args[0] & 0xff; | |
1328 | atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff; | |
1329 | ||
1330 | return chan; | |
1331 | } | |
1332 | #else | |
1333 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1334 | struct of_dma *of_dma) | |
1335 | { | |
1336 | return NULL; | |
1337 | } | |
1338 | #endif | |
dc78baa2 NF |
1339 | |
1340 | /*-- Module Management -----------------------------------------------*/ | |
1341 | ||
02f88be9 NF |
1342 | /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */ |
1343 | static struct at_dma_platform_data at91sam9rl_config = { | |
1344 | .nr_channels = 2, | |
1345 | }; | |
1346 | static struct at_dma_platform_data at91sam9g45_config = { | |
1347 | .nr_channels = 8, | |
1348 | }; | |
1349 | ||
c5115953 NF |
1350 | #if defined(CONFIG_OF) |
1351 | static const struct of_device_id atmel_dma_dt_ids[] = { | |
1352 | { | |
1353 | .compatible = "atmel,at91sam9rl-dma", | |
02f88be9 | 1354 | .data = &at91sam9rl_config, |
c5115953 NF |
1355 | }, { |
1356 | .compatible = "atmel,at91sam9g45-dma", | |
02f88be9 | 1357 | .data = &at91sam9g45_config, |
dcc81734 NF |
1358 | }, { |
1359 | /* sentinel */ | |
1360 | } | |
c5115953 NF |
1361 | }; |
1362 | ||
1363 | MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids); | |
1364 | #endif | |
1365 | ||
0ab88a01 | 1366 | static const struct platform_device_id atdma_devtypes[] = { |
67348450 NF |
1367 | { |
1368 | .name = "at91sam9rl_dma", | |
02f88be9 | 1369 | .driver_data = (unsigned long) &at91sam9rl_config, |
67348450 NF |
1370 | }, { |
1371 | .name = "at91sam9g45_dma", | |
02f88be9 | 1372 | .driver_data = (unsigned long) &at91sam9g45_config, |
67348450 NF |
1373 | }, { |
1374 | /* sentinel */ | |
1375 | } | |
1376 | }; | |
1377 | ||
7fd63ccd | 1378 | static inline const struct at_dma_platform_data * __init at_dma_get_driver_data( |
02f88be9 | 1379 | struct platform_device *pdev) |
c5115953 NF |
1380 | { |
1381 | if (pdev->dev.of_node) { | |
1382 | const struct of_device_id *match; | |
1383 | match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node); | |
1384 | if (match == NULL) | |
02f88be9 NF |
1385 | return NULL; |
1386 | return match->data; | |
c5115953 | 1387 | } |
02f88be9 NF |
1388 | return (struct at_dma_platform_data *) |
1389 | platform_get_device_id(pdev)->driver_data; | |
c5115953 NF |
1390 | } |
1391 | ||
dc78baa2 NF |
1392 | /** |
1393 | * at_dma_off - disable DMA controller | |
1394 | * @atdma: the Atmel HDAMC device | |
1395 | */ | |
1396 | static void at_dma_off(struct at_dma *atdma) | |
1397 | { | |
1398 | dma_writel(atdma, EN, 0); | |
1399 | ||
1400 | /* disable all interrupts */ | |
1401 | dma_writel(atdma, EBCIDR, -1L); | |
1402 | ||
1403 | /* confirm that all channels are disabled */ | |
1404 | while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) | |
1405 | cpu_relax(); | |
1406 | } | |
1407 | ||
1408 | static int __init at_dma_probe(struct platform_device *pdev) | |
1409 | { | |
dc78baa2 NF |
1410 | struct resource *io; |
1411 | struct at_dma *atdma; | |
1412 | size_t size; | |
1413 | int irq; | |
1414 | int err; | |
1415 | int i; | |
7fd63ccd | 1416 | const struct at_dma_platform_data *plat_dat; |
67348450 | 1417 | |
02f88be9 NF |
1418 | /* setup platform data for each SoC */ |
1419 | dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask); | |
1420 | dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); | |
1421 | dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); | |
67348450 NF |
1422 | |
1423 | /* get DMA parameters from controller type */ | |
02f88be9 NF |
1424 | plat_dat = at_dma_get_driver_data(pdev); |
1425 | if (!plat_dat) | |
1426 | return -ENODEV; | |
dc78baa2 NF |
1427 | |
1428 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1429 | if (!io) | |
1430 | return -EINVAL; | |
1431 | ||
1432 | irq = platform_get_irq(pdev, 0); | |
1433 | if (irq < 0) | |
1434 | return irq; | |
1435 | ||
1436 | size = sizeof(struct at_dma); | |
02f88be9 | 1437 | size += plat_dat->nr_channels * sizeof(struct at_dma_chan); |
dc78baa2 NF |
1438 | atdma = kzalloc(size, GFP_KERNEL); |
1439 | if (!atdma) | |
1440 | return -ENOMEM; | |
1441 | ||
67348450 | 1442 | /* discover transaction capabilities */ |
02f88be9 NF |
1443 | atdma->dma_common.cap_mask = plat_dat->cap_mask; |
1444 | atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; | |
dc78baa2 | 1445 | |
114df7d6 | 1446 | size = resource_size(io); |
dc78baa2 NF |
1447 | if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { |
1448 | err = -EBUSY; | |
1449 | goto err_kfree; | |
1450 | } | |
1451 | ||
1452 | atdma->regs = ioremap(io->start, size); | |
1453 | if (!atdma->regs) { | |
1454 | err = -ENOMEM; | |
1455 | goto err_release_r; | |
1456 | } | |
1457 | ||
1458 | atdma->clk = clk_get(&pdev->dev, "dma_clk"); | |
1459 | if (IS_ERR(atdma->clk)) { | |
1460 | err = PTR_ERR(atdma->clk); | |
1461 | goto err_clk; | |
1462 | } | |
f784d9c9 BB |
1463 | err = clk_prepare_enable(atdma->clk); |
1464 | if (err) | |
1465 | goto err_clk_prepare; | |
dc78baa2 NF |
1466 | |
1467 | /* force dma off, just in case */ | |
1468 | at_dma_off(atdma); | |
1469 | ||
1470 | err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); | |
1471 | if (err) | |
1472 | goto err_irq; | |
1473 | ||
1474 | platform_set_drvdata(pdev, atdma); | |
1475 | ||
1476 | /* create a pool of consistent memory blocks for hardware descriptors */ | |
1477 | atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", | |
1478 | &pdev->dev, sizeof(struct at_desc), | |
1479 | 4 /* word alignment */, 0); | |
1480 | if (!atdma->dma_desc_pool) { | |
1481 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1482 | err = -ENOMEM; | |
1483 | goto err_pool_create; | |
1484 | } | |
1485 | ||
1486 | /* clear any pending interrupt */ | |
1487 | while (dma_readl(atdma, EBCISR)) | |
1488 | cpu_relax(); | |
1489 | ||
1490 | /* initialize channels related values */ | |
1491 | INIT_LIST_HEAD(&atdma->dma_common.channels); | |
02f88be9 | 1492 | for (i = 0; i < plat_dat->nr_channels; i++) { |
dc78baa2 NF |
1493 | struct at_dma_chan *atchan = &atdma->chan[i]; |
1494 | ||
bbe89c8e LD |
1495 | atchan->mem_if = AT_DMA_MEM_IF; |
1496 | atchan->per_if = AT_DMA_PER_IF; | |
dc78baa2 | 1497 | atchan->chan_common.device = &atdma->dma_common; |
d3ee98cd | 1498 | dma_cookie_init(&atchan->chan_common); |
dc78baa2 NF |
1499 | list_add_tail(&atchan->chan_common.device_node, |
1500 | &atdma->dma_common.channels); | |
1501 | ||
1502 | atchan->ch_regs = atdma->regs + ch_regs(i); | |
1503 | spin_lock_init(&atchan->lock); | |
1504 | atchan->mask = 1 << i; | |
1505 | ||
1506 | INIT_LIST_HEAD(&atchan->active_list); | |
1507 | INIT_LIST_HEAD(&atchan->queue); | |
1508 | INIT_LIST_HEAD(&atchan->free_list); | |
1509 | ||
1510 | tasklet_init(&atchan->tasklet, atc_tasklet, | |
1511 | (unsigned long)atchan); | |
bda3a47c | 1512 | atc_enable_chan_irq(atdma, i); |
dc78baa2 NF |
1513 | } |
1514 | ||
1515 | /* set base routines */ | |
1516 | atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; | |
1517 | atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; | |
07934481 | 1518 | atdma->dma_common.device_tx_status = atc_tx_status; |
dc78baa2 NF |
1519 | atdma->dma_common.device_issue_pending = atc_issue_pending; |
1520 | atdma->dma_common.dev = &pdev->dev; | |
1521 | ||
1522 | /* set prep routines based on capability */ | |
1523 | if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) | |
1524 | atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; | |
1525 | ||
d7db8080 | 1526 | if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { |
808347f6 | 1527 | atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; |
d7db8080 NF |
1528 | /* controller can do slave DMA: can trigger cyclic transfers */ |
1529 | dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask); | |
53830cc7 | 1530 | atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; |
c3635c78 | 1531 | atdma->dma_common.device_control = atc_control; |
d7db8080 | 1532 | } |
808347f6 | 1533 | |
dc78baa2 NF |
1534 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
1535 | ||
1536 | dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n", | |
1537 | dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", | |
1538 | dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", | |
02f88be9 | 1539 | plat_dat->nr_channels); |
dc78baa2 NF |
1540 | |
1541 | dma_async_device_register(&atdma->dma_common); | |
1542 | ||
bbe89c8e LD |
1543 | /* |
1544 | * Do not return an error if the dmac node is not present in order to | |
1545 | * not break the existing way of requesting channel with | |
1546 | * dma_request_channel(). | |
1547 | */ | |
1548 | if (pdev->dev.of_node) { | |
1549 | err = of_dma_controller_register(pdev->dev.of_node, | |
1550 | at_dma_xlate, atdma); | |
1551 | if (err) { | |
1552 | dev_err(&pdev->dev, "could not register of_dma_controller\n"); | |
1553 | goto err_of_dma_controller_register; | |
1554 | } | |
1555 | } | |
1556 | ||
dc78baa2 NF |
1557 | return 0; |
1558 | ||
bbe89c8e LD |
1559 | err_of_dma_controller_register: |
1560 | dma_async_device_unregister(&atdma->dma_common); | |
1561 | dma_pool_destroy(atdma->dma_desc_pool); | |
dc78baa2 | 1562 | err_pool_create: |
dc78baa2 NF |
1563 | free_irq(platform_get_irq(pdev, 0), atdma); |
1564 | err_irq: | |
f784d9c9 BB |
1565 | clk_disable_unprepare(atdma->clk); |
1566 | err_clk_prepare: | |
dc78baa2 NF |
1567 | clk_put(atdma->clk); |
1568 | err_clk: | |
1569 | iounmap(atdma->regs); | |
1570 | atdma->regs = NULL; | |
1571 | err_release_r: | |
1572 | release_mem_region(io->start, size); | |
1573 | err_kfree: | |
1574 | kfree(atdma); | |
1575 | return err; | |
1576 | } | |
1577 | ||
1d1bbd30 | 1578 | static int at_dma_remove(struct platform_device *pdev) |
dc78baa2 NF |
1579 | { |
1580 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1581 | struct dma_chan *chan, *_chan; | |
1582 | struct resource *io; | |
1583 | ||
1584 | at_dma_off(atdma); | |
1585 | dma_async_device_unregister(&atdma->dma_common); | |
1586 | ||
1587 | dma_pool_destroy(atdma->dma_desc_pool); | |
dc78baa2 NF |
1588 | free_irq(platform_get_irq(pdev, 0), atdma); |
1589 | ||
1590 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1591 | device_node) { | |
1592 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1593 | ||
1594 | /* Disable interrupts */ | |
bda3a47c | 1595 | atc_disable_chan_irq(atdma, chan->chan_id); |
dc78baa2 NF |
1596 | tasklet_disable(&atchan->tasklet); |
1597 | ||
1598 | tasklet_kill(&atchan->tasklet); | |
1599 | list_del(&chan->device_node); | |
1600 | } | |
1601 | ||
f784d9c9 | 1602 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
1603 | clk_put(atdma->clk); |
1604 | ||
1605 | iounmap(atdma->regs); | |
1606 | atdma->regs = NULL; | |
1607 | ||
1608 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
114df7d6 | 1609 | release_mem_region(io->start, resource_size(io)); |
dc78baa2 NF |
1610 | |
1611 | kfree(atdma); | |
1612 | ||
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | static void at_dma_shutdown(struct platform_device *pdev) | |
1617 | { | |
1618 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1619 | ||
1620 | at_dma_off(platform_get_drvdata(pdev)); | |
f784d9c9 | 1621 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
1622 | } |
1623 | ||
c0ba5947 NF |
1624 | static int at_dma_prepare(struct device *dev) |
1625 | { | |
1626 | struct platform_device *pdev = to_platform_device(dev); | |
1627 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1628 | struct dma_chan *chan, *_chan; | |
1629 | ||
1630 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1631 | device_node) { | |
1632 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1633 | /* wait for transaction completion (except in cyclic case) */ | |
3c477482 | 1634 | if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1635 | return -EAGAIN; |
1636 | } | |
1637 | return 0; | |
1638 | } | |
1639 | ||
1640 | static void atc_suspend_cyclic(struct at_dma_chan *atchan) | |
1641 | { | |
1642 | struct dma_chan *chan = &atchan->chan_common; | |
1643 | ||
1644 | /* Channel should be paused by user | |
1645 | * do it anyway even if it is not done already */ | |
3c477482 | 1646 | if (!atc_chan_is_paused(atchan)) { |
c0ba5947 NF |
1647 | dev_warn(chan2dev(chan), |
1648 | "cyclic channel not paused, should be done by channel user\n"); | |
1649 | atc_control(chan, DMA_PAUSE, 0); | |
1650 | } | |
1651 | ||
1652 | /* now preserve additional data for cyclic operations */ | |
1653 | /* next descriptor address in the cyclic list */ | |
1654 | atchan->save_dscr = channel_readl(atchan, DSCR); | |
1655 | ||
1656 | vdbg_dump_regs(atchan); | |
1657 | } | |
1658 | ||
33f82d14 | 1659 | static int at_dma_suspend_noirq(struct device *dev) |
dc78baa2 | 1660 | { |
33f82d14 DW |
1661 | struct platform_device *pdev = to_platform_device(dev); |
1662 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 1663 | struct dma_chan *chan, *_chan; |
dc78baa2 | 1664 | |
c0ba5947 NF |
1665 | /* preserve data */ |
1666 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1667 | device_node) { | |
1668 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1669 | ||
3c477482 | 1670 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1671 | atc_suspend_cyclic(atchan); |
1672 | atchan->save_cfg = channel_readl(atchan, CFG); | |
1673 | } | |
1674 | atdma->save_imr = dma_readl(atdma, EBCIMR); | |
1675 | ||
1676 | /* disable DMA controller */ | |
1677 | at_dma_off(atdma); | |
f784d9c9 | 1678 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
1679 | return 0; |
1680 | } | |
1681 | ||
c0ba5947 NF |
1682 | static void atc_resume_cyclic(struct at_dma_chan *atchan) |
1683 | { | |
1684 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
1685 | ||
1686 | /* restore channel status for cyclic descriptors list: | |
1687 | * next descriptor in the cyclic list at the time of suspend */ | |
1688 | channel_writel(atchan, SADDR, 0); | |
1689 | channel_writel(atchan, DADDR, 0); | |
1690 | channel_writel(atchan, CTRLA, 0); | |
1691 | channel_writel(atchan, CTRLB, 0); | |
1692 | channel_writel(atchan, DSCR, atchan->save_dscr); | |
1693 | dma_writel(atdma, CHER, atchan->mask); | |
1694 | ||
1695 | /* channel pause status should be removed by channel user | |
1696 | * We cannot take the initiative to do it here */ | |
1697 | ||
1698 | vdbg_dump_regs(atchan); | |
1699 | } | |
1700 | ||
33f82d14 | 1701 | static int at_dma_resume_noirq(struct device *dev) |
dc78baa2 | 1702 | { |
33f82d14 DW |
1703 | struct platform_device *pdev = to_platform_device(dev); |
1704 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 1705 | struct dma_chan *chan, *_chan; |
dc78baa2 | 1706 | |
c0ba5947 | 1707 | /* bring back DMA controller */ |
f784d9c9 | 1708 | clk_prepare_enable(atdma->clk); |
dc78baa2 | 1709 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
c0ba5947 NF |
1710 | |
1711 | /* clear any pending interrupt */ | |
1712 | while (dma_readl(atdma, EBCISR)) | |
1713 | cpu_relax(); | |
1714 | ||
1715 | /* restore saved data */ | |
1716 | dma_writel(atdma, EBCIER, atdma->save_imr); | |
1717 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1718 | device_node) { | |
1719 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1720 | ||
1721 | channel_writel(atchan, CFG, atchan->save_cfg); | |
3c477482 | 1722 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1723 | atc_resume_cyclic(atchan); |
1724 | } | |
dc78baa2 | 1725 | return 0; |
dc78baa2 NF |
1726 | } |
1727 | ||
47145210 | 1728 | static const struct dev_pm_ops at_dma_dev_pm_ops = { |
c0ba5947 | 1729 | .prepare = at_dma_prepare, |
33f82d14 DW |
1730 | .suspend_noirq = at_dma_suspend_noirq, |
1731 | .resume_noirq = at_dma_resume_noirq, | |
1732 | }; | |
1733 | ||
dc78baa2 | 1734 | static struct platform_driver at_dma_driver = { |
1d1bbd30 | 1735 | .remove = at_dma_remove, |
dc78baa2 | 1736 | .shutdown = at_dma_shutdown, |
67348450 | 1737 | .id_table = atdma_devtypes, |
dc78baa2 NF |
1738 | .driver = { |
1739 | .name = "at_hdmac", | |
33f82d14 | 1740 | .pm = &at_dma_dev_pm_ops, |
c5115953 | 1741 | .of_match_table = of_match_ptr(atmel_dma_dt_ids), |
dc78baa2 NF |
1742 | }, |
1743 | }; | |
1744 | ||
1745 | static int __init at_dma_init(void) | |
1746 | { | |
1747 | return platform_driver_probe(&at_dma_driver, at_dma_probe); | |
1748 | } | |
93d0bec2 | 1749 | subsys_initcall(at_dma_init); |
dc78baa2 NF |
1750 | |
1751 | static void __exit at_dma_exit(void) | |
1752 | { | |
1753 | platform_driver_unregister(&at_dma_driver); | |
1754 | } | |
1755 | module_exit(at_dma_exit); | |
1756 | ||
1757 | MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); | |
1758 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); | |
1759 | MODULE_LICENSE("GPL"); | |
1760 | MODULE_ALIAS("platform:at_hdmac"); |