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dc78baa2 NF |
1 | /* |
2 | * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) | |
3 | * | |
4 | * Copyright (C) 2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * | |
12 | * This supports the Atmel AHB DMA Controller, | |
13 | * | |
14 | * The driver has currently been tested with the Atmel AT91SAM9RL | |
15 | * and AT91SAM9G45 series. | |
16 | */ | |
17 | ||
18 | #include <linux/clk.h> | |
19 | #include <linux/dmaengine.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
dc78baa2 NF |
26 | |
27 | #include "at_hdmac_regs.h" | |
28 | ||
29 | /* | |
30 | * Glossary | |
31 | * -------- | |
32 | * | |
33 | * at_hdmac : Name of the ATmel AHB DMA Controller | |
34 | * at_dma_ / atdma : ATmel DMA controller entity related | |
35 | * atc_ / atchan : ATmel DMA Channel entity related | |
36 | */ | |
37 | ||
38 | #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) | |
39 | #define ATC_DEFAULT_CTRLA (0) | |
ae14d4b5 NF |
40 | #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ |
41 | |ATC_DIF(AT_DMA_MEM_IF)) | |
dc78baa2 NF |
42 | |
43 | /* | |
44 | * Initial number of descriptors to allocate for each channel. This could | |
45 | * be increased during dma usage. | |
46 | */ | |
47 | static unsigned int init_nr_desc_per_channel = 64; | |
48 | module_param(init_nr_desc_per_channel, uint, 0644); | |
49 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
50 | "initial descriptors per channel (default: 64)"); | |
51 | ||
52 | ||
53 | /* prototypes */ | |
54 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); | |
55 | ||
56 | ||
57 | /*----------------------------------------------------------------------*/ | |
58 | ||
59 | static struct at_desc *atc_first_active(struct at_dma_chan *atchan) | |
60 | { | |
61 | return list_first_entry(&atchan->active_list, | |
62 | struct at_desc, desc_node); | |
63 | } | |
64 | ||
65 | static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) | |
66 | { | |
67 | return list_first_entry(&atchan->queue, | |
68 | struct at_desc, desc_node); | |
69 | } | |
70 | ||
71 | /** | |
421f91d2 | 72 | * atc_alloc_descriptor - allocate and return an initialized descriptor |
dc78baa2 NF |
73 | * @chan: the channel to allocate descriptors for |
74 | * @gfp_flags: GFP allocation flags | |
75 | * | |
76 | * Note: The ack-bit is positioned in the descriptor flag at creation time | |
77 | * to make initial allocation more convenient. This bit will be cleared | |
78 | * and control will be given to client at usage time (during | |
79 | * preparation functions). | |
80 | */ | |
81 | static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, | |
82 | gfp_t gfp_flags) | |
83 | { | |
84 | struct at_desc *desc = NULL; | |
85 | struct at_dma *atdma = to_at_dma(chan->device); | |
86 | dma_addr_t phys; | |
87 | ||
88 | desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); | |
89 | if (desc) { | |
90 | memset(desc, 0, sizeof(struct at_desc)); | |
285a3c71 | 91 | INIT_LIST_HEAD(&desc->tx_list); |
dc78baa2 NF |
92 | dma_async_tx_descriptor_init(&desc->txd, chan); |
93 | /* txd.flags will be overwritten in prep functions */ | |
94 | desc->txd.flags = DMA_CTRL_ACK; | |
95 | desc->txd.tx_submit = atc_tx_submit; | |
96 | desc->txd.phys = phys; | |
97 | } | |
98 | ||
99 | return desc; | |
100 | } | |
101 | ||
102 | /** | |
af901ca1 | 103 | * atc_desc_get - get an unused descriptor from free_list |
dc78baa2 NF |
104 | * @atchan: channel we want a new descriptor for |
105 | */ | |
106 | static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) | |
107 | { | |
108 | struct at_desc *desc, *_desc; | |
109 | struct at_desc *ret = NULL; | |
110 | unsigned int i = 0; | |
111 | LIST_HEAD(tmp_list); | |
112 | ||
113 | spin_lock_bh(&atchan->lock); | |
114 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { | |
115 | i++; | |
116 | if (async_tx_test_ack(&desc->txd)) { | |
117 | list_del(&desc->desc_node); | |
118 | ret = desc; | |
119 | break; | |
120 | } | |
121 | dev_dbg(chan2dev(&atchan->chan_common), | |
122 | "desc %p not ACKed\n", desc); | |
123 | } | |
124 | spin_unlock_bh(&atchan->lock); | |
125 | dev_vdbg(chan2dev(&atchan->chan_common), | |
126 | "scanned %u descriptors on freelist\n", i); | |
127 | ||
128 | /* no more descriptor available in initial pool: create one more */ | |
129 | if (!ret) { | |
130 | ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); | |
131 | if (ret) { | |
132 | spin_lock_bh(&atchan->lock); | |
133 | atchan->descs_allocated++; | |
134 | spin_unlock_bh(&atchan->lock); | |
135 | } else { | |
136 | dev_err(chan2dev(&atchan->chan_common), | |
137 | "not enough descriptors available\n"); | |
138 | } | |
139 | } | |
140 | ||
141 | return ret; | |
142 | } | |
143 | ||
144 | /** | |
145 | * atc_desc_put - move a descriptor, including any children, to the free list | |
146 | * @atchan: channel we work on | |
147 | * @desc: descriptor, at the head of a chain, to move to free list | |
148 | */ | |
149 | static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) | |
150 | { | |
151 | if (desc) { | |
152 | struct at_desc *child; | |
153 | ||
154 | spin_lock_bh(&atchan->lock); | |
285a3c71 | 155 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
156 | dev_vdbg(chan2dev(&atchan->chan_common), |
157 | "moving child desc %p to freelist\n", | |
158 | child); | |
285a3c71 | 159 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
160 | dev_vdbg(chan2dev(&atchan->chan_common), |
161 | "moving desc %p to freelist\n", desc); | |
162 | list_add(&desc->desc_node, &atchan->free_list); | |
163 | spin_unlock_bh(&atchan->lock); | |
164 | } | |
165 | } | |
166 | ||
53830cc7 NF |
167 | /** |
168 | * atc_desc_chain - build chain adding a descripor | |
169 | * @first: address of first descripor of the chain | |
170 | * @prev: address of previous descripor of the chain | |
171 | * @desc: descriptor to queue | |
172 | * | |
173 | * Called from prep_* functions | |
174 | */ | |
175 | static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, | |
176 | struct at_desc *desc) | |
177 | { | |
178 | if (!(*first)) { | |
179 | *first = desc; | |
180 | } else { | |
181 | /* inform the HW lli about chaining */ | |
182 | (*prev)->lli.dscr = desc->txd.phys; | |
183 | /* insert the link descriptor to the LD ring */ | |
184 | list_add_tail(&desc->desc_node, | |
185 | &(*first)->tx_list); | |
186 | } | |
187 | *prev = desc; | |
188 | } | |
189 | ||
dc78baa2 NF |
190 | /** |
191 | * atc_assign_cookie - compute and assign new cookie | |
192 | * @atchan: channel we work on | |
193 | * @desc: descriptor to asign cookie for | |
194 | * | |
195 | * Called with atchan->lock held and bh disabled | |
196 | */ | |
197 | static dma_cookie_t | |
198 | atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc) | |
199 | { | |
200 | dma_cookie_t cookie = atchan->chan_common.cookie; | |
201 | ||
202 | if (++cookie < 0) | |
203 | cookie = 1; | |
204 | ||
205 | atchan->chan_common.cookie = cookie; | |
206 | desc->txd.cookie = cookie; | |
207 | ||
208 | return cookie; | |
209 | } | |
210 | ||
211 | /** | |
212 | * atc_dostart - starts the DMA engine for real | |
213 | * @atchan: the channel we want to start | |
214 | * @first: first descriptor in the list we want to begin with | |
215 | * | |
216 | * Called with atchan->lock held and bh disabled | |
217 | */ | |
218 | static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) | |
219 | { | |
220 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
221 | ||
222 | /* ASSERT: channel is idle */ | |
223 | if (atc_chan_is_enabled(atchan)) { | |
224 | dev_err(chan2dev(&atchan->chan_common), | |
225 | "BUG: Attempted to start non-idle channel\n"); | |
226 | dev_err(chan2dev(&atchan->chan_common), | |
227 | " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", | |
228 | channel_readl(atchan, SADDR), | |
229 | channel_readl(atchan, DADDR), | |
230 | channel_readl(atchan, CTRLA), | |
231 | channel_readl(atchan, CTRLB), | |
232 | channel_readl(atchan, DSCR)); | |
233 | ||
234 | /* The tasklet will hopefully advance the queue... */ | |
235 | return; | |
236 | } | |
237 | ||
238 | vdbg_dump_regs(atchan); | |
239 | ||
240 | /* clear any pending interrupt */ | |
241 | while (dma_readl(atdma, EBCISR)) | |
242 | cpu_relax(); | |
243 | ||
244 | channel_writel(atchan, SADDR, 0); | |
245 | channel_writel(atchan, DADDR, 0); | |
246 | channel_writel(atchan, CTRLA, 0); | |
247 | channel_writel(atchan, CTRLB, 0); | |
248 | channel_writel(atchan, DSCR, first->txd.phys); | |
249 | dma_writel(atdma, CHER, atchan->mask); | |
250 | ||
251 | vdbg_dump_regs(atchan); | |
252 | } | |
253 | ||
254 | /** | |
255 | * atc_chain_complete - finish work for one transaction chain | |
256 | * @atchan: channel we work on | |
257 | * @desc: descriptor at the head of the chain we want do complete | |
258 | * | |
259 | * Called with atchan->lock held and bh disabled */ | |
260 | static void | |
261 | atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) | |
262 | { | |
dc78baa2 NF |
263 | struct dma_async_tx_descriptor *txd = &desc->txd; |
264 | ||
265 | dev_vdbg(chan2dev(&atchan->chan_common), | |
266 | "descriptor %u complete\n", txd->cookie); | |
267 | ||
268 | atchan->completed_cookie = txd->cookie; | |
dc78baa2 NF |
269 | |
270 | /* move children to free_list */ | |
285a3c71 | 271 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
272 | /* move myself to free_list */ |
273 | list_move(&desc->desc_node, &atchan->free_list); | |
274 | ||
ebcf9b80 | 275 | /* unmap dma addresses (not on slave channels) */ |
657a77fa AN |
276 | if (!atchan->chan_common.private) { |
277 | struct device *parent = chan2parent(&atchan->chan_common); | |
278 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
279 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
280 | dma_unmap_single(parent, | |
281 | desc->lli.daddr, | |
282 | desc->len, DMA_FROM_DEVICE); | |
283 | else | |
284 | dma_unmap_page(parent, | |
285 | desc->lli.daddr, | |
286 | desc->len, DMA_FROM_DEVICE); | |
287 | } | |
288 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
289 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
290 | dma_unmap_single(parent, | |
291 | desc->lli.saddr, | |
292 | desc->len, DMA_TO_DEVICE); | |
293 | else | |
294 | dma_unmap_page(parent, | |
295 | desc->lli.saddr, | |
296 | desc->len, DMA_TO_DEVICE); | |
297 | } | |
dc78baa2 NF |
298 | } |
299 | ||
53830cc7 NF |
300 | /* for cyclic transfers, |
301 | * no need to replay callback function while stopping */ | |
302 | if (!test_bit(ATC_IS_CYCLIC, &atchan->status)) { | |
303 | dma_async_tx_callback callback = txd->callback; | |
304 | void *param = txd->callback_param; | |
305 | ||
306 | /* | |
307 | * The API requires that no submissions are done from a | |
308 | * callback, so we don't need to drop the lock here | |
309 | */ | |
310 | if (callback) | |
311 | callback(param); | |
312 | } | |
dc78baa2 NF |
313 | |
314 | dma_run_dependencies(txd); | |
315 | } | |
316 | ||
317 | /** | |
318 | * atc_complete_all - finish work for all transactions | |
319 | * @atchan: channel to complete transactions for | |
320 | * | |
321 | * Eventually submit queued descriptors if any | |
322 | * | |
323 | * Assume channel is idle while calling this function | |
324 | * Called with atchan->lock held and bh disabled | |
325 | */ | |
326 | static void atc_complete_all(struct at_dma_chan *atchan) | |
327 | { | |
328 | struct at_desc *desc, *_desc; | |
329 | LIST_HEAD(list); | |
330 | ||
331 | dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); | |
332 | ||
333 | BUG_ON(atc_chan_is_enabled(atchan)); | |
334 | ||
335 | /* | |
336 | * Submit queued descriptors ASAP, i.e. before we go through | |
337 | * the completed ones. | |
338 | */ | |
339 | if (!list_empty(&atchan->queue)) | |
340 | atc_dostart(atchan, atc_first_queued(atchan)); | |
341 | /* empty active_list now it is completed */ | |
342 | list_splice_init(&atchan->active_list, &list); | |
343 | /* empty queue list by moving descriptors (if any) to active_list */ | |
344 | list_splice_init(&atchan->queue, &atchan->active_list); | |
345 | ||
346 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
347 | atc_chain_complete(atchan, desc); | |
348 | } | |
349 | ||
350 | /** | |
351 | * atc_cleanup_descriptors - cleanup up finished descriptors in active_list | |
352 | * @atchan: channel to be cleaned up | |
353 | * | |
354 | * Called with atchan->lock held and bh disabled | |
355 | */ | |
356 | static void atc_cleanup_descriptors(struct at_dma_chan *atchan) | |
357 | { | |
358 | struct at_desc *desc, *_desc; | |
359 | struct at_desc *child; | |
360 | ||
361 | dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n"); | |
362 | ||
363 | list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { | |
364 | if (!(desc->lli.ctrla & ATC_DONE)) | |
365 | /* This one is currently in progress */ | |
366 | return; | |
367 | ||
285a3c71 | 368 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
369 | if (!(child->lli.ctrla & ATC_DONE)) |
370 | /* Currently in progress */ | |
371 | return; | |
372 | ||
373 | /* | |
374 | * No descriptors so far seem to be in progress, i.e. | |
375 | * this chain must be done. | |
376 | */ | |
377 | atc_chain_complete(atchan, desc); | |
378 | } | |
379 | } | |
380 | ||
381 | /** | |
382 | * atc_advance_work - at the end of a transaction, move forward | |
383 | * @atchan: channel where the transaction ended | |
384 | * | |
385 | * Called with atchan->lock held and bh disabled | |
386 | */ | |
387 | static void atc_advance_work(struct at_dma_chan *atchan) | |
388 | { | |
389 | dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); | |
390 | ||
391 | if (list_empty(&atchan->active_list) || | |
392 | list_is_singular(&atchan->active_list)) { | |
393 | atc_complete_all(atchan); | |
394 | } else { | |
395 | atc_chain_complete(atchan, atc_first_active(atchan)); | |
396 | /* advance work */ | |
397 | atc_dostart(atchan, atc_first_active(atchan)); | |
398 | } | |
399 | } | |
400 | ||
401 | ||
402 | /** | |
403 | * atc_handle_error - handle errors reported by DMA controller | |
404 | * @atchan: channel where error occurs | |
405 | * | |
406 | * Called with atchan->lock held and bh disabled | |
407 | */ | |
408 | static void atc_handle_error(struct at_dma_chan *atchan) | |
409 | { | |
410 | struct at_desc *bad_desc; | |
411 | struct at_desc *child; | |
412 | ||
413 | /* | |
414 | * The descriptor currently at the head of the active list is | |
415 | * broked. Since we don't have any way to report errors, we'll | |
416 | * just have to scream loudly and try to carry on. | |
417 | */ | |
418 | bad_desc = atc_first_active(atchan); | |
419 | list_del_init(&bad_desc->desc_node); | |
420 | ||
421 | /* As we are stopped, take advantage to push queued descriptors | |
422 | * in active_list */ | |
423 | list_splice_init(&atchan->queue, atchan->active_list.prev); | |
424 | ||
425 | /* Try to restart the controller */ | |
426 | if (!list_empty(&atchan->active_list)) | |
427 | atc_dostart(atchan, atc_first_active(atchan)); | |
428 | ||
429 | /* | |
430 | * KERN_CRITICAL may seem harsh, but since this only happens | |
431 | * when someone submits a bad physical address in a | |
432 | * descriptor, we should consider ourselves lucky that the | |
433 | * controller flagged an error instead of scribbling over | |
434 | * random memory locations. | |
435 | */ | |
436 | dev_crit(chan2dev(&atchan->chan_common), | |
437 | "Bad descriptor submitted for DMA!\n"); | |
438 | dev_crit(chan2dev(&atchan->chan_common), | |
439 | " cookie: %d\n", bad_desc->txd.cookie); | |
440 | atc_dump_lli(atchan, &bad_desc->lli); | |
285a3c71 | 441 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
dc78baa2 NF |
442 | atc_dump_lli(atchan, &child->lli); |
443 | ||
444 | /* Pretend the descriptor completed successfully */ | |
445 | atc_chain_complete(atchan, bad_desc); | |
446 | } | |
447 | ||
53830cc7 NF |
448 | /** |
449 | * atc_handle_cyclic - at the end of a period, run callback function | |
450 | * @atchan: channel used for cyclic operations | |
451 | * | |
452 | * Called with atchan->lock held and bh disabled | |
453 | */ | |
454 | static void atc_handle_cyclic(struct at_dma_chan *atchan) | |
455 | { | |
456 | struct at_desc *first = atc_first_active(atchan); | |
457 | struct dma_async_tx_descriptor *txd = &first->txd; | |
458 | dma_async_tx_callback callback = txd->callback; | |
459 | void *param = txd->callback_param; | |
460 | ||
461 | dev_vdbg(chan2dev(&atchan->chan_common), | |
462 | "new cyclic period llp 0x%08x\n", | |
463 | channel_readl(atchan, DSCR)); | |
464 | ||
465 | if (callback) | |
466 | callback(param); | |
467 | } | |
dc78baa2 NF |
468 | |
469 | /*-- IRQ & Tasklet ---------------------------------------------------*/ | |
470 | ||
471 | static void atc_tasklet(unsigned long data) | |
472 | { | |
473 | struct at_dma_chan *atchan = (struct at_dma_chan *)data; | |
474 | ||
dc78baa2 | 475 | spin_lock(&atchan->lock); |
53830cc7 | 476 | if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) |
dc78baa2 | 477 | atc_handle_error(atchan); |
53830cc7 NF |
478 | else if (test_bit(ATC_IS_CYCLIC, &atchan->status)) |
479 | atc_handle_cyclic(atchan); | |
dc78baa2 NF |
480 | else |
481 | atc_advance_work(atchan); | |
482 | ||
483 | spin_unlock(&atchan->lock); | |
484 | } | |
485 | ||
486 | static irqreturn_t at_dma_interrupt(int irq, void *dev_id) | |
487 | { | |
488 | struct at_dma *atdma = (struct at_dma *)dev_id; | |
489 | struct at_dma_chan *atchan; | |
490 | int i; | |
491 | u32 status, pending, imr; | |
492 | int ret = IRQ_NONE; | |
493 | ||
494 | do { | |
495 | imr = dma_readl(atdma, EBCIMR); | |
496 | status = dma_readl(atdma, EBCISR); | |
497 | pending = status & imr; | |
498 | ||
499 | if (!pending) | |
500 | break; | |
501 | ||
502 | dev_vdbg(atdma->dma_common.dev, | |
503 | "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", | |
504 | status, imr, pending); | |
505 | ||
506 | for (i = 0; i < atdma->dma_common.chancnt; i++) { | |
507 | atchan = &atdma->chan[i]; | |
9b3aa589 | 508 | if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { |
dc78baa2 NF |
509 | if (pending & AT_DMA_ERR(i)) { |
510 | /* Disable channel on AHB error */ | |
23b5e3ad NF |
511 | dma_writel(atdma, CHDR, |
512 | AT_DMA_RES(i) | atchan->mask); | |
dc78baa2 | 513 | /* Give information to tasklet */ |
53830cc7 | 514 | set_bit(ATC_IS_ERROR, &atchan->status); |
dc78baa2 NF |
515 | } |
516 | tasklet_schedule(&atchan->tasklet); | |
517 | ret = IRQ_HANDLED; | |
518 | } | |
519 | } | |
520 | ||
521 | } while (pending); | |
522 | ||
523 | return ret; | |
524 | } | |
525 | ||
526 | ||
527 | /*-- DMA Engine API --------------------------------------------------*/ | |
528 | ||
529 | /** | |
530 | * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine | |
531 | * @desc: descriptor at the head of the transaction chain | |
532 | * | |
533 | * Queue chain if DMA engine is working already | |
534 | * | |
535 | * Cookie increment and adding to active_list or queue must be atomic | |
536 | */ | |
537 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) | |
538 | { | |
539 | struct at_desc *desc = txd_to_at_desc(tx); | |
540 | struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); | |
541 | dma_cookie_t cookie; | |
542 | ||
543 | spin_lock_bh(&atchan->lock); | |
544 | cookie = atc_assign_cookie(atchan, desc); | |
545 | ||
546 | if (list_empty(&atchan->active_list)) { | |
547 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", | |
548 | desc->txd.cookie); | |
549 | atc_dostart(atchan, desc); | |
550 | list_add_tail(&desc->desc_node, &atchan->active_list); | |
551 | } else { | |
552 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", | |
553 | desc->txd.cookie); | |
554 | list_add_tail(&desc->desc_node, &atchan->queue); | |
555 | } | |
556 | ||
557 | spin_unlock_bh(&atchan->lock); | |
558 | ||
559 | return cookie; | |
560 | } | |
561 | ||
562 | /** | |
563 | * atc_prep_dma_memcpy - prepare a memcpy operation | |
564 | * @chan: the channel to prepare operation on | |
565 | * @dest: operation virtual destination address | |
566 | * @src: operation virtual source address | |
567 | * @len: operation length | |
568 | * @flags: tx descriptor status flags | |
569 | */ | |
570 | static struct dma_async_tx_descriptor * | |
571 | atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
572 | size_t len, unsigned long flags) | |
573 | { | |
574 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
575 | struct at_desc *desc = NULL; | |
576 | struct at_desc *first = NULL; | |
577 | struct at_desc *prev = NULL; | |
578 | size_t xfer_count; | |
579 | size_t offset; | |
580 | unsigned int src_width; | |
581 | unsigned int dst_width; | |
582 | u32 ctrla; | |
583 | u32 ctrlb; | |
584 | ||
585 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", | |
586 | dest, src, len, flags); | |
587 | ||
588 | if (unlikely(!len)) { | |
589 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
590 | return NULL; | |
591 | } | |
592 | ||
593 | ctrla = ATC_DEFAULT_CTRLA; | |
9b3aa589 | 594 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
dc78baa2 NF |
595 | | ATC_SRC_ADDR_MODE_INCR |
596 | | ATC_DST_ADDR_MODE_INCR | |
597 | | ATC_FC_MEM2MEM; | |
598 | ||
599 | /* | |
600 | * We can be a lot more clever here, but this should take care | |
601 | * of the most common optimization. | |
602 | */ | |
603 | if (!((src | dest | len) & 3)) { | |
604 | ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; | |
605 | src_width = dst_width = 2; | |
606 | } else if (!((src | dest | len) & 1)) { | |
607 | ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; | |
608 | src_width = dst_width = 1; | |
609 | } else { | |
610 | ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; | |
611 | src_width = dst_width = 0; | |
612 | } | |
613 | ||
614 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
615 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
616 | ATC_BTSIZE_MAX); | |
617 | ||
618 | desc = atc_desc_get(atchan); | |
619 | if (!desc) | |
620 | goto err_desc_get; | |
621 | ||
622 | desc->lli.saddr = src + offset; | |
623 | desc->lli.daddr = dest + offset; | |
624 | desc->lli.ctrla = ctrla | xfer_count; | |
625 | desc->lli.ctrlb = ctrlb; | |
626 | ||
627 | desc->txd.cookie = 0; | |
dc78baa2 NF |
628 | |
629 | if (!first) { | |
630 | first = desc; | |
631 | } else { | |
632 | /* inform the HW lli about chaining */ | |
633 | prev->lli.dscr = desc->txd.phys; | |
634 | /* insert the link descriptor to the LD ring */ | |
635 | list_add_tail(&desc->desc_node, | |
285a3c71 | 636 | &first->tx_list); |
dc78baa2 NF |
637 | } |
638 | prev = desc; | |
639 | } | |
640 | ||
641 | /* First descriptor of the chain embedds additional information */ | |
642 | first->txd.cookie = -EBUSY; | |
643 | first->len = len; | |
644 | ||
645 | /* set end-of-link to the last link descriptor of list*/ | |
646 | set_desc_eol(desc); | |
647 | ||
568f7f0c | 648 | first->txd.flags = flags; /* client is in control of this ack */ |
dc78baa2 NF |
649 | |
650 | return &first->txd; | |
651 | ||
652 | err_desc_get: | |
653 | atc_desc_put(atchan, first); | |
654 | return NULL; | |
655 | } | |
656 | ||
808347f6 NF |
657 | |
658 | /** | |
659 | * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
660 | * @chan: DMA channel | |
661 | * @sgl: scatterlist to transfer to/from | |
662 | * @sg_len: number of entries in @scatterlist | |
663 | * @direction: DMA direction | |
664 | * @flags: tx descriptor status flags | |
665 | */ | |
666 | static struct dma_async_tx_descriptor * | |
667 | atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
668 | unsigned int sg_len, enum dma_data_direction direction, | |
669 | unsigned long flags) | |
670 | { | |
671 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
672 | struct at_dma_slave *atslave = chan->private; | |
673 | struct at_desc *first = NULL; | |
674 | struct at_desc *prev = NULL; | |
675 | u32 ctrla; | |
676 | u32 ctrlb; | |
677 | dma_addr_t reg; | |
678 | unsigned int reg_width; | |
679 | unsigned int mem_width; | |
680 | unsigned int i; | |
681 | struct scatterlist *sg; | |
682 | size_t total_len = 0; | |
683 | ||
cc52a10a NF |
684 | dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", |
685 | sg_len, | |
808347f6 NF |
686 | direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", |
687 | flags); | |
688 | ||
689 | if (unlikely(!atslave || !sg_len)) { | |
690 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
691 | return NULL; | |
692 | } | |
693 | ||
694 | reg_width = atslave->reg_width; | |
695 | ||
808347f6 | 696 | ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; |
ae14d4b5 | 697 | ctrlb = ATC_IEN; |
808347f6 NF |
698 | |
699 | switch (direction) { | |
700 | case DMA_TO_DEVICE: | |
701 | ctrla |= ATC_DST_WIDTH(reg_width); | |
702 | ctrlb |= ATC_DST_ADDR_MODE_FIXED | |
703 | | ATC_SRC_ADDR_MODE_INCR | |
ae14d4b5 NF |
704 | | ATC_FC_MEM2PER |
705 | | ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF); | |
808347f6 NF |
706 | reg = atslave->tx_reg; |
707 | for_each_sg(sgl, sg, sg_len, i) { | |
708 | struct at_desc *desc; | |
709 | u32 len; | |
710 | u32 mem; | |
711 | ||
712 | desc = atc_desc_get(atchan); | |
713 | if (!desc) | |
714 | goto err_desc_get; | |
715 | ||
0f70e8ce | 716 | mem = sg_dma_address(sg); |
808347f6 NF |
717 | len = sg_dma_len(sg); |
718 | mem_width = 2; | |
719 | if (unlikely(mem & 3 || len & 3)) | |
720 | mem_width = 0; | |
721 | ||
722 | desc->lli.saddr = mem; | |
723 | desc->lli.daddr = reg; | |
724 | desc->lli.ctrla = ctrla | |
725 | | ATC_SRC_WIDTH(mem_width) | |
726 | | len >> mem_width; | |
727 | desc->lli.ctrlb = ctrlb; | |
728 | ||
729 | if (!first) { | |
730 | first = desc; | |
731 | } else { | |
732 | /* inform the HW lli about chaining */ | |
733 | prev->lli.dscr = desc->txd.phys; | |
734 | /* insert the link descriptor to the LD ring */ | |
735 | list_add_tail(&desc->desc_node, | |
285a3c71 | 736 | &first->tx_list); |
808347f6 NF |
737 | } |
738 | prev = desc; | |
739 | total_len += len; | |
740 | } | |
741 | break; | |
742 | case DMA_FROM_DEVICE: | |
743 | ctrla |= ATC_SRC_WIDTH(reg_width); | |
744 | ctrlb |= ATC_DST_ADDR_MODE_INCR | |
745 | | ATC_SRC_ADDR_MODE_FIXED | |
ae14d4b5 NF |
746 | | ATC_FC_PER2MEM |
747 | | ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF); | |
808347f6 NF |
748 | |
749 | reg = atslave->rx_reg; | |
750 | for_each_sg(sgl, sg, sg_len, i) { | |
751 | struct at_desc *desc; | |
752 | u32 len; | |
753 | u32 mem; | |
754 | ||
755 | desc = atc_desc_get(atchan); | |
756 | if (!desc) | |
757 | goto err_desc_get; | |
758 | ||
0f70e8ce | 759 | mem = sg_dma_address(sg); |
808347f6 NF |
760 | len = sg_dma_len(sg); |
761 | mem_width = 2; | |
762 | if (unlikely(mem & 3 || len & 3)) | |
763 | mem_width = 0; | |
764 | ||
765 | desc->lli.saddr = reg; | |
766 | desc->lli.daddr = mem; | |
767 | desc->lli.ctrla = ctrla | |
768 | | ATC_DST_WIDTH(mem_width) | |
59a609d9 | 769 | | len >> reg_width; |
808347f6 NF |
770 | desc->lli.ctrlb = ctrlb; |
771 | ||
772 | if (!first) { | |
773 | first = desc; | |
774 | } else { | |
775 | /* inform the HW lli about chaining */ | |
776 | prev->lli.dscr = desc->txd.phys; | |
777 | /* insert the link descriptor to the LD ring */ | |
778 | list_add_tail(&desc->desc_node, | |
285a3c71 | 779 | &first->tx_list); |
808347f6 NF |
780 | } |
781 | prev = desc; | |
782 | total_len += len; | |
783 | } | |
784 | break; | |
785 | default: | |
786 | return NULL; | |
787 | } | |
788 | ||
789 | /* set end-of-link to the last link descriptor of list*/ | |
790 | set_desc_eol(prev); | |
791 | ||
792 | /* First descriptor of the chain embedds additional information */ | |
793 | first->txd.cookie = -EBUSY; | |
794 | first->len = total_len; | |
795 | ||
568f7f0c NF |
796 | /* first link descriptor of list is responsible of flags */ |
797 | first->txd.flags = flags; /* client is in control of this ack */ | |
808347f6 NF |
798 | |
799 | return &first->txd; | |
800 | ||
801 | err_desc_get: | |
802 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
803 | atc_desc_put(atchan, first); | |
804 | return NULL; | |
805 | } | |
806 | ||
53830cc7 NF |
807 | /** |
808 | * atc_dma_cyclic_check_values | |
809 | * Check for too big/unaligned periods and unaligned DMA buffer | |
810 | */ | |
811 | static int | |
812 | atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, | |
813 | size_t period_len, enum dma_data_direction direction) | |
814 | { | |
815 | if (period_len > (ATC_BTSIZE_MAX << reg_width)) | |
816 | goto err_out; | |
817 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
818 | goto err_out; | |
819 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
820 | goto err_out; | |
821 | if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) | |
822 | goto err_out; | |
823 | ||
824 | return 0; | |
825 | ||
826 | err_out: | |
827 | return -EINVAL; | |
828 | } | |
829 | ||
830 | /** | |
831 | * atc_dma_cyclic_fill_desc - Fill one period decriptor | |
832 | */ | |
833 | static int | |
834 | atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc, | |
835 | unsigned int period_index, dma_addr_t buf_addr, | |
836 | size_t period_len, enum dma_data_direction direction) | |
837 | { | |
838 | u32 ctrla; | |
839 | unsigned int reg_width = atslave->reg_width; | |
840 | ||
841 | /* prepare common CRTLA value */ | |
842 | ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla | |
843 | | ATC_DST_WIDTH(reg_width) | |
844 | | ATC_SRC_WIDTH(reg_width) | |
845 | | period_len >> reg_width; | |
846 | ||
847 | switch (direction) { | |
848 | case DMA_TO_DEVICE: | |
849 | desc->lli.saddr = buf_addr + (period_len * period_index); | |
850 | desc->lli.daddr = atslave->tx_reg; | |
851 | desc->lli.ctrla = ctrla; | |
ae14d4b5 | 852 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED |
53830cc7 | 853 | | ATC_SRC_ADDR_MODE_INCR |
ae14d4b5 NF |
854 | | ATC_FC_MEM2PER |
855 | | ATC_SIF(AT_DMA_MEM_IF) | |
856 | | ATC_DIF(AT_DMA_PER_IF); | |
53830cc7 NF |
857 | break; |
858 | ||
859 | case DMA_FROM_DEVICE: | |
860 | desc->lli.saddr = atslave->rx_reg; | |
861 | desc->lli.daddr = buf_addr + (period_len * period_index); | |
862 | desc->lli.ctrla = ctrla; | |
ae14d4b5 | 863 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR |
53830cc7 | 864 | | ATC_SRC_ADDR_MODE_FIXED |
ae14d4b5 NF |
865 | | ATC_FC_PER2MEM |
866 | | ATC_SIF(AT_DMA_PER_IF) | |
867 | | ATC_DIF(AT_DMA_MEM_IF); | |
53830cc7 NF |
868 | break; |
869 | ||
870 | default: | |
871 | return -EINVAL; | |
872 | } | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
877 | /** | |
878 | * atc_prep_dma_cyclic - prepare the cyclic DMA transfer | |
879 | * @chan: the DMA channel to prepare | |
880 | * @buf_addr: physical DMA address where the buffer starts | |
881 | * @buf_len: total number of bytes for the entire buffer | |
882 | * @period_len: number of bytes for each period | |
883 | * @direction: transfer direction, to or from device | |
884 | */ | |
885 | static struct dma_async_tx_descriptor * | |
886 | atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
887 | size_t period_len, enum dma_data_direction direction) | |
888 | { | |
889 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
890 | struct at_dma_slave *atslave = chan->private; | |
891 | struct at_desc *first = NULL; | |
892 | struct at_desc *prev = NULL; | |
893 | unsigned long was_cyclic; | |
894 | unsigned int periods = buf_len / period_len; | |
895 | unsigned int i; | |
896 | ||
897 | dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", | |
898 | direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", | |
899 | buf_addr, | |
900 | periods, buf_len, period_len); | |
901 | ||
902 | if (unlikely(!atslave || !buf_len || !period_len)) { | |
903 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); | |
904 | return NULL; | |
905 | } | |
906 | ||
907 | was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); | |
908 | if (was_cyclic) { | |
909 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); | |
910 | return NULL; | |
911 | } | |
912 | ||
913 | /* Check for too big/unaligned periods and unaligned DMA buffer */ | |
914 | if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr, | |
915 | period_len, direction)) | |
916 | goto err_out; | |
917 | ||
918 | /* build cyclic linked list */ | |
919 | for (i = 0; i < periods; i++) { | |
920 | struct at_desc *desc; | |
921 | ||
922 | desc = atc_desc_get(atchan); | |
923 | if (!desc) | |
924 | goto err_desc_get; | |
925 | ||
926 | if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr, | |
927 | period_len, direction)) | |
928 | goto err_desc_get; | |
929 | ||
930 | atc_desc_chain(&first, &prev, desc); | |
931 | } | |
932 | ||
933 | /* lets make a cyclic list */ | |
934 | prev->lli.dscr = first->txd.phys; | |
935 | ||
936 | /* First descriptor of the chain embedds additional information */ | |
937 | first->txd.cookie = -EBUSY; | |
938 | first->len = buf_len; | |
939 | ||
940 | return &first->txd; | |
941 | ||
942 | err_desc_get: | |
943 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
944 | atc_desc_put(atchan, first); | |
945 | err_out: | |
946 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
947 | return NULL; | |
948 | } | |
949 | ||
950 | ||
05827630 LW |
951 | static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
952 | unsigned long arg) | |
808347f6 NF |
953 | { |
954 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
955 | struct at_dma *atdma = to_at_dma(chan->device); | |
23b5e3ad NF |
956 | int chan_id = atchan->chan_common.chan_id; |
957 | ||
808347f6 NF |
958 | LIST_HEAD(list); |
959 | ||
23b5e3ad | 960 | dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd); |
c3635c78 | 961 | |
23b5e3ad NF |
962 | if (cmd == DMA_PAUSE) { |
963 | int pause_timeout = 1000; | |
808347f6 | 964 | |
23b5e3ad | 965 | spin_lock_bh(&atchan->lock); |
808347f6 | 966 | |
23b5e3ad NF |
967 | dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); |
968 | ||
969 | /* wait for FIFO to be empty */ | |
970 | while (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id))) { | |
971 | if (pause_timeout-- > 0) { | |
972 | /* the FIFO can only drain if the peripheral | |
973 | * is still requesting data: | |
974 | * -> timeout if it is not the case. */ | |
975 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); | |
976 | spin_unlock_bh(&atchan->lock); | |
977 | return -ETIMEDOUT; | |
978 | } | |
979 | cpu_relax(); | |
980 | } | |
808347f6 | 981 | |
23b5e3ad | 982 | set_bit(ATC_IS_PAUSED, &atchan->status); |
808347f6 | 983 | |
23b5e3ad NF |
984 | spin_unlock_bh(&atchan->lock); |
985 | } else if (cmd == DMA_RESUME) { | |
986 | if (!test_bit(ATC_IS_PAUSED, &atchan->status)) | |
987 | return 0; | |
c3635c78 | 988 | |
23b5e3ad | 989 | spin_lock_bh(&atchan->lock); |
53830cc7 | 990 | |
23b5e3ad NF |
991 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); |
992 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
993 | ||
994 | spin_unlock_bh(&atchan->lock); | |
995 | } else if (cmd == DMA_TERMINATE_ALL) { | |
996 | struct at_desc *desc, *_desc; | |
997 | /* | |
998 | * This is only called when something went wrong elsewhere, so | |
999 | * we don't really care about the data. Just disable the | |
1000 | * channel. We still have to poll the channel enable bit due | |
1001 | * to AHB/HSB limitations. | |
1002 | */ | |
1003 | spin_lock_bh(&atchan->lock); | |
1004 | ||
1005 | /* disabling channel: must also remove suspend state */ | |
1006 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); | |
1007 | ||
1008 | /* confirm that this channel is disabled */ | |
1009 | while (dma_readl(atdma, CHSR) & atchan->mask) | |
1010 | cpu_relax(); | |
1011 | ||
1012 | /* active_list entries will end up before queued entries */ | |
1013 | list_splice_init(&atchan->queue, &list); | |
1014 | list_splice_init(&atchan->active_list, &list); | |
1015 | ||
1016 | /* Flush all pending and queued descriptors */ | |
1017 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1018 | atc_chain_complete(atchan, desc); | |
1019 | ||
1020 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
1021 | /* if channel dedicated to cyclic operations, free it */ | |
1022 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
1023 | ||
1024 | spin_unlock_bh(&atchan->lock); | |
1025 | } else { | |
1026 | return -ENXIO; | |
1027 | } | |
b0ebeb9c | 1028 | |
c3635c78 | 1029 | return 0; |
808347f6 NF |
1030 | } |
1031 | ||
dc78baa2 | 1032 | /** |
07934481 | 1033 | * atc_tx_status - poll for transaction completion |
dc78baa2 NF |
1034 | * @chan: DMA channel |
1035 | * @cookie: transaction identifier to check status of | |
07934481 | 1036 | * @txstate: if not %NULL updated with transaction state |
dc78baa2 | 1037 | * |
07934481 | 1038 | * If @txstate is passed in, upon return it reflect the driver |
dc78baa2 NF |
1039 | * internal state and can be used with dma_async_is_complete() to check |
1040 | * the status of multiple cookies without re-checking hardware state. | |
1041 | */ | |
1042 | static enum dma_status | |
07934481 | 1043 | atc_tx_status(struct dma_chan *chan, |
dc78baa2 | 1044 | dma_cookie_t cookie, |
07934481 | 1045 | struct dma_tx_state *txstate) |
dc78baa2 NF |
1046 | { |
1047 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1048 | dma_cookie_t last_used; | |
1049 | dma_cookie_t last_complete; | |
1050 | enum dma_status ret; | |
1051 | ||
4297a462 | 1052 | spin_lock_bh(&atchan->lock); |
dc78baa2 NF |
1053 | |
1054 | last_complete = atchan->completed_cookie; | |
1055 | last_used = chan->cookie; | |
1056 | ||
1057 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
1058 | if (ret != DMA_SUCCESS) { | |
1059 | atc_cleanup_descriptors(atchan); | |
1060 | ||
1061 | last_complete = atchan->completed_cookie; | |
1062 | last_used = chan->cookie; | |
1063 | ||
1064 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
1065 | } | |
1066 | ||
4297a462 | 1067 | spin_unlock_bh(&atchan->lock); |
dc78baa2 | 1068 | |
543aabc7 NF |
1069 | if (ret != DMA_SUCCESS) |
1070 | dma_set_tx_state(txstate, last_complete, last_used, | |
1071 | atc_first_active(atchan)->len); | |
1072 | else | |
1073 | dma_set_tx_state(txstate, last_complete, last_used, 0); | |
1074 | ||
23b5e3ad NF |
1075 | if (test_bit(ATC_IS_PAUSED, &atchan->status)) |
1076 | ret = DMA_PAUSED; | |
1077 | ||
1078 | dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n", | |
1079 | ret, cookie, last_complete ? last_complete : 0, | |
07934481 | 1080 | last_used ? last_used : 0); |
dc78baa2 NF |
1081 | |
1082 | return ret; | |
1083 | } | |
1084 | ||
1085 | /** | |
1086 | * atc_issue_pending - try to finish work | |
1087 | * @chan: target DMA channel | |
1088 | */ | |
1089 | static void atc_issue_pending(struct dma_chan *chan) | |
1090 | { | |
1091 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1092 | ||
1093 | dev_vdbg(chan2dev(chan), "issue_pending\n"); | |
1094 | ||
53830cc7 NF |
1095 | /* Not needed for cyclic transfers */ |
1096 | if (test_bit(ATC_IS_CYCLIC, &atchan->status)) | |
1097 | return; | |
1098 | ||
dda36f98 | 1099 | spin_lock_bh(&atchan->lock); |
dc78baa2 | 1100 | if (!atc_chan_is_enabled(atchan)) { |
dc78baa2 | 1101 | atc_advance_work(atchan); |
dc78baa2 | 1102 | } |
dda36f98 | 1103 | spin_unlock_bh(&atchan->lock); |
dc78baa2 NF |
1104 | } |
1105 | ||
1106 | /** | |
1107 | * atc_alloc_chan_resources - allocate resources for DMA channel | |
1108 | * @chan: allocate descriptor resources for this channel | |
1109 | * @client: current client requesting the channel be ready for requests | |
1110 | * | |
1111 | * return - the number of allocated descriptors | |
1112 | */ | |
1113 | static int atc_alloc_chan_resources(struct dma_chan *chan) | |
1114 | { | |
1115 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1116 | struct at_dma *atdma = to_at_dma(chan->device); | |
1117 | struct at_desc *desc; | |
808347f6 | 1118 | struct at_dma_slave *atslave; |
dc78baa2 | 1119 | int i; |
808347f6 | 1120 | u32 cfg; |
dc78baa2 NF |
1121 | LIST_HEAD(tmp_list); |
1122 | ||
1123 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); | |
1124 | ||
1125 | /* ASSERT: channel is idle */ | |
1126 | if (atc_chan_is_enabled(atchan)) { | |
1127 | dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); | |
1128 | return -EIO; | |
1129 | } | |
1130 | ||
808347f6 NF |
1131 | cfg = ATC_DEFAULT_CFG; |
1132 | ||
1133 | atslave = chan->private; | |
1134 | if (atslave) { | |
1135 | /* | |
1136 | * We need controller-specific data to set up slave | |
1137 | * transfers. | |
1138 | */ | |
1139 | BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); | |
1140 | ||
1141 | /* if cfg configuration specified take it instad of default */ | |
1142 | if (atslave->cfg) | |
1143 | cfg = atslave->cfg; | |
1144 | } | |
1145 | ||
1146 | /* have we already been set up? | |
1147 | * reconfigure channel but no need to reallocate descriptors */ | |
dc78baa2 NF |
1148 | if (!list_empty(&atchan->free_list)) |
1149 | return atchan->descs_allocated; | |
1150 | ||
1151 | /* Allocate initial pool of descriptors */ | |
1152 | for (i = 0; i < init_nr_desc_per_channel; i++) { | |
1153 | desc = atc_alloc_descriptor(chan, GFP_KERNEL); | |
1154 | if (!desc) { | |
1155 | dev_err(atdma->dma_common.dev, | |
1156 | "Only %d initial descriptors\n", i); | |
1157 | break; | |
1158 | } | |
1159 | list_add_tail(&desc->desc_node, &tmp_list); | |
1160 | } | |
1161 | ||
1162 | spin_lock_bh(&atchan->lock); | |
1163 | atchan->descs_allocated = i; | |
1164 | list_splice(&tmp_list, &atchan->free_list); | |
1165 | atchan->completed_cookie = chan->cookie = 1; | |
1166 | spin_unlock_bh(&atchan->lock); | |
1167 | ||
1168 | /* channel parameters */ | |
808347f6 | 1169 | channel_writel(atchan, CFG, cfg); |
dc78baa2 NF |
1170 | |
1171 | dev_dbg(chan2dev(chan), | |
1172 | "alloc_chan_resources: allocated %d descriptors\n", | |
1173 | atchan->descs_allocated); | |
1174 | ||
1175 | return atchan->descs_allocated; | |
1176 | } | |
1177 | ||
1178 | /** | |
1179 | * atc_free_chan_resources - free all channel resources | |
1180 | * @chan: DMA channel | |
1181 | */ | |
1182 | static void atc_free_chan_resources(struct dma_chan *chan) | |
1183 | { | |
1184 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1185 | struct at_dma *atdma = to_at_dma(chan->device); | |
1186 | struct at_desc *desc, *_desc; | |
1187 | LIST_HEAD(list); | |
1188 | ||
1189 | dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", | |
1190 | atchan->descs_allocated); | |
1191 | ||
1192 | /* ASSERT: channel is idle */ | |
1193 | BUG_ON(!list_empty(&atchan->active_list)); | |
1194 | BUG_ON(!list_empty(&atchan->queue)); | |
1195 | BUG_ON(atc_chan_is_enabled(atchan)); | |
1196 | ||
1197 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { | |
1198 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); | |
1199 | list_del(&desc->desc_node); | |
1200 | /* free link descriptor */ | |
1201 | dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); | |
1202 | } | |
1203 | list_splice_init(&atchan->free_list, &list); | |
1204 | atchan->descs_allocated = 0; | |
53830cc7 | 1205 | atchan->status = 0; |
dc78baa2 NF |
1206 | |
1207 | dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); | |
1208 | } | |
1209 | ||
1210 | ||
1211 | /*-- Module Management -----------------------------------------------*/ | |
1212 | ||
1213 | /** | |
1214 | * at_dma_off - disable DMA controller | |
1215 | * @atdma: the Atmel HDAMC device | |
1216 | */ | |
1217 | static void at_dma_off(struct at_dma *atdma) | |
1218 | { | |
1219 | dma_writel(atdma, EN, 0); | |
1220 | ||
1221 | /* disable all interrupts */ | |
1222 | dma_writel(atdma, EBCIDR, -1L); | |
1223 | ||
1224 | /* confirm that all channels are disabled */ | |
1225 | while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) | |
1226 | cpu_relax(); | |
1227 | } | |
1228 | ||
1229 | static int __init at_dma_probe(struct platform_device *pdev) | |
1230 | { | |
1231 | struct at_dma_platform_data *pdata; | |
1232 | struct resource *io; | |
1233 | struct at_dma *atdma; | |
1234 | size_t size; | |
1235 | int irq; | |
1236 | int err; | |
1237 | int i; | |
1238 | ||
1239 | /* get DMA Controller parameters from platform */ | |
1240 | pdata = pdev->dev.platform_data; | |
1241 | if (!pdata || pdata->nr_channels > AT_DMA_MAX_NR_CHANNELS) | |
1242 | return -EINVAL; | |
1243 | ||
1244 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1245 | if (!io) | |
1246 | return -EINVAL; | |
1247 | ||
1248 | irq = platform_get_irq(pdev, 0); | |
1249 | if (irq < 0) | |
1250 | return irq; | |
1251 | ||
1252 | size = sizeof(struct at_dma); | |
1253 | size += pdata->nr_channels * sizeof(struct at_dma_chan); | |
1254 | atdma = kzalloc(size, GFP_KERNEL); | |
1255 | if (!atdma) | |
1256 | return -ENOMEM; | |
1257 | ||
1258 | /* discover transaction capabilites from the platform data */ | |
1259 | atdma->dma_common.cap_mask = pdata->cap_mask; | |
1260 | atdma->all_chan_mask = (1 << pdata->nr_channels) - 1; | |
1261 | ||
1262 | size = io->end - io->start + 1; | |
1263 | if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { | |
1264 | err = -EBUSY; | |
1265 | goto err_kfree; | |
1266 | } | |
1267 | ||
1268 | atdma->regs = ioremap(io->start, size); | |
1269 | if (!atdma->regs) { | |
1270 | err = -ENOMEM; | |
1271 | goto err_release_r; | |
1272 | } | |
1273 | ||
1274 | atdma->clk = clk_get(&pdev->dev, "dma_clk"); | |
1275 | if (IS_ERR(atdma->clk)) { | |
1276 | err = PTR_ERR(atdma->clk); | |
1277 | goto err_clk; | |
1278 | } | |
1279 | clk_enable(atdma->clk); | |
1280 | ||
1281 | /* force dma off, just in case */ | |
1282 | at_dma_off(atdma); | |
1283 | ||
1284 | err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); | |
1285 | if (err) | |
1286 | goto err_irq; | |
1287 | ||
1288 | platform_set_drvdata(pdev, atdma); | |
1289 | ||
1290 | /* create a pool of consistent memory blocks for hardware descriptors */ | |
1291 | atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", | |
1292 | &pdev->dev, sizeof(struct at_desc), | |
1293 | 4 /* word alignment */, 0); | |
1294 | if (!atdma->dma_desc_pool) { | |
1295 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1296 | err = -ENOMEM; | |
1297 | goto err_pool_create; | |
1298 | } | |
1299 | ||
1300 | /* clear any pending interrupt */ | |
1301 | while (dma_readl(atdma, EBCISR)) | |
1302 | cpu_relax(); | |
1303 | ||
1304 | /* initialize channels related values */ | |
1305 | INIT_LIST_HEAD(&atdma->dma_common.channels); | |
1306 | for (i = 0; i < pdata->nr_channels; i++, atdma->dma_common.chancnt++) { | |
1307 | struct at_dma_chan *atchan = &atdma->chan[i]; | |
1308 | ||
1309 | atchan->chan_common.device = &atdma->dma_common; | |
1310 | atchan->chan_common.cookie = atchan->completed_cookie = 1; | |
1311 | atchan->chan_common.chan_id = i; | |
1312 | list_add_tail(&atchan->chan_common.device_node, | |
1313 | &atdma->dma_common.channels); | |
1314 | ||
1315 | atchan->ch_regs = atdma->regs + ch_regs(i); | |
1316 | spin_lock_init(&atchan->lock); | |
1317 | atchan->mask = 1 << i; | |
1318 | ||
1319 | INIT_LIST_HEAD(&atchan->active_list); | |
1320 | INIT_LIST_HEAD(&atchan->queue); | |
1321 | INIT_LIST_HEAD(&atchan->free_list); | |
1322 | ||
1323 | tasklet_init(&atchan->tasklet, atc_tasklet, | |
1324 | (unsigned long)atchan); | |
1325 | atc_enable_irq(atchan); | |
1326 | } | |
1327 | ||
1328 | /* set base routines */ | |
1329 | atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; | |
1330 | atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; | |
07934481 | 1331 | atdma->dma_common.device_tx_status = atc_tx_status; |
dc78baa2 NF |
1332 | atdma->dma_common.device_issue_pending = atc_issue_pending; |
1333 | atdma->dma_common.dev = &pdev->dev; | |
1334 | ||
1335 | /* set prep routines based on capability */ | |
1336 | if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) | |
1337 | atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; | |
1338 | ||
53830cc7 | 1339 | if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) |
808347f6 | 1340 | atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; |
53830cc7 NF |
1341 | |
1342 | if (dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask)) | |
1343 | atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; | |
1344 | ||
1345 | if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) || | |
1346 | dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask)) | |
c3635c78 | 1347 | atdma->dma_common.device_control = atc_control; |
808347f6 | 1348 | |
dc78baa2 NF |
1349 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
1350 | ||
1351 | dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n", | |
1352 | dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", | |
1353 | dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", | |
1354 | atdma->dma_common.chancnt); | |
1355 | ||
1356 | dma_async_device_register(&atdma->dma_common); | |
1357 | ||
1358 | return 0; | |
1359 | ||
1360 | err_pool_create: | |
1361 | platform_set_drvdata(pdev, NULL); | |
1362 | free_irq(platform_get_irq(pdev, 0), atdma); | |
1363 | err_irq: | |
1364 | clk_disable(atdma->clk); | |
1365 | clk_put(atdma->clk); | |
1366 | err_clk: | |
1367 | iounmap(atdma->regs); | |
1368 | atdma->regs = NULL; | |
1369 | err_release_r: | |
1370 | release_mem_region(io->start, size); | |
1371 | err_kfree: | |
1372 | kfree(atdma); | |
1373 | return err; | |
1374 | } | |
1375 | ||
1376 | static int __exit at_dma_remove(struct platform_device *pdev) | |
1377 | { | |
1378 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1379 | struct dma_chan *chan, *_chan; | |
1380 | struct resource *io; | |
1381 | ||
1382 | at_dma_off(atdma); | |
1383 | dma_async_device_unregister(&atdma->dma_common); | |
1384 | ||
1385 | dma_pool_destroy(atdma->dma_desc_pool); | |
1386 | platform_set_drvdata(pdev, NULL); | |
1387 | free_irq(platform_get_irq(pdev, 0), atdma); | |
1388 | ||
1389 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1390 | device_node) { | |
1391 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1392 | ||
1393 | /* Disable interrupts */ | |
1394 | atc_disable_irq(atchan); | |
1395 | tasklet_disable(&atchan->tasklet); | |
1396 | ||
1397 | tasklet_kill(&atchan->tasklet); | |
1398 | list_del(&chan->device_node); | |
1399 | } | |
1400 | ||
1401 | clk_disable(atdma->clk); | |
1402 | clk_put(atdma->clk); | |
1403 | ||
1404 | iounmap(atdma->regs); | |
1405 | atdma->regs = NULL; | |
1406 | ||
1407 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1408 | release_mem_region(io->start, io->end - io->start + 1); | |
1409 | ||
1410 | kfree(atdma); | |
1411 | ||
1412 | return 0; | |
1413 | } | |
1414 | ||
1415 | static void at_dma_shutdown(struct platform_device *pdev) | |
1416 | { | |
1417 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1418 | ||
1419 | at_dma_off(platform_get_drvdata(pdev)); | |
1420 | clk_disable(atdma->clk); | |
1421 | } | |
1422 | ||
33f82d14 | 1423 | static int at_dma_suspend_noirq(struct device *dev) |
dc78baa2 | 1424 | { |
33f82d14 DW |
1425 | struct platform_device *pdev = to_platform_device(dev); |
1426 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
dc78baa2 NF |
1427 | |
1428 | at_dma_off(platform_get_drvdata(pdev)); | |
1429 | clk_disable(atdma->clk); | |
1430 | return 0; | |
1431 | } | |
1432 | ||
33f82d14 | 1433 | static int at_dma_resume_noirq(struct device *dev) |
dc78baa2 | 1434 | { |
33f82d14 DW |
1435 | struct platform_device *pdev = to_platform_device(dev); |
1436 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
dc78baa2 NF |
1437 | |
1438 | clk_enable(atdma->clk); | |
1439 | dma_writel(atdma, EN, AT_DMA_ENABLE); | |
1440 | return 0; | |
dc78baa2 NF |
1441 | } |
1442 | ||
47145210 | 1443 | static const struct dev_pm_ops at_dma_dev_pm_ops = { |
33f82d14 DW |
1444 | .suspend_noirq = at_dma_suspend_noirq, |
1445 | .resume_noirq = at_dma_resume_noirq, | |
1446 | }; | |
1447 | ||
dc78baa2 NF |
1448 | static struct platform_driver at_dma_driver = { |
1449 | .remove = __exit_p(at_dma_remove), | |
1450 | .shutdown = at_dma_shutdown, | |
dc78baa2 NF |
1451 | .driver = { |
1452 | .name = "at_hdmac", | |
33f82d14 | 1453 | .pm = &at_dma_dev_pm_ops, |
dc78baa2 NF |
1454 | }, |
1455 | }; | |
1456 | ||
1457 | static int __init at_dma_init(void) | |
1458 | { | |
1459 | return platform_driver_probe(&at_dma_driver, at_dma_probe); | |
1460 | } | |
93d0bec2 | 1461 | subsys_initcall(at_dma_init); |
dc78baa2 NF |
1462 | |
1463 | static void __exit at_dma_exit(void) | |
1464 | { | |
1465 | platform_driver_unregister(&at_dma_driver); | |
1466 | } | |
1467 | module_exit(at_dma_exit); | |
1468 | ||
1469 | MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); | |
1470 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); | |
1471 | MODULE_LICENSE("GPL"); | |
1472 | MODULE_ALIAS("platform:at_hdmac"); |