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Commit | Line | Data |
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dc78baa2 NF |
1 | /* |
2 | * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) | |
3 | * | |
4 | * Copyright (C) 2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * | |
9102d871 NF |
12 | * This supports the Atmel AHB DMA Controller found in several Atmel SoCs. |
13 | * The only Atmel DMA Controller that is not covered by this driver is the one | |
14 | * found on AT91SAM9263. | |
dc78baa2 NF |
15 | */ |
16 | ||
62971b29 | 17 | #include <dt-bindings/dma/at91.h> |
dc78baa2 NF |
18 | #include <linux/clk.h> |
19 | #include <linux/dmaengine.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
c5115953 NF |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
bbe89c8e | 28 | #include <linux/of_dma.h> |
dc78baa2 NF |
29 | |
30 | #include "at_hdmac_regs.h" | |
d2ebfb33 | 31 | #include "dmaengine.h" |
dc78baa2 NF |
32 | |
33 | /* | |
34 | * Glossary | |
35 | * -------- | |
36 | * | |
37 | * at_hdmac : Name of the ATmel AHB DMA Controller | |
38 | * at_dma_ / atdma : ATmel DMA controller entity related | |
39 | * atc_ / atchan : ATmel DMA Channel entity related | |
40 | */ | |
41 | ||
42 | #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) | |
ae14d4b5 NF |
43 | #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ |
44 | |ATC_DIF(AT_DMA_MEM_IF)) | |
dc78baa2 NF |
45 | |
46 | /* | |
47 | * Initial number of descriptors to allocate for each channel. This could | |
48 | * be increased during dma usage. | |
49 | */ | |
50 | static unsigned int init_nr_desc_per_channel = 64; | |
51 | module_param(init_nr_desc_per_channel, uint, 0644); | |
52 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
53 | "initial descriptors per channel (default: 64)"); | |
54 | ||
55 | ||
56 | /* prototypes */ | |
57 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); | |
d48de6f1 | 58 | static void atc_issue_pending(struct dma_chan *chan); |
dc78baa2 NF |
59 | |
60 | ||
61 | /*----------------------------------------------------------------------*/ | |
62 | ||
63 | static struct at_desc *atc_first_active(struct at_dma_chan *atchan) | |
64 | { | |
65 | return list_first_entry(&atchan->active_list, | |
66 | struct at_desc, desc_node); | |
67 | } | |
68 | ||
69 | static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) | |
70 | { | |
71 | return list_first_entry(&atchan->queue, | |
72 | struct at_desc, desc_node); | |
73 | } | |
74 | ||
75 | /** | |
421f91d2 | 76 | * atc_alloc_descriptor - allocate and return an initialized descriptor |
dc78baa2 NF |
77 | * @chan: the channel to allocate descriptors for |
78 | * @gfp_flags: GFP allocation flags | |
79 | * | |
80 | * Note: The ack-bit is positioned in the descriptor flag at creation time | |
81 | * to make initial allocation more convenient. This bit will be cleared | |
82 | * and control will be given to client at usage time (during | |
83 | * preparation functions). | |
84 | */ | |
85 | static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, | |
86 | gfp_t gfp_flags) | |
87 | { | |
88 | struct at_desc *desc = NULL; | |
89 | struct at_dma *atdma = to_at_dma(chan->device); | |
90 | dma_addr_t phys; | |
91 | ||
92 | desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); | |
93 | if (desc) { | |
94 | memset(desc, 0, sizeof(struct at_desc)); | |
285a3c71 | 95 | INIT_LIST_HEAD(&desc->tx_list); |
dc78baa2 NF |
96 | dma_async_tx_descriptor_init(&desc->txd, chan); |
97 | /* txd.flags will be overwritten in prep functions */ | |
98 | desc->txd.flags = DMA_CTRL_ACK; | |
99 | desc->txd.tx_submit = atc_tx_submit; | |
100 | desc->txd.phys = phys; | |
101 | } | |
102 | ||
103 | return desc; | |
104 | } | |
105 | ||
106 | /** | |
af901ca1 | 107 | * atc_desc_get - get an unused descriptor from free_list |
dc78baa2 NF |
108 | * @atchan: channel we want a new descriptor for |
109 | */ | |
110 | static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) | |
111 | { | |
112 | struct at_desc *desc, *_desc; | |
113 | struct at_desc *ret = NULL; | |
d8cb04b0 | 114 | unsigned long flags; |
dc78baa2 NF |
115 | unsigned int i = 0; |
116 | LIST_HEAD(tmp_list); | |
117 | ||
d8cb04b0 | 118 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
119 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { |
120 | i++; | |
121 | if (async_tx_test_ack(&desc->txd)) { | |
122 | list_del(&desc->desc_node); | |
123 | ret = desc; | |
124 | break; | |
125 | } | |
126 | dev_dbg(chan2dev(&atchan->chan_common), | |
127 | "desc %p not ACKed\n", desc); | |
128 | } | |
d8cb04b0 | 129 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
130 | dev_vdbg(chan2dev(&atchan->chan_common), |
131 | "scanned %u descriptors on freelist\n", i); | |
132 | ||
133 | /* no more descriptor available in initial pool: create one more */ | |
134 | if (!ret) { | |
135 | ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); | |
136 | if (ret) { | |
d8cb04b0 | 137 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 138 | atchan->descs_allocated++; |
d8cb04b0 | 139 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
140 | } else { |
141 | dev_err(chan2dev(&atchan->chan_common), | |
142 | "not enough descriptors available\n"); | |
143 | } | |
144 | } | |
145 | ||
146 | return ret; | |
147 | } | |
148 | ||
149 | /** | |
150 | * atc_desc_put - move a descriptor, including any children, to the free list | |
151 | * @atchan: channel we work on | |
152 | * @desc: descriptor, at the head of a chain, to move to free list | |
153 | */ | |
154 | static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) | |
155 | { | |
156 | if (desc) { | |
157 | struct at_desc *child; | |
d8cb04b0 | 158 | unsigned long flags; |
dc78baa2 | 159 | |
d8cb04b0 | 160 | spin_lock_irqsave(&atchan->lock, flags); |
285a3c71 | 161 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
162 | dev_vdbg(chan2dev(&atchan->chan_common), |
163 | "moving child desc %p to freelist\n", | |
164 | child); | |
285a3c71 | 165 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
166 | dev_vdbg(chan2dev(&atchan->chan_common), |
167 | "moving desc %p to freelist\n", desc); | |
168 | list_add(&desc->desc_node, &atchan->free_list); | |
d8cb04b0 | 169 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
170 | } |
171 | } | |
172 | ||
53830cc7 | 173 | /** |
d73111c6 MI |
174 | * atc_desc_chain - build chain adding a descriptor |
175 | * @first: address of first descriptor of the chain | |
176 | * @prev: address of previous descriptor of the chain | |
53830cc7 NF |
177 | * @desc: descriptor to queue |
178 | * | |
179 | * Called from prep_* functions | |
180 | */ | |
181 | static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, | |
182 | struct at_desc *desc) | |
183 | { | |
184 | if (!(*first)) { | |
185 | *first = desc; | |
186 | } else { | |
187 | /* inform the HW lli about chaining */ | |
188 | (*prev)->lli.dscr = desc->txd.phys; | |
189 | /* insert the link descriptor to the LD ring */ | |
190 | list_add_tail(&desc->desc_node, | |
191 | &(*first)->tx_list); | |
192 | } | |
193 | *prev = desc; | |
194 | } | |
195 | ||
dc78baa2 NF |
196 | /** |
197 | * atc_dostart - starts the DMA engine for real | |
198 | * @atchan: the channel we want to start | |
199 | * @first: first descriptor in the list we want to begin with | |
200 | * | |
201 | * Called with atchan->lock held and bh disabled | |
202 | */ | |
203 | static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) | |
204 | { | |
205 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
206 | ||
207 | /* ASSERT: channel is idle */ | |
208 | if (atc_chan_is_enabled(atchan)) { | |
209 | dev_err(chan2dev(&atchan->chan_common), | |
210 | "BUG: Attempted to start non-idle channel\n"); | |
211 | dev_err(chan2dev(&atchan->chan_common), | |
212 | " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", | |
213 | channel_readl(atchan, SADDR), | |
214 | channel_readl(atchan, DADDR), | |
215 | channel_readl(atchan, CTRLA), | |
216 | channel_readl(atchan, CTRLB), | |
217 | channel_readl(atchan, DSCR)); | |
218 | ||
219 | /* The tasklet will hopefully advance the queue... */ | |
220 | return; | |
221 | } | |
222 | ||
223 | vdbg_dump_regs(atchan); | |
224 | ||
dc78baa2 NF |
225 | channel_writel(atchan, SADDR, 0); |
226 | channel_writel(atchan, DADDR, 0); | |
227 | channel_writel(atchan, CTRLA, 0); | |
228 | channel_writel(atchan, CTRLB, 0); | |
229 | channel_writel(atchan, DSCR, first->txd.phys); | |
230 | dma_writel(atdma, CHER, atchan->mask); | |
231 | ||
232 | vdbg_dump_regs(atchan); | |
233 | } | |
234 | ||
d48de6f1 ES |
235 | /* |
236 | * atc_get_current_descriptors - | |
237 | * locate the descriptor which equal to physical address in DSCR | |
238 | * @atchan: the channel we want to start | |
239 | * @dscr_addr: physical descriptor address in DSCR | |
240 | */ | |
241 | static struct at_desc *atc_get_current_descriptors(struct at_dma_chan *atchan, | |
242 | u32 dscr_addr) | |
243 | { | |
244 | struct at_desc *desc, *_desc, *child, *desc_cur = NULL; | |
245 | ||
246 | list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { | |
247 | if (desc->lli.dscr == dscr_addr) { | |
248 | desc_cur = desc; | |
249 | break; | |
250 | } | |
251 | ||
252 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
253 | if (child->lli.dscr == dscr_addr) { | |
254 | desc_cur = child; | |
255 | break; | |
256 | } | |
257 | } | |
258 | } | |
259 | ||
260 | return desc_cur; | |
261 | } | |
262 | ||
263 | /* | |
264 | * atc_get_bytes_left - | |
265 | * Get the number of bytes residue in dma buffer, | |
266 | * @chan: the channel we want to start | |
267 | */ | |
268 | static int atc_get_bytes_left(struct dma_chan *chan) | |
269 | { | |
270 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
271 | struct at_dma *atdma = to_at_dma(chan->device); | |
272 | int chan_id = atchan->chan_common.chan_id; | |
273 | struct at_desc *desc_first = atc_first_active(atchan); | |
274 | struct at_desc *desc_cur; | |
275 | int ret = 0, count = 0; | |
276 | ||
277 | /* | |
278 | * Initialize necessary values in the first time. | |
279 | * remain_desc record remain desc length. | |
280 | */ | |
281 | if (atchan->remain_desc == 0) | |
282 | /* First descriptor embedds the transaction length */ | |
283 | atchan->remain_desc = desc_first->len; | |
284 | ||
285 | /* | |
286 | * This happens when current descriptor transfer complete. | |
287 | * The residual buffer size should reduce current descriptor length. | |
288 | */ | |
289 | if (unlikely(test_bit(ATC_IS_BTC, &atchan->status))) { | |
290 | clear_bit(ATC_IS_BTC, &atchan->status); | |
291 | desc_cur = atc_get_current_descriptors(atchan, | |
292 | channel_readl(atchan, DSCR)); | |
293 | if (!desc_cur) { | |
294 | ret = -EINVAL; | |
295 | goto out; | |
296 | } | |
297 | atchan->remain_desc -= (desc_cur->lli.ctrla & ATC_BTSIZE_MAX) | |
298 | << (desc_first->tx_width); | |
299 | if (atchan->remain_desc < 0) { | |
300 | ret = -EINVAL; | |
301 | goto out; | |
302 | } else | |
303 | ret = atchan->remain_desc; | |
304 | } else { | |
305 | /* | |
306 | * Get residual bytes when current | |
307 | * descriptor transfer in progress. | |
308 | */ | |
309 | count = (channel_readl(atchan, CTRLA) & ATC_BTSIZE_MAX) | |
310 | << (desc_first->tx_width); | |
311 | ret = atchan->remain_desc - count; | |
312 | } | |
313 | /* | |
314 | * Check fifo empty. | |
315 | */ | |
316 | if (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id))) | |
317 | atc_issue_pending(chan); | |
318 | ||
319 | out: | |
320 | return ret; | |
321 | } | |
322 | ||
dc78baa2 NF |
323 | /** |
324 | * atc_chain_complete - finish work for one transaction chain | |
325 | * @atchan: channel we work on | |
326 | * @desc: descriptor at the head of the chain we want do complete | |
327 | * | |
328 | * Called with atchan->lock held and bh disabled */ | |
329 | static void | |
330 | atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) | |
331 | { | |
dc78baa2 NF |
332 | struct dma_async_tx_descriptor *txd = &desc->txd; |
333 | ||
334 | dev_vdbg(chan2dev(&atchan->chan_common), | |
335 | "descriptor %u complete\n", txd->cookie); | |
336 | ||
d4116052 VK |
337 | /* mark the descriptor as complete for non cyclic cases only */ |
338 | if (!atc_chan_is_cyclic(atchan)) | |
339 | dma_cookie_complete(txd); | |
dc78baa2 NF |
340 | |
341 | /* move children to free_list */ | |
285a3c71 | 342 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
343 | /* move myself to free_list */ |
344 | list_move(&desc->desc_node, &atchan->free_list); | |
345 | ||
ebcf9b80 | 346 | /* unmap dma addresses (not on slave channels) */ |
657a77fa AN |
347 | if (!atchan->chan_common.private) { |
348 | struct device *parent = chan2parent(&atchan->chan_common); | |
349 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
350 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
351 | dma_unmap_single(parent, | |
352 | desc->lli.daddr, | |
353 | desc->len, DMA_FROM_DEVICE); | |
354 | else | |
355 | dma_unmap_page(parent, | |
356 | desc->lli.daddr, | |
357 | desc->len, DMA_FROM_DEVICE); | |
358 | } | |
359 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
360 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
361 | dma_unmap_single(parent, | |
362 | desc->lli.saddr, | |
363 | desc->len, DMA_TO_DEVICE); | |
364 | else | |
365 | dma_unmap_page(parent, | |
366 | desc->lli.saddr, | |
367 | desc->len, DMA_TO_DEVICE); | |
368 | } | |
dc78baa2 NF |
369 | } |
370 | ||
53830cc7 NF |
371 | /* for cyclic transfers, |
372 | * no need to replay callback function while stopping */ | |
3c477482 | 373 | if (!atc_chan_is_cyclic(atchan)) { |
53830cc7 NF |
374 | dma_async_tx_callback callback = txd->callback; |
375 | void *param = txd->callback_param; | |
376 | ||
377 | /* | |
378 | * The API requires that no submissions are done from a | |
379 | * callback, so we don't need to drop the lock here | |
380 | */ | |
381 | if (callback) | |
382 | callback(param); | |
383 | } | |
dc78baa2 NF |
384 | |
385 | dma_run_dependencies(txd); | |
386 | } | |
387 | ||
388 | /** | |
389 | * atc_complete_all - finish work for all transactions | |
390 | * @atchan: channel to complete transactions for | |
391 | * | |
392 | * Eventually submit queued descriptors if any | |
393 | * | |
394 | * Assume channel is idle while calling this function | |
395 | * Called with atchan->lock held and bh disabled | |
396 | */ | |
397 | static void atc_complete_all(struct at_dma_chan *atchan) | |
398 | { | |
399 | struct at_desc *desc, *_desc; | |
400 | LIST_HEAD(list); | |
401 | ||
402 | dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); | |
403 | ||
dc78baa2 NF |
404 | /* |
405 | * Submit queued descriptors ASAP, i.e. before we go through | |
406 | * the completed ones. | |
407 | */ | |
408 | if (!list_empty(&atchan->queue)) | |
409 | atc_dostart(atchan, atc_first_queued(atchan)); | |
410 | /* empty active_list now it is completed */ | |
411 | list_splice_init(&atchan->active_list, &list); | |
412 | /* empty queue list by moving descriptors (if any) to active_list */ | |
413 | list_splice_init(&atchan->queue, &atchan->active_list); | |
414 | ||
415 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
416 | atc_chain_complete(atchan, desc); | |
417 | } | |
418 | ||
dc78baa2 NF |
419 | /** |
420 | * atc_advance_work - at the end of a transaction, move forward | |
421 | * @atchan: channel where the transaction ended | |
422 | * | |
423 | * Called with atchan->lock held and bh disabled | |
424 | */ | |
425 | static void atc_advance_work(struct at_dma_chan *atchan) | |
426 | { | |
427 | dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); | |
428 | ||
d202f051 LD |
429 | if (atc_chan_is_enabled(atchan)) |
430 | return; | |
431 | ||
dc78baa2 NF |
432 | if (list_empty(&atchan->active_list) || |
433 | list_is_singular(&atchan->active_list)) { | |
434 | atc_complete_all(atchan); | |
435 | } else { | |
436 | atc_chain_complete(atchan, atc_first_active(atchan)); | |
437 | /* advance work */ | |
438 | atc_dostart(atchan, atc_first_active(atchan)); | |
439 | } | |
440 | } | |
441 | ||
442 | ||
443 | /** | |
444 | * atc_handle_error - handle errors reported by DMA controller | |
445 | * @atchan: channel where error occurs | |
446 | * | |
447 | * Called with atchan->lock held and bh disabled | |
448 | */ | |
449 | static void atc_handle_error(struct at_dma_chan *atchan) | |
450 | { | |
451 | struct at_desc *bad_desc; | |
452 | struct at_desc *child; | |
453 | ||
454 | /* | |
455 | * The descriptor currently at the head of the active list is | |
456 | * broked. Since we don't have any way to report errors, we'll | |
457 | * just have to scream loudly and try to carry on. | |
458 | */ | |
459 | bad_desc = atc_first_active(atchan); | |
460 | list_del_init(&bad_desc->desc_node); | |
461 | ||
462 | /* As we are stopped, take advantage to push queued descriptors | |
463 | * in active_list */ | |
464 | list_splice_init(&atchan->queue, atchan->active_list.prev); | |
465 | ||
466 | /* Try to restart the controller */ | |
467 | if (!list_empty(&atchan->active_list)) | |
468 | atc_dostart(atchan, atc_first_active(atchan)); | |
469 | ||
470 | /* | |
471 | * KERN_CRITICAL may seem harsh, but since this only happens | |
472 | * when someone submits a bad physical address in a | |
473 | * descriptor, we should consider ourselves lucky that the | |
474 | * controller flagged an error instead of scribbling over | |
475 | * random memory locations. | |
476 | */ | |
477 | dev_crit(chan2dev(&atchan->chan_common), | |
478 | "Bad descriptor submitted for DMA!\n"); | |
479 | dev_crit(chan2dev(&atchan->chan_common), | |
480 | " cookie: %d\n", bad_desc->txd.cookie); | |
481 | atc_dump_lli(atchan, &bad_desc->lli); | |
285a3c71 | 482 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
dc78baa2 NF |
483 | atc_dump_lli(atchan, &child->lli); |
484 | ||
485 | /* Pretend the descriptor completed successfully */ | |
486 | atc_chain_complete(atchan, bad_desc); | |
487 | } | |
488 | ||
53830cc7 NF |
489 | /** |
490 | * atc_handle_cyclic - at the end of a period, run callback function | |
491 | * @atchan: channel used for cyclic operations | |
492 | * | |
493 | * Called with atchan->lock held and bh disabled | |
494 | */ | |
495 | static void atc_handle_cyclic(struct at_dma_chan *atchan) | |
496 | { | |
497 | struct at_desc *first = atc_first_active(atchan); | |
498 | struct dma_async_tx_descriptor *txd = &first->txd; | |
499 | dma_async_tx_callback callback = txd->callback; | |
500 | void *param = txd->callback_param; | |
501 | ||
502 | dev_vdbg(chan2dev(&atchan->chan_common), | |
503 | "new cyclic period llp 0x%08x\n", | |
504 | channel_readl(atchan, DSCR)); | |
505 | ||
506 | if (callback) | |
507 | callback(param); | |
508 | } | |
dc78baa2 NF |
509 | |
510 | /*-- IRQ & Tasklet ---------------------------------------------------*/ | |
511 | ||
512 | static void atc_tasklet(unsigned long data) | |
513 | { | |
514 | struct at_dma_chan *atchan = (struct at_dma_chan *)data; | |
d8cb04b0 | 515 | unsigned long flags; |
dc78baa2 | 516 | |
d8cb04b0 | 517 | spin_lock_irqsave(&atchan->lock, flags); |
53830cc7 | 518 | if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) |
dc78baa2 | 519 | atc_handle_error(atchan); |
3c477482 | 520 | else if (atc_chan_is_cyclic(atchan)) |
53830cc7 | 521 | atc_handle_cyclic(atchan); |
dc78baa2 NF |
522 | else |
523 | atc_advance_work(atchan); | |
524 | ||
d8cb04b0 | 525 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
526 | } |
527 | ||
528 | static irqreturn_t at_dma_interrupt(int irq, void *dev_id) | |
529 | { | |
530 | struct at_dma *atdma = (struct at_dma *)dev_id; | |
531 | struct at_dma_chan *atchan; | |
532 | int i; | |
533 | u32 status, pending, imr; | |
534 | int ret = IRQ_NONE; | |
535 | ||
536 | do { | |
537 | imr = dma_readl(atdma, EBCIMR); | |
538 | status = dma_readl(atdma, EBCISR); | |
539 | pending = status & imr; | |
540 | ||
541 | if (!pending) | |
542 | break; | |
543 | ||
544 | dev_vdbg(atdma->dma_common.dev, | |
545 | "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", | |
546 | status, imr, pending); | |
547 | ||
548 | for (i = 0; i < atdma->dma_common.chancnt; i++) { | |
549 | atchan = &atdma->chan[i]; | |
9b3aa589 | 550 | if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { |
dc78baa2 NF |
551 | if (pending & AT_DMA_ERR(i)) { |
552 | /* Disable channel on AHB error */ | |
23b5e3ad NF |
553 | dma_writel(atdma, CHDR, |
554 | AT_DMA_RES(i) | atchan->mask); | |
dc78baa2 | 555 | /* Give information to tasklet */ |
53830cc7 | 556 | set_bit(ATC_IS_ERROR, &atchan->status); |
dc78baa2 | 557 | } |
d48de6f1 ES |
558 | if (pending & AT_DMA_BTC(i)) |
559 | set_bit(ATC_IS_BTC, &atchan->status); | |
dc78baa2 NF |
560 | tasklet_schedule(&atchan->tasklet); |
561 | ret = IRQ_HANDLED; | |
562 | } | |
563 | } | |
564 | ||
565 | } while (pending); | |
566 | ||
567 | return ret; | |
568 | } | |
569 | ||
570 | ||
571 | /*-- DMA Engine API --------------------------------------------------*/ | |
572 | ||
573 | /** | |
574 | * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine | |
575 | * @desc: descriptor at the head of the transaction chain | |
576 | * | |
577 | * Queue chain if DMA engine is working already | |
578 | * | |
579 | * Cookie increment and adding to active_list or queue must be atomic | |
580 | */ | |
581 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) | |
582 | { | |
583 | struct at_desc *desc = txd_to_at_desc(tx); | |
584 | struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); | |
585 | dma_cookie_t cookie; | |
d8cb04b0 | 586 | unsigned long flags; |
dc78baa2 | 587 | |
d8cb04b0 | 588 | spin_lock_irqsave(&atchan->lock, flags); |
884485e1 | 589 | cookie = dma_cookie_assign(tx); |
dc78baa2 NF |
590 | |
591 | if (list_empty(&atchan->active_list)) { | |
592 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", | |
593 | desc->txd.cookie); | |
594 | atc_dostart(atchan, desc); | |
595 | list_add_tail(&desc->desc_node, &atchan->active_list); | |
596 | } else { | |
597 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", | |
598 | desc->txd.cookie); | |
599 | list_add_tail(&desc->desc_node, &atchan->queue); | |
600 | } | |
601 | ||
d8cb04b0 | 602 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
603 | |
604 | return cookie; | |
605 | } | |
606 | ||
607 | /** | |
608 | * atc_prep_dma_memcpy - prepare a memcpy operation | |
609 | * @chan: the channel to prepare operation on | |
610 | * @dest: operation virtual destination address | |
611 | * @src: operation virtual source address | |
612 | * @len: operation length | |
613 | * @flags: tx descriptor status flags | |
614 | */ | |
615 | static struct dma_async_tx_descriptor * | |
616 | atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
617 | size_t len, unsigned long flags) | |
618 | { | |
619 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
620 | struct at_desc *desc = NULL; | |
621 | struct at_desc *first = NULL; | |
622 | struct at_desc *prev = NULL; | |
623 | size_t xfer_count; | |
624 | size_t offset; | |
625 | unsigned int src_width; | |
626 | unsigned int dst_width; | |
627 | u32 ctrla; | |
628 | u32 ctrlb; | |
629 | ||
630 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", | |
631 | dest, src, len, flags); | |
632 | ||
633 | if (unlikely(!len)) { | |
634 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
635 | return NULL; | |
636 | } | |
637 | ||
9b3aa589 | 638 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
dc78baa2 NF |
639 | | ATC_SRC_ADDR_MODE_INCR |
640 | | ATC_DST_ADDR_MODE_INCR | |
641 | | ATC_FC_MEM2MEM; | |
642 | ||
643 | /* | |
644 | * We can be a lot more clever here, but this should take care | |
645 | * of the most common optimization. | |
646 | */ | |
647 | if (!((src | dest | len) & 3)) { | |
b409ebfb | 648 | ctrla = ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; |
dc78baa2 NF |
649 | src_width = dst_width = 2; |
650 | } else if (!((src | dest | len) & 1)) { | |
b409ebfb | 651 | ctrla = ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; |
dc78baa2 NF |
652 | src_width = dst_width = 1; |
653 | } else { | |
b409ebfb | 654 | ctrla = ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; |
dc78baa2 NF |
655 | src_width = dst_width = 0; |
656 | } | |
657 | ||
658 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
659 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
660 | ATC_BTSIZE_MAX); | |
661 | ||
662 | desc = atc_desc_get(atchan); | |
663 | if (!desc) | |
664 | goto err_desc_get; | |
665 | ||
666 | desc->lli.saddr = src + offset; | |
667 | desc->lli.daddr = dest + offset; | |
668 | desc->lli.ctrla = ctrla | xfer_count; | |
669 | desc->lli.ctrlb = ctrlb; | |
670 | ||
671 | desc->txd.cookie = 0; | |
dc78baa2 | 672 | |
e257e156 | 673 | atc_desc_chain(&first, &prev, desc); |
dc78baa2 NF |
674 | } |
675 | ||
676 | /* First descriptor of the chain embedds additional information */ | |
677 | first->txd.cookie = -EBUSY; | |
678 | first->len = len; | |
d088c33b | 679 | first->tx_width = src_width; |
dc78baa2 NF |
680 | |
681 | /* set end-of-link to the last link descriptor of list*/ | |
682 | set_desc_eol(desc); | |
683 | ||
568f7f0c | 684 | first->txd.flags = flags; /* client is in control of this ack */ |
dc78baa2 NF |
685 | |
686 | return &first->txd; | |
687 | ||
688 | err_desc_get: | |
689 | atc_desc_put(atchan, first); | |
690 | return NULL; | |
691 | } | |
692 | ||
808347f6 NF |
693 | |
694 | /** | |
695 | * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
696 | * @chan: DMA channel | |
697 | * @sgl: scatterlist to transfer to/from | |
698 | * @sg_len: number of entries in @scatterlist | |
699 | * @direction: DMA direction | |
700 | * @flags: tx descriptor status flags | |
185ecb5f | 701 | * @context: transaction context (ignored) |
808347f6 NF |
702 | */ |
703 | static struct dma_async_tx_descriptor * | |
704 | atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 705 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 706 | unsigned long flags, void *context) |
808347f6 NF |
707 | { |
708 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
709 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 710 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
808347f6 NF |
711 | struct at_desc *first = NULL; |
712 | struct at_desc *prev = NULL; | |
713 | u32 ctrla; | |
714 | u32 ctrlb; | |
715 | dma_addr_t reg; | |
716 | unsigned int reg_width; | |
717 | unsigned int mem_width; | |
718 | unsigned int i; | |
719 | struct scatterlist *sg; | |
720 | size_t total_len = 0; | |
721 | ||
cc52a10a NF |
722 | dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", |
723 | sg_len, | |
db8196df | 724 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
808347f6 NF |
725 | flags); |
726 | ||
727 | if (unlikely(!atslave || !sg_len)) { | |
c618a9be | 728 | dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n"); |
808347f6 NF |
729 | return NULL; |
730 | } | |
731 | ||
1dd1ea8e NF |
732 | ctrla = ATC_SCSIZE(sconfig->src_maxburst) |
733 | | ATC_DCSIZE(sconfig->dst_maxburst); | |
ae14d4b5 | 734 | ctrlb = ATC_IEN; |
808347f6 NF |
735 | |
736 | switch (direction) { | |
db8196df | 737 | case DMA_MEM_TO_DEV: |
beeaa103 | 738 | reg_width = convert_buswidth(sconfig->dst_addr_width); |
808347f6 NF |
739 | ctrla |= ATC_DST_WIDTH(reg_width); |
740 | ctrlb |= ATC_DST_ADDR_MODE_FIXED | |
741 | | ATC_SRC_ADDR_MODE_INCR | |
ae14d4b5 | 742 | | ATC_FC_MEM2PER |
bbe89c8e | 743 | | ATC_SIF(atchan->mem_if) | ATC_DIF(atchan->per_if); |
beeaa103 | 744 | reg = sconfig->dst_addr; |
808347f6 NF |
745 | for_each_sg(sgl, sg, sg_len, i) { |
746 | struct at_desc *desc; | |
747 | u32 len; | |
748 | u32 mem; | |
749 | ||
750 | desc = atc_desc_get(atchan); | |
751 | if (!desc) | |
752 | goto err_desc_get; | |
753 | ||
0f70e8ce | 754 | mem = sg_dma_address(sg); |
808347f6 | 755 | len = sg_dma_len(sg); |
c4567976 NF |
756 | if (unlikely(!len)) { |
757 | dev_dbg(chan2dev(chan), | |
758 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
759 | goto err; | |
760 | } | |
808347f6 NF |
761 | mem_width = 2; |
762 | if (unlikely(mem & 3 || len & 3)) | |
763 | mem_width = 0; | |
764 | ||
765 | desc->lli.saddr = mem; | |
766 | desc->lli.daddr = reg; | |
767 | desc->lli.ctrla = ctrla | |
768 | | ATC_SRC_WIDTH(mem_width) | |
769 | | len >> mem_width; | |
770 | desc->lli.ctrlb = ctrlb; | |
771 | ||
e257e156 | 772 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
773 | total_len += len; |
774 | } | |
775 | break; | |
db8196df | 776 | case DMA_DEV_TO_MEM: |
beeaa103 | 777 | reg_width = convert_buswidth(sconfig->src_addr_width); |
808347f6 NF |
778 | ctrla |= ATC_SRC_WIDTH(reg_width); |
779 | ctrlb |= ATC_DST_ADDR_MODE_INCR | |
780 | | ATC_SRC_ADDR_MODE_FIXED | |
ae14d4b5 | 781 | | ATC_FC_PER2MEM |
bbe89c8e | 782 | | ATC_SIF(atchan->per_if) | ATC_DIF(atchan->mem_if); |
808347f6 | 783 | |
beeaa103 | 784 | reg = sconfig->src_addr; |
808347f6 NF |
785 | for_each_sg(sgl, sg, sg_len, i) { |
786 | struct at_desc *desc; | |
787 | u32 len; | |
788 | u32 mem; | |
789 | ||
790 | desc = atc_desc_get(atchan); | |
791 | if (!desc) | |
792 | goto err_desc_get; | |
793 | ||
0f70e8ce | 794 | mem = sg_dma_address(sg); |
808347f6 | 795 | len = sg_dma_len(sg); |
c4567976 NF |
796 | if (unlikely(!len)) { |
797 | dev_dbg(chan2dev(chan), | |
798 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
799 | goto err; | |
800 | } | |
808347f6 NF |
801 | mem_width = 2; |
802 | if (unlikely(mem & 3 || len & 3)) | |
803 | mem_width = 0; | |
804 | ||
805 | desc->lli.saddr = reg; | |
806 | desc->lli.daddr = mem; | |
807 | desc->lli.ctrla = ctrla | |
808 | | ATC_DST_WIDTH(mem_width) | |
59a609d9 | 809 | | len >> reg_width; |
808347f6 NF |
810 | desc->lli.ctrlb = ctrlb; |
811 | ||
e257e156 | 812 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
813 | total_len += len; |
814 | } | |
815 | break; | |
816 | default: | |
817 | return NULL; | |
818 | } | |
819 | ||
820 | /* set end-of-link to the last link descriptor of list*/ | |
821 | set_desc_eol(prev); | |
822 | ||
823 | /* First descriptor of the chain embedds additional information */ | |
824 | first->txd.cookie = -EBUSY; | |
825 | first->len = total_len; | |
d088c33b | 826 | first->tx_width = reg_width; |
808347f6 | 827 | |
568f7f0c NF |
828 | /* first link descriptor of list is responsible of flags */ |
829 | first->txd.flags = flags; /* client is in control of this ack */ | |
808347f6 NF |
830 | |
831 | return &first->txd; | |
832 | ||
833 | err_desc_get: | |
834 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
c4567976 | 835 | err: |
808347f6 NF |
836 | atc_desc_put(atchan, first); |
837 | return NULL; | |
838 | } | |
839 | ||
53830cc7 NF |
840 | /** |
841 | * atc_dma_cyclic_check_values | |
842 | * Check for too big/unaligned periods and unaligned DMA buffer | |
843 | */ | |
844 | static int | |
845 | atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, | |
0e7264cc | 846 | size_t period_len) |
53830cc7 NF |
847 | { |
848 | if (period_len > (ATC_BTSIZE_MAX << reg_width)) | |
849 | goto err_out; | |
850 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
851 | goto err_out; | |
852 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
853 | goto err_out; | |
53830cc7 NF |
854 | |
855 | return 0; | |
856 | ||
857 | err_out: | |
858 | return -EINVAL; | |
859 | } | |
860 | ||
861 | /** | |
d73111c6 | 862 | * atc_dma_cyclic_fill_desc - Fill one period descriptor |
53830cc7 NF |
863 | */ |
864 | static int | |
beeaa103 | 865 | atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc, |
53830cc7 | 866 | unsigned int period_index, dma_addr_t buf_addr, |
beeaa103 NF |
867 | unsigned int reg_width, size_t period_len, |
868 | enum dma_transfer_direction direction) | |
53830cc7 | 869 | { |
beeaa103 | 870 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
beeaa103 NF |
871 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
872 | u32 ctrla; | |
53830cc7 NF |
873 | |
874 | /* prepare common CRTLA value */ | |
1dd1ea8e NF |
875 | ctrla = ATC_SCSIZE(sconfig->src_maxburst) |
876 | | ATC_DCSIZE(sconfig->dst_maxburst) | |
53830cc7 NF |
877 | | ATC_DST_WIDTH(reg_width) |
878 | | ATC_SRC_WIDTH(reg_width) | |
879 | | period_len >> reg_width; | |
880 | ||
881 | switch (direction) { | |
db8196df | 882 | case DMA_MEM_TO_DEV: |
53830cc7 | 883 | desc->lli.saddr = buf_addr + (period_len * period_index); |
beeaa103 | 884 | desc->lli.daddr = sconfig->dst_addr; |
53830cc7 | 885 | desc->lli.ctrla = ctrla; |
ae14d4b5 | 886 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED |
53830cc7 | 887 | | ATC_SRC_ADDR_MODE_INCR |
ae14d4b5 | 888 | | ATC_FC_MEM2PER |
bbe89c8e LD |
889 | | ATC_SIF(atchan->mem_if) |
890 | | ATC_DIF(atchan->per_if); | |
53830cc7 NF |
891 | break; |
892 | ||
db8196df | 893 | case DMA_DEV_TO_MEM: |
beeaa103 | 894 | desc->lli.saddr = sconfig->src_addr; |
53830cc7 NF |
895 | desc->lli.daddr = buf_addr + (period_len * period_index); |
896 | desc->lli.ctrla = ctrla; | |
ae14d4b5 | 897 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR |
53830cc7 | 898 | | ATC_SRC_ADDR_MODE_FIXED |
ae14d4b5 | 899 | | ATC_FC_PER2MEM |
bbe89c8e LD |
900 | | ATC_SIF(atchan->per_if) |
901 | | ATC_DIF(atchan->mem_if); | |
53830cc7 NF |
902 | break; |
903 | ||
904 | default: | |
905 | return -EINVAL; | |
906 | } | |
907 | ||
908 | return 0; | |
909 | } | |
910 | ||
911 | /** | |
912 | * atc_prep_dma_cyclic - prepare the cyclic DMA transfer | |
913 | * @chan: the DMA channel to prepare | |
914 | * @buf_addr: physical DMA address where the buffer starts | |
915 | * @buf_len: total number of bytes for the entire buffer | |
916 | * @period_len: number of bytes for each period | |
917 | * @direction: transfer direction, to or from device | |
ec8b5e48 | 918 | * @flags: tx descriptor status flags |
185ecb5f | 919 | * @context: transfer context (ignored) |
53830cc7 NF |
920 | */ |
921 | static struct dma_async_tx_descriptor * | |
922 | atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 923 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 924 | unsigned long flags, void *context) |
53830cc7 NF |
925 | { |
926 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
927 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 928 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
53830cc7 NF |
929 | struct at_desc *first = NULL; |
930 | struct at_desc *prev = NULL; | |
931 | unsigned long was_cyclic; | |
beeaa103 | 932 | unsigned int reg_width; |
53830cc7 NF |
933 | unsigned int periods = buf_len / period_len; |
934 | unsigned int i; | |
935 | ||
936 | dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", | |
db8196df | 937 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
53830cc7 NF |
938 | buf_addr, |
939 | periods, buf_len, period_len); | |
940 | ||
941 | if (unlikely(!atslave || !buf_len || !period_len)) { | |
942 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); | |
943 | return NULL; | |
944 | } | |
945 | ||
946 | was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); | |
947 | if (was_cyclic) { | |
948 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); | |
949 | return NULL; | |
950 | } | |
951 | ||
0e7264cc AS |
952 | if (unlikely(!is_slave_direction(direction))) |
953 | goto err_out; | |
954 | ||
beeaa103 NF |
955 | if (sconfig->direction == DMA_MEM_TO_DEV) |
956 | reg_width = convert_buswidth(sconfig->dst_addr_width); | |
957 | else | |
958 | reg_width = convert_buswidth(sconfig->src_addr_width); | |
959 | ||
53830cc7 | 960 | /* Check for too big/unaligned periods and unaligned DMA buffer */ |
0e7264cc | 961 | if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len)) |
53830cc7 NF |
962 | goto err_out; |
963 | ||
964 | /* build cyclic linked list */ | |
965 | for (i = 0; i < periods; i++) { | |
966 | struct at_desc *desc; | |
967 | ||
968 | desc = atc_desc_get(atchan); | |
969 | if (!desc) | |
970 | goto err_desc_get; | |
971 | ||
beeaa103 NF |
972 | if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr, |
973 | reg_width, period_len, direction)) | |
53830cc7 NF |
974 | goto err_desc_get; |
975 | ||
976 | atc_desc_chain(&first, &prev, desc); | |
977 | } | |
978 | ||
979 | /* lets make a cyclic list */ | |
980 | prev->lli.dscr = first->txd.phys; | |
981 | ||
982 | /* First descriptor of the chain embedds additional information */ | |
983 | first->txd.cookie = -EBUSY; | |
984 | first->len = buf_len; | |
d088c33b | 985 | first->tx_width = reg_width; |
53830cc7 NF |
986 | |
987 | return &first->txd; | |
988 | ||
989 | err_desc_get: | |
990 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
991 | atc_desc_put(atchan, first); | |
992 | err_out: | |
993 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
994 | return NULL; | |
995 | } | |
996 | ||
beeaa103 NF |
997 | static int set_runtime_config(struct dma_chan *chan, |
998 | struct dma_slave_config *sconfig) | |
999 | { | |
1000 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1001 | ||
1002 | /* Check if it is chan is configured for slave transfers */ | |
1003 | if (!chan->private) | |
1004 | return -EINVAL; | |
1005 | ||
1006 | memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig)); | |
1007 | ||
1008 | convert_burst(&atchan->dma_sconfig.src_maxburst); | |
1009 | convert_burst(&atchan->dma_sconfig.dst_maxburst); | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
53830cc7 | 1014 | |
05827630 LW |
1015 | static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
1016 | unsigned long arg) | |
808347f6 NF |
1017 | { |
1018 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1019 | struct at_dma *atdma = to_at_dma(chan->device); | |
23b5e3ad | 1020 | int chan_id = atchan->chan_common.chan_id; |
d8cb04b0 | 1021 | unsigned long flags; |
23b5e3ad | 1022 | |
808347f6 NF |
1023 | LIST_HEAD(list); |
1024 | ||
23b5e3ad | 1025 | dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd); |
c3635c78 | 1026 | |
23b5e3ad | 1027 | if (cmd == DMA_PAUSE) { |
d8cb04b0 | 1028 | spin_lock_irqsave(&atchan->lock, flags); |
808347f6 | 1029 | |
23b5e3ad | 1030 | dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); |
23b5e3ad | 1031 | set_bit(ATC_IS_PAUSED, &atchan->status); |
808347f6 | 1032 | |
d8cb04b0 | 1033 | spin_unlock_irqrestore(&atchan->lock, flags); |
23b5e3ad | 1034 | } else if (cmd == DMA_RESUME) { |
3c477482 | 1035 | if (!atc_chan_is_paused(atchan)) |
23b5e3ad | 1036 | return 0; |
808347f6 | 1037 | |
d8cb04b0 | 1038 | spin_lock_irqsave(&atchan->lock, flags); |
808347f6 | 1039 | |
23b5e3ad NF |
1040 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); |
1041 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
c3635c78 | 1042 | |
d8cb04b0 | 1043 | spin_unlock_irqrestore(&atchan->lock, flags); |
23b5e3ad NF |
1044 | } else if (cmd == DMA_TERMINATE_ALL) { |
1045 | struct at_desc *desc, *_desc; | |
1046 | /* | |
1047 | * This is only called when something went wrong elsewhere, so | |
1048 | * we don't really care about the data. Just disable the | |
1049 | * channel. We still have to poll the channel enable bit due | |
1050 | * to AHB/HSB limitations. | |
1051 | */ | |
d8cb04b0 | 1052 | spin_lock_irqsave(&atchan->lock, flags); |
23b5e3ad NF |
1053 | |
1054 | /* disabling channel: must also remove suspend state */ | |
1055 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); | |
1056 | ||
1057 | /* confirm that this channel is disabled */ | |
1058 | while (dma_readl(atdma, CHSR) & atchan->mask) | |
1059 | cpu_relax(); | |
1060 | ||
1061 | /* active_list entries will end up before queued entries */ | |
1062 | list_splice_init(&atchan->queue, &list); | |
1063 | list_splice_init(&atchan->active_list, &list); | |
1064 | ||
1065 | /* Flush all pending and queued descriptors */ | |
1066 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1067 | atc_chain_complete(atchan, desc); | |
1068 | ||
1069 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
1070 | /* if channel dedicated to cyclic operations, free it */ | |
1071 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
1072 | ||
d8cb04b0 | 1073 | spin_unlock_irqrestore(&atchan->lock, flags); |
beeaa103 NF |
1074 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1075 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
23b5e3ad NF |
1076 | } else { |
1077 | return -ENXIO; | |
1078 | } | |
b0ebeb9c | 1079 | |
c3635c78 | 1080 | return 0; |
808347f6 NF |
1081 | } |
1082 | ||
dc78baa2 | 1083 | /** |
07934481 | 1084 | * atc_tx_status - poll for transaction completion |
dc78baa2 NF |
1085 | * @chan: DMA channel |
1086 | * @cookie: transaction identifier to check status of | |
07934481 | 1087 | * @txstate: if not %NULL updated with transaction state |
dc78baa2 | 1088 | * |
07934481 | 1089 | * If @txstate is passed in, upon return it reflect the driver |
dc78baa2 NF |
1090 | * internal state and can be used with dma_async_is_complete() to check |
1091 | * the status of multiple cookies without re-checking hardware state. | |
1092 | */ | |
1093 | static enum dma_status | |
07934481 | 1094 | atc_tx_status(struct dma_chan *chan, |
dc78baa2 | 1095 | dma_cookie_t cookie, |
07934481 | 1096 | struct dma_tx_state *txstate) |
dc78baa2 NF |
1097 | { |
1098 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1099 | unsigned long flags; |
dc78baa2 | 1100 | enum dma_status ret; |
d48de6f1 | 1101 | int bytes = 0; |
dc78baa2 | 1102 | |
96a2af41 | 1103 | ret = dma_cookie_status(chan, cookie, txstate); |
d48de6f1 ES |
1104 | if (ret == DMA_SUCCESS) |
1105 | return ret; | |
1106 | /* | |
1107 | * There's no point calculating the residue if there's | |
1108 | * no txstate to store the value. | |
1109 | */ | |
1110 | if (!txstate) | |
1111 | return DMA_ERROR; | |
dc78baa2 | 1112 | |
d48de6f1 | 1113 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 1114 | |
d48de6f1 ES |
1115 | /* Get number of bytes left in the active transactions */ |
1116 | bytes = atc_get_bytes_left(chan); | |
96a2af41 | 1117 | |
d8cb04b0 | 1118 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 | 1119 | |
d48de6f1 ES |
1120 | if (unlikely(bytes < 0)) { |
1121 | dev_vdbg(chan2dev(chan), "get residual bytes error\n"); | |
1122 | return DMA_ERROR; | |
1123 | } else | |
1124 | dma_set_residue(txstate, bytes); | |
23b5e3ad | 1125 | |
d48de6f1 ES |
1126 | dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n", |
1127 | ret, cookie, bytes); | |
dc78baa2 NF |
1128 | |
1129 | return ret; | |
1130 | } | |
1131 | ||
1132 | /** | |
1133 | * atc_issue_pending - try to finish work | |
1134 | * @chan: target DMA channel | |
1135 | */ | |
1136 | static void atc_issue_pending(struct dma_chan *chan) | |
1137 | { | |
1138 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1139 | unsigned long flags; |
dc78baa2 NF |
1140 | |
1141 | dev_vdbg(chan2dev(chan), "issue_pending\n"); | |
1142 | ||
53830cc7 | 1143 | /* Not needed for cyclic transfers */ |
3c477482 | 1144 | if (atc_chan_is_cyclic(atchan)) |
53830cc7 NF |
1145 | return; |
1146 | ||
d8cb04b0 | 1147 | spin_lock_irqsave(&atchan->lock, flags); |
d202f051 | 1148 | atc_advance_work(atchan); |
d8cb04b0 | 1149 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1150 | } |
1151 | ||
1152 | /** | |
1153 | * atc_alloc_chan_resources - allocate resources for DMA channel | |
1154 | * @chan: allocate descriptor resources for this channel | |
1155 | * @client: current client requesting the channel be ready for requests | |
1156 | * | |
1157 | * return - the number of allocated descriptors | |
1158 | */ | |
1159 | static int atc_alloc_chan_resources(struct dma_chan *chan) | |
1160 | { | |
1161 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1162 | struct at_dma *atdma = to_at_dma(chan->device); | |
1163 | struct at_desc *desc; | |
808347f6 | 1164 | struct at_dma_slave *atslave; |
d8cb04b0 | 1165 | unsigned long flags; |
dc78baa2 | 1166 | int i; |
808347f6 | 1167 | u32 cfg; |
dc78baa2 NF |
1168 | LIST_HEAD(tmp_list); |
1169 | ||
1170 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); | |
1171 | ||
1172 | /* ASSERT: channel is idle */ | |
1173 | if (atc_chan_is_enabled(atchan)) { | |
1174 | dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); | |
1175 | return -EIO; | |
1176 | } | |
1177 | ||
808347f6 NF |
1178 | cfg = ATC_DEFAULT_CFG; |
1179 | ||
1180 | atslave = chan->private; | |
1181 | if (atslave) { | |
1182 | /* | |
1183 | * We need controller-specific data to set up slave | |
1184 | * transfers. | |
1185 | */ | |
1186 | BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); | |
1187 | ||
ea7e7906 | 1188 | /* if cfg configuration specified take it instead of default */ |
808347f6 NF |
1189 | if (atslave->cfg) |
1190 | cfg = atslave->cfg; | |
1191 | } | |
1192 | ||
1193 | /* have we already been set up? | |
1194 | * reconfigure channel but no need to reallocate descriptors */ | |
dc78baa2 NF |
1195 | if (!list_empty(&atchan->free_list)) |
1196 | return atchan->descs_allocated; | |
1197 | ||
1198 | /* Allocate initial pool of descriptors */ | |
1199 | for (i = 0; i < init_nr_desc_per_channel; i++) { | |
1200 | desc = atc_alloc_descriptor(chan, GFP_KERNEL); | |
1201 | if (!desc) { | |
1202 | dev_err(atdma->dma_common.dev, | |
1203 | "Only %d initial descriptors\n", i); | |
1204 | break; | |
1205 | } | |
1206 | list_add_tail(&desc->desc_node, &tmp_list); | |
1207 | } | |
1208 | ||
d8cb04b0 | 1209 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 1210 | atchan->descs_allocated = i; |
d48de6f1 | 1211 | atchan->remain_desc = 0; |
dc78baa2 | 1212 | list_splice(&tmp_list, &atchan->free_list); |
d3ee98cd | 1213 | dma_cookie_init(chan); |
d8cb04b0 | 1214 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1215 | |
1216 | /* channel parameters */ | |
808347f6 | 1217 | channel_writel(atchan, CFG, cfg); |
dc78baa2 NF |
1218 | |
1219 | dev_dbg(chan2dev(chan), | |
1220 | "alloc_chan_resources: allocated %d descriptors\n", | |
1221 | atchan->descs_allocated); | |
1222 | ||
1223 | return atchan->descs_allocated; | |
1224 | } | |
1225 | ||
1226 | /** | |
1227 | * atc_free_chan_resources - free all channel resources | |
1228 | * @chan: DMA channel | |
1229 | */ | |
1230 | static void atc_free_chan_resources(struct dma_chan *chan) | |
1231 | { | |
1232 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1233 | struct at_dma *atdma = to_at_dma(chan->device); | |
1234 | struct at_desc *desc, *_desc; | |
1235 | LIST_HEAD(list); | |
1236 | ||
1237 | dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", | |
1238 | atchan->descs_allocated); | |
1239 | ||
1240 | /* ASSERT: channel is idle */ | |
1241 | BUG_ON(!list_empty(&atchan->active_list)); | |
1242 | BUG_ON(!list_empty(&atchan->queue)); | |
1243 | BUG_ON(atc_chan_is_enabled(atchan)); | |
1244 | ||
1245 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { | |
1246 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); | |
1247 | list_del(&desc->desc_node); | |
1248 | /* free link descriptor */ | |
1249 | dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); | |
1250 | } | |
1251 | list_splice_init(&atchan->free_list, &list); | |
1252 | atchan->descs_allocated = 0; | |
53830cc7 | 1253 | atchan->status = 0; |
d48de6f1 | 1254 | atchan->remain_desc = 0; |
dc78baa2 NF |
1255 | |
1256 | dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); | |
1257 | } | |
1258 | ||
bbe89c8e LD |
1259 | #ifdef CONFIG_OF |
1260 | static bool at_dma_filter(struct dma_chan *chan, void *slave) | |
1261 | { | |
1262 | struct at_dma_slave *atslave = slave; | |
1263 | ||
1264 | if (atslave->dma_dev == chan->device->dev) { | |
1265 | chan->private = atslave; | |
1266 | return true; | |
1267 | } else { | |
1268 | return false; | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1273 | struct of_dma *of_dma) | |
1274 | { | |
1275 | struct dma_chan *chan; | |
1276 | struct at_dma_chan *atchan; | |
1277 | struct at_dma_slave *atslave; | |
1278 | dma_cap_mask_t mask; | |
1279 | unsigned int per_id; | |
1280 | struct platform_device *dmac_pdev; | |
1281 | ||
1282 | if (dma_spec->args_count != 2) | |
1283 | return NULL; | |
1284 | ||
1285 | dmac_pdev = of_find_device_by_node(dma_spec->np); | |
1286 | ||
1287 | dma_cap_zero(mask); | |
1288 | dma_cap_set(DMA_SLAVE, mask); | |
1289 | ||
1290 | atslave = devm_kzalloc(&dmac_pdev->dev, sizeof(*atslave), GFP_KERNEL); | |
1291 | if (!atslave) | |
1292 | return NULL; | |
62971b29 LD |
1293 | |
1294 | atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW; | |
bbe89c8e LD |
1295 | /* |
1296 | * We can fill both SRC_PER and DST_PER, one of these fields will be | |
1297 | * ignored depending on DMA transfer direction. | |
1298 | */ | |
62971b29 LD |
1299 | per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK; |
1300 | atslave->cfg |= ATC_DST_PER_MSB(per_id) | ATC_DST_PER(per_id) | |
6c22770f | 1301 | | ATC_SRC_PER_MSB(per_id) | ATC_SRC_PER(per_id); |
62971b29 LD |
1302 | /* |
1303 | * We have to translate the value we get from the device tree since | |
1304 | * the half FIFO configuration value had to be 0 to keep backward | |
1305 | * compatibility. | |
1306 | */ | |
1307 | switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) { | |
1308 | case AT91_DMA_CFG_FIFOCFG_ALAP: | |
1309 | atslave->cfg |= ATC_FIFOCFG_LARGESTBURST; | |
1310 | break; | |
1311 | case AT91_DMA_CFG_FIFOCFG_ASAP: | |
1312 | atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE; | |
1313 | break; | |
1314 | case AT91_DMA_CFG_FIFOCFG_HALF: | |
1315 | default: | |
1316 | atslave->cfg |= ATC_FIFOCFG_HALFFIFO; | |
1317 | } | |
bbe89c8e LD |
1318 | atslave->dma_dev = &dmac_pdev->dev; |
1319 | ||
1320 | chan = dma_request_channel(mask, at_dma_filter, atslave); | |
1321 | if (!chan) | |
1322 | return NULL; | |
1323 | ||
1324 | atchan = to_at_dma_chan(chan); | |
1325 | atchan->per_if = dma_spec->args[0] & 0xff; | |
1326 | atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff; | |
1327 | ||
1328 | return chan; | |
1329 | } | |
1330 | #else | |
1331 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1332 | struct of_dma *of_dma) | |
1333 | { | |
1334 | return NULL; | |
1335 | } | |
1336 | #endif | |
dc78baa2 NF |
1337 | |
1338 | /*-- Module Management -----------------------------------------------*/ | |
1339 | ||
02f88be9 NF |
1340 | /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */ |
1341 | static struct at_dma_platform_data at91sam9rl_config = { | |
1342 | .nr_channels = 2, | |
1343 | }; | |
1344 | static struct at_dma_platform_data at91sam9g45_config = { | |
1345 | .nr_channels = 8, | |
1346 | }; | |
1347 | ||
c5115953 NF |
1348 | #if defined(CONFIG_OF) |
1349 | static const struct of_device_id atmel_dma_dt_ids[] = { | |
1350 | { | |
1351 | .compatible = "atmel,at91sam9rl-dma", | |
02f88be9 | 1352 | .data = &at91sam9rl_config, |
c5115953 NF |
1353 | }, { |
1354 | .compatible = "atmel,at91sam9g45-dma", | |
02f88be9 | 1355 | .data = &at91sam9g45_config, |
dcc81734 NF |
1356 | }, { |
1357 | /* sentinel */ | |
1358 | } | |
c5115953 NF |
1359 | }; |
1360 | ||
1361 | MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids); | |
1362 | #endif | |
1363 | ||
0ab88a01 | 1364 | static const struct platform_device_id atdma_devtypes[] = { |
67348450 NF |
1365 | { |
1366 | .name = "at91sam9rl_dma", | |
02f88be9 | 1367 | .driver_data = (unsigned long) &at91sam9rl_config, |
67348450 NF |
1368 | }, { |
1369 | .name = "at91sam9g45_dma", | |
02f88be9 | 1370 | .driver_data = (unsigned long) &at91sam9g45_config, |
67348450 NF |
1371 | }, { |
1372 | /* sentinel */ | |
1373 | } | |
1374 | }; | |
1375 | ||
7fd63ccd | 1376 | static inline const struct at_dma_platform_data * __init at_dma_get_driver_data( |
02f88be9 | 1377 | struct platform_device *pdev) |
c5115953 NF |
1378 | { |
1379 | if (pdev->dev.of_node) { | |
1380 | const struct of_device_id *match; | |
1381 | match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node); | |
1382 | if (match == NULL) | |
02f88be9 NF |
1383 | return NULL; |
1384 | return match->data; | |
c5115953 | 1385 | } |
02f88be9 NF |
1386 | return (struct at_dma_platform_data *) |
1387 | platform_get_device_id(pdev)->driver_data; | |
c5115953 NF |
1388 | } |
1389 | ||
dc78baa2 NF |
1390 | /** |
1391 | * at_dma_off - disable DMA controller | |
1392 | * @atdma: the Atmel HDAMC device | |
1393 | */ | |
1394 | static void at_dma_off(struct at_dma *atdma) | |
1395 | { | |
1396 | dma_writel(atdma, EN, 0); | |
1397 | ||
1398 | /* disable all interrupts */ | |
1399 | dma_writel(atdma, EBCIDR, -1L); | |
1400 | ||
1401 | /* confirm that all channels are disabled */ | |
1402 | while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) | |
1403 | cpu_relax(); | |
1404 | } | |
1405 | ||
1406 | static int __init at_dma_probe(struct platform_device *pdev) | |
1407 | { | |
dc78baa2 NF |
1408 | struct resource *io; |
1409 | struct at_dma *atdma; | |
1410 | size_t size; | |
1411 | int irq; | |
1412 | int err; | |
1413 | int i; | |
7fd63ccd | 1414 | const struct at_dma_platform_data *plat_dat; |
67348450 | 1415 | |
02f88be9 NF |
1416 | /* setup platform data for each SoC */ |
1417 | dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask); | |
1418 | dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); | |
1419 | dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); | |
67348450 NF |
1420 | |
1421 | /* get DMA parameters from controller type */ | |
02f88be9 NF |
1422 | plat_dat = at_dma_get_driver_data(pdev); |
1423 | if (!plat_dat) | |
1424 | return -ENODEV; | |
dc78baa2 NF |
1425 | |
1426 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1427 | if (!io) | |
1428 | return -EINVAL; | |
1429 | ||
1430 | irq = platform_get_irq(pdev, 0); | |
1431 | if (irq < 0) | |
1432 | return irq; | |
1433 | ||
1434 | size = sizeof(struct at_dma); | |
02f88be9 | 1435 | size += plat_dat->nr_channels * sizeof(struct at_dma_chan); |
dc78baa2 NF |
1436 | atdma = kzalloc(size, GFP_KERNEL); |
1437 | if (!atdma) | |
1438 | return -ENOMEM; | |
1439 | ||
67348450 | 1440 | /* discover transaction capabilities */ |
02f88be9 NF |
1441 | atdma->dma_common.cap_mask = plat_dat->cap_mask; |
1442 | atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; | |
dc78baa2 | 1443 | |
114df7d6 | 1444 | size = resource_size(io); |
dc78baa2 NF |
1445 | if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { |
1446 | err = -EBUSY; | |
1447 | goto err_kfree; | |
1448 | } | |
1449 | ||
1450 | atdma->regs = ioremap(io->start, size); | |
1451 | if (!atdma->regs) { | |
1452 | err = -ENOMEM; | |
1453 | goto err_release_r; | |
1454 | } | |
1455 | ||
1456 | atdma->clk = clk_get(&pdev->dev, "dma_clk"); | |
1457 | if (IS_ERR(atdma->clk)) { | |
1458 | err = PTR_ERR(atdma->clk); | |
1459 | goto err_clk; | |
1460 | } | |
1461 | clk_enable(atdma->clk); | |
1462 | ||
1463 | /* force dma off, just in case */ | |
1464 | at_dma_off(atdma); | |
1465 | ||
1466 | err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); | |
1467 | if (err) | |
1468 | goto err_irq; | |
1469 | ||
1470 | platform_set_drvdata(pdev, atdma); | |
1471 | ||
1472 | /* create a pool of consistent memory blocks for hardware descriptors */ | |
1473 | atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", | |
1474 | &pdev->dev, sizeof(struct at_desc), | |
1475 | 4 /* word alignment */, 0); | |
1476 | if (!atdma->dma_desc_pool) { | |
1477 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1478 | err = -ENOMEM; | |
1479 | goto err_pool_create; | |
1480 | } | |
1481 | ||
1482 | /* clear any pending interrupt */ | |
1483 | while (dma_readl(atdma, EBCISR)) | |
1484 | cpu_relax(); | |
1485 | ||
1486 | /* initialize channels related values */ | |
1487 | INIT_LIST_HEAD(&atdma->dma_common.channels); | |
02f88be9 | 1488 | for (i = 0; i < plat_dat->nr_channels; i++) { |
dc78baa2 NF |
1489 | struct at_dma_chan *atchan = &atdma->chan[i]; |
1490 | ||
bbe89c8e LD |
1491 | atchan->mem_if = AT_DMA_MEM_IF; |
1492 | atchan->per_if = AT_DMA_PER_IF; | |
dc78baa2 | 1493 | atchan->chan_common.device = &atdma->dma_common; |
d3ee98cd | 1494 | dma_cookie_init(&atchan->chan_common); |
dc78baa2 NF |
1495 | list_add_tail(&atchan->chan_common.device_node, |
1496 | &atdma->dma_common.channels); | |
1497 | ||
1498 | atchan->ch_regs = atdma->regs + ch_regs(i); | |
1499 | spin_lock_init(&atchan->lock); | |
1500 | atchan->mask = 1 << i; | |
1501 | ||
1502 | INIT_LIST_HEAD(&atchan->active_list); | |
1503 | INIT_LIST_HEAD(&atchan->queue); | |
1504 | INIT_LIST_HEAD(&atchan->free_list); | |
1505 | ||
1506 | tasklet_init(&atchan->tasklet, atc_tasklet, | |
1507 | (unsigned long)atchan); | |
bda3a47c | 1508 | atc_enable_chan_irq(atdma, i); |
dc78baa2 NF |
1509 | } |
1510 | ||
1511 | /* set base routines */ | |
1512 | atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; | |
1513 | atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; | |
07934481 | 1514 | atdma->dma_common.device_tx_status = atc_tx_status; |
dc78baa2 NF |
1515 | atdma->dma_common.device_issue_pending = atc_issue_pending; |
1516 | atdma->dma_common.dev = &pdev->dev; | |
1517 | ||
1518 | /* set prep routines based on capability */ | |
1519 | if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) | |
1520 | atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; | |
1521 | ||
d7db8080 | 1522 | if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { |
808347f6 | 1523 | atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; |
d7db8080 NF |
1524 | /* controller can do slave DMA: can trigger cyclic transfers */ |
1525 | dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask); | |
53830cc7 | 1526 | atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; |
c3635c78 | 1527 | atdma->dma_common.device_control = atc_control; |
d7db8080 | 1528 | } |
808347f6 | 1529 | |
dc78baa2 NF |
1530 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
1531 | ||
1532 | dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n", | |
1533 | dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", | |
1534 | dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", | |
02f88be9 | 1535 | plat_dat->nr_channels); |
dc78baa2 NF |
1536 | |
1537 | dma_async_device_register(&atdma->dma_common); | |
1538 | ||
bbe89c8e LD |
1539 | /* |
1540 | * Do not return an error if the dmac node is not present in order to | |
1541 | * not break the existing way of requesting channel with | |
1542 | * dma_request_channel(). | |
1543 | */ | |
1544 | if (pdev->dev.of_node) { | |
1545 | err = of_dma_controller_register(pdev->dev.of_node, | |
1546 | at_dma_xlate, atdma); | |
1547 | if (err) { | |
1548 | dev_err(&pdev->dev, "could not register of_dma_controller\n"); | |
1549 | goto err_of_dma_controller_register; | |
1550 | } | |
1551 | } | |
1552 | ||
dc78baa2 NF |
1553 | return 0; |
1554 | ||
bbe89c8e LD |
1555 | err_of_dma_controller_register: |
1556 | dma_async_device_unregister(&atdma->dma_common); | |
1557 | dma_pool_destroy(atdma->dma_desc_pool); | |
dc78baa2 | 1558 | err_pool_create: |
dc78baa2 NF |
1559 | free_irq(platform_get_irq(pdev, 0), atdma); |
1560 | err_irq: | |
1561 | clk_disable(atdma->clk); | |
1562 | clk_put(atdma->clk); | |
1563 | err_clk: | |
1564 | iounmap(atdma->regs); | |
1565 | atdma->regs = NULL; | |
1566 | err_release_r: | |
1567 | release_mem_region(io->start, size); | |
1568 | err_kfree: | |
1569 | kfree(atdma); | |
1570 | return err; | |
1571 | } | |
1572 | ||
1d1bbd30 | 1573 | static int at_dma_remove(struct platform_device *pdev) |
dc78baa2 NF |
1574 | { |
1575 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1576 | struct dma_chan *chan, *_chan; | |
1577 | struct resource *io; | |
1578 | ||
1579 | at_dma_off(atdma); | |
1580 | dma_async_device_unregister(&atdma->dma_common); | |
1581 | ||
1582 | dma_pool_destroy(atdma->dma_desc_pool); | |
dc78baa2 NF |
1583 | free_irq(platform_get_irq(pdev, 0), atdma); |
1584 | ||
1585 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1586 | device_node) { | |
1587 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1588 | ||
1589 | /* Disable interrupts */ | |
bda3a47c | 1590 | atc_disable_chan_irq(atdma, chan->chan_id); |
dc78baa2 NF |
1591 | tasklet_disable(&atchan->tasklet); |
1592 | ||
1593 | tasklet_kill(&atchan->tasklet); | |
1594 | list_del(&chan->device_node); | |
1595 | } | |
1596 | ||
1597 | clk_disable(atdma->clk); | |
1598 | clk_put(atdma->clk); | |
1599 | ||
1600 | iounmap(atdma->regs); | |
1601 | atdma->regs = NULL; | |
1602 | ||
1603 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
114df7d6 | 1604 | release_mem_region(io->start, resource_size(io)); |
dc78baa2 NF |
1605 | |
1606 | kfree(atdma); | |
1607 | ||
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | static void at_dma_shutdown(struct platform_device *pdev) | |
1612 | { | |
1613 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1614 | ||
1615 | at_dma_off(platform_get_drvdata(pdev)); | |
1616 | clk_disable(atdma->clk); | |
1617 | } | |
1618 | ||
c0ba5947 NF |
1619 | static int at_dma_prepare(struct device *dev) |
1620 | { | |
1621 | struct platform_device *pdev = to_platform_device(dev); | |
1622 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1623 | struct dma_chan *chan, *_chan; | |
1624 | ||
1625 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1626 | device_node) { | |
1627 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1628 | /* wait for transaction completion (except in cyclic case) */ | |
3c477482 | 1629 | if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1630 | return -EAGAIN; |
1631 | } | |
1632 | return 0; | |
1633 | } | |
1634 | ||
1635 | static void atc_suspend_cyclic(struct at_dma_chan *atchan) | |
1636 | { | |
1637 | struct dma_chan *chan = &atchan->chan_common; | |
1638 | ||
1639 | /* Channel should be paused by user | |
1640 | * do it anyway even if it is not done already */ | |
3c477482 | 1641 | if (!atc_chan_is_paused(atchan)) { |
c0ba5947 NF |
1642 | dev_warn(chan2dev(chan), |
1643 | "cyclic channel not paused, should be done by channel user\n"); | |
1644 | atc_control(chan, DMA_PAUSE, 0); | |
1645 | } | |
1646 | ||
1647 | /* now preserve additional data for cyclic operations */ | |
1648 | /* next descriptor address in the cyclic list */ | |
1649 | atchan->save_dscr = channel_readl(atchan, DSCR); | |
1650 | ||
1651 | vdbg_dump_regs(atchan); | |
1652 | } | |
1653 | ||
33f82d14 | 1654 | static int at_dma_suspend_noirq(struct device *dev) |
dc78baa2 | 1655 | { |
33f82d14 DW |
1656 | struct platform_device *pdev = to_platform_device(dev); |
1657 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 1658 | struct dma_chan *chan, *_chan; |
dc78baa2 | 1659 | |
c0ba5947 NF |
1660 | /* preserve data */ |
1661 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1662 | device_node) { | |
1663 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1664 | ||
3c477482 | 1665 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1666 | atc_suspend_cyclic(atchan); |
1667 | atchan->save_cfg = channel_readl(atchan, CFG); | |
1668 | } | |
1669 | atdma->save_imr = dma_readl(atdma, EBCIMR); | |
1670 | ||
1671 | /* disable DMA controller */ | |
1672 | at_dma_off(atdma); | |
dc78baa2 NF |
1673 | clk_disable(atdma->clk); |
1674 | return 0; | |
1675 | } | |
1676 | ||
c0ba5947 NF |
1677 | static void atc_resume_cyclic(struct at_dma_chan *atchan) |
1678 | { | |
1679 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
1680 | ||
1681 | /* restore channel status for cyclic descriptors list: | |
1682 | * next descriptor in the cyclic list at the time of suspend */ | |
1683 | channel_writel(atchan, SADDR, 0); | |
1684 | channel_writel(atchan, DADDR, 0); | |
1685 | channel_writel(atchan, CTRLA, 0); | |
1686 | channel_writel(atchan, CTRLB, 0); | |
1687 | channel_writel(atchan, DSCR, atchan->save_dscr); | |
1688 | dma_writel(atdma, CHER, atchan->mask); | |
1689 | ||
1690 | /* channel pause status should be removed by channel user | |
1691 | * We cannot take the initiative to do it here */ | |
1692 | ||
1693 | vdbg_dump_regs(atchan); | |
1694 | } | |
1695 | ||
33f82d14 | 1696 | static int at_dma_resume_noirq(struct device *dev) |
dc78baa2 | 1697 | { |
33f82d14 DW |
1698 | struct platform_device *pdev = to_platform_device(dev); |
1699 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 1700 | struct dma_chan *chan, *_chan; |
dc78baa2 | 1701 | |
c0ba5947 | 1702 | /* bring back DMA controller */ |
dc78baa2 NF |
1703 | clk_enable(atdma->clk); |
1704 | dma_writel(atdma, EN, AT_DMA_ENABLE); | |
c0ba5947 NF |
1705 | |
1706 | /* clear any pending interrupt */ | |
1707 | while (dma_readl(atdma, EBCISR)) | |
1708 | cpu_relax(); | |
1709 | ||
1710 | /* restore saved data */ | |
1711 | dma_writel(atdma, EBCIER, atdma->save_imr); | |
1712 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1713 | device_node) { | |
1714 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1715 | ||
1716 | channel_writel(atchan, CFG, atchan->save_cfg); | |
3c477482 | 1717 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1718 | atc_resume_cyclic(atchan); |
1719 | } | |
dc78baa2 | 1720 | return 0; |
dc78baa2 NF |
1721 | } |
1722 | ||
47145210 | 1723 | static const struct dev_pm_ops at_dma_dev_pm_ops = { |
c0ba5947 | 1724 | .prepare = at_dma_prepare, |
33f82d14 DW |
1725 | .suspend_noirq = at_dma_suspend_noirq, |
1726 | .resume_noirq = at_dma_resume_noirq, | |
1727 | }; | |
1728 | ||
dc78baa2 | 1729 | static struct platform_driver at_dma_driver = { |
1d1bbd30 | 1730 | .remove = at_dma_remove, |
dc78baa2 | 1731 | .shutdown = at_dma_shutdown, |
67348450 | 1732 | .id_table = atdma_devtypes, |
dc78baa2 NF |
1733 | .driver = { |
1734 | .name = "at_hdmac", | |
33f82d14 | 1735 | .pm = &at_dma_dev_pm_ops, |
c5115953 | 1736 | .of_match_table = of_match_ptr(atmel_dma_dt_ids), |
dc78baa2 NF |
1737 | }, |
1738 | }; | |
1739 | ||
1740 | static int __init at_dma_init(void) | |
1741 | { | |
1742 | return platform_driver_probe(&at_dma_driver, at_dma_probe); | |
1743 | } | |
93d0bec2 | 1744 | subsys_initcall(at_dma_init); |
dc78baa2 NF |
1745 | |
1746 | static void __exit at_dma_exit(void) | |
1747 | { | |
1748 | platform_driver_unregister(&at_dma_driver); | |
1749 | } | |
1750 | module_exit(at_dma_exit); | |
1751 | ||
1752 | MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); | |
1753 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); | |
1754 | MODULE_LICENSE("GPL"); | |
1755 | MODULE_ALIAS("platform:at_hdmac"); |